drivers/mailbox/mtk-cmdq-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2018 MediaTek Inc.
   4
   5 #include <linux/bitops.h>
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/errno.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mailbox_controller.h>
  17 #include <linux/mailbox/mtk-cmdq-mailbox.h>
  18 #include <linux/of_device.h>
  19
  20 #define CMDQ_OP_CODE_MASK               (0xff << CMDQ_OP_CODE_SHIFT)
  21 #define CMDQ_NUM_CMD(t)                 (t->cmd_buf_size / CMDQ_INST_SIZE)
  22 #define CMDQ_GCE_NUM_MAX                (2)
  23
  24 #define CMDQ_CURR_IRQ_STATUS            0x10
  25 #define CMDQ_SYNC_TOKEN_UPDATE          0x68
  26 #define CMDQ_THR_SLOT_CYCLES            0x30
  27 #define CMDQ_THR_BASE                   0x100
  28 #define CMDQ_THR_SIZE                   0x80
  29 #define CMDQ_THR_WARM_RESET             0x00
  30 #define CMDQ_THR_ENABLE_TASK            0x04
  31 #define CMDQ_THR_SUSPEND_TASK           0x08
  32 #define CMDQ_THR_CURR_STATUS            0x0c
  33 #define CMDQ_THR_IRQ_STATUS             0x10
  34 #define CMDQ_THR_IRQ_ENABLE             0x14
  35 #define CMDQ_THR_CURR_ADDR              0x20
  36 #define CMDQ_THR_END_ADDR               0x24
  37 #define CMDQ_THR_WAIT_TOKEN             0x30
  38 #define CMDQ_THR_PRIORITY               0x40
  39
  40 #define GCE_GCTL_VALUE                  0x48
  41
  42 #define CMDQ_THR_ACTIVE_SLOT_CYCLES     0x3200
  43 #define CMDQ_THR_ENABLED                0x1
  44 #define CMDQ_THR_DISABLED               0x0
  45 #define CMDQ_THR_SUSPEND                0x1
  46 #define CMDQ_THR_RESUME                 0x0
  47 #define CMDQ_THR_STATUS_SUSPENDED       BIT(1)
  48 #define CMDQ_THR_DO_WARM_RESET          BIT(0)
  49 #define CMDQ_THR_IRQ_DONE               0x1
  50 #define CMDQ_THR_IRQ_ERROR              0x12
  51 #define CMDQ_THR_IRQ_EN                 (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
  52 #define CMDQ_THR_IS_WAITING             BIT(31)
  53
  54 #define CMDQ_JUMP_BY_OFFSET             0x10000000
  55 #define CMDQ_JUMP_BY_PA                 0x10000001
  56
  57 struct cmdq_thread {
  58         struct mbox_chan        *chan;
  59         void __iomem            *base;
  60         struct list_head        task_busy_list;
  61         u32                     priority;
  62 };
  63
  64 struct cmdq_task {
  65         struct cmdq             *cmdq;
  66         struct list_head        list_entry;
  67         dma_addr_t              pa_base;
  68         struct cmdq_thread      *thread;
  69         struct cmdq_pkt         *pkt; /* the packet sent from mailbox client */
  70 };
  71
  72 struct cmdq {
  73         struct mbox_controller  mbox;
  74         void __iomem            *base;
  75         int                     irq;
  76         u32                     thread_nr;
  77         u32                     irq_mask;
  78         struct cmdq_thread      *thread;
  79         struct clk_bulk_data    clocks[CMDQ_GCE_NUM_MAX];
  80         bool                    suspended;
  81         u8                      shift_pa;
  82         bool                    control_by_sw;
  83         u32                     gce_num;
  84 };
  85
  86 struct gce_plat {
  87         u32 thread_nr;
  88         u8 shift;
  89         bool control_by_sw;
  90         u32 gce_num;
  91 };
  92
  93 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
  94 {
  95         struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
  96
  97         return cmdq->shift_pa;
  98 }
  99 EXPORT_SYMBOL(cmdq_get_shift_pa);
 100
 101 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
 102 {
 103         u32 status;
 104
 105         writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
 106
 107         /* If already disabled, treat as suspended successful. */
 108         if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
 109                 return 0;
 110
 111         if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
 112                         status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
 113                 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
 114                         (u32)(thread->base - cmdq->base));
 115                 return -EFAULT;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static void cmdq_thread_resume(struct cmdq_thread *thread)
 122 {
 123         writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
 124 }
 125
 126 static void cmdq_init(struct cmdq *cmdq)
 127 {
 128         int i;
 129
 130         WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 131         if (cmdq->control_by_sw)
 132                 writel(0x7, cmdq->base + GCE_GCTL_VALUE);
 133         writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 134         for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 135                 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
 136         clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
 137 }
 138
 139 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
 140 {
 141         u32 warm_reset;
 142
 143         writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
 144         if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
 145                         warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
 146                         0, 10)) {
 147                 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
 148                         (u32)(thread->base - cmdq->base));
 149                 return -EFAULT;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
 156 {
 157         cmdq_thread_reset(cmdq, thread);
 158         writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
 159 }
 160
 161 /* notify GCE to re-fetch commands by setting GCE thread PC */
 162 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
 163 {
 164         writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
 165                thread->base + CMDQ_THR_CURR_ADDR);
 166 }
 167
 168 static void cmdq_task_insert_into_thread(struct cmdq_task *task)
 169 {
 170         struct device *dev = task->cmdq->mbox.dev;
 171         struct cmdq_thread *thread = task->thread;
 172         struct cmdq_task *prev_task = list_last_entry(
 173                         &thread->task_busy_list, typeof(*task), list_entry);
 174         u64 *prev_task_base = prev_task->pkt->va_base;
 175
 176         /* let previous task jump to this task */
 177         dma_sync_single_for_cpu(dev, prev_task->pa_base,
 178                                 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 179         prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
 180                 (u64)CMDQ_JUMP_BY_PA << 32 |
 181                 (task->pa_base >> task->cmdq->shift_pa);
 182         dma_sync_single_for_device(dev, prev_task->pa_base,
 183                                    prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 184
 185         cmdq_thread_invalidate_fetched_data(thread);
 186 }
 187
 188 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
 189 {
 190         return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
 191 }
 192
 193 static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
 194 {
 195         struct cmdq_cb_data data;
 196
 197         data.sta = sta;
 198         data.pkt = task->pkt;
 199         mbox_chan_received_data(task->thread->chan, &data);
 200
 201         list_del(&task->list_entry);
 202 }
 203
 204 static void cmdq_task_handle_error(struct cmdq_task *task)
 205 {
 206         struct cmdq_thread *thread = task->thread;
 207         struct cmdq_task *next_task;
 208         struct cmdq *cmdq = task->cmdq;
 209
 210         dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
 211         WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 212         next_task = list_first_entry_or_null(&thread->task_busy_list,
 213                         struct cmdq_task, list_entry);
 214         if (next_task)
 215                 writel(next_task->pa_base >> cmdq->shift_pa,
 216                        thread->base + CMDQ_THR_CURR_ADDR);
 217         cmdq_thread_resume(thread);
 218 }
 219
 220 static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 221                                     struct cmdq_thread *thread)
 222 {
 223         struct cmdq_task *task, *tmp, *curr_task = NULL;
 224         u32 curr_pa, irq_flag, task_end_pa;
 225         bool err;
 226
 227         irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
 228         writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
 229
 230         /*
 231          * When ISR call this function, another CPU core could run
 232          * "release task" right before we acquire the spin lock, and thus
 233          * reset / disable this GCE thread, so we need to check the enable
 234          * bit of this GCE thread.
 235          */
 236         if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
 237                 return;
 238
 239         if (irq_flag & CMDQ_THR_IRQ_ERROR)
 240                 err = true;
 241         else if (irq_flag & CMDQ_THR_IRQ_DONE)
 242                 err = false;
 243         else
 244                 return;
 245
 246         curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
 247
 248         list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 249                                  list_entry) {
 250                 task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
 251                 if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
 252                         curr_task = task;
 253
 254                 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
 255                         cmdq_task_exec_done(task, 0);
 256                         kfree(task);
 257                 } else if (err) {
 258                         cmdq_task_exec_done(task, -ENOEXEC);
 259                         cmdq_task_handle_error(curr_task);
 260                         kfree(task);
 261                 }
 262
 263                 if (curr_task)
 264                         break;
 265         }
 266
 267         if (list_empty(&thread->task_busy_list)) {
 268                 cmdq_thread_disable(cmdq, thread);
 269                 clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
 270         }
 271 }
 272
 273 static irqreturn_t cmdq_irq_handler(int irq, void *dev)
 274 {
 275         struct cmdq *cmdq = dev;
 276         unsigned long irq_status, flags = 0L;
 277         int bit;
 278
 279         irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
 280         if (!(irq_status ^ cmdq->irq_mask))
 281                 return IRQ_NONE;
 282
 283         for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
 284                 struct cmdq_thread *thread = &cmdq->thread[bit];
 285
 286                 spin_lock_irqsave(&thread->chan->lock, flags);
 287                 cmdq_thread_irq_handler(cmdq, thread);
 288                 spin_unlock_irqrestore(&thread->chan->lock, flags);
 289         }
 290
 291         return IRQ_HANDLED;
 292 }
 293
 294 static int cmdq_suspend(struct device *dev)
 295 {
 296         struct cmdq *cmdq = dev_get_drvdata(dev);
 297         struct cmdq_thread *thread;
 298         int i;
 299         bool task_running = false;
 300
 301         cmdq->suspended = true;
 302
 303         for (i = 0; i < cmdq->thread_nr; i++) {
 304                 thread = &cmdq->thread[i];
 305                 if (!list_empty(&thread->task_busy_list)) {
 306                         task_running = true;
 307                         break;
 308                 }
 309         }
 310
 311         if (task_running)
 312                 dev_warn(dev, "exist running task(s) in suspend\n");
 313
 314         clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 315
 316         return 0;
 317 }
 318
 319 static int cmdq_resume(struct device *dev)
 320 {
 321         struct cmdq *cmdq = dev_get_drvdata(dev);
 322
 323         WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
 324         cmdq->suspended = false;
 325         return 0;
 326 }
 327
 328 static int cmdq_remove(struct platform_device *pdev)
 329 {
 330         struct cmdq *cmdq = platform_get_drvdata(pdev);
 331
 332         clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 333         return 0;
 334 }
 335
 336 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 337 {
 338         struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
 339         struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
 340         struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
 341         struct cmdq_task *task;
 342         unsigned long curr_pa, end_pa;
 343
 344         /* Client should not flush new tasks if suspended. */
 345         WARN_ON(cmdq->suspended);
 346
 347         task = kzalloc(sizeof(*task), GFP_ATOMIC);
 348         if (!task)
 349                 return -ENOMEM;
 350
 351         task->cmdq = cmdq;
 352         INIT_LIST_HEAD(&task->list_entry);
 353         task->pa_base = pkt->pa_base;
 354         task->thread = thread;
 355         task->pkt = pkt;
 356
 357         if (list_empty(&thread->task_busy_list)) {
 358                 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 359
 360                 /*
 361                  * The thread reset will clear thread related register to 0,
 362                  * including pc, end, priority, irq, suspend and enable. Thus
 363                  * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
 364                  * thread and make it running.
 365                  */
 366                 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
 367
 368                 writel(task->pa_base >> cmdq->shift_pa,
 369                        thread->base + CMDQ_THR_CURR_ADDR);
 370                 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
 371                        thread->base + CMDQ_THR_END_ADDR);
 372
 373                 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
 374                 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
 375                 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
 376         } else {
 377                 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 378                 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
 379                         cmdq->shift_pa;
 380                 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
 381                         cmdq->shift_pa;
 382                 /* check boundary */
 383                 if (curr_pa == end_pa - CMDQ_INST_SIZE ||
 384                     curr_pa == end_pa) {
 385                         /* set to this task directly */
 386                         writel(task->pa_base >> cmdq->shift_pa,
 387                                thread->base + CMDQ_THR_CURR_ADDR);
 388                 } else {
 389                         cmdq_task_insert_into_thread(task);
 390                         smp_mb(); /* modify jump before enable thread */
 391                 }
 392                 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
 393                        thread->base + CMDQ_THR_END_ADDR);
 394                 cmdq_thread_resume(thread);
 395         }
 396         list_move_tail(&task->list_entry, &thread->task_busy_list);
 397
 398         return 0;
 399 }
 400
 401 static int cmdq_mbox_startup(struct mbox_chan *chan)
 402 {
 403         return 0;
 404 }
 405
 406 static void cmdq_mbox_shutdown(struct mbox_chan *chan)
 407 {
 408         struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
 409         struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
 410         struct cmdq_task *task, *tmp;
 411         unsigned long flags;
 412
 413         spin_lock_irqsave(&thread->chan->lock, flags);
 414         if (list_empty(&thread->task_busy_list))
 415                 goto done;
 416
 417         WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 418
 419         /* make sure executed tasks have success callback */
 420         cmdq_thread_irq_handler(cmdq, thread);
 421         if (list_empty(&thread->task_busy_list))
 422                 goto done;
 423
 424         list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 425                                  list_entry) {
 426                 cmdq_task_exec_done(task, -ECONNABORTED);
 427                 kfree(task);
 428         }
 429
 430         cmdq_thread_disable(cmdq, thread);
 431         clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
 432
 433 done:
 434         /*
 435          * The thread->task_busy_list empty means thread already disable. The
 436          * cmdq_mbox_send_data() always reset thread which clear disable and
 437          * suspend statue when first pkt send to channel, so there is no need
 438          * to do any operation here, only unlock and leave.
 439          */
 440         spin_unlock_irqrestore(&thread->chan->lock, flags);
 441 }
 442
 443 static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
 444 {
 445         struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
 446         struct cmdq_cb_data data;
 447         struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
 448         struct cmdq_task *task, *tmp;
 449         unsigned long flags;
 450         u32 enable;
 451
 452         spin_lock_irqsave(&thread->chan->lock, flags);
 453         if (list_empty(&thread->task_busy_list))
 454                 goto out;
 455
 456         WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 457         if (!cmdq_thread_is_in_wfe(thread))
 458                 goto wait;
 459
 460         list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 461                                  list_entry) {
 462                 data.sta = -ECONNABORTED;
 463                 data.pkt = task->pkt;
 464                 mbox_chan_received_data(task->thread->chan, &data);
 465                 list_del(&task->list_entry);
 466                 kfree(task);
 467         }
 468
 469         cmdq_thread_resume(thread);
 470         cmdq_thread_disable(cmdq, thread);
 471         clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
 472
 473 out:
 474         spin_unlock_irqrestore(&thread->chan->lock, flags);
 475         return 0;
 476
 477 wait:
 478         cmdq_thread_resume(thread);
 479         spin_unlock_irqrestore(&thread->chan->lock, flags);
 480         if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
 481                                       enable, enable == 0, 1, timeout)) {
 482                 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
 483                         (u32)(thread->base - cmdq->base));
 484
 485                 return -EFAULT;
 486         }
 487         return 0;
 488 }
 489
 490 static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
 491         .send_data = cmdq_mbox_send_data,
 492         .startup = cmdq_mbox_startup,
 493         .shutdown = cmdq_mbox_shutdown,
 494         .flush = cmdq_mbox_flush,
 495 };
 496
 497 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
 498                 const struct of_phandle_args *sp)
 499 {
 500         int ind = sp->args[0];
 501         struct cmdq_thread *thread;
 502
 503         if (ind >= mbox->num_chans)
 504                 return ERR_PTR(-EINVAL);
 505
 506         thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
 507         thread->priority = sp->args[1];
 508         thread->chan = &mbox->chans[ind];
 509
 510         return &mbox->chans[ind];
 511 }
 512
 513 static int cmdq_probe(struct platform_device *pdev)
 514 {
 515         struct device *dev = &pdev->dev;
 516         struct cmdq *cmdq;
 517         int err, i;
 518         struct gce_plat *plat_data;
 519         struct device_node *phandle = dev->of_node;
 520         struct device_node *node;
 521         int alias_id = 0;
 522         static const char * const clk_name = "gce";
 523         static const char * const clk_names[] = { "gce0", "gce1" };
 524
 525         cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
 526         if (!cmdq)
 527                 return -ENOMEM;
 528
 529         cmdq->base = devm_platform_ioremap_resource(pdev, 0);
 530         if (IS_ERR(cmdq->base))
 531                 return PTR_ERR(cmdq->base);
 532
 533         cmdq->irq = platform_get_irq(pdev, 0);
 534         if (cmdq->irq < 0)
 535                 return cmdq->irq;
 536
 537         plat_data = (struct gce_plat *)of_device_get_match_data(dev);
 538         if (!plat_data) {
 539                 dev_err(dev, "failed to get match data\n");
 540                 return -EINVAL;
 541         }
 542
 543         cmdq->thread_nr = plat_data->thread_nr;
 544         cmdq->shift_pa = plat_data->shift;
 545         cmdq->control_by_sw = plat_data->control_by_sw;
 546         cmdq->gce_num = plat_data->gce_num;
 547         cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
 548         err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
 549                                "mtk_cmdq", cmdq);
 550         if (err < 0) {
 551                 dev_err(dev, "failed to register ISR (%d)\n", err);
 552                 return err;
 553         }
 554
 555         dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
 556                 dev, cmdq->base, cmdq->irq);
 557
 558         if (cmdq->gce_num > 1) {
 559                 for_each_child_of_node(phandle->parent, node) {
 560                         alias_id = of_alias_get_id(node, clk_name);
 561                         if (alias_id >= 0 && alias_id < cmdq->gce_num) {
 562                                 cmdq->clocks[alias_id].id = clk_names[alias_id];
 563                                 cmdq->clocks[alias_id].clk = of_clk_get(node, 0);
 564                                 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
 565                                         of_node_put(node);
 566                                         return dev_err_probe(dev,
 567                                                              PTR_ERR(cmdq->clocks[alias_id].clk),
 568                                                              "failed to get gce clk: %d\n",
 569                                                              alias_id);
 570                                 }
 571                         }
 572                 }
 573         } else {
 574                 cmdq->clocks[alias_id].id = clk_name;
 575                 cmdq->clocks[alias_id].clk = devm_clk_get(&pdev->dev, clk_name);
 576                 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
 577                         return dev_err_probe(dev, PTR_ERR(cmdq->clocks[alias_id].clk),
 578                                              "failed to get gce clk\n");
 579                 }
 580         }
 581
 582         cmdq->mbox.dev = dev;
 583         cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
 584                                         sizeof(*cmdq->mbox.chans), GFP_KERNEL);
 585         if (!cmdq->mbox.chans)
 586                 return -ENOMEM;
 587
 588         cmdq->mbox.num_chans = cmdq->thread_nr;
 589         cmdq->mbox.ops = &cmdq_mbox_chan_ops;
 590         cmdq->mbox.of_xlate = cmdq_xlate;
 591
 592         /* make use of TXDONE_BY_ACK */
 593         cmdq->mbox.txdone_irq = false;
 594         cmdq->mbox.txdone_poll = false;
 595
 596         cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
 597                                         sizeof(*cmdq->thread), GFP_KERNEL);
 598         if (!cmdq->thread)
 599                 return -ENOMEM;
 600
 601         for (i = 0; i < cmdq->thread_nr; i++) {
 602                 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
 603                                 CMDQ_THR_SIZE * i;
 604                 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
 605                 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
 606         }
 607
 608         err = devm_mbox_controller_register(dev, &cmdq->mbox);
 609         if (err < 0) {
 610                 dev_err(dev, "failed to register mailbox: %d\n", err);
 611                 return err;
 612         }
 613
 614         platform_set_drvdata(pdev, cmdq);
 615
 616         WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
 617
 618         cmdq_init(cmdq);
 619
 620         return 0;
 621 }
 622
 623 static const struct dev_pm_ops cmdq_pm_ops = {
 624         .suspend = cmdq_suspend,
 625         .resume = cmdq_resume,
 626 };
 627
 628 static const struct gce_plat gce_plat_v2 = {
 629         .thread_nr = 16,
 630         .shift = 0,
 631         .control_by_sw = false,
 632         .gce_num = 1
 633 };
 634
 635 static const struct gce_plat gce_plat_v3 = {
 636         .thread_nr = 24,
 637         .shift = 0,
 638         .control_by_sw = false,
 639         .gce_num = 1
 640 };
 641
 642 static const struct gce_plat gce_plat_v4 = {
 643         .thread_nr = 24,
 644         .shift = 3,
 645         .control_by_sw = false,
 646         .gce_num = 1
 647 };
 648
 649 static const struct gce_plat gce_plat_v5 = {
 650         .thread_nr = 24,
 651         .shift = 3,
 652         .control_by_sw = true,
 653         .gce_num = 1
 654 };
 655
 656 static const struct gce_plat gce_plat_v6 = {
 657         .thread_nr = 24,
 658         .shift = 3,
 659         .control_by_sw = true,
 660         .gce_num = 2
 661 };
 662
 663 static const struct of_device_id cmdq_of_ids[] = {
 664         {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
 665         {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
 666         {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
 667         {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
 668         {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
 669         {}
 670 };
 671
 672 static struct platform_driver cmdq_drv = {
 673         .probe = cmdq_probe,
 674         .remove = cmdq_remove,
 675         .driver = {
 676                 .name = "mtk_cmdq",
 677                 .pm = &cmdq_pm_ops,
 678                 .of_match_table = cmdq_of_ids,
 679         }
 680 };
 681
 682 static int __init cmdq_drv_init(void)
 683 {
 684         return platform_driver_register(&cmdq_drv);
 685 }
 686
 687 static void __exit cmdq_drv_exit(void)
 688 {
 689         platform_driver_unregister(&cmdq_drv);
 690 }
 691
 692 subsys_initcall(cmdq_drv_init);
 693 module_exit(cmdq_drv_exit);
 694
 695 MODULE_LICENSE("GPL v2");