drivers/isdn/hisax/hfc4s8s_l1.c

   1 /*************************************************************************/
   2 /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $           */
   3 /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips   */
   4 /* The low layer (L1) is implemented as a loadable module for usage with */
   5 /* the HiSax isdn driver for passive cards.                              */
   6 /*                                                                       */
   7 /* Author: Werner Cornelius                                              */
   8 /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de)              */
   9 /*                                                                       */
  10 /* Driver maintained by Cologne Chip                                     */
  11 /*   - Martin Bachem, support@colognechip.com                            */
  12 /*                                                                       */
  13 /* This driver only works with chip revisions >= 1, older revision 0     */
  14 /* engineering samples (only first manufacturer sample cards) will not   */
  15 /* work and are rejected by the driver.                                  */
  16 /*                                                                       */
  17 /* This file distributed under the GNU GPL.                              */
  18 /*                                                                       */
  19 /* See Version History at the end of this file                           */
  20 /*                                                                       */
  21 /*************************************************************************/
  22
  23 #include <linux/module.h>
  24 #include <linux/init.h>
  25 #include <linux/pci.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/delay.h>
  28 #include <linux/slab.h>
  29 #include <linux/timer.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/wait.h>
  32 #include <asm/io.h>
  33 #include "hisax_if.h"
  34 #include "hfc4s8s_l1.h"
  35
  36 static const char hfc4s8s_rev[] = "Revision: 1.10";
  37
  38 /***************************************************************/
  39 /* adjustable transparent mode fifo threshold                  */
  40 /* The value defines the used fifo threshold with the equation */
  41 /*                                                             */
  42 /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES           */
  43 /*                                                             */
  44 /* The default value is 5 which results in a buffer size of 64 */
  45 /* and an interrupt rate of 8ms.                               */
  46 /* The maximum value is 7 due to fifo size restrictions.       */
  47 /* Values below 3-4 are not recommended due to high interrupt  */
  48 /* load of the processor. For non critical applications the    */
  49 /* value should be raised to 7 to reduce any interrupt overhead*/
  50 /***************************************************************/
  51 #define TRANS_FIFO_THRES 5
  52
  53 /*************/
  54 /* constants */
  55 /*************/
  56 #define CLOCKMODE_0     0       /* ext. 24.576 MhZ clk freq, int. single clock mode */
  57 #define CLOCKMODE_1     1       /* ext. 49.576 MhZ clk freq, int. single clock mode */
  58 #define CHIP_ID_SHIFT   4
  59 #define HFC_MAX_ST 8
  60 #define MAX_D_FRAME_SIZE 270
  61 #define MAX_B_FRAME_SIZE 1536
  62 #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf)
  63 #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES)
  64 #define MAX_F_CNT 0x0f
  65
  66 #define CLKDEL_NT 0x6c
  67 #define CLKDEL_TE 0xf
  68 #define CTRL0_NT  4
  69 #define CTRL0_TE  0
  70
  71 #define L1_TIMER_T4 2           /* minimum in jiffies */
  72 #define L1_TIMER_T3 (7 * HZ)    /* activation timeout */
  73 #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */
  74
  75
  76 /******************/
  77 /* types and vars */
  78 /******************/
  79 static int card_cnt;
  80
  81 /* private driver_data */
  82 typedef struct {
  83         int chip_id;
  84         int clock_mode;
  85         int max_st_ports;
  86         char *device_name;
  87 } hfc4s8s_param;
  88
  89 static const struct pci_device_id hfc4s8s_ids[] = {
  90         {.vendor = PCI_VENDOR_ID_CCD,
  91          .device = PCI_DEVICE_ID_4S,
  92          .subvendor = 0x1397,
  93          .subdevice = 0x08b4,
  94          .driver_data =
  95          (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4,
  96                                  "HFC-4S Evaluation Board"}),
  97         },
  98         {.vendor = PCI_VENDOR_ID_CCD,
  99          .device = PCI_DEVICE_ID_8S,
 100          .subvendor = 0x1397,
 101          .subdevice = 0x16b8,
 102          .driver_data =
 103          (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8,
 104                                  "HFC-8S Evaluation Board"}),
 105         },
 106         {.vendor = PCI_VENDOR_ID_CCD,
 107          .device = PCI_DEVICE_ID_4S,
 108          .subvendor = 0x1397,
 109          .subdevice = 0xb520,
 110          .driver_data =
 111          (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4,
 112                                  "IOB4ST"}),
 113         },
 114         {.vendor = PCI_VENDOR_ID_CCD,
 115          .device = PCI_DEVICE_ID_8S,
 116          .subvendor = 0x1397,
 117          .subdevice = 0xb522,
 118          .driver_data =
 119          (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8,
 120                                  "IOB8ST"}),
 121         },
 122         {}
 123 };
 124
 125 MODULE_DEVICE_TABLE(pci, hfc4s8s_ids);
 126
 127 MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de");
 128 MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips");
 129 MODULE_LICENSE("GPL");
 130
 131 /***********/
 132 /* layer 1 */
 133 /***********/
 134 struct hfc4s8s_btype {
 135         spinlock_t lock;
 136         struct hisax_b_if b_if;
 137         struct hfc4s8s_l1 *l1p;
 138         struct sk_buff_head tx_queue;
 139         struct sk_buff *tx_skb;
 140         struct sk_buff *rx_skb;
 141         __u8 *rx_ptr;
 142         int tx_cnt;
 143         int bchan;
 144         int mode;
 145 };
 146
 147 struct _hfc4s8s_hw;
 148
 149 struct hfc4s8s_l1 {
 150         spinlock_t lock;
 151         struct _hfc4s8s_hw *hw; /* pointer to hardware area */
 152         int l1_state;           /* actual l1 state */
 153         struct timer_list l1_timer;     /* layer 1 timer structure */
 154         int nt_mode;            /* set to nt mode */
 155         int st_num;             /* own index */
 156         int enabled;            /* interface is enabled */
 157         struct sk_buff_head d_tx_queue; /* send queue */
 158         int tx_cnt;             /* bytes to send */
 159         struct hisax_d_if d_if; /* D-channel interface */
 160         struct hfc4s8s_btype b_ch[2];   /* B-channel data */
 161         struct hisax_b_if *b_table[2];
 162 };
 163
 164 /**********************/
 165 /* hardware structure */
 166 /**********************/
 167 typedef struct _hfc4s8s_hw {
 168         spinlock_t lock;
 169
 170         int cardnum;
 171         int ifnum;
 172         int iobase;
 173         int nt_mode;
 174         u_char *membase;
 175         u_char *hw_membase;
 176         void *pdev;
 177         int max_fifo;
 178         hfc4s8s_param driver_data;
 179         int irq;
 180         int fifo_sched_cnt;
 181         struct work_struct tqueue;
 182         struct hfc4s8s_l1 l1[HFC_MAX_ST];
 183         char card_name[60];
 184         struct {
 185                 u_char r_irq_ctrl;
 186                 u_char r_ctrl0;
 187                 volatile u_char r_irq_statech;  /* active isdn l1 status */
 188                 u_char r_irqmsk_statchg;        /* enabled isdn status ints */
 189                 u_char r_irq_fifo_blx[8];       /* fifo status registers */
 190                 u_char fifo_rx_trans_enables[8];        /* mask for enabled transparent rx fifos */
 191                 u_char fifo_slow_timer_service[8];      /* mask for fifos needing slower timer service */
 192                 volatile u_char r_irq_oview;    /* contents of overview register */
 193                 volatile u_char timer_irq;
 194                 int timer_usg_cnt;      /* number of channels using timer */
 195         } mr;
 196 } hfc4s8s_hw;
 197
 198
 199
 200 /* inline functions io mapped */
 201 static inline void
 202 SetRegAddr(hfc4s8s_hw *a, u_char b)
 203 {
 204         outb(b, (a->iobase) + 4);
 205 }
 206
 207 static inline u_char
 208 GetRegAddr(hfc4s8s_hw *a)
 209 {
 210         return (inb((volatile u_int) (a->iobase + 4)));
 211 }
 212
 213
 214 static inline void
 215 Write_hfc8(hfc4s8s_hw *a, u_char b, u_char c)
 216 {
 217         SetRegAddr(a, b);
 218         outb(c, a->iobase);
 219 }
 220
 221 static inline void
 222 fWrite_hfc8(hfc4s8s_hw *a, u_char c)
 223 {
 224         outb(c, a->iobase);
 225 }
 226
 227 static inline void
 228 fWrite_hfc32(hfc4s8s_hw *a, u_long c)
 229 {
 230         outl(c, a->iobase);
 231 }
 232
 233 static inline u_char
 234 Read_hfc8(hfc4s8s_hw *a, u_char b)
 235 {
 236         SetRegAddr(a, b);
 237         return (inb((volatile u_int) a->iobase));
 238 }
 239
 240 static inline u_char
 241 fRead_hfc8(hfc4s8s_hw *a)
 242 {
 243         return (inb((volatile u_int) a->iobase));
 244 }
 245
 246
 247 static inline u_short
 248 Read_hfc16(hfc4s8s_hw *a, u_char b)
 249 {
 250         SetRegAddr(a, b);
 251         return (inw((volatile u_int) a->iobase));
 252 }
 253
 254 static inline u_long
 255 fRead_hfc32(hfc4s8s_hw *a)
 256 {
 257         return (inl((volatile u_int) a->iobase));
 258 }
 259
 260 static inline void
 261 wait_busy(hfc4s8s_hw *a)
 262 {
 263         SetRegAddr(a, R_STATUS);
 264         while (inb((volatile u_int) a->iobase) & M_BUSY);
 265 }
 266
 267 #define PCI_ENA_REGIO   0x01
 268
 269 /******************************************************/
 270 /* function to read critical counter registers that   */
 271 /* may be updated by the chip during read             */
 272 /******************************************************/
 273 static u_char
 274 Read_hfc8_stable(hfc4s8s_hw *hw, int reg)
 275 {
 276         u_char ref8;
 277         u_char in8;
 278         ref8 = Read_hfc8(hw, reg);
 279         while (((in8 = Read_hfc8(hw, reg)) != ref8)) {
 280                 ref8 = in8;
 281         }
 282         return in8;
 283 }
 284
 285 static int
 286 Read_hfc16_stable(hfc4s8s_hw *hw, int reg)
 287 {
 288         int ref16;
 289         int in16;
 290
 291         ref16 = Read_hfc16(hw, reg);
 292         while (((in16 = Read_hfc16(hw, reg)) != ref16)) {
 293                 ref16 = in16;
 294         }
 295         return in16;
 296 }
 297
 298 /*****************************/
 299 /* D-channel call from HiSax */
 300 /*****************************/
 301 static void
 302 dch_l2l1(struct hisax_d_if *iface, int pr, void *arg)
 303 {
 304         struct hfc4s8s_l1 *l1 = iface->ifc.priv;
 305         struct sk_buff *skb = (struct sk_buff *) arg;
 306         u_long flags;
 307
 308         switch (pr) {
 309
 310         case (PH_DATA | REQUEST):
 311                 if (!l1->enabled) {
 312                         dev_kfree_skb(skb);
 313                         break;
 314                 }
 315                 spin_lock_irqsave(&l1->lock, flags);
 316                 skb_queue_tail(&l1->d_tx_queue, skb);
 317                 if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
 318                     (l1->tx_cnt <= 0)) {
 319                         l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
 320                                 0x10;
 321                         spin_unlock_irqrestore(&l1->lock, flags);
 322                         schedule_work(&l1->hw->tqueue);
 323                 } else
 324                         spin_unlock_irqrestore(&l1->lock, flags);
 325                 break;
 326
 327         case (PH_ACTIVATE | REQUEST):
 328                 if (!l1->enabled)
 329                         break;
 330                 if (!l1->nt_mode) {
 331                         if (l1->l1_state < 6) {
 332                                 spin_lock_irqsave(&l1->lock,
 333                                                   flags);
 334
 335                                 Write_hfc8(l1->hw, R_ST_SEL,
 336                                            l1->st_num);
 337                                 Write_hfc8(l1->hw, A_ST_WR_STA,
 338                                            0x60);
 339                                 mod_timer(&l1->l1_timer,
 340                                           jiffies + L1_TIMER_T3);
 341                                 spin_unlock_irqrestore(&l1->lock,
 342                                                        flags);
 343                         } else if (l1->l1_state == 7)
 344                                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 345                                                   PH_ACTIVATE |
 346                                                   INDICATION,
 347                                                   NULL);
 348                 } else {
 349                         if (l1->l1_state != 3) {
 350                                 spin_lock_irqsave(&l1->lock,
 351                                                   flags);
 352                                 Write_hfc8(l1->hw, R_ST_SEL,
 353                                            l1->st_num);
 354                                 Write_hfc8(l1->hw, A_ST_WR_STA,
 355                                            0x60);
 356                                 spin_unlock_irqrestore(&l1->lock,
 357                                                        flags);
 358                         } else if (l1->l1_state == 3)
 359                                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 360                                                   PH_ACTIVATE |
 361                                                   INDICATION,
 362                                                   NULL);
 363                 }
 364                 break;
 365
 366         default:
 367                 printk(KERN_INFO
 368                        "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
 369                        pr);
 370                 break;
 371         }
 372         if (!l1->enabled)
 373                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 374                                   PH_DEACTIVATE | INDICATION, NULL);
 375 }                               /* dch_l2l1 */
 376
 377 /*****************************/
 378 /* B-channel call from HiSax */
 379 /*****************************/
 380 static void
 381 bch_l2l1(struct hisax_if *ifc, int pr, void *arg)
 382 {
 383         struct hfc4s8s_btype *bch = ifc->priv;
 384         struct hfc4s8s_l1 *l1 = bch->l1p;
 385         struct sk_buff *skb = (struct sk_buff *) arg;
 386         long mode = (long) arg;
 387         u_long flags;
 388
 389         switch (pr) {
 390
 391         case (PH_DATA | REQUEST):
 392                 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
 393                         dev_kfree_skb(skb);
 394                         break;
 395                 }
 396                 spin_lock_irqsave(&l1->lock, flags);
 397                 skb_queue_tail(&bch->tx_queue, skb);
 398                 if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
 399                         l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
 400                                 ((bch->bchan == 1) ? 1 : 4);
 401                         spin_unlock_irqrestore(&l1->lock, flags);
 402                         schedule_work(&l1->hw->tqueue);
 403                 } else
 404                         spin_unlock_irqrestore(&l1->lock, flags);
 405                 break;
 406
 407         case (PH_ACTIVATE | REQUEST):
 408         case (PH_DEACTIVATE | REQUEST):
 409                 if (!l1->enabled)
 410                         break;
 411                 if (pr == (PH_DEACTIVATE | REQUEST))
 412                         mode = L1_MODE_NULL;
 413
 414                 switch (mode) {
 415                 case L1_MODE_HDLC:
 416                         spin_lock_irqsave(&l1->lock,
 417                                           flags);
 418                         l1->hw->mr.timer_usg_cnt++;
 419                         l1->hw->mr.
 420                                 fifo_slow_timer_service[l1->
 421                                                         st_num]
 422                                 |=
 423                                 ((bch->bchan ==
 424                                   1) ? 0x2 : 0x8);
 425                         Write_hfc8(l1->hw, R_FIFO,
 426                                    (l1->st_num * 8 +
 427                                     ((bch->bchan ==
 428                                       1) ? 0 : 2)));
 429                         wait_busy(l1->hw);
 430                         Write_hfc8(l1->hw, A_CON_HDLC, 0xc);    /* HDLC mode, flag fill, connect ST */
 431                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 432                         Write_hfc8(l1->hw, A_IRQ_MSK, 1);       /* enable TX interrupts for hdlc */
 433                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 434                         wait_busy(l1->hw);
 435
 436                         Write_hfc8(l1->hw, R_FIFO,
 437                                    (l1->st_num * 8 +
 438                                     ((bch->bchan ==
 439                                       1) ? 1 : 3)));
 440                         wait_busy(l1->hw);
 441                         Write_hfc8(l1->hw, A_CON_HDLC, 0xc);    /* HDLC mode, flag fill, connect ST */
 442                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 443                         Write_hfc8(l1->hw, A_IRQ_MSK, 1);       /* enable RX interrupts for hdlc */
 444                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 445
 446                         Write_hfc8(l1->hw, R_ST_SEL,
 447                                    l1->st_num);
 448                         l1->hw->mr.r_ctrl0 |=
 449                                 (bch->bchan & 3);
 450                         Write_hfc8(l1->hw, A_ST_CTRL0,
 451                                    l1->hw->mr.r_ctrl0);
 452                         bch->mode = L1_MODE_HDLC;
 453                         spin_unlock_irqrestore(&l1->lock,
 454                                                flags);
 455
 456                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 457                                            PH_ACTIVATE |
 458                                            INDICATION,
 459                                            NULL);
 460                         break;
 461
 462                 case L1_MODE_TRANS:
 463                         spin_lock_irqsave(&l1->lock,
 464                                           flags);
 465                         l1->hw->mr.
 466                                 fifo_rx_trans_enables[l1->
 467                                                       st_num]
 468                                 |=
 469                                 ((bch->bchan ==
 470                                   1) ? 0x2 : 0x8);
 471                         l1->hw->mr.timer_usg_cnt++;
 472                         Write_hfc8(l1->hw, R_FIFO,
 473                                    (l1->st_num * 8 +
 474                                     ((bch->bchan ==
 475                                       1) ? 0 : 2)));
 476                         wait_busy(l1->hw);
 477                         Write_hfc8(l1->hw, A_CON_HDLC, 0xf);    /* Transparent mode, 1 fill, connect ST */
 478                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 479                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable TX interrupts */
 480                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 481                         wait_busy(l1->hw);
 482
 483                         Write_hfc8(l1->hw, R_FIFO,
 484                                    (l1->st_num * 8 +
 485                                     ((bch->bchan ==
 486                                       1) ? 1 : 3)));
 487                         wait_busy(l1->hw);
 488                         Write_hfc8(l1->hw, A_CON_HDLC, 0xf);    /* Transparent mode, 1 fill, connect ST */
 489                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 490                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable RX interrupts */
 491                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 492
 493                         Write_hfc8(l1->hw, R_ST_SEL,
 494                                    l1->st_num);
 495                         l1->hw->mr.r_ctrl0 |=
 496                                 (bch->bchan & 3);
 497                         Write_hfc8(l1->hw, A_ST_CTRL0,
 498                                    l1->hw->mr.r_ctrl0);
 499                         bch->mode = L1_MODE_TRANS;
 500                         spin_unlock_irqrestore(&l1->lock,
 501                                                flags);
 502
 503                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 504                                            PH_ACTIVATE |
 505                                            INDICATION,
 506                                            NULL);
 507                         break;
 508
 509                 default:
 510                         if (bch->mode == L1_MODE_NULL)
 511                                 break;
 512                         spin_lock_irqsave(&l1->lock,
 513                                           flags);
 514                         l1->hw->mr.
 515                                 fifo_slow_timer_service[l1->
 516                                                         st_num]
 517                                 &=
 518                                 ~((bch->bchan ==
 519                                    1) ? 0x3 : 0xc);
 520                         l1->hw->mr.
 521                                 fifo_rx_trans_enables[l1->
 522                                                       st_num]
 523                                 &=
 524                                 ~((bch->bchan ==
 525                                    1) ? 0x3 : 0xc);
 526                         l1->hw->mr.timer_usg_cnt--;
 527                         Write_hfc8(l1->hw, R_FIFO,
 528                                    (l1->st_num * 8 +
 529                                     ((bch->bchan ==
 530                                       1) ? 0 : 2)));
 531                         wait_busy(l1->hw);
 532                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable TX interrupts */
 533                         wait_busy(l1->hw);
 534                         Write_hfc8(l1->hw, R_FIFO,
 535                                    (l1->st_num * 8 +
 536                                     ((bch->bchan ==
 537                                       1) ? 1 : 3)));
 538                         wait_busy(l1->hw);
 539                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable RX interrupts */
 540                         Write_hfc8(l1->hw, R_ST_SEL,
 541                                    l1->st_num);
 542                         l1->hw->mr.r_ctrl0 &=
 543                                 ~(bch->bchan & 3);
 544                         Write_hfc8(l1->hw, A_ST_CTRL0,
 545                                    l1->hw->mr.r_ctrl0);
 546                         spin_unlock_irqrestore(&l1->lock,
 547                                                flags);
 548
 549                         bch->mode = L1_MODE_NULL;
 550                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 551                                            PH_DEACTIVATE |
 552                                            INDICATION,
 553                                            NULL);
 554                         if (bch->tx_skb) {
 555                                 dev_kfree_skb(bch->tx_skb);
 556                                 bch->tx_skb = NULL;
 557                         }
 558                         if (bch->rx_skb) {
 559                                 dev_kfree_skb(bch->rx_skb);
 560                                 bch->rx_skb = NULL;
 561                         }
 562                         skb_queue_purge(&bch->tx_queue);
 563                         bch->tx_cnt = 0;
 564                         bch->rx_ptr = NULL;
 565                         break;
 566                 }
 567
 568                 /* timer is only used when at least one b channel */
 569                 /* is set up to transparent mode */
 570                 if (l1->hw->mr.timer_usg_cnt) {
 571                         Write_hfc8(l1->hw, R_IRQMSK_MISC,
 572                                    M_TI_IRQMSK);
 573                 } else {
 574                         Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
 575                 }
 576
 577                 break;
 578
 579         default:
 580                 printk(KERN_INFO
 581                        "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
 582                        pr);
 583                 break;
 584         }
 585         if (!l1->enabled)
 586                 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 587                                    PH_DEACTIVATE | INDICATION, NULL);
 588 }                               /* bch_l2l1 */
 589
 590 /**************************/
 591 /* layer 1 timer function */
 592 /**************************/
 593 static void
 594 hfc_l1_timer(struct timer_list *t)
 595 {
 596         struct hfc4s8s_l1 *l1 = from_timer(l1, t, l1_timer);
 597         u_long flags;
 598
 599         if (!l1->enabled)
 600                 return;
 601
 602         spin_lock_irqsave(&l1->lock, flags);
 603         if (l1->nt_mode) {
 604                 l1->l1_state = 1;
 605                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 606                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11);
 607                 spin_unlock_irqrestore(&l1->lock, flags);
 608                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 609                                   PH_DEACTIVATE | INDICATION, NULL);
 610                 spin_lock_irqsave(&l1->lock, flags);
 611                 l1->l1_state = 1;
 612                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1);
 613                 spin_unlock_irqrestore(&l1->lock, flags);
 614         } else {
 615                 /* activation timed out */
 616                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 617                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13);
 618                 spin_unlock_irqrestore(&l1->lock, flags);
 619                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 620                                   PH_DEACTIVATE | INDICATION, NULL);
 621                 spin_lock_irqsave(&l1->lock, flags);
 622                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 623                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3);
 624                 spin_unlock_irqrestore(&l1->lock, flags);
 625         }
 626 }                               /* hfc_l1_timer */
 627
 628 /****************************************/
 629 /* a complete D-frame has been received */
 630 /****************************************/
 631 static void
 632 rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
 633 {
 634         int z1, z2;
 635         u_char f1, f2, df;
 636         struct sk_buff *skb;
 637         u_char *cp;
 638
 639
 640         if (!l1p->enabled)
 641                 return;
 642         do {
 643                 /* E/D RX fifo */
 644                 Write_hfc8(l1p->hw, R_FIFO,
 645                            (l1p->st_num * 8 + ((ech) ? 7 : 5)));
 646                 wait_busy(l1p->hw);
 647
 648                 f1 = Read_hfc8_stable(l1p->hw, A_F1);
 649                 f2 = Read_hfc8(l1p->hw, A_F2);
 650
 651                 if (f1 < f2)
 652                         df = MAX_F_CNT + 1 + f1 - f2;
 653                 else
 654                         df = f1 - f2;
 655
 656                 if (!df)
 657                         return; /* no complete frame in fifo */
 658
 659                 z1 = Read_hfc16_stable(l1p->hw, A_Z1);
 660                 z2 = Read_hfc16(l1p->hw, A_Z2);
 661
 662                 z1 = z1 - z2 + 1;
 663                 if (z1 < 0)
 664                         z1 += 384;
 665
 666                 if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) {
 667                         printk(KERN_INFO
 668                                "HFC-4S/8S: Could not allocate D/E "
 669                                "channel receive buffer");
 670                         Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
 671                         wait_busy(l1p->hw);
 672                         return;
 673                 }
 674
 675                 if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) {
 676                         if (skb)
 677                                 dev_kfree_skb(skb);
 678                         /* remove errornous D frame */
 679                         if (df == 1) {
 680                                 /* reset fifo */
 681                                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
 682                                 wait_busy(l1p->hw);
 683                                 return;
 684                         } else {
 685                                 /* read errornous D frame */
 686                                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 687
 688                                 while (z1 >= 4) {
 689                                         fRead_hfc32(l1p->hw);
 690                                         z1 -= 4;
 691                                 }
 692
 693                                 while (z1--)
 694                                         fRead_hfc8(l1p->hw);
 695
 696                                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
 697                                 wait_busy(l1p->hw);
 698                                 return;
 699                         }
 700                 }
 701
 702                 cp = skb->data;
 703
 704                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 705
 706                 while (z1 >= 4) {
 707                         *((unsigned long *) cp) = fRead_hfc32(l1p->hw);
 708                         cp += 4;
 709                         z1 -= 4;
 710                 }
 711
 712                 while (z1--)
 713                         *cp++ = fRead_hfc8(l1p->hw);
 714
 715                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
 716                 wait_busy(l1p->hw);
 717
 718                 if (*(--cp)) {
 719                         dev_kfree_skb(skb);
 720                 } else {
 721                         skb->len = (cp - skb->data) - 2;
 722                         if (ech)
 723                                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
 724                                                    PH_DATA_E | INDICATION,
 725                                                    skb);
 726                         else
 727                                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
 728                                                    PH_DATA | INDICATION,
 729                                                    skb);
 730                 }
 731         } while (1);
 732 }                               /* rx_d_frame */
 733
 734 /*************************************************************/
 735 /* a B-frame has been received (perhaps not fully completed) */
 736 /*************************************************************/
 737 static void
 738 rx_b_frame(struct hfc4s8s_btype *bch)
 739 {
 740         int z1, z2, hdlc_complete;
 741         u_char f1, f2;
 742         struct hfc4s8s_l1 *l1 = bch->l1p;
 743         struct sk_buff *skb;
 744
 745         if (!l1->enabled || (bch->mode == L1_MODE_NULL))
 746                 return;
 747
 748         do {
 749                 /* RX Fifo */
 750                 Write_hfc8(l1->hw, R_FIFO,
 751                            (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3)));
 752                 wait_busy(l1->hw);
 753
 754                 if (bch->mode == L1_MODE_HDLC) {
 755                         f1 = Read_hfc8_stable(l1->hw, A_F1);
 756                         f2 = Read_hfc8(l1->hw, A_F2);
 757                         hdlc_complete = ((f1 ^ f2) & MAX_F_CNT);
 758                 } else
 759                         hdlc_complete = 0;
 760                 z1 = Read_hfc16_stable(l1->hw, A_Z1);
 761                 z2 = Read_hfc16(l1->hw, A_Z2);
 762                 z1 = (z1 - z2);
 763                 if (hdlc_complete)
 764                         z1++;
 765                 if (z1 < 0)
 766                         z1 += 384;
 767
 768                 if (!z1)
 769                         break;
 770
 771                 if (!(skb = bch->rx_skb)) {
 772                         if (!
 773                             (skb =
 774                              dev_alloc_skb((bch->mode ==
 775                                             L1_MODE_TRANS) ? z1
 776                                            : (MAX_B_FRAME_SIZE + 3)))) {
 777                                 printk(KERN_ERR
 778                                        "HFC-4S/8S: Could not allocate B "
 779                                        "channel receive buffer");
 780                                 return;
 781                         }
 782                         bch->rx_ptr = skb->data;
 783                         bch->rx_skb = skb;
 784                 }
 785
 786                 skb->len = (bch->rx_ptr - skb->data) + z1;
 787
 788                 /* HDLC length check */
 789                 if ((bch->mode == L1_MODE_HDLC) &&
 790                     ((hdlc_complete && (skb->len < 4)) ||
 791                      (skb->len > (MAX_B_FRAME_SIZE + 3)))) {
 792
 793                         skb->len = 0;
 794                         bch->rx_ptr = skb->data;
 795                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 796                         wait_busy(l1->hw);
 797                         return;
 798                 }
 799                 SetRegAddr(l1->hw, A_FIFO_DATA0);
 800
 801                 while (z1 >= 4) {
 802                         *((unsigned long *) bch->rx_ptr) =
 803                                 fRead_hfc32(l1->hw);
 804                         bch->rx_ptr += 4;
 805                         z1 -= 4;
 806                 }
 807
 808                 while (z1--)
 809                         *(bch->rx_ptr++) = fRead_hfc8(l1->hw);
 810
 811                 if (hdlc_complete) {
 812                         /* increment f counter */
 813                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
 814                         wait_busy(l1->hw);
 815
 816                         /* hdlc crc check */
 817                         bch->rx_ptr--;
 818                         if (*bch->rx_ptr) {
 819                                 skb->len = 0;
 820                                 bch->rx_ptr = skb->data;
 821                                 continue;
 822                         }
 823                         skb->len -= 3;
 824                 }
 825                 if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) {
 826                         bch->rx_skb = NULL;
 827                         bch->rx_ptr = NULL;
 828                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 829                                            PH_DATA | INDICATION, skb);
 830                 }
 831
 832         } while (1);
 833 }                               /* rx_b_frame */
 834
 835 /********************************************/
 836 /* a D-frame has been/should be transmitted */
 837 /********************************************/
 838 static void
 839 tx_d_frame(struct hfc4s8s_l1 *l1p)
 840 {
 841         struct sk_buff *skb;
 842         u_char f1, f2;
 843         u_char *cp;
 844         long cnt;
 845
 846         if (l1p->l1_state != 7)
 847                 return;
 848
 849         /* TX fifo */
 850         Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4));
 851         wait_busy(l1p->hw);
 852
 853         f1 = Read_hfc8(l1p->hw, A_F1);
 854         f2 = Read_hfc8_stable(l1p->hw, A_F2);
 855
 856         if ((f1 ^ f2) & MAX_F_CNT)
 857                 return;         /* fifo is still filled */
 858
 859         if (l1p->tx_cnt > 0) {
 860                 cnt = l1p->tx_cnt;
 861                 l1p->tx_cnt = 0;
 862                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM,
 863                                    (void *) cnt);
 864         }
 865
 866         if ((skb = skb_dequeue(&l1p->d_tx_queue))) {
 867                 cp = skb->data;
 868                 cnt = skb->len;
 869                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 870
 871                 while (cnt >= 4) {
 872                         SetRegAddr(l1p->hw, A_FIFO_DATA0);
 873                         fWrite_hfc32(l1p->hw, *(unsigned long *) cp);
 874                         cp += 4;
 875                         cnt -= 4;
 876                 }
 877
 878                 while (cnt--)
 879                         fWrite_hfc8(l1p->hw, *cp++);
 880
 881                 l1p->tx_cnt = skb->truesize;
 882                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
 883                 wait_busy(l1p->hw);
 884
 885                 dev_kfree_skb(skb);
 886         }
 887 }                               /* tx_d_frame */
 888
 889 /******************************************************/
 890 /* a B-frame may be transmitted (or is not completed) */
 891 /******************************************************/
 892 static void
 893 tx_b_frame(struct hfc4s8s_btype *bch)
 894 {
 895         struct sk_buff *skb;
 896         struct hfc4s8s_l1 *l1 = bch->l1p;
 897         u_char *cp;
 898         int cnt, max, hdlc_num;
 899         long ack_len = 0;
 900
 901         if (!l1->enabled || (bch->mode == L1_MODE_NULL))
 902                 return;
 903
 904         /* TX fifo */
 905         Write_hfc8(l1->hw, R_FIFO,
 906                    (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2)));
 907         wait_busy(l1->hw);
 908         do {
 909
 910                 if (bch->mode == L1_MODE_HDLC) {
 911                         hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
 912                         hdlc_num -=
 913                                 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
 914                         if (hdlc_num < 0)
 915                                 hdlc_num += 16;
 916                         if (hdlc_num >= 15)
 917                                 break;  /* fifo still filled up with hdlc frames */
 918                 } else
 919                         hdlc_num = 0;
 920
 921                 if (!(skb = bch->tx_skb)) {
 922                         if (!(skb = skb_dequeue(&bch->tx_queue))) {
 923                                 l1->hw->mr.fifo_slow_timer_service[l1->
 924                                                                    st_num]
 925                                         &= ~((bch->bchan == 1) ? 1 : 4);
 926                                 break;  /* list empty */
 927                         }
 928                         bch->tx_skb = skb;
 929                         bch->tx_cnt = 0;
 930                 }
 931
 932                 if (!hdlc_num)
 933                         l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
 934                                 ((bch->bchan == 1) ? 1 : 4);
 935                 else
 936                         l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
 937                                 ~((bch->bchan == 1) ? 1 : 4);
 938
 939                 max = Read_hfc16_stable(l1->hw, A_Z2);
 940                 max -= Read_hfc16(l1->hw, A_Z1);
 941                 if (max <= 0)
 942                         max += 384;
 943                 max--;
 944
 945                 if (max < 16)
 946                         break;  /* don't write to small amounts of bytes */
 947
 948                 cnt = skb->len - bch->tx_cnt;
 949                 if (cnt > max)
 950                         cnt = max;
 951                 cp = skb->data + bch->tx_cnt;
 952                 bch->tx_cnt += cnt;
 953
 954                 SetRegAddr(l1->hw, A_FIFO_DATA0);
 955                 while (cnt >= 4) {
 956                         fWrite_hfc32(l1->hw, *(unsigned long *) cp);
 957                         cp += 4;
 958                         cnt -= 4;
 959                 }
 960
 961                 while (cnt--)
 962                         fWrite_hfc8(l1->hw, *cp++);
 963
 964                 if (bch->tx_cnt >= skb->len) {
 965                         if (bch->mode == L1_MODE_HDLC) {
 966                                 /* increment f counter */
 967                                 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
 968                         }
 969                         ack_len += skb->truesize;
 970                         bch->tx_skb = NULL;
 971                         bch->tx_cnt = 0;
 972                         dev_kfree_skb(skb);
 973                 } else
 974                         /* Re-Select */
 975                         Write_hfc8(l1->hw, R_FIFO,
 976                                    (l1->st_num * 8 +
 977                                     ((bch->bchan == 1) ? 0 : 2)));
 978                 wait_busy(l1->hw);
 979         } while (1);
 980
 981         if (ack_len)
 982                 bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if,
 983                                    PH_DATA | CONFIRM, (void *) ack_len);
 984 }                               /* tx_b_frame */
 985
 986 /*************************************/
 987 /* bottom half handler for interrupt */
 988 /*************************************/
 989 static void
 990 hfc4s8s_bh(struct work_struct *work)
 991 {
 992         hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue);
 993         u_char b;
 994         struct hfc4s8s_l1 *l1p;
 995         volatile u_char *fifo_stat;
 996         int idx;
 997
 998         /* handle layer 1 state changes */
 999         b = 1;
1000         l1p = hw->l1;
1001         while (b) {
1002                 if ((b & hw->mr.r_irq_statech)) {
1003                         /* reset l1 event */
1004                         hw->mr.r_irq_statech &= ~b;
1005                         if (l1p->enabled) {
1006                                 if (l1p->nt_mode) {
1007                                         u_char oldstate = l1p->l1_state;
1008
1009                                         Write_hfc8(l1p->hw, R_ST_SEL,
1010                                                    l1p->st_num);
1011                                         l1p->l1_state =
1012                                                 Read_hfc8(l1p->hw,
1013                                                           A_ST_RD_STA) & 0xf;
1014
1015                                         if ((oldstate == 3)
1016                                             && (l1p->l1_state != 3))
1017                                                 l1p->d_if.ifc.l1l2(&l1p->
1018                                                                    d_if.
1019                                                                    ifc,
1020                                                                    PH_DEACTIVATE
1021                                                                    |
1022                                                                    INDICATION,
1023                                                                    NULL);
1024
1025                                         if (l1p->l1_state != 2) {
1026                                                 del_timer(&l1p->l1_timer);
1027                                                 if (l1p->l1_state == 3) {
1028                                                         l1p->d_if.ifc.
1029                                                                 l1l2(&l1p->
1030                                                                      d_if.ifc,
1031                                                                      PH_ACTIVATE
1032                                                                      |
1033                                                                      INDICATION,
1034                                                                      NULL);
1035                                                 }
1036                                         } else {
1037                                                 /* allow transition */
1038                                                 Write_hfc8(hw, A_ST_WR_STA,
1039                                                            M_SET_G2_G3);
1040                                                 mod_timer(&l1p->l1_timer,
1041                                                           jiffies +
1042                                                           L1_TIMER_T1);
1043                                         }
1044                                         printk(KERN_INFO
1045                                                "HFC-4S/8S: NT ch %d l1 state %d -> %d\n",
1046                                                l1p->st_num, oldstate,
1047                                                l1p->l1_state);
1048                                 } else {
1049                                         u_char oldstate = l1p->l1_state;
1050
1051                                         Write_hfc8(l1p->hw, R_ST_SEL,
1052                                                    l1p->st_num);
1053                                         l1p->l1_state =
1054                                                 Read_hfc8(l1p->hw,
1055                                                           A_ST_RD_STA) & 0xf;
1056
1057                                         if (((l1p->l1_state == 3) &&
1058                                              ((oldstate == 7) ||
1059                                               (oldstate == 8))) ||
1060                                             ((timer_pending
1061                                               (&l1p->l1_timer))
1062                                              && (l1p->l1_state == 8))) {
1063                                                 mod_timer(&l1p->l1_timer,
1064                                                           L1_TIMER_T4 +
1065                                                           jiffies);
1066                                         } else {
1067                                                 if (l1p->l1_state == 7) {
1068                                                         del_timer(&l1p->
1069                                                                   l1_timer);
1070                                                         l1p->d_if.ifc.
1071                                                                 l1l2(&l1p->
1072                                                                      d_if.ifc,
1073                                                                      PH_ACTIVATE
1074                                                                      |
1075                                                                      INDICATION,
1076                                                                      NULL);
1077                                                         tx_d_frame(l1p);
1078                                                 }
1079                                                 if (l1p->l1_state == 3) {
1080                                                         if (oldstate != 3)
1081                                                                 l1p->d_if.
1082                                                                         ifc.
1083                                                                         l1l2
1084                                                                         (&l1p->
1085                                                                          d_if.
1086                                                                          ifc,
1087                                                                          PH_DEACTIVATE
1088                                                                          |
1089                                                                          INDICATION,
1090                                                                          NULL);
1091                                                 }
1092                                         }
1093                                         printk(KERN_INFO
1094                                                "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n",
1095                                                l1p->hw->cardnum,
1096                                                l1p->st_num, oldstate,
1097                                                l1p->l1_state);
1098                                 }
1099                         }
1100                 }
1101                 b <<= 1;
1102                 l1p++;
1103         }
1104
1105         /* now handle the fifos */
1106         idx = 0;
1107         fifo_stat = hw->mr.r_irq_fifo_blx;
1108         l1p = hw->l1;
1109         while (idx < hw->driver_data.max_st_ports) {
1110
1111                 if (hw->mr.timer_irq) {
1112                         *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
1113                         if (hw->fifo_sched_cnt <= 0) {
1114                                 *fifo_stat |=
1115                                         hw->mr.fifo_slow_timer_service[l1p->
1116                                                                        st_num];
1117                         }
1118                 }
1119                 /* ignore fifo 6 (TX E fifo) */
1120                 *fifo_stat &= 0xff - 0x40;
1121
1122                 while (*fifo_stat) {
1123
1124                         if (!l1p->nt_mode) {
1125                                 /* RX Fifo has data to read */
1126                                 if ((*fifo_stat & 0x20)) {
1127                                         *fifo_stat &= ~0x20;
1128                                         rx_d_frame(l1p, 0);
1129                                 }
1130                                 /* E Fifo has data to read */
1131                                 if ((*fifo_stat & 0x80)) {
1132                                         *fifo_stat &= ~0x80;
1133                                         rx_d_frame(l1p, 1);
1134                                 }
1135                                 /* TX Fifo completed send */
1136                                 if ((*fifo_stat & 0x10)) {
1137                                         *fifo_stat &= ~0x10;
1138                                         tx_d_frame(l1p);
1139                                 }
1140                         }
1141                         /* B1 RX Fifo has data to read */
1142                         if ((*fifo_stat & 0x2)) {
1143                                 *fifo_stat &= ~0x2;
1144                                 rx_b_frame(l1p->b_ch);
1145                         }
1146                         /* B1 TX Fifo has send completed */
1147                         if ((*fifo_stat & 0x1)) {
1148                                 *fifo_stat &= ~0x1;
1149                                 tx_b_frame(l1p->b_ch);
1150                         }
1151                         /* B2 RX Fifo has data to read */
1152                         if ((*fifo_stat & 0x8)) {
1153                                 *fifo_stat &= ~0x8;
1154                                 rx_b_frame(l1p->b_ch + 1);
1155                         }
1156                         /* B2 TX Fifo has send completed */
1157                         if ((*fifo_stat & 0x4)) {
1158                                 *fifo_stat &= ~0x4;
1159                                 tx_b_frame(l1p->b_ch + 1);
1160                         }
1161                 }
1162                 fifo_stat++;
1163                 l1p++;
1164                 idx++;
1165         }
1166
1167         if (hw->fifo_sched_cnt <= 0)
1168                 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE));
1169         hw->mr.timer_irq = 0;   /* clear requested timer irq */
1170 }                               /* hfc4s8s_bh */
1171
1172 /*********************/
1173 /* interrupt handler */
1174 /*********************/
1175 static irqreturn_t
1176 hfc4s8s_interrupt(int intno, void *dev_id)
1177 {
1178         hfc4s8s_hw *hw = dev_id;
1179         u_char b, ovr;
1180         volatile u_char *ovp;
1181         int idx;
1182         u_char old_ioreg;
1183
1184         if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN))
1185                 return IRQ_NONE;
1186
1187         /* read current selected regsister */
1188         old_ioreg = GetRegAddr(hw);
1189
1190         /* Layer 1 State change */
1191         hw->mr.r_irq_statech |=
1192                 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
1193         if (!
1194             (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
1195             && !hw->mr.r_irq_statech) {
1196                 SetRegAddr(hw, old_ioreg);
1197                 return IRQ_NONE;
1198         }
1199
1200         /* timer event */
1201         if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) {
1202                 hw->mr.timer_irq = 1;
1203                 hw->fifo_sched_cnt--;
1204         }
1205
1206         /* FIFO event */
1207         if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) {
1208                 hw->mr.r_irq_oview |= ovr;
1209                 idx = R_IRQ_FIFO_BL0;
1210                 ovp = hw->mr.r_irq_fifo_blx;
1211                 while (ovr) {
1212                         if ((ovr & 1)) {
1213                                 *ovp |= Read_hfc8(hw, idx);
1214                         }
1215                         ovp++;
1216                         idx++;
1217                         ovr >>= 1;
1218                 }
1219         }
1220
1221         /* queue the request to allow other cards to interrupt */
1222         schedule_work(&hw->tqueue);
1223
1224         SetRegAddr(hw, old_ioreg);
1225         return IRQ_HANDLED;
1226 }                               /* hfc4s8s_interrupt */
1227
1228 /***********************************************************************/
1229 /* reset the complete chip, don't release the chips irq but disable it */
1230 /***********************************************************************/
1231 static void
1232 chipreset(hfc4s8s_hw *hw)
1233 {
1234         u_long flags;
1235
1236         spin_lock_irqsave(&hw->lock, flags);
1237         Write_hfc8(hw, R_CTRL, 0);      /* use internal RAM */
1238         Write_hfc8(hw, R_RAM_MISC, 0);  /* 32k*8 RAM */
1239         Write_hfc8(hw, R_FIFO_MD, 0);   /* fifo mode 386 byte/fifo simple mode */
1240         Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */
1241         hw->mr.r_irq_ctrl = 0;  /* interrupt is inactive */
1242         spin_unlock_irqrestore(&hw->lock, flags);
1243
1244         udelay(3);
1245         Write_hfc8(hw, R_CIRM, 0);      /* disable reset */
1246         wait_busy(hw);
1247
1248         Write_hfc8(hw, R_PCM_MD0, M_PCM_MD);    /* master mode */
1249         Write_hfc8(hw, R_RAM_MISC, M_FZ_MD);    /* transmit fifo option */
1250         if (hw->driver_data.clock_mode == 1)
1251                 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK);       /* PCM clk / 2 */
1252         Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE);      /* timer interval */
1253
1254         memset(&hw->mr, 0, sizeof(hw->mr));
1255 }                               /* chipreset */
1256
1257 /********************************************/
1258 /* disable/enable hardware in nt or te mode */
1259 /********************************************/
1260 static void
1261 hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode)
1262 {
1263         u_long flags;
1264         char if_name[40];
1265         int i;
1266
1267         if (enable) {
1268                 /* save system vars */
1269                 hw->nt_mode = nt_mode;
1270
1271                 /* enable fifo and state irqs, but not global irq enable */
1272                 hw->mr.r_irq_ctrl = M_FIFO_IRQ;
1273                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1274                 hw->mr.r_irqmsk_statchg = 0;
1275                 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1276                 Write_hfc8(hw, R_PWM_MD, 0x80);
1277                 Write_hfc8(hw, R_PWM1, 26);
1278                 if (!nt_mode)
1279                         Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC);
1280
1281                 /* enable the line interfaces and fifos */
1282                 for (i = 0; i < hw->driver_data.max_st_ports; i++) {
1283                         hw->mr.r_irqmsk_statchg |= (1 << i);
1284                         Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1285                         Write_hfc8(hw, R_ST_SEL, i);
1286                         Write_hfc8(hw, A_ST_CLK_DLY,
1287                                    ((nt_mode) ? CLKDEL_NT : CLKDEL_TE));
1288                         hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE);
1289                         Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0);
1290                         Write_hfc8(hw, A_ST_CTRL2, 3);
1291                         Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */
1292
1293                         hw->l1[i].enabled = 1;
1294                         hw->l1[i].nt_mode = nt_mode;
1295
1296                         if (!nt_mode) {
1297                                 /* setup E-fifo */
1298                                 Write_hfc8(hw, R_FIFO, i * 8 + 7);      /* E fifo */
1299                                 wait_busy(hw);
1300                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1301                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1302                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1303                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1304                                 wait_busy(hw);
1305
1306                                 /* setup D RX-fifo */
1307                                 Write_hfc8(hw, R_FIFO, i * 8 + 5);      /* RX fifo */
1308                                 wait_busy(hw);
1309                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1310                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1311                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1312                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1313                                 wait_busy(hw);
1314
1315                                 /* setup D TX-fifo */
1316                                 Write_hfc8(hw, R_FIFO, i * 8 + 4);      /* TX fifo */
1317                                 wait_busy(hw);
1318                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1319                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1320                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1321                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1322                                 wait_busy(hw);
1323                         }
1324
1325                         sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i);
1326
1327                         if (hisax_register
1328                             (&hw->l1[i].d_if, hw->l1[i].b_table, if_name,
1329                              ((nt_mode) ? 3 : 2))) {
1330
1331                                 hw->l1[i].enabled = 0;
1332                                 hw->mr.r_irqmsk_statchg &= ~(1 << i);
1333                                 Write_hfc8(hw, R_SCI_MSK,
1334                                            hw->mr.r_irqmsk_statchg);
1335                                 printk(KERN_INFO
1336                                        "HFC-4S/8S: Unable to register S/T device %s, break\n",
1337                                        if_name);
1338                                 break;
1339                         }
1340                 }
1341                 spin_lock_irqsave(&hw->lock, flags);
1342                 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN;
1343                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1344                 spin_unlock_irqrestore(&hw->lock, flags);
1345         } else {
1346                 /* disable hardware */
1347                 spin_lock_irqsave(&hw->lock, flags);
1348                 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN;
1349                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1350                 spin_unlock_irqrestore(&hw->lock, flags);
1351
1352                 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) {
1353                         hw->l1[i].enabled = 0;
1354                         hisax_unregister(&hw->l1[i].d_if);
1355                         del_timer(&hw->l1[i].l1_timer);
1356                         skb_queue_purge(&hw->l1[i].d_tx_queue);
1357                         skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue);
1358                         skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue);
1359                 }
1360                 chipreset(hw);
1361         }
1362 }                               /* hfc_hardware_enable */
1363
1364 /******************************************/
1365 /* disable memory mapped ports / io ports */
1366 /******************************************/
1367 static void
1368 release_pci_ports(hfc4s8s_hw *hw)
1369 {
1370         pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
1371         if (hw->iobase)
1372                 release_region(hw->iobase, 8);
1373 }
1374
1375 /*****************************************/
1376 /* enable memory mapped ports / io ports */
1377 /*****************************************/
1378 static void
1379 enable_pci_ports(hfc4s8s_hw *hw)
1380 {
1381         pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO);
1382 }
1383
1384 /*************************************/
1385 /* initialise the HFC-4s/8s hardware */
1386 /* return 0 on success.              */
1387 /*************************************/
1388 static int
1389 setup_instance(hfc4s8s_hw *hw)
1390 {
1391         int err = -EIO;
1392         int i;
1393
1394         for (i = 0; i < HFC_MAX_ST; i++) {
1395                 struct hfc4s8s_l1 *l1p;
1396
1397                 l1p = hw->l1 + i;
1398                 spin_lock_init(&l1p->lock);
1399                 l1p->hw = hw;
1400                 timer_setup(&l1p->l1_timer, hfc_l1_timer, 0);
1401                 l1p->st_num = i;
1402                 skb_queue_head_init(&l1p->d_tx_queue);
1403                 l1p->d_if.ifc.priv = hw->l1 + i;
1404                 l1p->d_if.ifc.l2l1 = (void *) dch_l2l1;
1405
1406                 spin_lock_init(&l1p->b_ch[0].lock);
1407                 l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1;
1408                 l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0];
1409                 l1p->b_ch[0].l1p = hw->l1 + i;
1410                 l1p->b_ch[0].bchan = 1;
1411                 l1p->b_table[0] = &l1p->b_ch[0].b_if;
1412                 skb_queue_head_init(&l1p->b_ch[0].tx_queue);
1413
1414                 spin_lock_init(&l1p->b_ch[1].lock);
1415                 l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1;
1416                 l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1];
1417                 l1p->b_ch[1].l1p = hw->l1 + i;
1418                 l1p->b_ch[1].bchan = 2;
1419                 l1p->b_table[1] = &l1p->b_ch[1].b_if;
1420                 skb_queue_head_init(&l1p->b_ch[1].tx_queue);
1421         }
1422
1423         enable_pci_ports(hw);
1424         chipreset(hw);
1425
1426         i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT;
1427         if (i != hw->driver_data.chip_id) {
1428                 printk(KERN_INFO
1429                        "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n",
1430                        i, hw->driver_data.chip_id);
1431                 goto out;
1432         }
1433
1434         i = Read_hfc8(hw, R_CHIP_RV) & 0xf;
1435         if (!i) {
1436                 printk(KERN_INFO
1437                        "HFC-4S/8S: chip revision 0 not supported, card ignored\n");
1438                 goto out;
1439         }
1440
1441         INIT_WORK(&hw->tqueue, hfc4s8s_bh);
1442
1443         if (request_irq
1444             (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) {
1445                 printk(KERN_INFO
1446                        "HFC-4S/8S: unable to alloc irq %d, card ignored\n",
1447                        hw->irq);
1448                 goto out;
1449         }
1450         printk(KERN_INFO
1451                "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n",
1452                hw->iobase, hw->irq);
1453
1454         hfc_hardware_enable(hw, 1, 0);
1455
1456         return (0);
1457
1458 out:
1459         hw->irq = 0;
1460         release_pci_ports(hw);
1461         kfree(hw);
1462         return (err);
1463 }
1464
1465 /*****************************************/
1466 /* PCI hotplug interface: probe new card */
1467 /*****************************************/
1468 static int
1469 hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1470 {
1471         int err = -ENOMEM;
1472         hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data;
1473         hfc4s8s_hw *hw;
1474
1475         if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) {
1476                 printk(KERN_ERR "No kmem for HFC-4S/8S card\n");
1477                 return (err);
1478         }
1479
1480         hw->pdev = pdev;
1481         err = pci_enable_device(pdev);
1482
1483         if (err)
1484                 goto out;
1485
1486         hw->cardnum = card_cnt;
1487         sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum);
1488         printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n",
1489                driver_data->device_name, hw->card_name, pci_name(pdev));
1490
1491         spin_lock_init(&hw->lock);
1492
1493         hw->driver_data = *driver_data;
1494         hw->irq = pdev->irq;
1495         hw->iobase = pci_resource_start(pdev, 0);
1496
1497         if (!request_region(hw->iobase, 8, hw->card_name)) {
1498                 printk(KERN_INFO
1499                        "HFC-4S/8S: failed to request address space at 0x%04x\n",
1500                        hw->iobase);
1501                 err = -EBUSY;
1502                 goto out;
1503         }
1504
1505         pci_set_drvdata(pdev, hw);
1506         err = setup_instance(hw);
1507         if (!err)
1508                 card_cnt++;
1509         return (err);
1510
1511 out:
1512         kfree(hw);
1513         return (err);
1514 }
1515
1516 /**************************************/
1517 /* PCI hotplug interface: remove card */
1518 /**************************************/
1519 static void
1520 hfc4s8s_remove(struct pci_dev *pdev)
1521 {
1522         hfc4s8s_hw *hw = pci_get_drvdata(pdev);
1523
1524         printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum);
1525         hfc_hardware_enable(hw, 0, 0);
1526
1527         if (hw->irq)
1528                 free_irq(hw->irq, hw);
1529         hw->irq = 0;
1530         release_pci_ports(hw);
1531
1532         card_cnt--;
1533         pci_disable_device(pdev);
1534         kfree(hw);
1535         return;
1536 }
1537
1538 static struct pci_driver hfc4s8s_driver = {
1539         .name   = "hfc4s8s_l1",
1540         .probe  = hfc4s8s_probe,
1541         .remove = hfc4s8s_remove,
1542         .id_table       = hfc4s8s_ids,
1543 };
1544
1545 /**********************/
1546 /* driver Module init */
1547 /**********************/
1548 static int __init
1549 hfc4s8s_module_init(void)
1550 {
1551         int err;
1552
1553         printk(KERN_INFO
1554                "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n",
1555                hfc4s8s_rev);
1556         printk(KERN_INFO
1557                "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n");
1558
1559         card_cnt = 0;
1560
1561         err = pci_register_driver(&hfc4s8s_driver);
1562         if (err < 0) {
1563                 goto out;
1564         }
1565         printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt);
1566
1567         return 0;
1568 out:
1569         return (err);
1570 }                               /* hfc4s8s_init_hw */
1571
1572 /*************************************/
1573 /* driver module exit :              */
1574 /* release the HFC-4s/8s hardware    */
1575 /*************************************/
1576 static void __exit
1577 hfc4s8s_module_exit(void)
1578 {
1579         pci_unregister_driver(&hfc4s8s_driver);
1580         printk(KERN_INFO "HFC-4S/8S: module removed\n");
1581 }                               /* hfc4s8s_release_hw */
1582
1583 module_init(hfc4s8s_module_init);
1584 module_exit(hfc4s8s_module_exit);