1 /* $Id: diva.c,v 1.33.2.6 2004/02/11 13:21:33 keil Exp $
3 * low level stuff for Eicon.Diehl Diva Family ISDN cards
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
11 * For changes and modifications please read
12 * Documentation/isdn/HiSax.cert
14 * Thanks to Eicon Technology for documents and information
18 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/isapnp.h>
28 static const char *Diva_revision = "$Revision: 1.33.2.6 $";
30 #define byteout(addr, val) outb(val, addr)
31 #define bytein(addr) inb(addr)
33 #define DIVA_HSCX_DATA 0
34 #define DIVA_HSCX_ADR 4
35 #define DIVA_ISA_ISAC_DATA 2
36 #define DIVA_ISA_ISAC_ADR 6
37 #define DIVA_ISA_CTRL 7
38 #define DIVA_IPAC_ADR 0
39 #define DIVA_IPAC_DATA 1
41 #define DIVA_PCI_ISAC_DATA 8
42 #define DIVA_PCI_ISAC_ADR 0xc
43 #define DIVA_PCI_CTRL 0x10
48 #define DIVA_IPAC_ISA 3
49 #define DIVA_IPAC_PCI 4
50 #define DIVA_IPACX_PCI 5
53 #define DIVA_IRQ_STAT 0x01
54 #define DIVA_EEPROM_SDA 0x02
57 #define DIVA_IRQ_REQ 0x01
58 #define DIVA_RESET 0x08
59 #define DIVA_EEPROM_CLK 0x40
60 #define DIVA_PCI_LED_A 0x10
61 #define DIVA_PCI_LED_B 0x20
62 #define DIVA_ISA_LED_A 0x20
63 #define DIVA_ISA_LED_B 0x40
64 #define DIVA_IRQ_CLR 0x80
67 #define PITA_MISC_REG 0x1c
69 #define PITA_PARA_SOFTRESET 0x00000001
70 #define PITA_SER_SOFTRESET 0x00000002
71 #define PITA_PARA_MPX_MODE 0x00000004
72 #define PITA_INT0_ENABLE 0x00000200
74 #define PITA_PARA_SOFTRESET 0x01000000
75 #define PITA_SER_SOFTRESET 0x02000000
76 #define PITA_PARA_MPX_MODE 0x04000000
77 #define PITA_INT0_ENABLE 0x00020000
79 #define PITA_INT0_STATUS 0x02
82 readreg(unsigned int ale, unsigned int adr, u_char off)
92 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
95 insb(adr, data, size);
100 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
107 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
110 outsb(adr, data, size);
114 memreadreg(unsigned long adr, u_char off)
116 return (*((unsigned char *)
117 (((unsigned int *)adr) + off)));
121 memwritereg(unsigned long adr, u_char off, u_char data)
125 p = (unsigned char *)(((unsigned int *)adr) + off);
129 /* Interface functions */
132 ReadISAC(struct IsdnCardState *cs, u_char offset)
134 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset));
138 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value);
144 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
146 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
150 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
152 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
156 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
158 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset + 0x80));
162 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
164 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset | 0x80, value);
168 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
170 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
174 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
176 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
180 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
182 return (readreg(cs->hw.diva.hscx_adr,
183 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0)));
187 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
189 writereg(cs->hw.diva.hscx_adr,
190 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value);
194 MemReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
196 return (memreadreg(cs->hw.diva.cfg_reg, offset + 0x80));
200 MemWriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
202 memwritereg(cs->hw.diva.cfg_reg, offset | 0x80, value);
206 MemReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
209 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80);
213 MemWriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
216 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++);
220 MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
226 MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
231 /* IO-Functions for IPACX type cards */
233 MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset)
235 return (memreadreg(cs->hw.diva.cfg_reg, offset));
239 MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value)
241 memwritereg(cs->hw.diva.cfg_reg, offset, value);
245 MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char *data, int size)
248 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
252 MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char *data, int size)
255 memwritereg(cs->hw.diva.cfg_reg, 0, *data++);
259 MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset)
261 return (memreadreg(cs->hw.diva.cfg_reg, offset +
262 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
266 MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
268 memwritereg(cs->hw.diva.cfg_reg, offset +
269 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
273 * fast interrupt HSCX stuff goes here
276 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
277 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
278 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
279 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
281 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
282 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
284 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
285 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
287 #include "hscx_irq.c"
290 diva_interrupt(int intno, void *dev_id)
292 struct IsdnCardState *cs = dev_id;
297 spin_lock_irqsave(&cs->lock, flags);
298 while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) {
299 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40);
301 hscx_int_main(cs, val);
302 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA);
304 isac_interrupt(cs, val);
308 printk(KERN_WARNING "Diva: IRQ LOOP\n");
309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF);
310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF);
311 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF);
312 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0);
313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0);
314 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0);
315 spin_unlock_irqrestore(&cs->lock, flags);
320 diva_irq_ipac_isa(int intno, void *dev_id)
322 struct IsdnCardState *cs = dev_id;
327 spin_lock_irqsave(&cs->lock, flags);
328 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
330 if (cs->debug & L1_DEB_IPAC)
331 debugl1(cs, "IPAC ISTA %02X", ista);
333 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40);
341 hscx_int_main(cs, val);
344 val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80);
346 isac_interrupt(cs, val);
351 isac_interrupt(cs, val);
353 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
354 if ((ista & 0x3f) && icnt) {
359 printk(KERN_WARNING "DIVA IPAC IRQ LOOP\n");
360 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF);
361 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0);
362 spin_unlock_irqrestore(&cs->lock, flags);
367 MemwaitforCEC(struct IsdnCardState *cs, int hscx)
371 while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
376 printk(KERN_WARNING "HiSax: waitforCEC timeout\n");
381 MemwaitforXFW(struct IsdnCardState *cs, int hscx)
385 while (((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) {
390 printk(KERN_WARNING "HiSax: waitforXFW timeout\n");
394 MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data)
396 MemwaitforCEC(cs, hscx);
397 MemWriteHSCX(cs, hscx, HSCX_CMDR, data);
401 Memhscx_empty_fifo(struct BCState *bcs, int count)
404 struct IsdnCardState *cs = bcs->cs;
407 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
408 debugl1(cs, "hscx_empty_fifo");
410 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
411 if (cs->debug & L1_DEB_WARN)
412 debugl1(cs, "hscx_empty_fifo: incoming packet too large");
413 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
414 bcs->hw.hscx.rcvidx = 0;
417 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
420 *ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0);
421 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
422 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
423 bcs->hw.hscx.rcvidx += count;
424 if (cs->debug & L1_DEB_HSCX_FIFO) {
427 t += sprintf(t, "hscx_empty_fifo %c cnt %d",
428 bcs->hw.hscx.hscx ? 'B' : 'A', count);
429 QuickHex(t, ptr, count);
430 debugl1(cs, "%s", bcs->blog);
435 Memhscx_fill_fifo(struct BCState *bcs)
437 struct IsdnCardState *cs = bcs->cs;
438 int more, count, cnt;
439 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32;
442 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
443 debugl1(cs, "hscx_fill_fifo");
447 if (bcs->tx_skb->len <= 0)
450 more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
451 if (bcs->tx_skb->len > fifo_size) {
455 count = bcs->tx_skb->len;
457 MemwaitforXFW(cs, bcs->hw.hscx.hscx);
458 p = ptr = bcs->tx_skb->data;
459 skb_pull(bcs->tx_skb, count);
460 bcs->tx_cnt -= count;
461 bcs->hw.hscx.count += count;
463 memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0,
465 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
466 if (cs->debug & L1_DEB_HSCX_FIFO) {
469 t += sprintf(t, "hscx_fill_fifo %c cnt %d",
470 bcs->hw.hscx.hscx ? 'B' : 'A', count);
471 QuickHex(t, ptr, count);
472 debugl1(cs, "%s", bcs->blog);
477 Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx)
480 struct BCState *bcs = cs->bcs + hscx;
482 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32;
485 if (!test_bit(BC_FLG_INIT, &bcs->Flag))
488 if (val & 0x80) { /* RME */
489 r = MemReadHSCX(cs, hscx, HSCX_RSTA);
490 if ((r & 0xf0) != 0xa0) {
492 if (cs->debug & L1_DEB_WARN)
493 debugl1(cs, "HSCX invalid frame");
494 if ((r & 0x40) && bcs->mode)
495 if (cs->debug & L1_DEB_WARN)
496 debugl1(cs, "HSCX RDO mode=%d",
499 if (cs->debug & L1_DEB_WARN)
500 debugl1(cs, "HSCX CRC error");
501 MemWriteHSCXCMDR(cs, hscx, 0x80);
503 count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (
504 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x3f : 0x1f);
507 Memhscx_empty_fifo(bcs, count);
508 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
509 if (cs->debug & L1_DEB_HSCX_FIFO)
510 debugl1(cs, "HX Frame %d", count);
511 if (!(skb = dev_alloc_skb(count)))
512 printk(KERN_WARNING "HSCX: receive out of memory\n");
514 skb_put_data(skb, bcs->hw.hscx.rcvbuf,
516 skb_queue_tail(&bcs->rqueue, skb);
520 bcs->hw.hscx.rcvidx = 0;
521 schedule_event(bcs, B_RCVBUFREADY);
523 if (val & 0x40) { /* RPF */
524 Memhscx_empty_fifo(bcs, fifo_size);
525 if (bcs->mode == L1_MODE_TRANS) {
526 /* receive audio data */
527 if (!(skb = dev_alloc_skb(fifo_size)))
528 printk(KERN_WARNING "HiSax: receive out of memory\n");
530 skb_put_data(skb, bcs->hw.hscx.rcvbuf,
532 skb_queue_tail(&bcs->rqueue, skb);
534 bcs->hw.hscx.rcvidx = 0;
535 schedule_event(bcs, B_RCVBUFREADY);
538 if (val & 0x10) { /* XPR */
540 if (bcs->tx_skb->len) {
541 Memhscx_fill_fifo(bcs);
544 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
545 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
547 spin_lock_irqsave(&bcs->aclock, flags);
548 bcs->ackcnt += bcs->hw.hscx.count;
549 spin_unlock_irqrestore(&bcs->aclock, flags);
550 schedule_event(bcs, B_ACKPENDING);
552 dev_kfree_skb_irq(bcs->tx_skb);
553 bcs->hw.hscx.count = 0;
557 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
558 bcs->hw.hscx.count = 0;
559 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
560 Memhscx_fill_fifo(bcs);
562 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
563 schedule_event(bcs, B_XMTBUFREADY);
569 Memhscx_int_main(struct IsdnCardState *cs, u_char val)
575 if (val & 0x01) { // EXB
577 exval = MemReadHSCX(cs, 1, HSCX_EXIR);
580 Memhscx_fill_fifo(bcs);
582 /* Here we lost an TX interrupt, so
583 * restart transmitting the whole frame.
586 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
587 bcs->tx_cnt += bcs->hw.hscx.count;
588 bcs->hw.hscx.count = 0;
590 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
591 if (cs->debug & L1_DEB_WARN)
592 debugl1(cs, "HSCX B EXIR %x Lost TX", exval);
594 } else if (cs->debug & L1_DEB_HSCX)
595 debugl1(cs, "HSCX B EXIR %x", exval);
598 if (cs->debug & L1_DEB_HSCX)
599 debugl1(cs, "HSCX B interrupt %x", val);
600 Memhscx_interrupt(cs, val, 1);
602 if (val & 0x02) { // EXA
604 exval = MemReadHSCX(cs, 0, HSCX_EXIR);
606 if (bcs->mode == L1_MODE_TRANS)
607 Memhscx_fill_fifo(bcs);
609 /* Here we lost an TX interrupt, so
610 * restart transmitting the whole frame.
613 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
614 bcs->tx_cnt += bcs->hw.hscx.count;
615 bcs->hw.hscx.count = 0;
617 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
618 if (cs->debug & L1_DEB_WARN)
619 debugl1(cs, "HSCX A EXIR %x Lost TX", exval);
621 } else if (cs->debug & L1_DEB_HSCX)
622 debugl1(cs, "HSCX A EXIR %x", exval);
624 if (val & 0x04) { // ICA
625 exval = MemReadHSCX(cs, 0, HSCX_ISTA);
626 if (cs->debug & L1_DEB_HSCX)
627 debugl1(cs, "HSCX A interrupt %x", exval);
628 Memhscx_interrupt(cs, exval, 0);
633 diva_irq_ipac_pci(int intno, void *dev_id)
635 struct IsdnCardState *cs = dev_id;
641 spin_lock_irqsave(&cs->lock, flags);
642 cfg = (u_char *) cs->hw.diva.pci_cfg;
644 if (!(val & PITA_INT0_STATUS)) {
645 spin_unlock_irqrestore(&cs->lock, flags);
646 return IRQ_NONE; /* other shared IRQ */
648 *cfg = PITA_INT0_STATUS; /* Reset pending INT0 */
649 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
651 if (cs->debug & L1_DEB_IPAC)
652 debugl1(cs, "IPAC ISTA %02X", ista);
654 val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40);
662 Memhscx_int_main(cs, val);
665 val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80);
667 isac_interrupt(cs, val);
672 isac_interrupt(cs, val);
674 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
675 if ((ista & 0x3f) && icnt) {
680 printk(KERN_WARNING "DIVA IPAC PCI IRQ LOOP\n");
681 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF);
682 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);
683 spin_unlock_irqrestore(&cs->lock, flags);
688 diva_irq_ipacx_pci(int intno, void *dev_id)
690 struct IsdnCardState *cs = dev_id;
695 spin_lock_irqsave(&cs->lock, flags);
696 cfg = (u_char *) cs->hw.diva.pci_cfg;
698 if (!(val & PITA_INT0_STATUS)) {
699 spin_unlock_irqrestore(&cs->lock, flags);
700 return IRQ_NONE; // other shared IRQ
702 interrupt_ipacx(cs); // handler for chip
703 *cfg = PITA_INT0_STATUS; // Reset PLX interrupt
704 spin_unlock_irqrestore(&cs->lock, flags);
709 release_io_diva(struct IsdnCardState *cs)
713 if ((cs->subtyp == DIVA_IPAC_PCI) ||
714 (cs->subtyp == DIVA_IPACX_PCI)) {
715 u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;
717 *cfg = 0; /* disable INT0/1 */
718 *cfg = 2; /* reset pending INT0 */
719 if (cs->hw.diva.cfg_reg)
720 iounmap((void *)cs->hw.diva.cfg_reg);
721 if (cs->hw.diva.pci_cfg)
722 iounmap((void *)cs->hw.diva.pci_cfg);
724 } else if (cs->subtyp != DIVA_IPAC_ISA) {
725 del_timer(&cs->hw.diva.tl);
726 if (cs->hw.diva.cfg_reg)
727 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
729 if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
733 if (cs->hw.diva.cfg_reg) {
734 release_region(cs->hw.diva.cfg_reg, bytecnt);
739 iounmap_diva(struct IsdnCardState *cs)
741 if ((cs->subtyp == DIVA_IPAC_PCI) || (cs->subtyp == DIVA_IPACX_PCI)) {
742 if (cs->hw.diva.cfg_reg) {
743 iounmap((void *)cs->hw.diva.cfg_reg);
744 cs->hw.diva.cfg_reg = 0;
746 if (cs->hw.diva.pci_cfg) {
747 iounmap((void *)cs->hw.diva.pci_cfg);
748 cs->hw.diva.pci_cfg = 0;
756 reset_diva(struct IsdnCardState *cs)
758 if (cs->subtyp == DIVA_IPAC_ISA) {
759 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20);
761 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00);
763 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0);
764 } else if (cs->subtyp == DIVA_IPAC_PCI) {
765 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
767 *ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
769 *ireg = PITA_PARA_MPX_MODE;
771 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);
772 } else if (cs->subtyp == DIVA_IPACX_PCI) {
773 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
775 *ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
777 *ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;
779 MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off
780 } else { /* DIVA 2.0 */
781 cs->hw.diva.ctrl_reg = 0; /* Reset On */
782 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
784 cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */
785 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
787 if (cs->subtyp == DIVA_ISA)
788 cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;
790 /* Workaround PCI9060 */
791 byteout(cs->hw.diva.pci_cfg + 0x69, 9);
792 cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;
794 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
798 #define DIVA_ASSIGN 1
801 diva_led_handler(struct IsdnCardState *cs)
805 if ((cs->subtyp == DIVA_IPAC_ISA) ||
806 (cs->subtyp == DIVA_IPAC_PCI) ||
807 (cs->subtyp == DIVA_IPACX_PCI))
809 del_timer(&cs->hw.diva.tl);
810 if (cs->hw.diva.status & DIVA_ASSIGN)
811 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
812 DIVA_ISA_LED_A : DIVA_PCI_LED_A;
814 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
815 DIVA_ISA_LED_A : DIVA_PCI_LED_A;
818 if (cs->hw.diva.status & 0xf000)
819 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
820 DIVA_ISA_LED_B : DIVA_PCI_LED_B;
821 else if (cs->hw.diva.status & 0x0f00) {
822 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
823 DIVA_ISA_LED_B : DIVA_PCI_LED_B;
826 cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ?
827 DIVA_ISA_LED_B : DIVA_PCI_LED_B);
829 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
831 init_timer(&cs->hw.diva.tl);
832 cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000);
833 add_timer(&cs->hw.diva.tl);
838 Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
845 spin_lock_irqsave(&cs->lock, flags);
847 spin_unlock_irqrestore(&cs->lock, flags);
853 spin_lock_irqsave(&cs->lock, flags);
855 if (cs->subtyp == DIVA_IPACX_PCI) {
856 ireg = (unsigned int *)cs->hw.diva.pci_cfg;
857 *ireg = PITA_INT0_ENABLE;
858 init_ipacx(cs, 3); // init chip and enable interrupts
859 spin_unlock_irqrestore(&cs->lock, flags);
862 if (cs->subtyp == DIVA_IPAC_PCI) {
863 ireg = (unsigned int *)cs->hw.diva.pci_cfg;
864 *ireg = PITA_INT0_ENABLE;
867 spin_unlock_irqrestore(&cs->lock, flags);
871 case (MDL_REMOVE | REQUEST):
872 cs->hw.diva.status = 0;
874 case (MDL_ASSIGN | REQUEST):
875 cs->hw.diva.status |= DIVA_ASSIGN;
879 cs->hw.diva.status |= 0x0200;
881 cs->hw.diva.status |= 0x0100;
885 cs->hw.diva.status |= 0x2000;
887 cs->hw.diva.status |= 0x1000;
891 cs->hw.diva.status &= ~0x2000;
892 cs->hw.diva.status &= ~0x0200;
894 cs->hw.diva.status &= ~0x1000;
895 cs->hw.diva.status &= ~0x0100;
899 if ((cs->subtyp != DIVA_IPAC_ISA) &&
900 (cs->subtyp != DIVA_IPAC_PCI) &&
901 (cs->subtyp != DIVA_IPACX_PCI)) {
902 spin_lock_irqsave(&cs->lock, flags);
903 diva_led_handler(cs);
904 spin_unlock_irqrestore(&cs->lock, flags);
909 static int setup_diva_common(struct IsdnCardState *cs)
914 if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
920 "Diva: %s card configured at %#lx IRQ %d\n",
921 (cs->subtyp == DIVA_PCI) ? "PCI" :
922 (cs->subtyp == DIVA_ISA) ? "ISA" :
923 (cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" :
924 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
925 cs->hw.diva.cfg_reg, cs->irq);
926 if ((cs->subtyp == DIVA_IPAC_PCI) ||
927 (cs->subtyp == DIVA_IPACX_PCI) ||
928 (cs->subtyp == DIVA_PCI))
929 printk(KERN_INFO "Diva: %s space at %#lx\n",
930 (cs->subtyp == DIVA_PCI) ? "PCI" :
931 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
932 cs->hw.diva.pci_cfg);
933 if ((cs->subtyp != DIVA_IPAC_PCI) &&
934 (cs->subtyp != DIVA_IPACX_PCI)) {
935 if (!request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn")) {
937 "HiSax: %s config port %lx-%lx already in use\n",
940 cs->hw.diva.cfg_reg + bytecnt);
945 cs->BC_Read_Reg = &ReadHSCX;
946 cs->BC_Write_Reg = &WriteHSCX;
947 cs->BC_Send_Data = &hscx_fill_fifo;
948 cs->cardmsg = &Diva_card_msg;
950 if (cs->subtyp == DIVA_IPAC_ISA) {
951 cs->readisac = &ReadISAC_IPAC;
952 cs->writeisac = &WriteISAC_IPAC;
953 cs->readisacfifo = &ReadISACfifo_IPAC;
954 cs->writeisacfifo = &WriteISACfifo_IPAC;
955 cs->irq_func = &diva_irq_ipac_isa;
956 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID);
957 printk(KERN_INFO "Diva: IPAC version %x\n", val);
958 } else if (cs->subtyp == DIVA_IPAC_PCI) {
959 cs->readisac = &MemReadISAC_IPAC;
960 cs->writeisac = &MemWriteISAC_IPAC;
961 cs->readisacfifo = &MemReadISACfifo_IPAC;
962 cs->writeisacfifo = &MemWriteISACfifo_IPAC;
963 cs->BC_Read_Reg = &MemReadHSCX;
964 cs->BC_Write_Reg = &MemWriteHSCX;
965 cs->BC_Send_Data = &Memhscx_fill_fifo;
966 cs->irq_func = &diva_irq_ipac_pci;
967 val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID);
968 printk(KERN_INFO "Diva: IPAC version %x\n", val);
969 } else if (cs->subtyp == DIVA_IPACX_PCI) {
970 cs->readisac = &MemReadISAC_IPACX;
971 cs->writeisac = &MemWriteISAC_IPACX;
972 cs->readisacfifo = &MemReadISACfifo_IPACX;
973 cs->writeisacfifo = &MemWriteISACfifo_IPACX;
974 cs->BC_Read_Reg = &MemReadHSCX_IPACX;
975 cs->BC_Write_Reg = &MemWriteHSCX_IPACX;
976 cs->BC_Send_Data = NULL; // function located in ipacx module
977 cs->irq_func = &diva_irq_ipacx_pci;
978 printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
979 MemReadISAC_IPACX(cs, IPACX_ID) & 0x3F);
980 } else { /* DIVA 2.0 */
981 setup_timer(&cs->hw.diva.tl, (void *)diva_led_handler,
983 cs->readisac = &ReadISAC;
984 cs->writeisac = &WriteISAC;
985 cs->readisacfifo = &ReadISACfifo;
986 cs->writeisacfifo = &WriteISACfifo;
987 cs->irq_func = &diva_interrupt;
988 ISACVersion(cs, "Diva:");
989 if (HscxVersion(cs, "Diva:")) {
991 "Diva: wrong HSCX versions check IO address\n");
1001 static int setup_diva_isa(struct IsdnCard *card)
1003 struct IsdnCardState *cs = card->cs;
1007 return (-1); /* card not found; continue search */
1009 cs->hw.diva.ctrl_reg = 0;
1010 cs->hw.diva.cfg_reg = card->para[1];
1011 val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR,
1012 cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID);
1013 printk(KERN_INFO "Diva: IPAC version %x\n", val);
1014 if ((val == 1) || (val == 2)) {
1015 cs->subtyp = DIVA_IPAC_ISA;
1016 cs->hw.diva.ctrl = 0;
1017 cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA;
1018 cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA;
1019 cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR;
1020 cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR;
1021 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1023 cs->subtyp = DIVA_ISA;
1024 cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL;
1025 cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA;
1026 cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA;
1027 cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR;
1028 cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR;
1030 cs->irq = card->para[0];
1032 return (1); /* card found */
1035 #else /* if !CONFIG_ISA */
1037 static int setup_diva_isa(struct IsdnCard *card)
1039 return (-1); /* card not found; continue search */
1042 #endif /* CONFIG_ISA */
1045 static struct isapnp_device_id diva_ids[] = {
1046 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
1047 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
1048 (unsigned long) "Diva picola" },
1049 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
1050 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x51),
1051 (unsigned long) "Diva picola" },
1052 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
1053 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
1054 (unsigned long) "Diva 2.0" },
1055 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
1056 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x71),
1057 (unsigned long) "Diva 2.0" },
1058 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
1059 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
1060 (unsigned long) "Diva 2.01" },
1061 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
1062 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0xA1),
1063 (unsigned long) "Diva 2.01" },
1067 static struct isapnp_device_id *ipid = &diva_ids[0];
1068 static struct pnp_card *pnp_c = NULL;
1070 static int setup_diva_isapnp(struct IsdnCard *card)
1072 struct IsdnCardState *cs = card->cs;
1073 struct pnp_dev *pnp_d;
1075 if (!isapnp_present())
1076 return (-1); /* card not found; continue search */
1078 while (ipid->card_vendor) {
1079 if ((pnp_c = pnp_find_card(ipid->card_vendor,
1080 ipid->card_device, pnp_c))) {
1082 if ((pnp_d = pnp_find_dev(pnp_c,
1083 ipid->vendor, ipid->function, pnp_d))) {
1086 printk(KERN_INFO "HiSax: %s detected\n",
1087 (char *)ipid->driver_data);
1088 pnp_disable_dev(pnp_d);
1089 err = pnp_activate_dev(pnp_d);
1091 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1095 card->para[1] = pnp_port_start(pnp_d, 0);
1096 card->para[0] = pnp_irq(pnp_d, 0);
1097 if (!card->para[0] || !card->para[1]) {
1098 printk(KERN_ERR "Diva PnP:some resources are missing %ld/%lx\n",
1099 card->para[0], card->para[1]);
1100 pnp_disable_dev(pnp_d);
1103 cs->hw.diva.cfg_reg = card->para[1];
1104 cs->irq = card->para[0];
1105 if (ipid->function == ISAPNP_FUNCTION(0xA1)) {
1106 cs->subtyp = DIVA_IPAC_ISA;
1107 cs->hw.diva.ctrl = 0;
1109 card->para[1] + DIVA_IPAC_DATA;
1111 card->para[1] + DIVA_IPAC_DATA;
1112 cs->hw.diva.isac_adr =
1113 card->para[1] + DIVA_IPAC_ADR;
1114 cs->hw.diva.hscx_adr =
1115 card->para[1] + DIVA_IPAC_ADR;
1116 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1118 cs->subtyp = DIVA_ISA;
1120 card->para[1] + DIVA_ISA_CTRL;
1122 card->para[1] + DIVA_ISA_ISAC_DATA;
1124 card->para[1] + DIVA_HSCX_DATA;
1125 cs->hw.diva.isac_adr =
1126 card->para[1] + DIVA_ISA_ISAC_ADR;
1127 cs->hw.diva.hscx_adr =
1128 card->para[1] + DIVA_HSCX_ADR;
1130 return (1); /* card found */
1132 printk(KERN_ERR "Diva PnP: PnP error card found, no device\n");
1140 return (-1); /* card not found; continue search */
1143 #else /* if !ISAPNP */
1145 static int setup_diva_isapnp(struct IsdnCard *card)
1147 return (-1); /* card not found; continue search */
1153 static struct pci_dev *dev_diva = NULL;
1154 static struct pci_dev *dev_diva_u = NULL;
1155 static struct pci_dev *dev_diva201 = NULL;
1156 static struct pci_dev *dev_diva202 = NULL;
1158 static int setup_diva_pci(struct IsdnCard *card)
1160 struct IsdnCardState *cs = card->cs;
1163 if ((dev_diva = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1164 PCI_DEVICE_ID_EICON_DIVA20, dev_diva))) {
1165 if (pci_enable_device(dev_diva))
1167 cs->subtyp = DIVA_PCI;
1168 cs->irq = dev_diva->irq;
1169 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva, 2);
1170 } else if ((dev_diva_u = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1171 PCI_DEVICE_ID_EICON_DIVA20_U, dev_diva_u))) {
1172 if (pci_enable_device(dev_diva_u))
1174 cs->subtyp = DIVA_PCI;
1175 cs->irq = dev_diva_u->irq;
1176 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva_u, 2);
1177 } else if ((dev_diva201 = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1178 PCI_DEVICE_ID_EICON_DIVA201, dev_diva201))) {
1179 if (pci_enable_device(dev_diva201))
1181 cs->subtyp = DIVA_IPAC_PCI;
1182 cs->irq = dev_diva201->irq;
1183 cs->hw.diva.pci_cfg =
1184 (ulong) ioremap(pci_resource_start(dev_diva201, 0), 4096);
1185 cs->hw.diva.cfg_reg =
1186 (ulong) ioremap(pci_resource_start(dev_diva201, 1), 4096);
1187 } else if ((dev_diva202 = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1188 PCI_DEVICE_ID_EICON_DIVA202, dev_diva202))) {
1189 if (pci_enable_device(dev_diva202))
1191 cs->subtyp = DIVA_IPACX_PCI;
1192 cs->irq = dev_diva202->irq;
1193 cs->hw.diva.pci_cfg =
1194 (ulong) ioremap(pci_resource_start(dev_diva202, 0), 4096);
1195 cs->hw.diva.cfg_reg =
1196 (ulong) ioremap(pci_resource_start(dev_diva202, 1), 4096);
1198 return (-1); /* card not found; continue search */
1202 printk(KERN_WARNING "Diva: No IRQ for PCI card found\n");
1207 if (!cs->hw.diva.cfg_reg) {
1208 printk(KERN_WARNING "Diva: No IO-Adr for PCI card found\n");
1212 cs->irq_flags |= IRQF_SHARED;
1214 if ((cs->subtyp == DIVA_IPAC_PCI) ||
1215 (cs->subtyp == DIVA_IPACX_PCI)) {
1216 cs->hw.diva.ctrl = 0;
1217 cs->hw.diva.isac = 0;
1218 cs->hw.diva.hscx = 0;
1219 cs->hw.diva.isac_adr = 0;
1220 cs->hw.diva.hscx_adr = 0;
1221 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1223 cs->hw.diva.ctrl = cs->hw.diva.cfg_reg + DIVA_PCI_CTRL;
1224 cs->hw.diva.isac = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_DATA;
1225 cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA;
1226 cs->hw.diva.isac_adr = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_ADR;
1227 cs->hw.diva.hscx_adr = cs->hw.diva.cfg_reg + DIVA_HSCX_ADR;
1230 return (1); /* card found */
1233 #else /* if !CONFIG_PCI */
1235 static int setup_diva_pci(struct IsdnCard *card)
1237 return (-1); /* card not found; continue search */
1240 #endif /* CONFIG_PCI */
1242 int setup_diva(struct IsdnCard *card)
1244 int rc, have_card = 0;
1245 struct IsdnCardState *cs = card->cs;
1248 strcpy(tmp, Diva_revision);
1249 printk(KERN_INFO "HiSax: Eicon.Diehl Diva driver Rev. %s\n", HiSax_getrev(tmp));
1250 if (cs->typ != ISDN_CTYPE_DIEHLDIVA)
1252 cs->hw.diva.status = 0;
1254 rc = setup_diva_isa(card);
1262 rc = setup_diva_isapnp(card);
1270 rc = setup_diva_pci(card);
1278 printk(KERN_WARNING "Diva: No ISA, ISAPNP or PCI card found\n");
1282 return setup_diva_common(card->cs);