drivers/isdn/hisax/avm_pci.c

   1 /* $Id: avm_pci.c,v 1.29.2.4 2004/02/11 13:21:32 keil Exp $
   2  *
   3  * low level stuff for AVM Fritz!PCI and ISA PnP isdn cards
   4  *
   5  * Author       Karsten Keil
   6  * Copyright    by Karsten Keil      <keil@isdn4linux.de>
   7  *
   8  * This software may be used and distributed according to the terms
   9  * of the GNU General Public License, incorporated herein by reference.
  10  *
  11  * Thanks to AVM, Berlin for information
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include "hisax.h"
  17 #include "isac.h"
  18 #include "isdnl1.h"
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/isapnp.h>
  22 #include <linux/interrupt.h>
  23
  24 static const char *avm_pci_rev = "$Revision: 1.29.2.4 $";
  25
  26 #define  AVM_FRITZ_PCI          1
  27 #define  AVM_FRITZ_PNP          2
  28
  29 #define  HDLC_FIFO              0x0
  30 #define  HDLC_STATUS            0x4
  31
  32 #define  AVM_HDLC_1             0x00
  33 #define  AVM_HDLC_2             0x01
  34 #define  AVM_ISAC_FIFO          0x02
  35 #define  AVM_ISAC_REG_LOW       0x04
  36 #define  AVM_ISAC_REG_HIGH      0x06
  37
  38 #define  AVM_STATUS0_IRQ_ISAC   0x01
  39 #define  AVM_STATUS0_IRQ_HDLC   0x02
  40 #define  AVM_STATUS0_IRQ_TIMER  0x04
  41 #define  AVM_STATUS0_IRQ_MASK   0x07
  42
  43 #define  AVM_STATUS0_RESET      0x01
  44 #define  AVM_STATUS0_DIS_TIMER  0x02
  45 #define  AVM_STATUS0_RES_TIMER  0x04
  46 #define  AVM_STATUS0_ENA_IRQ    0x08
  47 #define  AVM_STATUS0_TESTBIT    0x10
  48
  49 #define  AVM_STATUS1_INT_SEL    0x0f
  50 #define  AVM_STATUS1_ENA_IOM    0x80
  51
  52 #define  HDLC_MODE_ITF_FLG      0x01
  53 #define  HDLC_MODE_TRANS        0x02
  54 #define  HDLC_MODE_CCR_7        0x04
  55 #define  HDLC_MODE_CCR_16       0x08
  56 #define  HDLC_MODE_TESTLOOP     0x80
  57
  58 #define  HDLC_INT_XPR           0x80
  59 #define  HDLC_INT_XDU           0x40
  60 #define  HDLC_INT_RPR           0x20
  61 #define  HDLC_INT_MASK          0xE0
  62
  63 #define  HDLC_STAT_RME          0x01
  64 #define  HDLC_STAT_RDO          0x10
  65 #define  HDLC_STAT_CRCVFRRAB    0x0E
  66 #define  HDLC_STAT_CRCVFR       0x06
  67 #define  HDLC_STAT_RML_MASK     0x3f00
  68
  69 #define  HDLC_CMD_XRS           0x80
  70 #define  HDLC_CMD_XME           0x01
  71 #define  HDLC_CMD_RRS           0x20
  72 #define  HDLC_CMD_XML_MASK      0x3f00
  73
  74
  75 /* Interface functions */
  76
  77 static u_char
  78 ReadISAC(struct IsdnCardState *cs, u_char offset)
  79 {
  80         register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
  81         register u_char val;
  82
  83         outb(idx, cs->hw.avm.cfg_reg + 4);
  84         val = inb(cs->hw.avm.isac + (offset & 0xf));
  85         return (val);
  86 }
  87
  88 static void
  89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
  90 {
  91         register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
  92
  93         outb(idx, cs->hw.avm.cfg_reg + 4);
  94         outb(value, cs->hw.avm.isac + (offset & 0xf));
  95 }
  96
  97 static void
  98 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
  99 {
 100         outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
 101         insb(cs->hw.avm.isac, data, size);
 102 }
 103
 104 static void
 105 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
 106 {
 107         outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
 108         outsb(cs->hw.avm.isac, data, size);
 109 }
 110
 111 static inline u_int
 112 ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset)
 113 {
 114         register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
 115         register u_int val;
 116
 117         outl(idx, cs->hw.avm.cfg_reg + 4);
 118         val = inl(cs->hw.avm.isac + offset);
 119         return (val);
 120 }
 121
 122 static inline void
 123 WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value)
 124 {
 125         register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
 126
 127         outl(idx, cs->hw.avm.cfg_reg + 4);
 128         outl(value, cs->hw.avm.isac + offset);
 129 }
 130
 131 static inline u_char
 132 ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset)
 133 {
 134         register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
 135         register u_char val;
 136
 137         outb(idx, cs->hw.avm.cfg_reg + 4);
 138         val = inb(cs->hw.avm.isac + offset);
 139         return (val);
 140 }
 141
 142 static inline void
 143 WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
 144 {
 145         register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
 146
 147         outb(idx, cs->hw.avm.cfg_reg + 4);
 148         outb(value, cs->hw.avm.isac + offset);
 149 }
 150
 151 static u_char
 152 ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset)
 153 {
 154         return (0xff & ReadHDLCPCI(cs, chan, offset));
 155 }
 156
 157 static void
 158 WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
 159 {
 160         WriteHDLCPCI(cs, chan, offset, value);
 161 }
 162
 163 static inline
 164 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
 165 {
 166         if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
 167                 return (&cs->bcs[0]);
 168         else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
 169                 return (&cs->bcs[1]);
 170         else
 171                 return (NULL);
 172 }
 173
 174 static void
 175 write_ctrl(struct BCState *bcs, int which) {
 176
 177         if (bcs->cs->debug & L1_DEB_HSCX)
 178                 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
 179                         'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
 180         if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
 181                 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
 182         } else {
 183                 if (which & 4)
 184                         WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
 185                                      bcs->hw.hdlc.ctrl.sr.mode);
 186                 if (which & 2)
 187                         WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
 188                                      bcs->hw.hdlc.ctrl.sr.xml);
 189                 if (which & 1)
 190                         WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
 191                                      bcs->hw.hdlc.ctrl.sr.cmd);
 192         }
 193 }
 194
 195 static void
 196 modehdlc(struct BCState *bcs, int mode, int bc)
 197 {
 198         struct IsdnCardState *cs = bcs->cs;
 199         int hdlc = bcs->channel;
 200
 201         if (cs->debug & L1_DEB_HSCX)
 202                 debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d",
 203                         'A' + hdlc, bcs->mode, mode, hdlc, bc);
 204         bcs->hw.hdlc.ctrl.ctrl = 0;
 205         switch (mode) {
 206         case (-1): /* used for init */
 207                 bcs->mode = 1;
 208                 bcs->channel = bc;
 209                 bc = 0;
 210         case (L1_MODE_NULL):
 211                 if (bcs->mode == L1_MODE_NULL)
 212                         return;
 213                 bcs->hw.hdlc.ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
 214                 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
 215                 write_ctrl(bcs, 5);
 216                 bcs->mode = L1_MODE_NULL;
 217                 bcs->channel = bc;
 218                 break;
 219         case (L1_MODE_TRANS):
 220                 bcs->mode = mode;
 221                 bcs->channel = bc;
 222                 bcs->hw.hdlc.ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
 223                 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
 224                 write_ctrl(bcs, 5);
 225                 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
 226                 write_ctrl(bcs, 1);
 227                 bcs->hw.hdlc.ctrl.sr.cmd = 0;
 228                 schedule_event(bcs, B_XMTBUFREADY);
 229                 break;
 230         case (L1_MODE_HDLC):
 231                 bcs->mode = mode;
 232                 bcs->channel = bc;
 233                 bcs->hw.hdlc.ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
 234                 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
 235                 write_ctrl(bcs, 5);
 236                 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
 237                 write_ctrl(bcs, 1);
 238                 bcs->hw.hdlc.ctrl.sr.cmd = 0;
 239                 schedule_event(bcs, B_XMTBUFREADY);
 240                 break;
 241         }
 242 }
 243
 244 static inline void
 245 hdlc_empty_fifo(struct BCState *bcs, int count)
 246 {
 247         register u_int *ptr;
 248         u_char *p;
 249         u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
 250         int cnt = 0;
 251         struct IsdnCardState *cs = bcs->cs;
 252
 253         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 254                 debugl1(cs, "hdlc_empty_fifo %d", count);
 255         if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
 256                 if (cs->debug & L1_DEB_WARN)
 257                         debugl1(cs, "hdlc_empty_fifo: incoming packet too large");
 258                 return;
 259         }
 260         p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
 261         ptr = (u_int *)p;
 262         bcs->hw.hdlc.rcvidx += count;
 263         if (cs->subtyp == AVM_FRITZ_PCI) {
 264                 outl(idx, cs->hw.avm.cfg_reg + 4);
 265                 while (cnt < count) {
 266 #ifdef __powerpc__
 267                         *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE));
 268 #else
 269                         *ptr++ = inl(cs->hw.avm.isac);
 270 #endif /* __powerpc__ */
 271                         cnt += 4;
 272                 }
 273         } else {
 274                 outb(idx, cs->hw.avm.cfg_reg + 4);
 275                 while (cnt < count) {
 276                         *p++ = inb(cs->hw.avm.isac);
 277                         cnt++;
 278                 }
 279         }
 280         if (cs->debug & L1_DEB_HSCX_FIFO) {
 281                 char *t = bcs->blog;
 282
 283                 if (cs->subtyp == AVM_FRITZ_PNP)
 284                         p = (u_char *) ptr;
 285                 t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
 286                              bcs->channel ? 'B' : 'A', count);
 287                 QuickHex(t, p, count);
 288                 debugl1(cs, "%s", bcs->blog);
 289         }
 290 }
 291
 292 static inline void
 293 hdlc_fill_fifo(struct BCState *bcs)
 294 {
 295         struct IsdnCardState *cs = bcs->cs;
 296         int count, cnt = 0;
 297         int fifo_size = 32;
 298         u_char *p;
 299         u_int *ptr;
 300
 301         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 302                 debugl1(cs, "hdlc_fill_fifo");
 303         if (!bcs->tx_skb)
 304                 return;
 305         if (bcs->tx_skb->len <= 0)
 306                 return;
 307
 308         bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
 309         if (bcs->tx_skb->len > fifo_size) {
 310                 count = fifo_size;
 311         } else {
 312                 count = bcs->tx_skb->len;
 313                 if (bcs->mode != L1_MODE_TRANS)
 314                         bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
 315         }
 316         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 317                 debugl1(cs, "hdlc_fill_fifo %d/%u", count, bcs->tx_skb->len);
 318         p = bcs->tx_skb->data;
 319         ptr = (u_int *)p;
 320         skb_pull(bcs->tx_skb, count);
 321         bcs->tx_cnt -= count;
 322         bcs->hw.hdlc.count += count;
 323         bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
 324         write_ctrl(bcs, 3);  /* sets the correct index too */
 325         if (cs->subtyp == AVM_FRITZ_PCI) {
 326                 while (cnt < count) {
 327 #ifdef __powerpc__
 328                         out_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE), *ptr++);
 329 #else
 330                         outl(*ptr++, cs->hw.avm.isac);
 331 #endif /* __powerpc__ */
 332                         cnt += 4;
 333                 }
 334         } else {
 335                 while (cnt < count) {
 336                         outb(*p++, cs->hw.avm.isac);
 337                         cnt++;
 338                 }
 339         }
 340         if (cs->debug & L1_DEB_HSCX_FIFO) {
 341                 char *t = bcs->blog;
 342
 343                 if (cs->subtyp == AVM_FRITZ_PNP)
 344                         p = (u_char *) ptr;
 345                 t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
 346                              bcs->channel ? 'B' : 'A', count);
 347                 QuickHex(t, p, count);
 348                 debugl1(cs, "%s", bcs->blog);
 349         }
 350 }
 351
 352 static void
 353 HDLC_irq(struct BCState *bcs, u_int stat) {
 354         int len;
 355         struct sk_buff *skb;
 356
 357         if (bcs->cs->debug & L1_DEB_HSCX)
 358                 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
 359         if (stat & HDLC_INT_RPR) {
 360                 if (stat & HDLC_STAT_RDO) {
 361                         if (bcs->cs->debug & L1_DEB_HSCX)
 362                                 debugl1(bcs->cs, "RDO");
 363                         else
 364                                 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
 365                         bcs->hw.hdlc.ctrl.sr.xml = 0;
 366                         bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
 367                         write_ctrl(bcs, 1);
 368                         bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
 369                         write_ctrl(bcs, 1);
 370                         bcs->hw.hdlc.rcvidx = 0;
 371                 } else {
 372                         if (!(len = (stat & HDLC_STAT_RML_MASK) >> 8))
 373                                 len = 32;
 374                         hdlc_empty_fifo(bcs, len);
 375                         if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
 376                                 if (((stat & HDLC_STAT_CRCVFRRAB) == HDLC_STAT_CRCVFR) ||
 377                                     (bcs->mode == L1_MODE_TRANS)) {
 378                                         if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
 379                                                 printk(KERN_WARNING "HDLC: receive out of memory\n");
 380                                         else {
 381                                                 skb_put_data(skb,
 382                                                              bcs->hw.hdlc.rcvbuf,
 383                                                              bcs->hw.hdlc.rcvidx);
 384                                                 skb_queue_tail(&bcs->rqueue, skb);
 385                                         }
 386                                         bcs->hw.hdlc.rcvidx = 0;
 387                                         schedule_event(bcs, B_RCVBUFREADY);
 388                                 } else {
 389                                         if (bcs->cs->debug & L1_DEB_HSCX)
 390                                                 debugl1(bcs->cs, "invalid frame");
 391                                         else
 392                                                 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
 393                                         bcs->hw.hdlc.rcvidx = 0;
 394                                 }
 395                         }
 396                 }
 397         }
 398         if (stat & HDLC_INT_XDU) {
 399                 /* Here we lost an TX interrupt, so
 400                  * restart transmitting the whole frame.
 401                  */
 402                 if (bcs->tx_skb) {
 403                         skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
 404                         bcs->tx_cnt += bcs->hw.hdlc.count;
 405                         bcs->hw.hdlc.count = 0;
 406                         if (bcs->cs->debug & L1_DEB_WARN)
 407                                 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
 408                 } else if (bcs->cs->debug & L1_DEB_WARN)
 409                         debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
 410                 bcs->hw.hdlc.ctrl.sr.xml = 0;
 411                 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
 412                 write_ctrl(bcs, 1);
 413                 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
 414                 write_ctrl(bcs, 1);
 415                 hdlc_fill_fifo(bcs);
 416         } else if (stat & HDLC_INT_XPR) {
 417                 if (bcs->tx_skb) {
 418                         if (bcs->tx_skb->len) {
 419                                 hdlc_fill_fifo(bcs);
 420                                 return;
 421                         } else {
 422                                 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
 423                                     (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
 424                                         u_long flags;
 425                                         spin_lock_irqsave(&bcs->aclock, flags);
 426                                         bcs->ackcnt += bcs->hw.hdlc.count;
 427                                         spin_unlock_irqrestore(&bcs->aclock, flags);
 428                                         schedule_event(bcs, B_ACKPENDING);
 429                                 }
 430                                 dev_kfree_skb_irq(bcs->tx_skb);
 431                                 bcs->hw.hdlc.count = 0;
 432                                 bcs->tx_skb = NULL;
 433                         }
 434                 }
 435                 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 436                         bcs->hw.hdlc.count = 0;
 437                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
 438                         hdlc_fill_fifo(bcs);
 439                 } else {
 440                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 441                         schedule_event(bcs, B_XMTBUFREADY);
 442                 }
 443         }
 444 }
 445
 446 static inline void
 447 HDLC_irq_main(struct IsdnCardState *cs)
 448 {
 449         u_int stat;
 450         struct BCState *bcs;
 451
 452         if (cs->subtyp == AVM_FRITZ_PCI) {
 453                 stat = ReadHDLCPCI(cs, 0, HDLC_STATUS);
 454         } else {
 455                 stat = ReadHDLCPnP(cs, 0, HDLC_STATUS);
 456                 if (stat & HDLC_INT_RPR)
 457                         stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS + 1)) << 8;
 458         }
 459         if (stat & HDLC_INT_MASK) {
 460                 if (!(bcs = Sel_BCS(cs, 0))) {
 461                         if (cs->debug)
 462                                 debugl1(cs, "hdlc spurious channel 0 IRQ");
 463                 } else
 464                         HDLC_irq(bcs, stat);
 465         }
 466         if (cs->subtyp == AVM_FRITZ_PCI) {
 467                 stat = ReadHDLCPCI(cs, 1, HDLC_STATUS);
 468         } else {
 469                 stat = ReadHDLCPnP(cs, 1, HDLC_STATUS);
 470                 if (stat & HDLC_INT_RPR)
 471                         stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS + 1)) << 8;
 472         }
 473         if (stat & HDLC_INT_MASK) {
 474                 if (!(bcs = Sel_BCS(cs, 1))) {
 475                         if (cs->debug)
 476                                 debugl1(cs, "hdlc spurious channel 1 IRQ");
 477                 } else
 478                         HDLC_irq(bcs, stat);
 479         }
 480 }
 481
 482 static void
 483 hdlc_l2l1(struct PStack *st, int pr, void *arg)
 484 {
 485         struct BCState *bcs = st->l1.bcs;
 486         struct sk_buff *skb = arg;
 487         u_long flags;
 488
 489         switch (pr) {
 490         case (PH_DATA | REQUEST):
 491                 spin_lock_irqsave(&bcs->cs->lock, flags);
 492                 if (bcs->tx_skb) {
 493                         skb_queue_tail(&bcs->squeue, skb);
 494                 } else {
 495                         bcs->tx_skb = skb;
 496                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
 497                         bcs->hw.hdlc.count = 0;
 498                         bcs->cs->BC_Send_Data(bcs);
 499                 }
 500                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 501                 break;
 502         case (PH_PULL | INDICATION):
 503                 spin_lock_irqsave(&bcs->cs->lock, flags);
 504                 if (bcs->tx_skb) {
 505                         printk(KERN_WARNING "hdlc_l2l1: this shouldn't happen\n");
 506                 } else {
 507                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
 508                         bcs->tx_skb = skb;
 509                         bcs->hw.hdlc.count = 0;
 510                         bcs->cs->BC_Send_Data(bcs);
 511                 }
 512                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 513                 break;
 514         case (PH_PULL | REQUEST):
 515                 if (!bcs->tx_skb) {
 516                         test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 517                         st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 518                 } else
 519                         test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 520                 break;
 521         case (PH_ACTIVATE | REQUEST):
 522                 spin_lock_irqsave(&bcs->cs->lock, flags);
 523                 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
 524                 modehdlc(bcs, st->l1.mode, st->l1.bc);
 525                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 526                 l1_msg_b(st, pr, arg);
 527                 break;
 528         case (PH_DEACTIVATE | REQUEST):
 529                 l1_msg_b(st, pr, arg);
 530                 break;
 531         case (PH_DEACTIVATE | CONFIRM):
 532                 spin_lock_irqsave(&bcs->cs->lock, flags);
 533                 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
 534                 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 535                 modehdlc(bcs, 0, st->l1.bc);
 536                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 537                 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
 538                 break;
 539         }
 540 }
 541
 542 static void
 543 close_hdlcstate(struct BCState *bcs)
 544 {
 545         modehdlc(bcs, 0, 0);
 546         if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
 547                 kfree(bcs->hw.hdlc.rcvbuf);
 548                 bcs->hw.hdlc.rcvbuf = NULL;
 549                 kfree(bcs->blog);
 550                 bcs->blog = NULL;
 551                 skb_queue_purge(&bcs->rqueue);
 552                 skb_queue_purge(&bcs->squeue);
 553                 if (bcs->tx_skb) {
 554                         dev_kfree_skb_any(bcs->tx_skb);
 555                         bcs->tx_skb = NULL;
 556                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 557                 }
 558         }
 559 }
 560
 561 static int
 562 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
 563 {
 564         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
 565                 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
 566                         printk(KERN_WARNING
 567                                "HiSax: No memory for hdlc.rcvbuf\n");
 568                         return (1);
 569                 }
 570                 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
 571                         printk(KERN_WARNING
 572                                "HiSax: No memory for bcs->blog\n");
 573                         test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
 574                         kfree(bcs->hw.hdlc.rcvbuf);
 575                         bcs->hw.hdlc.rcvbuf = NULL;
 576                         return (2);
 577                 }
 578                 skb_queue_head_init(&bcs->rqueue);
 579                 skb_queue_head_init(&bcs->squeue);
 580         }
 581         bcs->tx_skb = NULL;
 582         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 583         bcs->event = 0;
 584         bcs->hw.hdlc.rcvidx = 0;
 585         bcs->tx_cnt = 0;
 586         return (0);
 587 }
 588
 589 static int
 590 setstack_hdlc(struct PStack *st, struct BCState *bcs)
 591 {
 592         bcs->channel = st->l1.bc;
 593         if (open_hdlcstate(st->l1.hardware, bcs))
 594                 return (-1);
 595         st->l1.bcs = bcs;
 596         st->l2.l2l1 = hdlc_l2l1;
 597         setstack_manager(st);
 598         bcs->st = st;
 599         setstack_l1_B(st);
 600         return (0);
 601 }
 602
 603 #if 0
 604 void __init
 605 clear_pending_hdlc_ints(struct IsdnCardState *cs)
 606 {
 607         u_int val;
 608
 609         if (cs->subtyp == AVM_FRITZ_PCI) {
 610                 val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
 611                 debugl1(cs, "HDLC 1 STA %x", val);
 612                 val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
 613                 debugl1(cs, "HDLC 2 STA %x", val);
 614         } else {
 615                 val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
 616                 debugl1(cs, "HDLC 1 STA %x", val);
 617                 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
 618                 debugl1(cs, "HDLC 1 RML %x", val);
 619                 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
 620                 debugl1(cs, "HDLC 1 MODE %x", val);
 621                 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
 622                 debugl1(cs, "HDLC 1 VIN %x", val);
 623                 val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
 624                 debugl1(cs, "HDLC 2 STA %x", val);
 625                 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
 626                 debugl1(cs, "HDLC 2 RML %x", val);
 627                 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
 628                 debugl1(cs, "HDLC 2 MODE %x", val);
 629                 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
 630                 debugl1(cs, "HDLC 2 VIN %x", val);
 631         }
 632 }
 633 #endif  /*  0  */
 634
 635 static void
 636 inithdlc(struct IsdnCardState *cs)
 637 {
 638         cs->bcs[0].BC_SetStack = setstack_hdlc;
 639         cs->bcs[1].BC_SetStack = setstack_hdlc;
 640         cs->bcs[0].BC_Close = close_hdlcstate;
 641         cs->bcs[1].BC_Close = close_hdlcstate;
 642         modehdlc(cs->bcs, -1, 0);
 643         modehdlc(cs->bcs + 1, -1, 1);
 644 }
 645
 646 static irqreturn_t
 647 avm_pcipnp_interrupt(int intno, void *dev_id)
 648 {
 649         struct IsdnCardState *cs = dev_id;
 650         u_long flags;
 651         u_char val;
 652         u_char sval;
 653
 654         spin_lock_irqsave(&cs->lock, flags);
 655         sval = inb(cs->hw.avm.cfg_reg + 2);
 656         if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) {
 657                 /* possible a shared  IRQ reqest */
 658                 spin_unlock_irqrestore(&cs->lock, flags);
 659                 return IRQ_NONE;
 660         }
 661         if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
 662                 val = ReadISAC(cs, ISAC_ISTA);
 663                 isac_interrupt(cs, val);
 664         }
 665         if (!(sval & AVM_STATUS0_IRQ_HDLC)) {
 666                 HDLC_irq_main(cs);
 667         }
 668         WriteISAC(cs, ISAC_MASK, 0xFF);
 669         WriteISAC(cs, ISAC_MASK, 0x0);
 670         spin_unlock_irqrestore(&cs->lock, flags);
 671         return IRQ_HANDLED;
 672 }
 673
 674 static void
 675 reset_avmpcipnp(struct IsdnCardState *cs)
 676 {
 677         printk(KERN_INFO "AVM PCI/PnP: reset\n");
 678         outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
 679         mdelay(10);
 680         outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
 681         outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
 682         mdelay(10);
 683         printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
 684 }
 685
 686 static int
 687 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
 688 {
 689         u_long flags;
 690
 691         switch (mt) {
 692         case CARD_RESET:
 693                 spin_lock_irqsave(&cs->lock, flags);
 694                 reset_avmpcipnp(cs);
 695                 spin_unlock_irqrestore(&cs->lock, flags);
 696                 return (0);
 697         case CARD_RELEASE:
 698                 outb(0, cs->hw.avm.cfg_reg + 2);
 699                 release_region(cs->hw.avm.cfg_reg, 32);
 700                 return (0);
 701         case CARD_INIT:
 702                 spin_lock_irqsave(&cs->lock, flags);
 703                 reset_avmpcipnp(cs);
 704                 clear_pending_isac_ints(cs);
 705                 initisac(cs);
 706                 inithdlc(cs);
 707                 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER,
 708                      cs->hw.avm.cfg_reg + 2);
 709                 WriteISAC(cs, ISAC_MASK, 0);
 710                 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER |
 711                      AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
 712                 /* RESET Receiver and Transmitter */
 713                 WriteISAC(cs, ISAC_CMDR, 0x41);
 714                 spin_unlock_irqrestore(&cs->lock, flags);
 715                 return (0);
 716         case CARD_TEST:
 717                 return (0);
 718         }
 719         return (0);
 720 }
 721
 722 static int avm_setup_rest(struct IsdnCardState *cs)
 723 {
 724         u_int val, ver;
 725
 726         cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
 727         if (!request_region(cs->hw.avm.cfg_reg, 32,
 728                             (cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP")) {
 729                 printk(KERN_WARNING
 730                        "HiSax: Fritz!PCI/PNP config port %x-%x already in use\n",
 731                        cs->hw.avm.cfg_reg,
 732                        cs->hw.avm.cfg_reg + 31);
 733                 return (0);
 734         }
 735         switch (cs->subtyp) {
 736         case AVM_FRITZ_PCI:
 737                 val = inl(cs->hw.avm.cfg_reg);
 738                 printk(KERN_INFO "AVM PCI: stat %#x\n", val);
 739                 printk(KERN_INFO "AVM PCI: Class %X Rev %d\n",
 740                        val & 0xff, (val >> 8) & 0xff);
 741                 cs->BC_Read_Reg = &ReadHDLC_s;
 742                 cs->BC_Write_Reg = &WriteHDLC_s;
 743                 break;
 744         case AVM_FRITZ_PNP:
 745                 val = inb(cs->hw.avm.cfg_reg);
 746                 ver = inb(cs->hw.avm.cfg_reg + 1);
 747                 printk(KERN_INFO "AVM PnP: Class %X Rev %d\n", val, ver);
 748                 cs->BC_Read_Reg = &ReadHDLCPnP;
 749                 cs->BC_Write_Reg = &WriteHDLCPnP;
 750                 break;
 751         default:
 752                 printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp);
 753                 return (0);
 754         }
 755         printk(KERN_INFO "HiSax: %s config irq:%d base:0x%X\n",
 756                (cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP",
 757                cs->irq, cs->hw.avm.cfg_reg);
 758
 759         setup_isac(cs);
 760         cs->readisac = &ReadISAC;
 761         cs->writeisac = &WriteISAC;
 762         cs->readisacfifo = &ReadISACfifo;
 763         cs->writeisacfifo = &WriteISACfifo;
 764         cs->BC_Send_Data = &hdlc_fill_fifo;
 765         cs->cardmsg = &AVM_card_msg;
 766         cs->irq_func = &avm_pcipnp_interrupt;
 767         cs->writeisac(cs, ISAC_MASK, 0xFF);
 768         ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:");
 769         return (1);
 770 }
 771
 772 #ifndef __ISAPNP__
 773
 774 static int avm_pnp_setup(struct IsdnCardState *cs)
 775 {
 776         return (1);     /* no-op: success */
 777 }
 778
 779 #else
 780
 781 static struct pnp_card *pnp_avm_c = NULL;
 782
 783 static int avm_pnp_setup(struct IsdnCardState *cs)
 784 {
 785         struct pnp_dev *pnp_avm_d = NULL;
 786
 787         if (!isapnp_present())
 788                 return (1);     /* no-op: success */
 789
 790         if ((pnp_avm_c = pnp_find_card(
 791                      ISAPNP_VENDOR('A', 'V', 'M'),
 792                      ISAPNP_FUNCTION(0x0900), pnp_avm_c))) {
 793                 if ((pnp_avm_d = pnp_find_dev(pnp_avm_c,
 794                                               ISAPNP_VENDOR('A', 'V', 'M'),
 795                                               ISAPNP_FUNCTION(0x0900), pnp_avm_d))) {
 796                         int err;
 797
 798                         pnp_disable_dev(pnp_avm_d);
 799                         err = pnp_activate_dev(pnp_avm_d);
 800                         if (err < 0) {
 801                                 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
 802                                        __func__, err);
 803                                 return (0);
 804                         }
 805                         cs->hw.avm.cfg_reg =
 806                                 pnp_port_start(pnp_avm_d, 0);
 807                         cs->irq = pnp_irq(pnp_avm_d, 0);
 808                         if (!cs->irq) {
 809                                 printk(KERN_ERR "FritzPnP:No IRQ\n");
 810                                 return (0);
 811                         }
 812                         if (!cs->hw.avm.cfg_reg) {
 813                                 printk(KERN_ERR "FritzPnP:No IO address\n");
 814                                 return (0);
 815                         }
 816                         cs->subtyp = AVM_FRITZ_PNP;
 817
 818                         return (2);     /* goto 'ready' label */
 819                 }
 820         }
 821
 822         return (1);
 823 }
 824
 825 #endif /* __ISAPNP__ */
 826
 827 #ifndef CONFIG_PCI
 828
 829 static int avm_pci_setup(struct IsdnCardState *cs)
 830 {
 831         return (1);     /* no-op: success */
 832 }
 833
 834 #else
 835
 836 static struct pci_dev *dev_avm = NULL;
 837
 838 static int avm_pci_setup(struct IsdnCardState *cs)
 839 {
 840         if ((dev_avm = hisax_find_pci_device(PCI_VENDOR_ID_AVM,
 841                                              PCI_DEVICE_ID_AVM_A1, dev_avm))) {
 842
 843                 if (pci_enable_device(dev_avm))
 844                         return (0);
 845
 846                 cs->irq = dev_avm->irq;
 847                 if (!cs->irq) {
 848                         printk(KERN_ERR "FritzPCI: No IRQ for PCI card found\n");
 849                         return (0);
 850                 }
 851
 852                 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1);
 853                 if (!cs->hw.avm.cfg_reg) {
 854                         printk(KERN_ERR "FritzPCI: No IO-Adr for PCI card found\n");
 855                         return (0);
 856                 }
 857
 858                 cs->subtyp = AVM_FRITZ_PCI;
 859         } else {
 860                 printk(KERN_WARNING "FritzPCI: No PCI card found\n");
 861                 return (0);
 862         }
 863
 864         cs->irq_flags |= IRQF_SHARED;
 865
 866         return (1);
 867 }
 868
 869 #endif /* CONFIG_PCI */
 870
 871 int setup_avm_pcipnp(struct IsdnCard *card)
 872 {
 873         struct IsdnCardState *cs = card->cs;
 874         char tmp[64];
 875         int rc;
 876
 877         strcpy(tmp, avm_pci_rev);
 878         printk(KERN_INFO "HiSax: AVM PCI driver Rev. %s\n", HiSax_getrev(tmp));
 879
 880         if (cs->typ != ISDN_CTYPE_FRITZPCI)
 881                 return (0);
 882
 883         if (card->para[1]) {
 884                 /* old manual method */
 885                 cs->hw.avm.cfg_reg = card->para[1];
 886                 cs->irq = card->para[0];
 887                 cs->subtyp = AVM_FRITZ_PNP;
 888                 goto ready;
 889         }
 890
 891         rc = avm_pnp_setup(cs);
 892         if (rc < 1)
 893                 return (0);
 894         if (rc == 2)
 895                 goto ready;
 896
 897         rc = avm_pci_setup(cs);
 898         if (rc < 1)
 899                 return (0);
 900
 901 ready:
 902         return avm_setup_rest(cs);
 903 }