1 /* $Id: avm_pci.c,v 1.29.2.4 2004/02/11 13:21:32 keil Exp $
3 * low level stuff for AVM Fritz!PCI and ISA PnP isdn cards
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
11 * Thanks to AVM, Berlin for information
15 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/isapnp.h>
22 #include <linux/interrupt.h>
24 static const char *avm_pci_rev = "$Revision: 1.29.2.4 $";
26 #define AVM_FRITZ_PCI 1
27 #define AVM_FRITZ_PNP 2
30 #define HDLC_STATUS 0x4
32 #define AVM_HDLC_1 0x00
33 #define AVM_HDLC_2 0x01
34 #define AVM_ISAC_FIFO 0x02
35 #define AVM_ISAC_REG_LOW 0x04
36 #define AVM_ISAC_REG_HIGH 0x06
38 #define AVM_STATUS0_IRQ_ISAC 0x01
39 #define AVM_STATUS0_IRQ_HDLC 0x02
40 #define AVM_STATUS0_IRQ_TIMER 0x04
41 #define AVM_STATUS0_IRQ_MASK 0x07
43 #define AVM_STATUS0_RESET 0x01
44 #define AVM_STATUS0_DIS_TIMER 0x02
45 #define AVM_STATUS0_RES_TIMER 0x04
46 #define AVM_STATUS0_ENA_IRQ 0x08
47 #define AVM_STATUS0_TESTBIT 0x10
49 #define AVM_STATUS1_INT_SEL 0x0f
50 #define AVM_STATUS1_ENA_IOM 0x80
52 #define HDLC_MODE_ITF_FLG 0x01
53 #define HDLC_MODE_TRANS 0x02
54 #define HDLC_MODE_CCR_7 0x04
55 #define HDLC_MODE_CCR_16 0x08
56 #define HDLC_MODE_TESTLOOP 0x80
58 #define HDLC_INT_XPR 0x80
59 #define HDLC_INT_XDU 0x40
60 #define HDLC_INT_RPR 0x20
61 #define HDLC_INT_MASK 0xE0
63 #define HDLC_STAT_RME 0x01
64 #define HDLC_STAT_RDO 0x10
65 #define HDLC_STAT_CRCVFRRAB 0x0E
66 #define HDLC_STAT_CRCVFR 0x06
67 #define HDLC_STAT_RML_MASK 0x3f00
69 #define HDLC_CMD_XRS 0x80
70 #define HDLC_CMD_XME 0x01
71 #define HDLC_CMD_RRS 0x20
72 #define HDLC_CMD_XML_MASK 0x3f00
75 /* Interface functions */
78 ReadISAC(struct IsdnCardState *cs, u_char offset)
80 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
83 outb(idx, cs->hw.avm.cfg_reg + 4);
84 val = inb(cs->hw.avm.isac + (offset & 0xf));
89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
91 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
93 outb(idx, cs->hw.avm.cfg_reg + 4);
94 outb(value, cs->hw.avm.isac + (offset & 0xf));
98 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
101 insb(cs->hw.avm.isac, data, size);
105 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
108 outsb(cs->hw.avm.isac, data, size);
112 ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset)
114 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
117 outl(idx, cs->hw.avm.cfg_reg + 4);
118 val = inl(cs->hw.avm.isac + offset);
123 WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value)
125 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
127 outl(idx, cs->hw.avm.cfg_reg + 4);
128 outl(value, cs->hw.avm.isac + offset);
132 ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset)
134 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
137 outb(idx, cs->hw.avm.cfg_reg + 4);
138 val = inb(cs->hw.avm.isac + offset);
143 WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
145 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
147 outb(idx, cs->hw.avm.cfg_reg + 4);
148 outb(value, cs->hw.avm.isac + offset);
152 ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset)
154 return (0xff & ReadHDLCPCI(cs, chan, offset));
158 WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
160 WriteHDLCPCI(cs, chan, offset, value);
164 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
166 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
167 return (&cs->bcs[0]);
168 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
169 return (&cs->bcs[1]);
175 write_ctrl(struct BCState *bcs, int which) {
177 if (bcs->cs->debug & L1_DEB_HSCX)
178 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
179 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
180 if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
184 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
185 bcs->hw.hdlc.ctrl.sr.mode);
187 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
188 bcs->hw.hdlc.ctrl.sr.xml);
190 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
191 bcs->hw.hdlc.ctrl.sr.cmd);
196 modehdlc(struct BCState *bcs, int mode, int bc)
198 struct IsdnCardState *cs = bcs->cs;
199 int hdlc = bcs->channel;
201 if (cs->debug & L1_DEB_HSCX)
202 debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d",
203 'A' + hdlc, bcs->mode, mode, hdlc, bc);
204 bcs->hw.hdlc.ctrl.ctrl = 0;
206 case (-1): /* used for init */
212 if (bcs->mode == L1_MODE_NULL)
214 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
215 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
217 bcs->mode = L1_MODE_NULL;
220 case (L1_MODE_TRANS):
223 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
224 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
226 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
228 bcs->hw.hdlc.ctrl.sr.cmd = 0;
229 schedule_event(bcs, B_XMTBUFREADY);
234 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
235 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
237 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
239 bcs->hw.hdlc.ctrl.sr.cmd = 0;
240 schedule_event(bcs, B_XMTBUFREADY);
246 hdlc_empty_fifo(struct BCState *bcs, int count)
250 u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
252 struct IsdnCardState *cs = bcs->cs;
254 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
255 debugl1(cs, "hdlc_empty_fifo %d", count);
256 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
257 if (cs->debug & L1_DEB_WARN)
258 debugl1(cs, "hdlc_empty_fifo: incoming packet too large");
261 p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
263 bcs->hw.hdlc.rcvidx += count;
264 if (cs->subtyp == AVM_FRITZ_PCI) {
265 outl(idx, cs->hw.avm.cfg_reg + 4);
266 while (cnt < count) {
268 *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE));
270 *ptr++ = inl(cs->hw.avm.isac);
271 #endif /* __powerpc__ */
275 outb(idx, cs->hw.avm.cfg_reg + 4);
276 while (cnt < count) {
277 *p++ = inb(cs->hw.avm.isac);
281 if (cs->debug & L1_DEB_HSCX_FIFO) {
284 if (cs->subtyp == AVM_FRITZ_PNP)
286 t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
287 bcs->channel ? 'B' : 'A', count);
288 QuickHex(t, p, count);
289 debugl1(cs, "%s", bcs->blog);
294 hdlc_fill_fifo(struct BCState *bcs)
296 struct IsdnCardState *cs = bcs->cs;
302 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
303 debugl1(cs, "hdlc_fill_fifo");
306 if (bcs->tx_skb->len <= 0)
309 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
310 if (bcs->tx_skb->len > fifo_size) {
313 count = bcs->tx_skb->len;
314 if (bcs->mode != L1_MODE_TRANS)
315 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
317 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
318 debugl1(cs, "hdlc_fill_fifo %d/%u", count, bcs->tx_skb->len);
319 p = bcs->tx_skb->data;
321 skb_pull(bcs->tx_skb, count);
322 bcs->tx_cnt -= count;
323 bcs->hw.hdlc.count += count;
324 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
325 write_ctrl(bcs, 3); /* sets the correct index too */
326 if (cs->subtyp == AVM_FRITZ_PCI) {
327 while (cnt < count) {
329 out_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE), *ptr++);
331 outl(*ptr++, cs->hw.avm.isac);
332 #endif /* __powerpc__ */
336 while (cnt < count) {
337 outb(*p++, cs->hw.avm.isac);
341 if (cs->debug & L1_DEB_HSCX_FIFO) {
344 if (cs->subtyp == AVM_FRITZ_PNP)
346 t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
347 bcs->channel ? 'B' : 'A', count);
348 QuickHex(t, p, count);
349 debugl1(cs, "%s", bcs->blog);
354 HDLC_irq(struct BCState *bcs, u_int stat) {
358 if (bcs->cs->debug & L1_DEB_HSCX)
359 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
360 if (stat & HDLC_INT_RPR) {
361 if (stat & HDLC_STAT_RDO) {
362 if (bcs->cs->debug & L1_DEB_HSCX)
363 debugl1(bcs->cs, "RDO");
365 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
366 bcs->hw.hdlc.ctrl.sr.xml = 0;
367 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
369 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
371 bcs->hw.hdlc.rcvidx = 0;
373 if (!(len = (stat & HDLC_STAT_RML_MASK) >> 8))
375 hdlc_empty_fifo(bcs, len);
376 if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
377 if (((stat & HDLC_STAT_CRCVFRRAB) == HDLC_STAT_CRCVFR) ||
378 (bcs->mode == L1_MODE_TRANS)) {
379 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
380 printk(KERN_WARNING "HDLC: receive out of memory\n");
384 bcs->hw.hdlc.rcvidx);
385 skb_queue_tail(&bcs->rqueue, skb);
387 bcs->hw.hdlc.rcvidx = 0;
388 schedule_event(bcs, B_RCVBUFREADY);
390 if (bcs->cs->debug & L1_DEB_HSCX)
391 debugl1(bcs->cs, "invalid frame");
393 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
394 bcs->hw.hdlc.rcvidx = 0;
399 if (stat & HDLC_INT_XDU) {
400 /* Here we lost an TX interrupt, so
401 * restart transmitting the whole frame.
404 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
405 bcs->tx_cnt += bcs->hw.hdlc.count;
406 bcs->hw.hdlc.count = 0;
407 if (bcs->cs->debug & L1_DEB_WARN)
408 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
409 } else if (bcs->cs->debug & L1_DEB_WARN)
410 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
411 bcs->hw.hdlc.ctrl.sr.xml = 0;
412 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
414 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
417 } else if (stat & HDLC_INT_XPR) {
419 if (bcs->tx_skb->len) {
423 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
424 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
426 spin_lock_irqsave(&bcs->aclock, flags);
427 bcs->ackcnt += bcs->hw.hdlc.count;
428 spin_unlock_irqrestore(&bcs->aclock, flags);
429 schedule_event(bcs, B_ACKPENDING);
431 dev_kfree_skb_irq(bcs->tx_skb);
432 bcs->hw.hdlc.count = 0;
436 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
437 bcs->hw.hdlc.count = 0;
438 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
441 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
442 schedule_event(bcs, B_XMTBUFREADY);
448 HDLC_irq_main(struct IsdnCardState *cs)
453 if (cs->subtyp == AVM_FRITZ_PCI) {
454 stat = ReadHDLCPCI(cs, 0, HDLC_STATUS);
456 stat = ReadHDLCPnP(cs, 0, HDLC_STATUS);
457 if (stat & HDLC_INT_RPR)
458 stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS + 1)) << 8;
460 if (stat & HDLC_INT_MASK) {
461 if (!(bcs = Sel_BCS(cs, 0))) {
463 debugl1(cs, "hdlc spurious channel 0 IRQ");
467 if (cs->subtyp == AVM_FRITZ_PCI) {
468 stat = ReadHDLCPCI(cs, 1, HDLC_STATUS);
470 stat = ReadHDLCPnP(cs, 1, HDLC_STATUS);
471 if (stat & HDLC_INT_RPR)
472 stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS + 1)) << 8;
474 if (stat & HDLC_INT_MASK) {
475 if (!(bcs = Sel_BCS(cs, 1))) {
477 debugl1(cs, "hdlc spurious channel 1 IRQ");
484 hdlc_l2l1(struct PStack *st, int pr, void *arg)
486 struct BCState *bcs = st->l1.bcs;
487 struct sk_buff *skb = arg;
491 case (PH_DATA | REQUEST):
492 spin_lock_irqsave(&bcs->cs->lock, flags);
494 skb_queue_tail(&bcs->squeue, skb);
497 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
498 bcs->hw.hdlc.count = 0;
499 bcs->cs->BC_Send_Data(bcs);
501 spin_unlock_irqrestore(&bcs->cs->lock, flags);
503 case (PH_PULL | INDICATION):
504 spin_lock_irqsave(&bcs->cs->lock, flags);
506 printk(KERN_WARNING "hdlc_l2l1: this shouldn't happen\n");
508 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
510 bcs->hw.hdlc.count = 0;
511 bcs->cs->BC_Send_Data(bcs);
513 spin_unlock_irqrestore(&bcs->cs->lock, flags);
515 case (PH_PULL | REQUEST):
517 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
518 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
520 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
522 case (PH_ACTIVATE | REQUEST):
523 spin_lock_irqsave(&bcs->cs->lock, flags);
524 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
525 modehdlc(bcs, st->l1.mode, st->l1.bc);
526 spin_unlock_irqrestore(&bcs->cs->lock, flags);
527 l1_msg_b(st, pr, arg);
529 case (PH_DEACTIVATE | REQUEST):
530 l1_msg_b(st, pr, arg);
532 case (PH_DEACTIVATE | CONFIRM):
533 spin_lock_irqsave(&bcs->cs->lock, flags);
534 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
535 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
536 modehdlc(bcs, 0, st->l1.bc);
537 spin_unlock_irqrestore(&bcs->cs->lock, flags);
538 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
544 close_hdlcstate(struct BCState *bcs)
547 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
548 kfree(bcs->hw.hdlc.rcvbuf);
549 bcs->hw.hdlc.rcvbuf = NULL;
552 skb_queue_purge(&bcs->rqueue);
553 skb_queue_purge(&bcs->squeue);
555 dev_kfree_skb_any(bcs->tx_skb);
557 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
563 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
565 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
566 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
568 "HiSax: No memory for hdlc.rcvbuf\n");
571 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
573 "HiSax: No memory for bcs->blog\n");
574 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
575 kfree(bcs->hw.hdlc.rcvbuf);
576 bcs->hw.hdlc.rcvbuf = NULL;
579 skb_queue_head_init(&bcs->rqueue);
580 skb_queue_head_init(&bcs->squeue);
583 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
585 bcs->hw.hdlc.rcvidx = 0;
591 setstack_hdlc(struct PStack *st, struct BCState *bcs)
593 bcs->channel = st->l1.bc;
594 if (open_hdlcstate(st->l1.hardware, bcs))
597 st->l2.l2l1 = hdlc_l2l1;
598 setstack_manager(st);
606 clear_pending_hdlc_ints(struct IsdnCardState *cs)
610 if (cs->subtyp == AVM_FRITZ_PCI) {
611 val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
612 debugl1(cs, "HDLC 1 STA %x", val);
613 val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
614 debugl1(cs, "HDLC 2 STA %x", val);
616 val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
617 debugl1(cs, "HDLC 1 STA %x", val);
618 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
619 debugl1(cs, "HDLC 1 RML %x", val);
620 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
621 debugl1(cs, "HDLC 1 MODE %x", val);
622 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
623 debugl1(cs, "HDLC 1 VIN %x", val);
624 val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
625 debugl1(cs, "HDLC 2 STA %x", val);
626 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
627 debugl1(cs, "HDLC 2 RML %x", val);
628 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
629 debugl1(cs, "HDLC 2 MODE %x", val);
630 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
631 debugl1(cs, "HDLC 2 VIN %x", val);
637 inithdlc(struct IsdnCardState *cs)
639 cs->bcs[0].BC_SetStack = setstack_hdlc;
640 cs->bcs[1].BC_SetStack = setstack_hdlc;
641 cs->bcs[0].BC_Close = close_hdlcstate;
642 cs->bcs[1].BC_Close = close_hdlcstate;
643 modehdlc(cs->bcs, -1, 0);
644 modehdlc(cs->bcs + 1, -1, 1);
648 avm_pcipnp_interrupt(int intno, void *dev_id)
650 struct IsdnCardState *cs = dev_id;
655 spin_lock_irqsave(&cs->lock, flags);
656 sval = inb(cs->hw.avm.cfg_reg + 2);
657 if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) {
658 /* possible a shared IRQ reqest */
659 spin_unlock_irqrestore(&cs->lock, flags);
662 if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
663 val = ReadISAC(cs, ISAC_ISTA);
664 isac_interrupt(cs, val);
666 if (!(sval & AVM_STATUS0_IRQ_HDLC)) {
669 WriteISAC(cs, ISAC_MASK, 0xFF);
670 WriteISAC(cs, ISAC_MASK, 0x0);
671 spin_unlock_irqrestore(&cs->lock, flags);
676 reset_avmpcipnp(struct IsdnCardState *cs)
678 printk(KERN_INFO "AVM PCI/PnP: reset\n");
679 outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
681 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
682 outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
684 printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
688 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
694 spin_lock_irqsave(&cs->lock, flags);
696 spin_unlock_irqrestore(&cs->lock, flags);
699 outb(0, cs->hw.avm.cfg_reg + 2);
700 release_region(cs->hw.avm.cfg_reg, 32);
703 spin_lock_irqsave(&cs->lock, flags);
705 clear_pending_isac_ints(cs);
708 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER,
709 cs->hw.avm.cfg_reg + 2);
710 WriteISAC(cs, ISAC_MASK, 0);
711 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER |
712 AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
713 /* RESET Receiver and Transmitter */
714 WriteISAC(cs, ISAC_CMDR, 0x41);
715 spin_unlock_irqrestore(&cs->lock, flags);
723 static int avm_setup_rest(struct IsdnCardState *cs)
727 cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
728 if (!request_region(cs->hw.avm.cfg_reg, 32,
729 (cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP")) {
731 "HiSax: Fritz!PCI/PNP config port %x-%x already in use\n",
733 cs->hw.avm.cfg_reg + 31);
736 switch (cs->subtyp) {
738 val = inl(cs->hw.avm.cfg_reg);
739 printk(KERN_INFO "AVM PCI: stat %#x\n", val);
740 printk(KERN_INFO "AVM PCI: Class %X Rev %d\n",
741 val & 0xff, (val >> 8) & 0xff);
742 cs->BC_Read_Reg = &ReadHDLC_s;
743 cs->BC_Write_Reg = &WriteHDLC_s;
746 val = inb(cs->hw.avm.cfg_reg);
747 ver = inb(cs->hw.avm.cfg_reg + 1);
748 printk(KERN_INFO "AVM PnP: Class %X Rev %d\n", val, ver);
749 cs->BC_Read_Reg = &ReadHDLCPnP;
750 cs->BC_Write_Reg = &WriteHDLCPnP;
753 printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp);
756 printk(KERN_INFO "HiSax: %s config irq:%d base:0x%X\n",
757 (cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP",
758 cs->irq, cs->hw.avm.cfg_reg);
761 cs->readisac = &ReadISAC;
762 cs->writeisac = &WriteISAC;
763 cs->readisacfifo = &ReadISACfifo;
764 cs->writeisacfifo = &WriteISACfifo;
765 cs->BC_Send_Data = &hdlc_fill_fifo;
766 cs->cardmsg = &AVM_card_msg;
767 cs->irq_func = &avm_pcipnp_interrupt;
768 cs->writeisac(cs, ISAC_MASK, 0xFF);
769 ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:");
775 static int avm_pnp_setup(struct IsdnCardState *cs)
777 return (1); /* no-op: success */
782 static struct pnp_card *pnp_avm_c = NULL;
784 static int avm_pnp_setup(struct IsdnCardState *cs)
786 struct pnp_dev *pnp_avm_d = NULL;
788 if (!isapnp_present())
789 return (1); /* no-op: success */
791 if ((pnp_avm_c = pnp_find_card(
792 ISAPNP_VENDOR('A', 'V', 'M'),
793 ISAPNP_FUNCTION(0x0900), pnp_avm_c))) {
794 if ((pnp_avm_d = pnp_find_dev(pnp_avm_c,
795 ISAPNP_VENDOR('A', 'V', 'M'),
796 ISAPNP_FUNCTION(0x0900), pnp_avm_d))) {
799 pnp_disable_dev(pnp_avm_d);
800 err = pnp_activate_dev(pnp_avm_d);
802 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
807 pnp_port_start(pnp_avm_d, 0);
808 cs->irq = pnp_irq(pnp_avm_d, 0);
810 printk(KERN_ERR "FritzPnP:No IRQ\n");
813 if (!cs->hw.avm.cfg_reg) {
814 printk(KERN_ERR "FritzPnP:No IO address\n");
817 cs->subtyp = AVM_FRITZ_PNP;
819 return (2); /* goto 'ready' label */
826 #endif /* __ISAPNP__ */
830 static int avm_pci_setup(struct IsdnCardState *cs)
832 return (1); /* no-op: success */
837 static struct pci_dev *dev_avm = NULL;
839 static int avm_pci_setup(struct IsdnCardState *cs)
841 if ((dev_avm = hisax_find_pci_device(PCI_VENDOR_ID_AVM,
842 PCI_DEVICE_ID_AVM_A1, dev_avm))) {
844 if (pci_enable_device(dev_avm))
847 cs->irq = dev_avm->irq;
849 printk(KERN_ERR "FritzPCI: No IRQ for PCI card found\n");
853 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1);
854 if (!cs->hw.avm.cfg_reg) {
855 printk(KERN_ERR "FritzPCI: No IO-Adr for PCI card found\n");
859 cs->subtyp = AVM_FRITZ_PCI;
861 printk(KERN_WARNING "FritzPCI: No PCI card found\n");
865 cs->irq_flags |= IRQF_SHARED;
870 #endif /* CONFIG_PCI */
872 int setup_avm_pcipnp(struct IsdnCard *card)
874 struct IsdnCardState *cs = card->cs;
878 strcpy(tmp, avm_pci_rev);
879 printk(KERN_INFO "HiSax: AVM PCI driver Rev. %s\n", HiSax_getrev(tmp));
881 if (cs->typ != ISDN_CTYPE_FRITZPCI)
885 /* old manual method */
886 cs->hw.avm.cfg_reg = card->para[1];
887 cs->irq = card->para[0];
888 cs->subtyp = AVM_FRITZ_PNP;
892 rc = avm_pnp_setup(cs);
898 rc = avm_pci_setup(cs);
903 return avm_setup_rest(cs);