3 * hfcpci.c low level driver for CCD's hfc-pci based cards
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * NOTE: only one poll value must be given for all cards
30 * See hfc_pci.h for debug flags.
33 * NOTE: only one poll value must be given for all cards
34 * Give the number of samples for each fifo process.
35 * By default 128 is used. Decrease to reduce delay, increase to
36 * reduce cpu load. If unsure, don't mess with it!
37 * A value of 128 will use controller's interrupt. Other values will
38 * use kernel timer, because the controller will not allow lower values
40 * Also note that the value depends on the kernel timer frequency.
41 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
42 * If the kernel uses 100 Hz, steps of 80 samples are possible.
43 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
47 #include <linux/interrupt.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/mISDNhw.h>
52 #include <linux/slab.h>
56 static const char *hfcpci_revision = "2.0";
60 static uint poll, tics;
61 static struct timer_list hfc_tl;
62 static unsigned long hfc_jiffies;
64 MODULE_AUTHOR("Karsten Keil");
65 MODULE_LICENSE("GPL");
66 module_param(debug, uint, S_IRUGO | S_IWUSR);
67 module_param(poll, uint, S_IRUGO | S_IWUSR);
102 unsigned char int_m1;
103 unsigned char int_m2;
105 unsigned char sctrl_r;
106 unsigned char sctrl_e;
108 unsigned char fifo_en;
109 unsigned char bswapped;
110 unsigned char protocol;
112 unsigned char __iomem *pci_io; /* start of PCI IO memory */
113 dma_addr_t dmahandle;
114 void *fifos; /* FIFO memory */
115 int last_bfifo_cnt[2];
116 /* marker saving last b-fifo frame count */
117 struct timer_list timer;
120 #define HFC_CFG_MASTER 1
121 #define HFC_CFG_SLAVE 2
122 #define HFC_CFG_PCM 3
123 #define HFC_CFG_2HFC 4
124 #define HFC_CFG_SLAVEHFC 5
125 #define HFC_CFG_NEG_F0 6
126 #define HFC_CFG_SW_DD_DU 7
128 #define FLG_HFC_TIMER_T1 16
129 #define FLG_HFC_TIMER_T3 17
131 #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
132 #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
133 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
134 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
144 struct pci_dev *pdev;
146 spinlock_t lock; /* card lock */
148 struct bchannel bch[2];
151 /* Interface functions */
153 enable_hwirq(struct hfc_pci *hc)
155 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
156 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
160 disable_hwirq(struct hfc_pci *hc)
162 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
163 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
167 * free hardware resources used by driver
170 release_io_hfcpci(struct hfc_pci *hc)
172 /* disable memory mapped ports + busmaster */
173 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
174 del_timer(&hc->hw.timer);
175 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
176 iounmap(hc->hw.pci_io);
180 * set mode (NT or TE)
183 hfcpci_setmode(struct hfc_pci *hc)
185 if (hc->hw.protocol == ISDN_P_NT_S0) {
186 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
187 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
188 hc->hw.states = 1; /* G1 */
190 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
191 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
192 hc->hw.states = 2; /* F2 */
194 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
195 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
197 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
198 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
202 * function called to reset the HFC PCI chip. A complete software reset of chip
206 reset_hfcpci(struct hfc_pci *hc)
211 printk(KERN_DEBUG "reset_hfcpci: entered\n");
212 val = Read_hfc(hc, HFCPCI_CHIP_ID);
213 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
214 /* enable memory mapped ports, disable busmaster */
215 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
217 /* enable memory ports + busmaster */
218 pci_write_config_word(hc->pdev, PCI_COMMAND,
219 PCI_ENA_MEMIO + PCI_ENA_MASTER);
220 val = Read_hfc(hc, HFCPCI_STATUS);
221 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
222 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
223 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
224 set_current_state(TASK_UNINTERRUPTIBLE);
225 mdelay(10); /* Timeout 10ms */
226 hc->hw.cirm = 0; /* Reset Off */
227 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
228 val = Read_hfc(hc, HFCPCI_STATUS);
229 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
230 while (cnt < 50000) { /* max 50000 us */
233 val = Read_hfc(hc, HFCPCI_STATUS);
237 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
239 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
241 hc->hw.bswapped = 0; /* no exchange */
242 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
243 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
244 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
246 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
248 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
249 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
250 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
251 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
252 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
253 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
254 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
255 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
257 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
258 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
259 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
261 /* Clear already pending ints */
262 val = Read_hfc(hc, HFCPCI_INT_S1);
267 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
268 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
271 * Init GCI/IOM2 in master mode
272 * Slots 0 and 1 are set for B-chan 1 and 2
273 * D- and monitor/CI channel are not enabled
274 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
275 * STIO2 is used as data input, B1+B2 from IOM->ST
276 * ST B-channel send disabled -> continuous 1s
277 * The IOM slots are always enabled
279 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
280 /* set data flow directions: connect B1,B2: HFC to/from PCM */
283 hc->hw.conn = 0x36; /* set data flow directions */
284 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
285 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
286 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
287 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
288 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
290 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
291 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
292 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
293 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
296 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
297 val = Read_hfc(hc, HFCPCI_INT_S2);
301 * Timer function called when kernel timer expires
304 hfcpci_Timer(struct timer_list *t)
306 struct hfc_pci *hc = from_timer(hc, t, hw.timer);
307 hc->hw.timer.expires = jiffies + 75;
310 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
311 * add_timer(&hc->hw.timer);
317 * select a b-channel entry matching and active
319 static struct bchannel *
320 Sel_BCS(struct hfc_pci *hc, int channel)
322 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
323 (hc->bch[0].nr & channel))
325 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
326 (hc->bch[1].nr & channel))
333 * clear the desired B-channel rx fifo
336 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
342 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
343 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
345 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
346 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
349 hc->hw.fifo_en ^= fifo_state;
350 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
351 hc->hw.last_bfifo_cnt[fifo] = 0;
352 bzr->f1 = MAX_B_FRAMES;
353 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
354 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
355 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
356 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
358 hc->hw.fifo_en |= fifo_state;
359 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
363 * clear the desired B-channel tx fifo
365 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
371 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
372 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
374 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
375 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
378 hc->hw.fifo_en ^= fifo_state;
379 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
380 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
381 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
382 "z1(%x) z2(%x) state(%x)\n",
383 fifo, bzt->f1, bzt->f2,
384 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
385 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
387 bzt->f2 = MAX_B_FRAMES;
388 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
389 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
390 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
392 hc->hw.fifo_en |= fifo_state;
393 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
394 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
396 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
397 fifo, bzt->f1, bzt->f2,
398 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
399 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
403 * read a complete B-frame out of the buffer
406 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
407 u_char *bdata, int count)
409 u_char *ptr, *ptr1, new_f2;
413 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
414 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
415 zp = &bz->za[bz->f2]; /* point to Z-Regs */
416 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
417 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
418 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
419 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
420 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
421 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
422 if (bch->debug & DEBUG_HW)
423 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
424 "invalid length %d or crc\n", count);
425 #ifdef ERROR_STATISTIC
428 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
429 bz->f2 = new_f2; /* next buffer */
431 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
433 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
437 ptr = skb_put(bch->rx_skb, count);
439 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
440 maxlen = count; /* complete transfer */
442 maxlen = B_FIFO_SIZE + B_SUB_VAL -
443 le16_to_cpu(zp->z2); /* maximum */
445 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
447 memcpy(ptr, ptr1, maxlen); /* copy data */
450 if (count) { /* rest remaining */
452 ptr1 = bdata; /* start of buffer */
453 memcpy(ptr, ptr1, count); /* rest */
455 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
456 bz->f2 = new_f2; /* next buffer */
457 recv_Bchannel(bch, MISDN_ID_ANY, false);
462 * D-channel receive procedure
465 receive_dmsg(struct hfc_pci *hc)
467 struct dchannel *dch = &hc->dch;
475 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
476 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
477 zp = &df->za[df->f2 & D_FREG_MASK];
478 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
482 if (dch->debug & DEBUG_HW_DCHANNEL)
484 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
490 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
491 (df->data[le16_to_cpu(zp->z1)])) {
492 if (dch->debug & DEBUG_HW)
494 "empty_fifo hfcpci packet inv. len "
497 df->data[le16_to_cpu(zp->z1)]);
498 #ifdef ERROR_STATISTIC
501 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
502 (MAX_D_FRAMES + 1); /* next buffer */
503 df->za[df->f2 & D_FREG_MASK].z2 =
504 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
507 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
510 "HFC-PCI: D receive out of memory\n");
515 ptr = skb_put(dch->rx_skb, rcnt);
517 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
518 maxlen = rcnt; /* complete transfer */
520 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
523 ptr1 = df->data + le16_to_cpu(zp->z2);
525 memcpy(ptr, ptr1, maxlen); /* copy data */
528 if (rcnt) { /* rest remaining */
530 ptr1 = df->data; /* start of buffer */
531 memcpy(ptr, ptr1, rcnt); /* rest */
533 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
534 (MAX_D_FRAMES + 1); /* next buffer */
535 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
536 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
544 * check for transparent receive data and read max one 'poll' size if avail
547 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
548 struct bzfifo *txbz, u_char *bdata)
550 __le16 *z1r, *z2r, *z1t, *z2t;
551 int new_z2, fcnt_rx, fcnt_tx, maxlen;
554 z1r = &rxbz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
556 z1t = &txbz->za[MAX_B_FRAMES].z1;
559 fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
561 return; /* no data avail */
564 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
565 new_z2 = le16_to_cpu(*z2r) + fcnt_rx; /* new position in fifo */
566 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
567 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
569 fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
571 fcnt_tx += B_FIFO_SIZE;
572 /* fcnt_tx contains available bytes in tx-fifo */
573 fcnt_tx = B_FIFO_SIZE - fcnt_tx;
574 /* remaining bytes to send (bytes in tx-fifo) */
576 if (test_bit(FLG_RX_OFF, &bch->Flags)) {
577 bch->dropcnt += fcnt_rx;
578 *z2r = cpu_to_le16(new_z2);
581 maxlen = bchannel_get_rxbuf(bch, fcnt_rx);
583 pr_warning("B%d: No bufferspace for %d bytes\n",
586 ptr = skb_put(bch->rx_skb, fcnt_rx);
587 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
588 maxlen = fcnt_rx; /* complete transfer */
590 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
593 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
595 memcpy(ptr, ptr1, maxlen); /* copy data */
598 if (fcnt_rx) { /* rest remaining */
600 ptr1 = bdata; /* start of buffer */
601 memcpy(ptr, ptr1, fcnt_rx); /* rest */
603 recv_Bchannel(bch, fcnt_tx, false); /* bch, id, !force */
605 *z2r = cpu_to_le16(new_z2); /* new position */
609 * B-channel main receive routine
612 main_rec_hfcpci(struct bchannel *bch)
614 struct hfc_pci *hc = bch->hw;
616 int receive = 0, count = 5;
617 struct bzfifo *txbz, *rxbz;
621 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
622 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
623 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
624 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
627 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
628 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
629 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
634 if (rxbz->f1 != rxbz->f2) {
635 if (bch->debug & DEBUG_HW_BCHANNEL)
636 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
637 bch->nr, rxbz->f1, rxbz->f2);
638 zp = &rxbz->za[rxbz->f2];
640 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
644 if (bch->debug & DEBUG_HW_BCHANNEL)
646 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
647 bch->nr, le16_to_cpu(zp->z1),
648 le16_to_cpu(zp->z2), rcnt);
649 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
650 rcnt = rxbz->f1 - rxbz->f2;
652 rcnt += MAX_B_FRAMES + 1;
653 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
655 hfcpci_clear_fifo_rx(hc, real_fifo);
657 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
662 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
663 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
667 if (count && receive)
673 * D-channel send routine
676 hfcpci_fill_dfifo(struct hfc_pci *hc)
678 struct dchannel *dch = &hc->dch;
680 int count, new_z1, maxlen;
682 u_char *src, *dst, new_f1;
684 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
685 printk(KERN_DEBUG "%s\n", __func__);
689 count = dch->tx_skb->len - dch->tx_idx;
692 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
694 if (dch->debug & DEBUG_HW_DFIFO)
695 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
697 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
698 fcnt = df->f1 - df->f2; /* frame count actually buffered */
700 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
701 if (fcnt > (MAX_D_FRAMES - 1)) {
702 if (dch->debug & DEBUG_HW_DCHANNEL)
704 "hfcpci_fill_Dfifo more as 14 frames\n");
705 #ifdef ERROR_STATISTIC
710 /* now determine free bytes in FIFO buffer */
711 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
712 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
714 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
716 if (dch->debug & DEBUG_HW_DCHANNEL)
717 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
719 if (count > maxlen) {
720 if (dch->debug & DEBUG_HW_DCHANNEL)
721 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
724 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
726 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
727 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
728 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
729 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
732 maxlen = count; /* limit size */
733 memcpy(dst, src, maxlen); /* first copy */
735 count -= maxlen; /* remaining bytes */
737 dst = df->data; /* start of buffer */
738 src += maxlen; /* new position */
739 memcpy(dst, src, count);
741 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
742 /* for next buffer */
743 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
744 /* new pos actual buffer */
745 df->f1 = new_f1; /* next frame */
746 dch->tx_idx = dch->tx_skb->len;
750 * B-channel send routine
753 hfcpci_fill_fifo(struct bchannel *bch)
755 struct hfc_pci *hc = bch->hw;
760 u_char new_f1, *src, *dst;
763 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
764 printk(KERN_DEBUG "%s\n", __func__);
765 if ((!bch->tx_skb) || bch->tx_skb->len == 0) {
766 if (!test_bit(FLG_FILLEMPTY, &bch->Flags) &&
767 !test_bit(FLG_TRANSPARENT, &bch->Flags))
769 count = HFCPCI_FILLEMPTY;
771 count = bch->tx_skb->len - bch->tx_idx;
773 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
774 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
775 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
777 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
778 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
781 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
782 z1t = &bz->za[MAX_B_FRAMES].z1;
784 if (bch->debug & DEBUG_HW_BCHANNEL)
785 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
786 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
787 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
788 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
791 if (test_bit(FLG_FILLEMPTY, &bch->Flags)) {
792 /* fcnt contains available bytes in fifo */
795 new_z1 = le16_to_cpu(*z1t) + count;
796 /* new buffer Position */
797 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
798 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
799 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
800 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
802 if (bch->debug & DEBUG_HW_BFIFO)
803 printk(KERN_DEBUG "hfcpci_FFt fillempty "
804 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
805 fcnt, maxlen, new_z1, dst);
807 maxlen = count; /* limit size */
808 memset(dst, bch->fill[0], maxlen); /* first copy */
809 count -= maxlen; /* remaining bytes */
811 dst = bdata; /* start of buffer */
812 memset(dst, bch->fill[0], count);
814 *z1t = cpu_to_le16(new_z1); /* now send data */
817 /* fcnt contains available bytes in fifo */
818 fcnt = B_FIFO_SIZE - fcnt;
819 /* remaining bytes to send (bytes in fifo) */
822 count = bch->tx_skb->len - bch->tx_idx;
823 /* maximum fill shall be poll*2 */
824 if (count > (poll << 1) - fcnt)
825 count = (poll << 1) - fcnt;
828 /* data is suitable for fifo */
829 new_z1 = le16_to_cpu(*z1t) + count;
830 /* new buffer Position */
831 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
832 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
833 src = bch->tx_skb->data + bch->tx_idx;
835 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
836 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
838 if (bch->debug & DEBUG_HW_BFIFO)
839 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
840 "maxl(%d) nz1(%x) dst(%p)\n",
841 fcnt, maxlen, new_z1, dst);
843 bch->tx_idx += count;
845 maxlen = count; /* limit size */
846 memcpy(dst, src, maxlen); /* first copy */
847 count -= maxlen; /* remaining bytes */
849 dst = bdata; /* start of buffer */
850 src += maxlen; /* new position */
851 memcpy(dst, src, count);
853 *z1t = cpu_to_le16(new_z1); /* now send data */
854 if (bch->tx_idx < bch->tx_skb->len)
856 dev_kfree_skb(bch->tx_skb);
857 if (get_next_bframe(bch))
861 if (bch->debug & DEBUG_HW_BCHANNEL)
863 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
864 __func__, bch->nr, bz->f1, bz->f2,
866 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
868 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
869 if (fcnt > (MAX_B_FRAMES - 1)) {
870 if (bch->debug & DEBUG_HW_BCHANNEL)
872 "hfcpci_fill_Bfifo more as 14 frames\n");
875 /* now determine free bytes in FIFO buffer */
876 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
877 le16_to_cpu(bz->za[bz->f1].z1) - 1;
879 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
881 if (bch->debug & DEBUG_HW_BCHANNEL)
882 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
883 bch->nr, count, maxlen);
885 if (maxlen < count) {
886 if (bch->debug & DEBUG_HW_BCHANNEL)
887 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
890 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
891 /* new buffer Position */
892 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
893 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
895 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
896 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
897 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
898 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
901 maxlen = count; /* limit size */
902 memcpy(dst, src, maxlen); /* first copy */
904 count -= maxlen; /* remaining bytes */
906 dst = bdata; /* start of buffer */
907 src += maxlen; /* new position */
908 memcpy(dst, src, count);
910 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
911 bz->f1 = new_f1; /* next frame */
912 dev_kfree_skb(bch->tx_skb);
913 get_next_bframe(bch);
919 * handle L1 state changes TE
923 ph_state_te(struct dchannel *dch)
926 printk(KERN_DEBUG "%s: TE newstate %x\n",
927 __func__, dch->state);
928 switch (dch->state) {
930 l1_event(dch->l1, HW_RESET_IND);
933 l1_event(dch->l1, HW_DEACT_IND);
937 l1_event(dch->l1, ANYSIGNAL);
940 l1_event(dch->l1, INFO2);
943 l1_event(dch->l1, INFO4_P8);
949 * handle L1 state changes NT
953 handle_nt_timer3(struct dchannel *dch) {
954 struct hfc_pci *hc = dch->hw;
956 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
957 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
958 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
960 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
961 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
962 hc->hw.mst_m |= HFCPCI_MASTER;
963 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
964 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
965 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
969 ph_state_nt(struct dchannel *dch)
971 struct hfc_pci *hc = dch->hw;
974 printk(KERN_DEBUG "%s: NT newstate %x\n",
975 __func__, dch->state);
976 switch (dch->state) {
978 if (hc->hw.nt_timer < 0) {
980 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
981 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
982 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
983 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
984 /* Clear already pending ints */
985 (void) Read_hfc(hc, HFCPCI_INT_S1);
986 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
988 Write_hfc(hc, HFCPCI_STATES, 4);
990 } else if (hc->hw.nt_timer == 0) {
991 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
992 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
993 hc->hw.nt_timer = NT_T1_COUNT;
994 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
995 hc->hw.ctmt |= HFCPCI_TIM3_125;
996 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
998 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
999 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1000 /* allow G2 -> G3 transition */
1001 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1003 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1007 hc->hw.nt_timer = 0;
1008 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1009 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1010 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1011 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1012 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1013 hc->hw.mst_m &= ~HFCPCI_MASTER;
1014 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1015 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1016 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1017 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1020 hc->hw.nt_timer = 0;
1021 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1022 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1023 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1024 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1027 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1028 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1030 handle_nt_timer3(dch);
1033 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1034 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1035 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1036 hc->hw.nt_timer = NT_T3_COUNT;
1037 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1038 hc->hw.ctmt |= HFCPCI_TIM3_125;
1039 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1047 ph_state(struct dchannel *dch)
1049 struct hfc_pci *hc = dch->hw;
1051 if (hc->hw.protocol == ISDN_P_NT_S0) {
1052 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1053 hc->hw.nt_timer < 0)
1054 handle_nt_timer3(dch);
1062 * Layer 1 callback function
1065 hfc_l1callback(struct dchannel *dch, u_int cmd)
1067 struct hfc_pci *hc = dch->hw;
1072 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1073 hc->hw.mst_m |= HFCPCI_MASTER;
1074 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1077 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1080 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1081 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1082 hc->hw.mst_m |= HFCPCI_MASTER;
1083 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1084 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1086 l1_event(dch->l1, HW_POWERUP_IND);
1089 hc->hw.mst_m &= ~HFCPCI_MASTER;
1090 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1091 skb_queue_purge(&dch->squeue);
1093 dev_kfree_skb(dch->tx_skb);
1098 dev_kfree_skb(dch->rx_skb);
1101 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1102 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1103 del_timer(&dch->timer);
1105 case HW_POWERUP_REQ:
1106 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1108 case PH_ACTIVATE_IND:
1109 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1110 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1113 case PH_DEACTIVATE_IND:
1114 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1115 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1119 if (dch->debug & DEBUG_HW)
1120 printk(KERN_DEBUG "%s: unknown command %x\n",
1131 tx_birq(struct bchannel *bch)
1133 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1134 hfcpci_fill_fifo(bch);
1137 dev_kfree_skb(bch->tx_skb);
1138 if (get_next_bframe(bch))
1139 hfcpci_fill_fifo(bch);
1144 tx_dirq(struct dchannel *dch)
1146 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1147 hfcpci_fill_dfifo(dch->hw);
1150 dev_kfree_skb(dch->tx_skb);
1151 if (get_next_dframe(dch))
1152 hfcpci_fill_dfifo(dch->hw);
1157 hfcpci_int(int intno, void *dev_id)
1159 struct hfc_pci *hc = dev_id;
1161 struct bchannel *bch;
1164 spin_lock(&hc->lock);
1165 if (!(hc->hw.int_m2 & 0x08)) {
1166 spin_unlock(&hc->lock);
1167 return IRQ_NONE; /* not initialised */
1169 stat = Read_hfc(hc, HFCPCI_STATUS);
1170 if (HFCPCI_ANYINT & stat) {
1171 val = Read_hfc(hc, HFCPCI_INT_S1);
1172 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1174 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1177 spin_unlock(&hc->lock);
1182 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1183 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1184 val &= hc->hw.int_m1;
1185 if (val & 0x40) { /* state machine irq */
1186 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1187 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1188 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1189 hc->dch.state, exval);
1190 hc->dch.state = exval;
1191 schedule_event(&hc->dch, FLG_PHCHANGE);
1194 if (val & 0x80) { /* timer irq */
1195 if (hc->hw.protocol == ISDN_P_NT_S0) {
1196 if ((--hc->hw.nt_timer) < 0)
1197 schedule_event(&hc->dch, FLG_PHCHANGE);
1200 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1202 if (val & 0x08) { /* B1 rx */
1203 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1205 main_rec_hfcpci(bch);
1206 else if (hc->dch.debug)
1207 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1209 if (val & 0x10) { /* B2 rx */
1210 bch = Sel_BCS(hc, 2);
1212 main_rec_hfcpci(bch);
1213 else if (hc->dch.debug)
1214 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1216 if (val & 0x01) { /* B1 tx */
1217 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1220 else if (hc->dch.debug)
1221 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1223 if (val & 0x02) { /* B2 tx */
1224 bch = Sel_BCS(hc, 2);
1227 else if (hc->dch.debug)
1228 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1230 if (val & 0x20) /* D rx */
1232 if (val & 0x04) { /* D tx */
1233 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1234 del_timer(&hc->dch.timer);
1237 spin_unlock(&hc->lock);
1242 * timer callback for D-chan busy resolution. Currently no function
1245 hfcpci_dbusy_timer(struct timer_list *t)
1250 * activate/deactivate hardware for selected channels and mode
1253 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1255 struct hfc_pci *hc = bch->hw;
1257 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1259 if (bch->debug & DEBUG_HW_BCHANNEL)
1261 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1262 bch->state, protocol, bch->nr, bc);
1265 pcm_mode = (bc >> 24) & 0xff;
1266 if (pcm_mode) { /* PCM SLOT USE */
1267 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1269 "%s: pcm channel id without HFC_CFG_PCM\n",
1271 rx_slot = (bc >> 8) & 0xff;
1272 tx_slot = (bc >> 16) & 0xff;
1274 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1275 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1277 if (hc->chanlimit > 1) {
1278 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1279 hc->hw.sctrl_e &= ~0x80;
1282 if (protocol != ISDN_P_NONE) {
1283 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1284 hc->hw.sctrl_e |= 0x80;
1286 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1287 hc->hw.sctrl_e &= ~0x80;
1291 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1292 hc->hw.sctrl_e &= ~0x80;
1296 case (-1): /* used for init */
1301 if (bch->state == ISDN_P_NONE)
1304 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1305 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1307 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1308 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1311 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1312 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS |
1315 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1316 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS |
1319 #ifdef REVERSE_BITORDER
1321 hc->hw.cirm &= 0x7f;
1323 hc->hw.cirm &= 0xbf;
1325 bch->state = ISDN_P_NONE;
1327 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1328 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1330 case (ISDN_P_B_RAW):
1331 bch->state = protocol;
1333 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1334 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1336 hc->hw.sctrl |= SCTRL_B2_ENA;
1337 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1338 #ifdef REVERSE_BITORDER
1339 hc->hw.cirm |= 0x80;
1342 hc->hw.sctrl |= SCTRL_B1_ENA;
1343 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1344 #ifdef REVERSE_BITORDER
1345 hc->hw.cirm |= 0x40;
1349 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1351 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1354 hc->hw.conn &= ~0x18;
1356 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1358 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1361 hc->hw.conn &= ~0x03;
1363 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1365 case (ISDN_P_B_HDLC):
1366 bch->state = protocol;
1368 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1369 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1371 hc->hw.sctrl |= SCTRL_B2_ENA;
1372 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1374 hc->hw.sctrl |= SCTRL_B1_ENA;
1375 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1378 hc->hw.last_bfifo_cnt[1] = 0;
1379 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1380 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1383 hc->hw.conn &= ~0x18;
1385 hc->hw.last_bfifo_cnt[0] = 0;
1386 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1387 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1390 hc->hw.conn &= ~0x03;
1392 test_and_set_bit(FLG_HDLC, &bch->Flags);
1395 printk(KERN_DEBUG "prot not known %x\n", protocol);
1396 return -ENOPROTOOPT;
1398 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1399 if ((protocol == ISDN_P_NONE) ||
1400 (protocol == -1)) { /* init case */
1404 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1413 hc->hw.conn &= 0xc7;
1414 hc->hw.conn |= 0x08;
1415 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1417 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1419 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1420 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1422 hc->hw.conn &= 0xf8;
1423 hc->hw.conn |= 0x01;
1424 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1426 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1428 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1429 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1432 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1433 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1434 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1435 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1436 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1437 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1438 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1439 #ifdef REVERSE_BITORDER
1440 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1446 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1448 struct hfc_pci *hc = bch->hw;
1450 if (bch->debug & DEBUG_HW_BCHANNEL)
1452 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1453 bch->state, protocol, bch->nr, chan);
1454 if (bch->nr != chan) {
1456 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1461 case (ISDN_P_B_RAW):
1462 bch->state = protocol;
1463 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1465 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1466 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1468 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1470 hc->hw.conn &= ~0x18;
1471 #ifdef REVERSE_BITORDER
1472 hc->hw.cirm |= 0x80;
1475 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1476 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1478 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1480 hc->hw.conn &= ~0x03;
1481 #ifdef REVERSE_BITORDER
1482 hc->hw.cirm |= 0x40;
1486 case (ISDN_P_B_HDLC):
1487 bch->state = protocol;
1488 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1490 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1491 hc->hw.last_bfifo_cnt[1] = 0;
1492 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1493 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1495 hc->hw.conn &= ~0x18;
1497 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1498 hc->hw.last_bfifo_cnt[0] = 0;
1499 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1500 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1502 hc->hw.conn &= ~0x03;
1506 printk(KERN_DEBUG "prot not known %x\n", protocol);
1507 return -ENOPROTOOPT;
1509 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1510 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1511 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1512 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1513 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1514 #ifdef REVERSE_BITORDER
1515 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1521 deactivate_bchannel(struct bchannel *bch)
1523 struct hfc_pci *hc = bch->hw;
1526 spin_lock_irqsave(&hc->lock, flags);
1527 mISDN_clear_bchannel(bch);
1528 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1529 spin_unlock_irqrestore(&hc->lock, flags);
1533 * Layer 1 B-channel hardware access
1536 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1538 return mISDN_ctrl_bchannel(bch, cq);
1541 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1543 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1544 struct hfc_pci *hc = bch->hw;
1548 if (bch->debug & DEBUG_HW)
1549 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1552 spin_lock_irqsave(&hc->lock, flags);
1553 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1554 spin_unlock_irqrestore(&hc->lock, flags);
1556 case HW_TESTRX_HDLC:
1557 spin_lock_irqsave(&hc->lock, flags);
1558 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1559 spin_unlock_irqrestore(&hc->lock, flags);
1562 spin_lock_irqsave(&hc->lock, flags);
1563 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1564 spin_unlock_irqrestore(&hc->lock, flags);
1568 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1569 deactivate_bchannel(bch);
1570 ch->protocol = ISDN_P_NONE;
1572 module_put(THIS_MODULE);
1575 case CONTROL_CHANNEL:
1576 ret = channel_bctrl(bch, arg);
1579 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1586 * Layer2 -> Layer 1 Dchannel data
1589 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1591 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1592 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1593 struct hfc_pci *hc = dch->hw;
1595 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1601 spin_lock_irqsave(&hc->lock, flags);
1602 ret = dchannel_senddata(dch, skb);
1603 if (ret > 0) { /* direct TX */
1604 id = hh->id; /* skb can be freed */
1605 hfcpci_fill_dfifo(dch->hw);
1607 spin_unlock_irqrestore(&hc->lock, flags);
1608 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1610 spin_unlock_irqrestore(&hc->lock, flags);
1612 case PH_ACTIVATE_REQ:
1613 spin_lock_irqsave(&hc->lock, flags);
1614 if (hc->hw.protocol == ISDN_P_NT_S0) {
1616 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1617 hc->hw.mst_m |= HFCPCI_MASTER;
1618 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1619 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1620 spin_unlock_irqrestore(&hc->lock, flags);
1621 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1622 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1625 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1626 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1627 HFCPCI_DO_ACTION | 1);
1629 ret = l1_event(dch->l1, hh->prim);
1630 spin_unlock_irqrestore(&hc->lock, flags);
1632 case PH_DEACTIVATE_REQ:
1633 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1634 spin_lock_irqsave(&hc->lock, flags);
1635 if (hc->hw.protocol == ISDN_P_NT_S0) {
1636 /* prepare deactivation */
1637 Write_hfc(hc, HFCPCI_STATES, 0x40);
1638 skb_queue_purge(&dch->squeue);
1640 dev_kfree_skb(dch->tx_skb);
1645 dev_kfree_skb(dch->rx_skb);
1648 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1649 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1650 del_timer(&dch->timer);
1652 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1653 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1655 hc->hw.mst_m &= ~HFCPCI_MASTER;
1656 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1659 ret = l1_event(dch->l1, hh->prim);
1661 spin_unlock_irqrestore(&hc->lock, flags);
1670 * Layer2 -> Layer 1 Bchannel data
1673 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1675 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1676 struct hfc_pci *hc = bch->hw;
1678 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1679 unsigned long flags;
1683 spin_lock_irqsave(&hc->lock, flags);
1684 ret = bchannel_senddata(bch, skb);
1685 if (ret > 0) { /* direct TX */
1686 hfcpci_fill_fifo(bch);
1689 spin_unlock_irqrestore(&hc->lock, flags);
1691 case PH_ACTIVATE_REQ:
1692 spin_lock_irqsave(&hc->lock, flags);
1693 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1694 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1697 spin_unlock_irqrestore(&hc->lock, flags);
1699 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1702 case PH_DEACTIVATE_REQ:
1703 deactivate_bchannel(bch);
1704 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1715 * called for card init message
1719 inithfcpci(struct hfc_pci *hc)
1721 printk(KERN_DEBUG "inithfcpci: entered\n");
1722 timer_setup(&hc->dch.timer, hfcpci_dbusy_timer, 0);
1724 mode_hfcpci(&hc->bch[0], 1, -1);
1725 mode_hfcpci(&hc->bch[1], 2, -1);
1730 init_card(struct hfc_pci *hc)
1735 printk(KERN_DEBUG "init_card: entered\n");
1738 spin_lock_irqsave(&hc->lock, flags);
1740 spin_unlock_irqrestore(&hc->lock, flags);
1741 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1743 "mISDN: couldn't get interrupt %d\n", hc->irq);
1746 spin_lock_irqsave(&hc->lock, flags);
1751 * Finally enable IRQ output
1752 * this is only allowed, if an IRQ routine is already
1753 * established for this HFC, so don't do that earlier
1756 spin_unlock_irqrestore(&hc->lock, flags);
1758 set_current_state(TASK_UNINTERRUPTIBLE);
1759 schedule_timeout((80 * HZ) / 1000);
1760 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1761 hc->irq, hc->irqcnt);
1762 /* now switch timer interrupt off */
1763 spin_lock_irqsave(&hc->lock, flags);
1764 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1765 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1766 /* reinit mode reg */
1767 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1770 "HFC PCI: IRQ(%d) getting no interrupts "
1771 "during init %d\n", hc->irq, 4 - cnt);
1779 spin_unlock_irqrestore(&hc->lock, flags);
1785 spin_unlock_irqrestore(&hc->lock, flags);
1786 free_irq(hc->irq, hc);
1791 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1797 case MISDN_CTRL_GETOP:
1798 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1799 MISDN_CTRL_DISCONNECT | MISDN_CTRL_L1_TIMER3;
1801 case MISDN_CTRL_LOOP:
1802 /* channel 0 disabled loop */
1803 if (cq->channel < 0 || cq->channel > 2) {
1807 if (cq->channel & 1) {
1808 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1812 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1814 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1815 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1816 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1817 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1819 if (cq->channel & 2) {
1820 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1824 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1826 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1827 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1828 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1829 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1831 if (cq->channel & 3)
1832 hc->hw.trm |= 0x80; /* enable IOM-loop */
1834 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1835 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1836 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1838 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1840 case MISDN_CTRL_CONNECT:
1841 if (cq->channel == cq->p1) {
1845 if (cq->channel < 1 || cq->channel > 2 ||
1846 cq->p1 < 1 || cq->p1 > 2) {
1850 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1854 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1856 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1857 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1858 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1862 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1864 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1865 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1866 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1867 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1869 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1871 case MISDN_CTRL_DISCONNECT:
1872 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1873 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1874 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1876 case MISDN_CTRL_L1_TIMER3:
1877 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1880 printk(KERN_WARNING "%s: unknown Op %x\n",
1889 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1890 struct channel_req *rq)
1894 if (debug & DEBUG_HW_OPEN)
1895 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1896 hc->dch.dev.id, __builtin_return_address(0));
1897 if (rq->protocol == ISDN_P_NONE)
1899 if (rq->adr.channel == 1) {
1900 /* TODO: E-Channel */
1903 if (!hc->initdone) {
1904 if (rq->protocol == ISDN_P_TE_S0) {
1905 err = create_l1(&hc->dch, hfc_l1callback);
1909 hc->hw.protocol = rq->protocol;
1910 ch->protocol = rq->protocol;
1911 err = init_card(hc);
1915 if (rq->protocol != ch->protocol) {
1916 if (hc->hw.protocol == ISDN_P_TE_S0)
1917 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1918 if (rq->protocol == ISDN_P_TE_S0) {
1919 err = create_l1(&hc->dch, hfc_l1callback);
1923 hc->hw.protocol = rq->protocol;
1924 ch->protocol = rq->protocol;
1929 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1930 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1931 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1932 0, NULL, GFP_KERNEL);
1935 if (!try_module_get(THIS_MODULE))
1936 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1941 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1943 struct bchannel *bch;
1945 if (rq->adr.channel == 0 || rq->adr.channel > 2)
1947 if (rq->protocol == ISDN_P_NONE)
1949 bch = &hc->bch[rq->adr.channel - 1];
1950 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1951 return -EBUSY; /* b-channel can be only open once */
1952 bch->ch.protocol = rq->protocol;
1953 rq->ch = &bch->ch; /* TODO: E-channel */
1954 if (!try_module_get(THIS_MODULE))
1955 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1960 * device control function
1963 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1965 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1966 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1967 struct hfc_pci *hc = dch->hw;
1968 struct channel_req *rq;
1971 if (dch->debug & DEBUG_HW)
1972 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1973 __func__, cmd, arg);
1977 if ((rq->protocol == ISDN_P_TE_S0) ||
1978 (rq->protocol == ISDN_P_NT_S0))
1979 err = open_dchannel(hc, ch, rq);
1981 err = open_bchannel(hc, rq);
1984 if (debug & DEBUG_HW_OPEN)
1985 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1986 __func__, hc->dch.dev.id,
1987 __builtin_return_address(0));
1988 module_put(THIS_MODULE);
1990 case CONTROL_CHANNEL:
1991 err = channel_ctrl(hc, arg);
1994 if (dch->debug & DEBUG_HW)
1995 printk(KERN_DEBUG "%s: unknown command %x\n",
2003 setup_hw(struct hfc_pci *hc)
2007 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2010 pci_set_master(hc->pdev);
2012 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2016 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2018 if (!hc->hw.pci_io) {
2019 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2022 /* Allocate memory for FIFOS */
2023 /* the memory needs to be on a 32k boundary within the first 4G */
2024 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2025 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2026 /* We silently assume the address is okay if nonzero */
2029 "HFC-PCI: Error allocating memory for FIFO!\n");
2032 hc->hw.fifos = buffer;
2033 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2034 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2036 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2037 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2038 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2039 /* enable memory mapped ports, disable busmaster */
2040 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2044 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2045 /* At this point the needed PCI config is done */
2046 /* fifos are still not enabled */
2047 timer_setup(&hc->hw.timer, hfcpci_Timer, 0);
2048 /* default PCM master */
2049 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2054 release_card(struct hfc_pci *hc) {
2057 spin_lock_irqsave(&hc->lock, flags);
2058 hc->hw.int_m2 = 0; /* interrupt output off ! */
2060 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2061 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2062 if (hc->dch.timer.function != NULL) {
2063 del_timer(&hc->dch.timer);
2064 hc->dch.timer.function = NULL;
2066 spin_unlock_irqrestore(&hc->lock, flags);
2067 if (hc->hw.protocol == ISDN_P_TE_S0)
2068 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2070 free_irq(hc->irq, hc);
2071 release_io_hfcpci(hc); /* must release after free_irq! */
2072 mISDN_unregister_device(&hc->dch.dev);
2073 mISDN_freebchannel(&hc->bch[1]);
2074 mISDN_freebchannel(&hc->bch[0]);
2075 mISDN_freedchannel(&hc->dch);
2076 pci_set_drvdata(hc->pdev, NULL);
2081 setup_card(struct hfc_pci *card)
2085 char name[MISDN_MAX_IDLEN];
2087 card->dch.debug = debug;
2088 spin_lock_init(&card->lock);
2089 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2090 card->dch.hw = card;
2091 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2092 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2093 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2094 card->dch.dev.D.send = hfcpci_l2l1D;
2095 card->dch.dev.D.ctrl = hfc_dctrl;
2096 card->dch.dev.nrbchan = 2;
2097 for (i = 0; i < 2; i++) {
2098 card->bch[i].nr = i + 1;
2099 set_channelmap(i + 1, card->dch.dev.channelmap);
2100 card->bch[i].debug = debug;
2101 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, poll >> 1);
2102 card->bch[i].hw = card;
2103 card->bch[i].ch.send = hfcpci_l2l1B;
2104 card->bch[i].ch.ctrl = hfc_bctrl;
2105 card->bch[i].ch.nr = i + 1;
2106 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2108 err = setup_hw(card);
2111 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2112 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2116 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2119 mISDN_freebchannel(&card->bch[1]);
2120 mISDN_freebchannel(&card->bch[0]);
2121 mISDN_freedchannel(&card->dch);
2126 /* private data in the PCI devices list */
2133 static const struct _hfc_map hfc_map[] =
2135 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2136 {HFC_CCD_B000, 0, "Billion B000"},
2137 {HFC_CCD_B006, 0, "Billion B006"},
2138 {HFC_CCD_B007, 0, "Billion B007"},
2139 {HFC_CCD_B008, 0, "Billion B008"},
2140 {HFC_CCD_B009, 0, "Billion B009"},
2141 {HFC_CCD_B00A, 0, "Billion B00A"},
2142 {HFC_CCD_B00B, 0, "Billion B00B"},
2143 {HFC_CCD_B00C, 0, "Billion B00C"},
2144 {HFC_CCD_B100, 0, "Seyeon B100"},
2145 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2146 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2147 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2148 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2149 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2150 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2151 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2152 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2153 {HFC_DIGI_DF_M_IOM2_E, 0,
2154 "Digi International DataFire Micro V IOM2 (Europe)"},
2155 {HFC_DIGI_DF_M_E, 0,
2156 "Digi International DataFire Micro V (Europe)"},
2157 {HFC_DIGI_DF_M_IOM2_A, 0,
2158 "Digi International DataFire Micro V IOM2 (North America)"},
2159 {HFC_DIGI_DF_M_A, 0,
2160 "Digi International DataFire Micro V (North America)"},
2161 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2165 static const struct pci_device_id hfc_ids[] =
2167 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2168 (unsigned long) &hfc_map[0] },
2169 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2170 (unsigned long) &hfc_map[1] },
2171 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2172 (unsigned long) &hfc_map[2] },
2173 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2174 (unsigned long) &hfc_map[3] },
2175 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2176 (unsigned long) &hfc_map[4] },
2177 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2178 (unsigned long) &hfc_map[5] },
2179 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2180 (unsigned long) &hfc_map[6] },
2181 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2182 (unsigned long) &hfc_map[7] },
2183 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2184 (unsigned long) &hfc_map[8] },
2185 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2186 (unsigned long) &hfc_map[9] },
2187 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2188 (unsigned long) &hfc_map[10] },
2189 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2190 (unsigned long) &hfc_map[11] },
2191 { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2192 (unsigned long) &hfc_map[12] },
2193 { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2194 (unsigned long) &hfc_map[13] },
2195 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2196 (unsigned long) &hfc_map[14] },
2197 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2198 (unsigned long) &hfc_map[15] },
2199 { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2200 (unsigned long) &hfc_map[16] },
2201 { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2202 (unsigned long) &hfc_map[17] },
2203 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2204 (unsigned long) &hfc_map[18] },
2205 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2206 (unsigned long) &hfc_map[19] },
2207 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2208 (unsigned long) &hfc_map[20] },
2209 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2210 (unsigned long) &hfc_map[21] },
2211 { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2212 (unsigned long) &hfc_map[22] },
2217 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2220 struct hfc_pci *card;
2221 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2223 card = kzalloc(sizeof(struct hfc_pci), GFP_KERNEL);
2225 printk(KERN_ERR "No kmem for HFC card\n");
2229 card->subtype = m->subtype;
2230 err = pci_enable_device(pdev);
2236 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2237 m->name, pci_name(pdev));
2239 card->irq = pdev->irq;
2240 pci_set_drvdata(pdev, card);
2241 err = setup_card(card);
2243 pci_set_drvdata(pdev, NULL);
2248 hfc_remove_pci(struct pci_dev *pdev)
2250 struct hfc_pci *card = pci_get_drvdata(pdev);
2256 printk(KERN_DEBUG "%s: drvdata already removed\n",
2261 static struct pci_driver hfc_driver = {
2264 .remove = hfc_remove_pci,
2265 .id_table = hfc_ids,
2269 _hfcpci_softirq(struct device *dev, void *unused)
2271 struct hfc_pci *hc = dev_get_drvdata(dev);
2272 struct bchannel *bch;
2276 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2277 spin_lock(&hc->lock);
2278 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2279 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2280 main_rec_hfcpci(bch);
2283 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2284 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2285 main_rec_hfcpci(bch);
2288 spin_unlock(&hc->lock);
2294 hfcpci_softirq(struct timer_list *unused)
2296 WARN_ON_ONCE(driver_for_each_device(&hfc_driver.driver, NULL, NULL,
2297 _hfcpci_softirq) != 0);
2299 /* if next event would be in the past ... */
2300 if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2301 hfc_jiffies = jiffies + 1;
2303 hfc_jiffies += tics;
2304 hfc_tl.expires = hfc_jiffies;
2314 poll = HFCPCI_BTRANS_THRESHOLD;
2316 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2317 tics = (poll * HZ) / 8000;
2320 poll = (tics * 8000) / HZ;
2321 if (poll > 256 || poll < 8) {
2322 printk(KERN_ERR "%s: Wrong poll value %d not in range "
2323 "of 8..256.\n", __func__, poll);
2328 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2329 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2331 timer_setup(&hfc_tl, hfcpci_softirq, 0);
2332 hfc_tl.expires = jiffies + tics;
2333 hfc_jiffies = hfc_tl.expires;
2336 tics = 0; /* indicate the use of controller's timer */
2338 err = pci_register_driver(&hfc_driver);
2340 if (timer_pending(&hfc_tl))
2350 if (timer_pending(&hfc_tl))
2351 del_timer_sync(&hfc_tl);
2353 pci_unregister_driver(&hfc_driver);
2356 module_init(HFC_init);
2357 module_exit(HFC_cleanup);
2359 MODULE_DEVICE_TABLE(pci, hfc_ids);