drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dmask and bmask:
 107  *      NOTE: One dmask value must be given for every HFC-E1 card.
 108  *      If omitted, the E1 card has D-channel on time slot 16, which is default.
 109  *      dmask is a 32 bit mask. The bit must be set for an alternate time slot.
 110  *      If multiple bits are set, multiple virtual card fragments are created.
 111  *      For each bit set, a bmask value must be given. Each bit on the bmask
 112  *      value stands for a B-channel. The bmask may not overlap with dmask or
 113  *      with other bmask values for that card.
 114  *      Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
 115  *              This will create one fragment with D-channel on slot 1 with
 116  *              B-channels on slots 2..15, and a second fragment with D-channel
 117  *              on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
 118  *      If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
 119  *      not function.
 120  *      Example: dmask=0x00000001 bmask=0xfffffffe
 121  *              This will create a port with all 31 usable timeslots as
 122  *              B-channels.
 123  *      If no bits are set on bmask, no B-channel is created for that fragment.
 124  *      Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
 125  *              This will create 31 ports with one D-channel only.
 126  *      If you don't know how to use it, you don't need it!
 127  *
 128  * iomode:
 129  *      NOTE: only one mode value must be given for every card.
 130  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 131  *      By default, the IO mode is pci memory IO (MEMIO).
 132  *      Some cards require specific IO mode, so it cannot be changed.
 133  *      It may be useful to set IO mode to register io (REGIO) to solve
 134  *      PCI bridge problems.
 135  *      If unsure, don't give this parameter.
 136  *
 137  * clockdelay_nt:
 138  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 139  *      Give the value of the clock control register (A_ST_CLK_DLY)
 140  *      of the S/T interfaces in NT mode.
 141  *      This register is needed for the TBR3 certification, so don't change it.
 142  *
 143  * clockdelay_te:
 144  *      NOTE: only one clockdelay_te value must be given once
 145  *      Give the value of the clock control register (A_ST_CLK_DLY)
 146  *      of the S/T interfaces in TE mode.
 147  *      This register is needed for the TBR3 certification, so don't change it.
 148  *
 149  * clock:
 150  *      NOTE: only one clock value must be given once
 151  *      Selects interface with clock source for mISDN and applications.
 152  *      Set to card number starting with 1. Set to -1 to disable.
 153  *      By default, the first card is used as clock source.
 154  *
 155  * hwid:
 156  *      NOTE: only one hwid value must be given once
 157  *      Enable special embedded devices with XHFC controllers.
 158  */
 159
 160 /*
 161  * debug register access (never use this, it will flood your system log)
 162  * #define HFC_REGISTER_DEBUG
 163  */
 164
 165 #define HFC_MULTI_VERSION       "2.03"
 166
 167 #include <linux/interrupt.h>
 168 #include <linux/module.h>
 169 #include <linux/slab.h>
 170 #include <linux/pci.h>
 171 #include <linux/delay.h>
 172 #include <linux/mISDNhw.h>
 173 #include <linux/mISDNdsp.h>
 174
 175 /*
 176   #define IRQCOUNT_DEBUG
 177   #define IRQ_DEBUG
 178 */
 179
 180 #include "hfc_multi.h"
 181 #ifdef ECHOPREP
 182 #include "gaintab.h"
 183 #endif
 184
 185 #define MAX_CARDS       8
 186 #define MAX_PORTS       (8 * MAX_CARDS)
 187 #define MAX_FRAGS       (32 * MAX_CARDS)
 188
 189 static LIST_HEAD(HFClist);
 190 static spinlock_t HFClock; /* global hfc list lock */
 191
 192 static void ph_state_change(struct dchannel *);
 193
 194 static struct hfc_multi *syncmaster;
 195 static int plxsd_master; /* if we have a master card (yet) */
 196 static spinlock_t plx_lock; /* may not acquire other lock inside */
 197
 198 #define TYP_E1          1
 199 #define TYP_4S          4
 200 #define TYP_8S          8
 201
 202 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 203 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 204 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 205 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 206 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 207                                    (0x60 MUST be included!) */
 208
 209 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 210 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 211 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 212
 213 /*
 214  * module stuff
 215  */
 216
 217 static uint     type[MAX_CARDS];
 218 static int      pcm[MAX_CARDS];
 219 static uint     dmask[MAX_CARDS];
 220 static uint     bmask[MAX_FRAGS];
 221 static uint     iomode[MAX_CARDS];
 222 static uint     port[MAX_PORTS];
 223 static uint     debug;
 224 static uint     poll;
 225 static int      clock;
 226 static uint     timer;
 227 static uint     clockdelay_te = CLKDEL_TE;
 228 static uint     clockdelay_nt = CLKDEL_NT;
 229 #define HWID_NONE       0
 230 #define HWID_MINIP4     1
 231 #define HWID_MINIP8     2
 232 #define HWID_MINIP16    3
 233 static uint     hwid = HWID_NONE;
 234
 235 static int      HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
 236
 237 MODULE_AUTHOR("Andreas Eversberg");
 238 MODULE_LICENSE("GPL");
 239 MODULE_VERSION(HFC_MULTI_VERSION);
 240 module_param(debug, uint, S_IRUGO | S_IWUSR);
 241 module_param(poll, uint, S_IRUGO | S_IWUSR);
 242 module_param(clock, int, S_IRUGO | S_IWUSR);
 243 module_param(timer, uint, S_IRUGO | S_IWUSR);
 244 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 245 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 246 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 247 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
 248 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
 249 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
 250 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 251 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 252 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
 253
 254 #ifdef HFC_REGISTER_DEBUG
 255 #define HFC_outb(hc, reg, val)                                  \
 256         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 257 #define HFC_outb_nodebug(hc, reg, val)                                  \
 258         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 259 #define HFC_inb(hc, reg)                                \
 260         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 261 #define HFC_inb_nodebug(hc, reg)                                \
 262         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 263 #define HFC_inw(hc, reg)                                \
 264         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 265 #define HFC_inw_nodebug(hc, reg)                                \
 266         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 267 #define HFC_wait(hc)                            \
 268         (hc->HFC_wait(hc, __func__, __LINE__))
 269 #define HFC_wait_nodebug(hc)                            \
 270         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 271 #else
 272 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 273 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 274 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 275 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 276 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 277 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 278 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 279 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 280 #endif
 281
 282 #ifdef CONFIG_MISDN_HFCMULTI_8xx
 283 #include "hfc_multi_8xx.h"
 284 #endif
 285
 286 /* HFC_IO_MODE_PCIMEM */
 287 static void
 288 #ifdef HFC_REGISTER_DEBUG
 289 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 290                 const char *function, int line)
 291 #else
 292         HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 293 #endif
 294 {
 295         writeb(val, hc->pci_membase + reg);
 296 }
 297 static u_char
 298 #ifdef HFC_REGISTER_DEBUG
 299 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 300 #else
 301         HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 302 #endif
 303 {
 304         return readb(hc->pci_membase + reg);
 305 }
 306 static u_short
 307 #ifdef HFC_REGISTER_DEBUG
 308 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 309 #else
 310         HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 311 #endif
 312 {
 313         return readw(hc->pci_membase + reg);
 314 }
 315 static void
 316 #ifdef HFC_REGISTER_DEBUG
 317 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 318 #else
 319         HFC_wait_pcimem(struct hfc_multi *hc)
 320 #endif
 321 {
 322         while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
 323                 cpu_relax();
 324 }
 325
 326 /* HFC_IO_MODE_REGIO */
 327 static void
 328 #ifdef HFC_REGISTER_DEBUG
 329 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 330                const char *function, int line)
 331 #else
 332         HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 333 #endif
 334 {
 335         outb(reg, hc->pci_iobase + 4);
 336         outb(val, hc->pci_iobase);
 337 }
 338 static u_char
 339 #ifdef HFC_REGISTER_DEBUG
 340 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 341 #else
 342         HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 343 #endif
 344 {
 345         outb(reg, hc->pci_iobase + 4);
 346         return inb(hc->pci_iobase);
 347 }
 348 static u_short
 349 #ifdef HFC_REGISTER_DEBUG
 350 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 351 #else
 352         HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 353 #endif
 354 {
 355         outb(reg, hc->pci_iobase + 4);
 356         return inw(hc->pci_iobase);
 357 }
 358 static void
 359 #ifdef HFC_REGISTER_DEBUG
 360 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 361 #else
 362         HFC_wait_regio(struct hfc_multi *hc)
 363 #endif
 364 {
 365         outb(R_STATUS, hc->pci_iobase + 4);
 366         while (inb(hc->pci_iobase) & V_BUSY)
 367                 cpu_relax();
 368 }
 369
 370 #ifdef HFC_REGISTER_DEBUG
 371 static void
 372 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 373                const char *function, int line)
 374 {
 375         char regname[256] = "", bits[9] = "xxxxxxxx";
 376         int i;
 377
 378         i = -1;
 379         while (hfc_register_names[++i].name) {
 380                 if (hfc_register_names[i].reg == reg)
 381                         strcat(regname, hfc_register_names[i].name);
 382         }
 383         if (regname[0] == '\0')
 384                 strcpy(regname, "register");
 385
 386         bits[7] = '0' + (!!(val & 1));
 387         bits[6] = '0' + (!!(val & 2));
 388         bits[5] = '0' + (!!(val & 4));
 389         bits[4] = '0' + (!!(val & 8));
 390         bits[3] = '0' + (!!(val & 16));
 391         bits[2] = '0' + (!!(val & 32));
 392         bits[1] = '0' + (!!(val & 64));
 393         bits[0] = '0' + (!!(val & 128));
 394         printk(KERN_DEBUG
 395                "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 396                hc->id, reg, regname, val, bits, function, line);
 397         HFC_outb_nodebug(hc, reg, val);
 398 }
 399 static u_char
 400 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 401 {
 402         char regname[256] = "", bits[9] = "xxxxxxxx";
 403         u_char val = HFC_inb_nodebug(hc, reg);
 404         int i;
 405
 406         i = 0;
 407         while (hfc_register_names[i++].name)
 408                 ;
 409         while (hfc_register_names[++i].name) {
 410                 if (hfc_register_names[i].reg == reg)
 411                         strcat(regname, hfc_register_names[i].name);
 412         }
 413         if (regname[0] == '\0')
 414                 strcpy(regname, "register");
 415
 416         bits[7] = '0' + (!!(val & 1));
 417         bits[6] = '0' + (!!(val & 2));
 418         bits[5] = '0' + (!!(val & 4));
 419         bits[4] = '0' + (!!(val & 8));
 420         bits[3] = '0' + (!!(val & 16));
 421         bits[2] = '0' + (!!(val & 32));
 422         bits[1] = '0' + (!!(val & 64));
 423         bits[0] = '0' + (!!(val & 128));
 424         printk(KERN_DEBUG
 425                "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 426                hc->id, reg, regname, val, bits, function, line);
 427         return val;
 428 }
 429 static u_short
 430 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 431 {
 432         char regname[256] = "";
 433         u_short val = HFC_inw_nodebug(hc, reg);
 434         int i;
 435
 436         i = 0;
 437         while (hfc_register_names[i++].name)
 438                 ;
 439         while (hfc_register_names[++i].name) {
 440                 if (hfc_register_names[i].reg == reg)
 441                         strcat(regname, hfc_register_names[i].name);
 442         }
 443         if (regname[0] == '\0')
 444                 strcpy(regname, "register");
 445
 446         printk(KERN_DEBUG
 447                "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 448                hc->id, reg, regname, val, function, line);
 449         return val;
 450 }
 451 static void
 452 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 453 {
 454         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 455                hc->id, function, line);
 456         HFC_wait_nodebug(hc);
 457 }
 458 #endif
 459
 460 /* write fifo data (REGIO) */
 461 static void
 462 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 463 {
 464         outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
 465         while (len >> 2) {
 466                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 467                 data += 4;
 468                 len -= 4;
 469         }
 470         while (len >> 1) {
 471                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 472                 data += 2;
 473                 len -= 2;
 474         }
 475         while (len) {
 476                 outb(*data, hc->pci_iobase);
 477                 data++;
 478                 len--;
 479         }
 480 }
 481 /* write fifo data (PCIMEM) */
 482 static void
 483 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 484 {
 485         while (len >> 2) {
 486                 writel(cpu_to_le32(*(u32 *)data),
 487                        hc->pci_membase + A_FIFO_DATA0);
 488                 data += 4;
 489                 len -= 4;
 490         }
 491         while (len >> 1) {
 492                 writew(cpu_to_le16(*(u16 *)data),
 493                        hc->pci_membase + A_FIFO_DATA0);
 494                 data += 2;
 495                 len -= 2;
 496         }
 497         while (len) {
 498                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 499                 data++;
 500                 len--;
 501         }
 502 }
 503
 504 /* read fifo data (REGIO) */
 505 static void
 506 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 507 {
 508         outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
 509         while (len >> 2) {
 510                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 511                 data += 4;
 512                 len -= 4;
 513         }
 514         while (len >> 1) {
 515                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 516                 data += 2;
 517                 len -= 2;
 518         }
 519         while (len) {
 520                 *data = inb(hc->pci_iobase);
 521                 data++;
 522                 len--;
 523         }
 524 }
 525
 526 /* read fifo data (PCIMEM) */
 527 static void
 528 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 529 {
 530         while (len >> 2) {
 531                 *(u32 *)data =
 532                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 533                 data += 4;
 534                 len -= 4;
 535         }
 536         while (len >> 1) {
 537                 *(u16 *)data =
 538                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 539                 data += 2;
 540                 len -= 2;
 541         }
 542         while (len) {
 543                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 544                 data++;
 545                 len--;
 546         }
 547 }
 548
 549 static void
 550 enable_hwirq(struct hfc_multi *hc)
 551 {
 552         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 553         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 554 }
 555
 556 static void
 557 disable_hwirq(struct hfc_multi *hc)
 558 {
 559         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 560         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 561 }
 562
 563 #define NUM_EC 2
 564 #define MAX_TDM_CHAN 32
 565
 566
 567 static inline void
 568 enablepcibridge(struct hfc_multi *c)
 569 {
 570         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 571 }
 572
 573 static inline void
 574 disablepcibridge(struct hfc_multi *c)
 575 {
 576         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 577 }
 578
 579 static inline unsigned char
 580 readpcibridge(struct hfc_multi *hc, unsigned char address)
 581 {
 582         unsigned short cipv;
 583         unsigned char data;
 584
 585         if (!hc->pci_iobase)
 586                 return 0;
 587
 588         /* slow down a PCI read access by 1 PCI clock cycle */
 589         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 590
 591         if (address == 0)
 592                 cipv = 0x4000;
 593         else
 594                 cipv = 0x5800;
 595
 596         /* select local bridge port address by writing to CIP port */
 597         /* data = HFC_inb(c, cipv); * was _io before */
 598         outw(cipv, hc->pci_iobase + 4);
 599         data = inb(hc->pci_iobase);
 600
 601         /* restore R_CTRL for normal PCI read cycle speed */
 602         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 603
 604         return data;
 605 }
 606
 607 static inline void
 608 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 609 {
 610         unsigned short cipv;
 611         unsigned int datav;
 612
 613         if (!hc->pci_iobase)
 614                 return;
 615
 616         if (address == 0)
 617                 cipv = 0x4000;
 618         else
 619                 cipv = 0x5800;
 620
 621         /* select local bridge port address by writing to CIP port */
 622         outw(cipv, hc->pci_iobase + 4);
 623         /* define a 32 bit dword with 4 identical bytes for write sequence */
 624         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 625                 ((__u32) data << 24);
 626
 627         /*
 628          * write this 32 bit dword to the bridge data port
 629          * this will initiate a write sequence of up to 4 writes to the same
 630          * address on the local bus interface the number of write accesses
 631          * is undefined but >=1 and depends on the next PCI transaction
 632          * during write sequence on the local bus
 633          */
 634         outl(datav, hc->pci_iobase);
 635 }
 636
 637 static inline void
 638 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 639 {
 640         /* Do data pin read low byte */
 641         HFC_outb(hc, R_GPIO_OUT1, reg);
 642 }
 643
 644 static inline void
 645 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 646 {
 647         cpld_set_reg(hc, reg);
 648
 649         enablepcibridge(hc);
 650         writepcibridge(hc, 1, val);
 651         disablepcibridge(hc);
 652
 653         return;
 654 }
 655
 656 static inline unsigned char
 657 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 658 {
 659         unsigned char bytein;
 660
 661         cpld_set_reg(hc, reg);
 662
 663         /* Do data pin read low byte */
 664         HFC_outb(hc, R_GPIO_OUT1, reg);
 665
 666         enablepcibridge(hc);
 667         bytein = readpcibridge(hc, 1);
 668         disablepcibridge(hc);
 669
 670         return bytein;
 671 }
 672
 673 static inline void
 674 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 675 {
 676         cpld_write_reg(hc, 0, 0xff & addr);
 677         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 678 }
 679
 680 static inline unsigned short
 681 vpm_read_address(struct hfc_multi *c)
 682 {
 683         unsigned short addr;
 684         unsigned short highbit;
 685
 686         addr = cpld_read_reg(c, 0);
 687         highbit = cpld_read_reg(c, 1);
 688
 689         addr = addr | (highbit << 8);
 690
 691         return addr & 0x1ff;
 692 }
 693
 694 static inline unsigned char
 695 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 696 {
 697         unsigned char res;
 698
 699         vpm_write_address(c, addr);
 700
 701         if (!which)
 702                 cpld_set_reg(c, 2);
 703         else
 704                 cpld_set_reg(c, 3);
 705
 706         enablepcibridge(c);
 707         res = readpcibridge(c, 1);
 708         disablepcibridge(c);
 709
 710         cpld_set_reg(c, 0);
 711
 712         return res;
 713 }
 714
 715 static inline void
 716 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 717         unsigned char data)
 718 {
 719         vpm_write_address(c, addr);
 720
 721         enablepcibridge(c);
 722
 723         if (!which)
 724                 cpld_set_reg(c, 2);
 725         else
 726                 cpld_set_reg(c, 3);
 727
 728         writepcibridge(c, 1, data);
 729
 730         cpld_set_reg(c, 0);
 731
 732         disablepcibridge(c);
 733
 734         {
 735                 unsigned char regin;
 736                 regin = vpm_in(c, which, addr);
 737                 if (regin != data)
 738                         printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 739                                "0x%x\n", data, addr, regin);
 740         }
 741
 742 }
 743
 744
 745 static void
 746 vpm_init(struct hfc_multi *wc)
 747 {
 748         unsigned char reg;
 749         unsigned int mask;
 750         unsigned int i, x, y;
 751         unsigned int ver;
 752
 753         for (x = 0; x < NUM_EC; x++) {
 754                 /* Setup GPIO's */
 755                 if (!x) {
 756                         ver = vpm_in(wc, x, 0x1a0);
 757                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 758                 }
 759
 760                 for (y = 0; y < 4; y++) {
 761                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 762                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 763                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 764                 }
 765
 766                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 767                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 768                 vpm_out(wc, x, 0x1a3, reg & ~2);
 769
 770                 /* Setup Echo length (256 taps) */
 771                 vpm_out(wc, x, 0x022, 1);
 772                 vpm_out(wc, x, 0x023, 0xff);
 773
 774                 /* Setup timeslots */
 775                 vpm_out(wc, x, 0x02f, 0x00);
 776                 mask = 0x02020202 << (x * 4);
 777
 778                 /* Setup the tdm channel masks for all chips */
 779                 for (i = 0; i < 4; i++)
 780                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 781
 782                 /* Setup convergence rate */
 783                 printk(KERN_DEBUG "VPM: A-law mode\n");
 784                 reg = 0x00 | 0x10 | 0x01;
 785                 vpm_out(wc, x, 0x20, reg);
 786                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 787                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 788
 789                 vpm_out(wc, x, 0x24, 0x02);
 790                 reg = vpm_in(wc, x, 0x24);
 791                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 792
 793                 /* Initialize echo cans */
 794                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 795                         if (mask & (0x00000001 << i))
 796                                 vpm_out(wc, x, i, 0x00);
 797                 }
 798
 799                 /*
 800                  * ARM arch at least disallows a udelay of
 801                  * more than 2ms... it gives a fake "__bad_udelay"
 802                  * reference at link-time.
 803                  * long delays in kernel code are pretty sucky anyway
 804                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 805                  */
 806
 807                 udelay(2000);
 808                 udelay(2000);
 809                 udelay(2000);
 810                 udelay(2000);
 811                 udelay(2000);
 812
 813                 /* Put in bypass mode */
 814                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 815                         if (mask & (0x00000001 << i))
 816                                 vpm_out(wc, x, i, 0x01);
 817                 }
 818
 819                 /* Enable bypass */
 820                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 821                         if (mask & (0x00000001 << i))
 822                                 vpm_out(wc, x, 0x78 + i, 0x01);
 823                 }
 824
 825         }
 826 }
 827
 828 #ifdef UNUSED
 829 static void
 830 vpm_check(struct hfc_multi *hctmp)
 831 {
 832         unsigned char gpi2;
 833
 834         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 835
 836         if ((gpi2 & 0x3) != 0x3)
 837                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 838 }
 839 #endif /* UNUSED */
 840
 841
 842 /*
 843  * Interface to enable/disable the HW Echocan
 844  *
 845  * these functions are called within a spin_lock_irqsave on
 846  * the channel instance lock, so we are not disturbed by irqs
 847  *
 848  * we can later easily change the interface to make  other
 849  * things configurable, for now we configure the taps
 850  *
 851  */
 852
 853 static void
 854 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 855 {
 856         unsigned int timeslot;
 857         unsigned int unit;
 858         struct bchannel *bch = hc->chan[ch].bch;
 859 #ifdef TXADJ
 860         int txadj = -4;
 861         struct sk_buff *skb;
 862 #endif
 863         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 864                 return;
 865
 866         if (!bch)
 867                 return;
 868
 869 #ifdef TXADJ
 870         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 871                                sizeof(int), &txadj, GFP_ATOMIC);
 872         if (skb)
 873                 recv_Bchannel_skb(bch, skb);
 874 #endif
 875
 876         timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
 877         unit = ch % 4;
 878
 879         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 880                taps, timeslot);
 881
 882         vpm_out(hc, unit, timeslot, 0x7e);
 883 }
 884
 885 static void
 886 vpm_echocan_off(struct hfc_multi *hc, int ch)
 887 {
 888         unsigned int timeslot;
 889         unsigned int unit;
 890         struct bchannel *bch = hc->chan[ch].bch;
 891 #ifdef TXADJ
 892         int txadj = 0;
 893         struct sk_buff *skb;
 894 #endif
 895
 896         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 897                 return;
 898
 899         if (!bch)
 900                 return;
 901
 902 #ifdef TXADJ
 903         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 904                                sizeof(int), &txadj, GFP_ATOMIC);
 905         if (skb)
 906                 recv_Bchannel_skb(bch, skb);
 907 #endif
 908
 909         timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
 910         unit = ch % 4;
 911
 912         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 913                timeslot);
 914         /* FILLME */
 915         vpm_out(hc, unit, timeslot, 0x01);
 916 }
 917
 918
 919 /*
 920  * Speech Design resync feature
 921  * NOTE: This is called sometimes outside interrupt handler.
 922  * We must lock irqsave, so no other interrupt (other card) will occur!
 923  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 924  */
 925 static inline void
 926 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 927 {
 928         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 929         void __iomem *plx_acc_32;
 930         u_int pv;
 931         u_long flags;
 932
 933         spin_lock_irqsave(&HFClock, flags);
 934         spin_lock(&plx_lock); /* must be locked inside other locks */
 935
 936         if (debug & DEBUG_HFCMULTI_PLXSD)
 937                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 938                        __func__, syncmaster);
 939
 940         /* select new master */
 941         if (newmaster) {
 942                 if (debug & DEBUG_HFCMULTI_PLXSD)
 943                         printk(KERN_DEBUG "using provided controller\n");
 944         } else {
 945                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 946                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 947                                 if (hc->syncronized) {
 948                                         newmaster = hc;
 949                                         break;
 950                                 }
 951                         }
 952                 }
 953         }
 954
 955         /* Disable sync of all cards */
 956         list_for_each_entry_safe(hc, next, &HFClist, list) {
 957                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 958                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 959                         pv = readl(plx_acc_32);
 960                         pv &= ~PLX_SYNC_O_EN;
 961                         writel(pv, plx_acc_32);
 962                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 963                                 pcmmaster = hc;
 964                                 if (hc->ctype == HFC_TYPE_E1) {
 965                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 966                                                 printk(KERN_DEBUG
 967                                                        "Schedule SYNC_I\n");
 968                                         hc->e1_resync |= 1; /* get SYNC_I */
 969                                 }
 970                         }
 971                 }
 972         }
 973
 974         if (newmaster) {
 975                 hc = newmaster;
 976                 if (debug & DEBUG_HFCMULTI_PLXSD)
 977                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 978                                "interface.\n", hc->id, hc);
 979                 /* Enable new sync master */
 980                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 981                 pv = readl(plx_acc_32);
 982                 pv |= PLX_SYNC_O_EN;
 983                 writel(pv, plx_acc_32);
 984                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 985                 if (hc->ctype == HFC_TYPE_E1
 986                     && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 987                         if (debug & DEBUG_HFCMULTI_PLXSD)
 988                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 989                         hc->e1_resync |= 2; /* switch to jatt */
 990                 }
 991         } else {
 992                 if (pcmmaster) {
 993                         hc = pcmmaster;
 994                         if (debug & DEBUG_HFCMULTI_PLXSD)
 995                                 printk(KERN_DEBUG
 996                                        "id=%d (0x%p) = PCM master syncronized "
 997                                        "with QUARTZ\n", hc->id, hc);
 998                         if (hc->ctype == HFC_TYPE_E1) {
 999                                 /* Use the crystal clock for the PCM
1000                                    master card */
1001                                 if (debug & DEBUG_HFCMULTI_PLXSD)
1002                                         printk(KERN_DEBUG
1003                                                "Schedule QUARTZ for HFC-E1\n");
1004                                 hc->e1_resync |= 4; /* switch quartz */
1005                         } else {
1006                                 if (debug & DEBUG_HFCMULTI_PLXSD)
1007                                         printk(KERN_DEBUG
1008                                                "QUARTZ is automatically "
1009                                                "enabled by HFC-%dS\n", hc->ctype);
1010                         }
1011                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1012                         pv = readl(plx_acc_32);
1013                         pv |= PLX_SYNC_O_EN;
1014                         writel(pv, plx_acc_32);
1015                 } else
1016                         if (!rm)
1017                                 printk(KERN_ERR "%s no pcm master, this MUST "
1018                                        "not happen!\n", __func__);
1019         }
1020         syncmaster = newmaster;
1021
1022         spin_unlock(&plx_lock);
1023         spin_unlock_irqrestore(&HFClock, flags);
1024 }
1025
1026 /* This must be called AND hc must be locked irqsave!!! */
1027 static inline void
1028 plxsd_checksync(struct hfc_multi *hc, int rm)
1029 {
1030         if (hc->syncronized) {
1031                 if (syncmaster == NULL) {
1032                         if (debug & DEBUG_HFCMULTI_PLXSD)
1033                                 printk(KERN_DEBUG "%s: GOT sync on card %d"
1034                                        " (id=%d)\n", __func__, hc->id + 1,
1035                                        hc->id);
1036                         hfcmulti_resync(hc, hc, rm);
1037                 }
1038         } else {
1039                 if (syncmaster == hc) {
1040                         if (debug & DEBUG_HFCMULTI_PLXSD)
1041                                 printk(KERN_DEBUG "%s: LOST sync on card %d"
1042                                        " (id=%d)\n", __func__, hc->id + 1,
1043                                        hc->id);
1044                         hfcmulti_resync(hc, NULL, rm);
1045                 }
1046         }
1047 }
1048
1049
1050 /*
1051  * free hardware resources used by driver
1052  */
1053 static void
1054 release_io_hfcmulti(struct hfc_multi *hc)
1055 {
1056         void __iomem *plx_acc_32;
1057         u_int   pv;
1058         u_long  plx_flags;
1059
1060         if (debug & DEBUG_HFCMULTI_INIT)
1061                 printk(KERN_DEBUG "%s: entered\n", __func__);
1062
1063         /* soft reset also masks all interrupts */
1064         hc->hw.r_cirm |= V_SRES;
1065         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1066         udelay(1000);
1067         hc->hw.r_cirm &= ~V_SRES;
1068         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1069         udelay(1000); /* instead of 'wait' that may cause locking */
1070
1071         /* release Speech Design card, if PLX was initialized */
1072         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1073                 if (debug & DEBUG_HFCMULTI_PLXSD)
1074                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1075                                __func__, hc->id + 1);
1076                 spin_lock_irqsave(&plx_lock, plx_flags);
1077                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1078                 writel(PLX_GPIOC_INIT, plx_acc_32);
1079                 pv = readl(plx_acc_32);
1080                 /* Termination off */
1081                 pv &= ~PLX_TERM_ON;
1082                 /* Disconnect the PCM */
1083                 pv |= PLX_SLAVE_EN_N;
1084                 pv &= ~PLX_MASTER_EN;
1085                 pv &= ~PLX_SYNC_O_EN;
1086                 /* Put the DSP in Reset */
1087                 pv &= ~PLX_DSP_RES_N;
1088                 writel(pv, plx_acc_32);
1089                 if (debug & DEBUG_HFCMULTI_INIT)
1090                         printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1091                                __func__, pv);
1092                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1093         }
1094
1095         /* disable memory mapped ports / io ports */
1096         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1097         if (hc->pci_dev)
1098                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1099         if (hc->pci_membase)
1100                 iounmap(hc->pci_membase);
1101         if (hc->plx_membase)
1102                 iounmap(hc->plx_membase);
1103         if (hc->pci_iobase)
1104                 release_region(hc->pci_iobase, 8);
1105         if (hc->xhfc_membase)
1106                 iounmap((void *)hc->xhfc_membase);
1107
1108         if (hc->pci_dev) {
1109                 pci_disable_device(hc->pci_dev);
1110                 pci_set_drvdata(hc->pci_dev, NULL);
1111         }
1112         if (debug & DEBUG_HFCMULTI_INIT)
1113                 printk(KERN_DEBUG "%s: done\n", __func__);
1114 }
1115
1116 /*
1117  * function called to reset the HFC chip. A complete software reset of chip
1118  * and fifos is done. All configuration of the chip is done.
1119  */
1120
1121 static int
1122 init_chip(struct hfc_multi *hc)
1123 {
1124         u_long                  flags, val, val2 = 0, rev;
1125         int                     i, err = 0;
1126         u_char                  r_conf_en, rval;
1127         void __iomem            *plx_acc_32;
1128         u_int                   pv;
1129         u_long                  plx_flags, hfc_flags;
1130         int                     plx_count;
1131         struct hfc_multi        *pos, *next, *plx_last_hc;
1132
1133         spin_lock_irqsave(&hc->lock, flags);
1134         /* reset all registers */
1135         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1136
1137         /* revision check */
1138         if (debug & DEBUG_HFCMULTI_INIT)
1139                 printk(KERN_DEBUG "%s: entered\n", __func__);
1140         val = HFC_inb(hc, R_CHIP_ID);
1141         if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1142             (val >> 1) != 0x31) {
1143                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1144                 err = -EIO;
1145                 goto out;
1146         }
1147         rev = HFC_inb(hc, R_CHIP_RV);
1148         printk(KERN_INFO
1149                "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1150                val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1151                " (old FIFO handling)" : "");
1152         if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1153                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1154                 printk(KERN_WARNING
1155                        "HFC_multi: NOTE: Your chip is revision 0, "
1156                        "ask Cologne Chip for update. Newer chips "
1157                        "have a better FIFO handling. Old chips "
1158                        "still work but may have slightly lower "
1159                        "HDLC transmit performance.\n");
1160         }
1161         if (rev > 1) {
1162                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1163                        "consider chip revision = %ld. The chip / "
1164                        "bridge may not work.\n", rev);
1165         }
1166
1167         /* set s-ram size */
1168         hc->Flen = 0x10;
1169         hc->Zmin = 0x80;
1170         hc->Zlen = 384;
1171         hc->DTMFbase = 0x1000;
1172         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1173                 if (debug & DEBUG_HFCMULTI_INIT)
1174                         printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
1175                                __func__);
1176                 hc->hw.r_ctrl |= V_EXT_RAM;
1177                 hc->hw.r_ram_sz = 1;
1178                 hc->Flen = 0x20;
1179                 hc->Zmin = 0xc0;
1180                 hc->Zlen = 1856;
1181                 hc->DTMFbase = 0x2000;
1182         }
1183         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1184                 if (debug & DEBUG_HFCMULTI_INIT)
1185                         printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
1186                                __func__);
1187                 hc->hw.r_ctrl |= V_EXT_RAM;
1188                 hc->hw.r_ram_sz = 2;
1189                 hc->Flen = 0x20;
1190                 hc->Zmin = 0xc0;
1191                 hc->Zlen = 8000;
1192                 hc->DTMFbase = 0x2000;
1193         }
1194         if (hc->ctype == HFC_TYPE_XHFC) {
1195                 hc->Flen = 0x8;
1196                 hc->Zmin = 0x0;
1197                 hc->Zlen = 64;
1198                 hc->DTMFbase = 0x0;
1199         }
1200         hc->max_trans = poll << 1;
1201         if (hc->max_trans > hc->Zlen)
1202                 hc->max_trans = hc->Zlen;
1203
1204         /* Speech Design PLX bridge */
1205         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1206                 if (debug & DEBUG_HFCMULTI_PLXSD)
1207                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1208                                __func__, hc->id + 1);
1209                 spin_lock_irqsave(&plx_lock, plx_flags);
1210                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1211                 writel(PLX_GPIOC_INIT, plx_acc_32);
1212                 pv = readl(plx_acc_32);
1213                 /* The first and the last cards are terminating the PCM bus */
1214                 pv |= PLX_TERM_ON; /* hc is currently the last */
1215                 /* Disconnect the PCM */
1216                 pv |= PLX_SLAVE_EN_N;
1217                 pv &= ~PLX_MASTER_EN;
1218                 pv &= ~PLX_SYNC_O_EN;
1219                 /* Put the DSP in Reset */
1220                 pv &= ~PLX_DSP_RES_N;
1221                 writel(pv, plx_acc_32);
1222                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1223                 if (debug & DEBUG_HFCMULTI_INIT)
1224                         printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1225                                __func__, pv);
1226                 /*
1227                  * If we are the 3rd PLXSD card or higher, we must turn
1228                  * termination of last PLXSD card off.
1229                  */
1230                 spin_lock_irqsave(&HFClock, hfc_flags);
1231                 plx_count = 0;
1232                 plx_last_hc = NULL;
1233                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1234                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1235                                 plx_count++;
1236                                 if (pos != hc)
1237                                         plx_last_hc = pos;
1238                         }
1239                 }
1240                 if (plx_count >= 3) {
1241                         if (debug & DEBUG_HFCMULTI_PLXSD)
1242                                 printk(KERN_DEBUG "%s: card %d is between, so "
1243                                        "we disable termination\n",
1244                                        __func__, plx_last_hc->id + 1);
1245                         spin_lock_irqsave(&plx_lock, plx_flags);
1246                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1247                         pv = readl(plx_acc_32);
1248                         pv &= ~PLX_TERM_ON;
1249                         writel(pv, plx_acc_32);
1250                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1251                         if (debug & DEBUG_HFCMULTI_INIT)
1252                                 printk(KERN_DEBUG
1253                                        "%s: term off: PLX_GPIO=%x\n",
1254                                        __func__, pv);
1255                 }
1256                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1257                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1258         }
1259
1260         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1261                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1262
1263         /* we only want the real Z2 read-pointer for revision > 0 */
1264         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1265                 hc->hw.r_ram_sz |= V_FZ_MD;
1266
1267         /* select pcm mode */
1268         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1269                 if (debug & DEBUG_HFCMULTI_INIT)
1270                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1271                                __func__);
1272         } else
1273                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1274                         if (debug & DEBUG_HFCMULTI_INIT)
1275                                 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1276                                        __func__);
1277                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1278                 } else {
1279                         if (debug & DEBUG_HFCMULTI_INIT)
1280                                 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1281                                        __func__);
1282                 }
1283
1284         /* soft reset */
1285         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1286         if (hc->ctype == HFC_TYPE_XHFC)
1287                 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1288                          0x11 /* 16 Bytes TX/RX */);
1289         else
1290                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1291         HFC_outb(hc, R_FIFO_MD, 0);
1292         if (hc->ctype == HFC_TYPE_XHFC)
1293                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1294         else
1295                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1296                         | V_RLD_EPR;
1297         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1298         udelay(100);
1299         hc->hw.r_cirm = 0;
1300         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1301         udelay(100);
1302         if (hc->ctype != HFC_TYPE_XHFC)
1303                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1304
1305         /* Speech Design PLX bridge pcm and sync mode */
1306         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1307                 spin_lock_irqsave(&plx_lock, plx_flags);
1308                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1309                 pv = readl(plx_acc_32);
1310                 /* Connect PCM */
1311                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1312                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1313                         pv |= PLX_SYNC_O_EN;
1314                         if (debug & DEBUG_HFCMULTI_INIT)
1315                                 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1316                                        __func__, pv);
1317                 } else {
1318                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1319                         pv &= ~PLX_SYNC_O_EN;
1320                         if (debug & DEBUG_HFCMULTI_INIT)
1321                                 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1322                                        __func__, pv);
1323                 }
1324                 writel(pv, plx_acc_32);
1325                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1326         }
1327
1328         /* PCM setup */
1329         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1330         if (hc->slots == 32)
1331                 HFC_outb(hc, R_PCM_MD1, 0x00);
1332         if (hc->slots == 64)
1333                 HFC_outb(hc, R_PCM_MD1, 0x10);
1334         if (hc->slots == 128)
1335                 HFC_outb(hc, R_PCM_MD1, 0x20);
1336         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1337         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1338                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1339         else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1340                 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1341         else
1342                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1343         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1344         for (i = 0; i < 256; i++) {
1345                 HFC_outb_nodebug(hc, R_SLOT, i);
1346                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1347                 if (hc->ctype != HFC_TYPE_XHFC)
1348                         HFC_outb_nodebug(hc, A_CONF, 0);
1349                 hc->slot_owner[i] = -1;
1350         }
1351
1352         /* set clock speed */
1353         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1354                 if (debug & DEBUG_HFCMULTI_INIT)
1355                         printk(KERN_DEBUG
1356                                "%s: setting double clock\n", __func__);
1357                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1358         }
1359
1360         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1361                 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1362
1363         /* B410P GPIO */
1364         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1365                 printk(KERN_NOTICE "Setting GPIOs\n");
1366                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1367                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1368                 udelay(1000);
1369                 printk(KERN_NOTICE "calling vpm_init\n");
1370                 vpm_init(hc);
1371         }
1372
1373         /* check if R_F0_CNT counts (8 kHz frame count) */
1374         val = HFC_inb(hc, R_F0_CNTL);
1375         val += HFC_inb(hc, R_F0_CNTH) << 8;
1376         if (debug & DEBUG_HFCMULTI_INIT)
1377                 printk(KERN_DEBUG
1378                        "HFC_multi F0_CNT %ld after reset\n", val);
1379         spin_unlock_irqrestore(&hc->lock, flags);
1380         set_current_state(TASK_UNINTERRUPTIBLE);
1381         schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1382         spin_lock_irqsave(&hc->lock, flags);
1383         val2 = HFC_inb(hc, R_F0_CNTL);
1384         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1385         if (debug & DEBUG_HFCMULTI_INIT)
1386                 printk(KERN_DEBUG
1387                        "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1388                        val2);
1389         if (val2 >= val + 8) { /* 1 ms */
1390                 /* it counts, so we keep the pcm mode */
1391                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1392                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1393                 else
1394                         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1395                                 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1396                         else {
1397                                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1398                                 printk(KERN_INFO "controller is PCM bus SLAVE "
1399                                        "(auto detected)\n");
1400                         }
1401         } else {
1402                 /* does not count */
1403                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1404                 controller_fail:
1405                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1406                                "pulse. Seems that controller fails.\n");
1407                         err = -EIO;
1408                         goto out;
1409                 }
1410                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1411                         printk(KERN_INFO "controller is PCM bus SLAVE "
1412                                "(ignoring missing PCM clock)\n");
1413                 } else {
1414                         /* only one pcm master */
1415                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1416                             && plxsd_master) {
1417                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1418                                        "on another Speech Design card found. "
1419                                        "Please be sure to connect PCM cable.\n");
1420                                 err = -EIO;
1421                                 goto out;
1422                         }
1423                         /* retry with master clock */
1424                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1425                                 spin_lock_irqsave(&plx_lock, plx_flags);
1426                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1427                                 pv = readl(plx_acc_32);
1428                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1429                                 pv |= PLX_SYNC_O_EN;
1430                                 writel(pv, plx_acc_32);
1431                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1432                                 if (debug & DEBUG_HFCMULTI_INIT)
1433                                         printk(KERN_DEBUG "%s: master: "
1434                                                "PLX_GPIO=%x\n", __func__, pv);
1435                         }
1436                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1437                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1438                         spin_unlock_irqrestore(&hc->lock, flags);
1439                         set_current_state(TASK_UNINTERRUPTIBLE);
1440                         schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1441                         spin_lock_irqsave(&hc->lock, flags);
1442                         val2 = HFC_inb(hc, R_F0_CNTL);
1443                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1444                         if (debug & DEBUG_HFCMULTI_INIT)
1445                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1446                                        "10 ms (2nd try)\n", val2);
1447                         if (val2 >= val + 8) { /* 1 ms */
1448                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1449                                                  &hc->chip);
1450                                 printk(KERN_INFO "controller is PCM bus MASTER "
1451                                        "(auto detected)\n");
1452                         } else
1453                                 goto controller_fail;
1454                 }
1455         }
1456
1457         /* Release the DSP Reset */
1458         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1459                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1460                         plxsd_master = 1;
1461                 spin_lock_irqsave(&plx_lock, plx_flags);
1462                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1463                 pv = readl(plx_acc_32);
1464                 pv |=  PLX_DSP_RES_N;
1465                 writel(pv, plx_acc_32);
1466                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1467                 if (debug & DEBUG_HFCMULTI_INIT)
1468                         printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1469                                __func__, pv);
1470         }
1471
1472         /* pcm id */
1473         if (hc->pcm)
1474                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1475                        hc->pcm);
1476         else {
1477                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1478                     || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1479                         PCM_cnt++; /* SD has proprietary bridging */
1480                 }
1481                 hc->pcm = PCM_cnt;
1482                 printk(KERN_INFO "controller has PCM BUS ID %d "
1483                        "(auto selected)\n", hc->pcm);
1484         }
1485
1486         /* set up timer */
1487         HFC_outb(hc, R_TI_WD, poll_timer);
1488         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1489
1490         /* set E1 state machine IRQ */
1491         if (hc->ctype == HFC_TYPE_E1)
1492                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1493
1494         /* set DTMF detection */
1495         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1496                 if (debug & DEBUG_HFCMULTI_INIT)
1497                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1498                                "for all B-channel\n", __func__);
1499                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1500                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1501                         hc->hw.r_dtmf |= V_ULAW_SEL;
1502                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1503                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1504         }
1505
1506         /* conference engine */
1507         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1508                 r_conf_en = V_CONF_EN | V_ULAW;
1509         else
1510                 r_conf_en = V_CONF_EN;
1511         if (hc->ctype != HFC_TYPE_XHFC)
1512                 HFC_outb(hc, R_CONF_EN, r_conf_en);
1513
1514         /* setting leds */
1515         switch (hc->leds) {
1516         case 1: /* HFC-E1 OEM */
1517                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1518                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1519                 else
1520                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1521
1522                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1523                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1524
1525                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1526                 break;
1527
1528         case 2: /* HFC-4S OEM */
1529         case 3:
1530                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1531                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1532                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1533                 break;
1534         }
1535
1536         if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1537                 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1538                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1539         }
1540
1541         /* set master clock */
1542         if (hc->masterclk >= 0) {
1543                 if (debug & DEBUG_HFCMULTI_INIT)
1544                         printk(KERN_DEBUG "%s: setting ST master clock "
1545                                "to port %d (0..%d)\n",
1546                                __func__, hc->masterclk, hc->ports - 1);
1547                 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1548                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1549         }
1550
1551
1552
1553         /* setting misc irq */
1554         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1555         if (debug & DEBUG_HFCMULTI_INIT)
1556                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1557                        hc->hw.r_irqmsk_misc);
1558
1559         /* RAM access test */
1560         HFC_outb(hc, R_RAM_ADDR0, 0);
1561         HFC_outb(hc, R_RAM_ADDR1, 0);
1562         HFC_outb(hc, R_RAM_ADDR2, 0);
1563         for (i = 0; i < 256; i++) {
1564                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1565                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1566         }
1567         for (i = 0; i < 256; i++) {
1568                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1569                 HFC_inb_nodebug(hc, R_RAM_DATA);
1570                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1571                 if (rval != ((i * 3) & 0xff)) {
1572                         printk(KERN_DEBUG
1573                                "addr:%x val:%x should:%x\n", i, rval,
1574                                (i * 3) & 0xff);
1575                         err++;
1576                 }
1577         }
1578         if (err) {
1579                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1580                 err = -EIO;
1581                 goto out;
1582         }
1583
1584         if (debug & DEBUG_HFCMULTI_INIT)
1585                 printk(KERN_DEBUG "%s: done\n", __func__);
1586 out:
1587         spin_unlock_irqrestore(&hc->lock, flags);
1588         return err;
1589 }
1590
1591
1592 /*
1593  * control the watchdog
1594  */
1595 static void
1596 hfcmulti_watchdog(struct hfc_multi *hc)
1597 {
1598         hc->wdcount++;
1599
1600         if (hc->wdcount > 10) {
1601                 hc->wdcount = 0;
1602                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1603                         V_GPIO_OUT3 : V_GPIO_OUT2;
1604
1605                 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1606                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1607                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1608         }
1609 }
1610
1611
1612
1613 /*
1614  * output leds
1615  */
1616 static void
1617 hfcmulti_leds(struct hfc_multi *hc)
1618 {
1619         unsigned long lled;
1620         unsigned long leddw;
1621         int i, state, active, leds;
1622         struct dchannel *dch;
1623         int led[4];
1624
1625         switch (hc->leds) {
1626         case 1: /* HFC-E1 OEM */
1627                 /* 2 red steady:       LOS
1628                  * 1 red steady:       L1 not active
1629                  * 2 green steady:     L1 active
1630                  * 1st green flashing: activity on TX
1631                  * 2nd green flashing: activity on RX
1632                  */
1633                 led[0] = 0;
1634                 led[1] = 0;
1635                 led[2] = 0;
1636                 led[3] = 0;
1637                 dch = hc->chan[hc->dnum[0]].dch;
1638                 if (dch) {
1639                         if (hc->chan[hc->dnum[0]].los)
1640                                 led[1] = 1;
1641                         if (hc->e1_state != 1) {
1642                                 led[0] = 1;
1643                                 hc->flash[2] = 0;
1644                                 hc->flash[3] = 0;
1645                         } else {
1646                                 led[2] = 1;
1647                                 led[3] = 1;
1648                                 if (!hc->flash[2] && hc->activity_tx)
1649                                         hc->flash[2] = poll;
1650                                 if (!hc->flash[3] && hc->activity_rx)
1651                                         hc->flash[3] = poll;
1652                                 if (hc->flash[2] && hc->flash[2] < 1024)
1653                                         led[2] = 0;
1654                                 if (hc->flash[3] && hc->flash[3] < 1024)
1655                                         led[3] = 0;
1656                                 if (hc->flash[2] >= 2048)
1657                                         hc->flash[2] = 0;
1658                                 if (hc->flash[3] >= 2048)
1659                                         hc->flash[3] = 0;
1660                                 if (hc->flash[2])
1661                                         hc->flash[2] += poll;
1662                                 if (hc->flash[3])
1663                                         hc->flash[3] += poll;
1664                         }
1665                 }
1666                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1667                 /* leds are inverted */
1668                 if (leds != (int)hc->ledstate) {
1669                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1670                         hc->ledstate = leds;
1671                 }
1672                 break;
1673
1674         case 2: /* HFC-4S OEM */
1675                 /* red steady:     PH_DEACTIVATE
1676                  * green steady:   PH_ACTIVATE
1677                  * green flashing: activity on TX
1678                  */
1679                 for (i = 0; i < 4; i++) {
1680                         state = 0;
1681                         active = -1;
1682                         dch = hc->chan[(i << 2) | 2].dch;
1683                         if (dch) {
1684                                 state = dch->state;
1685                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1686                                         active = 3;
1687                                 else
1688                                         active = 7;
1689                         }
1690                         if (state) {
1691                                 if (state == active) {
1692                                         led[i] = 1; /* led green */
1693                                         hc->activity_tx |= hc->activity_rx;
1694                                         if (!hc->flash[i] &&
1695                                                 (hc->activity_tx & (1 << i)))
1696                                                         hc->flash[i] = poll;
1697                                         if (hc->flash[i] && hc->flash[i] < 1024)
1698                                                 led[i] = 0; /* led off */
1699                                         if (hc->flash[i] >= 2048)
1700                                                 hc->flash[i] = 0;
1701                                         if (hc->flash[i])
1702                                                 hc->flash[i] += poll;
1703                                 } else {
1704                                         led[i] = 2; /* led red */
1705                                         hc->flash[i] = 0;
1706                                 }
1707                         } else
1708                                 led[i] = 0; /* led off */
1709                 }
1710                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1711                         leds = 0;
1712                         for (i = 0; i < 4; i++) {
1713                                 if (led[i] == 1) {
1714                                         /*green*/
1715                                         leds |= (0x2 << (i * 2));
1716                                 } else if (led[i] == 2) {
1717                                         /*red*/
1718                                         leds |= (0x1 << (i * 2));
1719                                 }
1720                         }
1721                         if (leds != (int)hc->ledstate) {
1722                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1723                                 hc->ledstate = leds;
1724                         }
1725                 } else {
1726                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1727                                 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1728                                 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1729                                 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1730                         if (leds != (int)hc->ledstate) {
1731                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1732                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1733                                 hc->ledstate = leds;
1734                         }
1735                 }
1736                 break;
1737
1738         case 3: /* HFC 1S/2S Beronet */
1739                 /* red steady:     PH_DEACTIVATE
1740                  * green steady:   PH_ACTIVATE
1741                  * green flashing: activity on TX
1742                  */
1743                 for (i = 0; i < 2; i++) {
1744                         state = 0;
1745                         active = -1;
1746                         dch = hc->chan[(i << 2) | 2].dch;
1747                         if (dch) {
1748                                 state = dch->state;
1749                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1750                                         active = 3;
1751                                 else
1752                                         active = 7;
1753                         }
1754                         if (state) {
1755                                 if (state == active) {
1756                                         led[i] = 1; /* led green */
1757                                         hc->activity_tx |= hc->activity_rx;
1758                                         if (!hc->flash[i] &&
1759                                                 (hc->activity_tx & (1 << i)))
1760                                                         hc->flash[i] = poll;
1761                                         if (hc->flash[i] < 1024)
1762                                                 led[i] = 0; /* led off */
1763                                         if (hc->flash[i] >= 2048)
1764                                                 hc->flash[i] = 0;
1765                                         if (hc->flash[i])
1766                                                 hc->flash[i] += poll;
1767                                 } else {
1768                                         led[i] = 2; /* led red */
1769                                         hc->flash[i] = 0;
1770                                 }
1771                         } else
1772                                 led[i] = 0; /* led off */
1773                 }
1774                 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1775                         | ((led[1]&1) << 3);
1776                 if (leds != (int)hc->ledstate) {
1777                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1778                                          ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1779                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1780                                          ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1781                         hc->ledstate = leds;
1782                 }
1783                 break;
1784         case 8: /* HFC 8S+ Beronet */
1785                 /* off:      PH_DEACTIVATE
1786                  * steady:   PH_ACTIVATE
1787                  * flashing: activity on TX
1788                  */
1789                 lled = 0xff; /* leds off */
1790                 for (i = 0; i < 8; i++) {
1791                         state = 0;
1792                         active = -1;
1793                         dch = hc->chan[(i << 2) | 2].dch;
1794                         if (dch) {
1795                                 state = dch->state;
1796                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1797                                         active = 3;
1798                                 else
1799                                         active = 7;
1800                         }
1801                         if (state) {
1802                                 if (state == active) {
1803                                         lled &= ~(1 << i); /* led on */
1804                                         hc->activity_tx |= hc->activity_rx;
1805                                         if (!hc->flash[i] &&
1806                                                 (hc->activity_tx & (1 << i)))
1807                                                         hc->flash[i] = poll;
1808                                         if (hc->flash[i] < 1024)
1809                                                 lled |= 1 << i; /* led off */
1810                                         if (hc->flash[i] >= 2048)
1811                                                 hc->flash[i] = 0;
1812                                         if (hc->flash[i])
1813                                                 hc->flash[i] += poll;
1814                                 } else
1815                                         hc->flash[i] = 0;
1816                         }
1817                 }
1818                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1819                 if (leddw != hc->ledstate) {
1820                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1821                            HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1822                         /* was _io before */
1823                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1824                         outw(0x4000, hc->pci_iobase + 4);
1825                         outl(leddw, hc->pci_iobase);
1826                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1827                         hc->ledstate = leddw;
1828                 }
1829                 break;
1830         }
1831         hc->activity_tx = 0;
1832         hc->activity_rx = 0;
1833 }
1834 /*
1835  * read dtmf coefficients
1836  */
1837
1838 static void
1839 hfcmulti_dtmf(struct hfc_multi *hc)
1840 {
1841         s32             *coeff;
1842         u_int           mantissa;
1843         int             co, ch;
1844         struct bchannel *bch = NULL;
1845         u8              exponent;
1846         int             dtmf = 0;
1847         int             addr;
1848         u16             w_float;
1849         struct sk_buff  *skb;
1850         struct mISDNhead *hh;
1851
1852         if (debug & DEBUG_HFCMULTI_DTMF)
1853                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1854         for (ch = 0; ch <= 31; ch++) {
1855                 /* only process enabled B-channels */
1856                 bch = hc->chan[ch].bch;
1857                 if (!bch)
1858                         continue;
1859                 if (!hc->created[hc->chan[ch].port])
1860                         continue;
1861                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1862                         continue;
1863                 if (debug & DEBUG_HFCMULTI_DTMF)
1864                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1865                                __func__, ch);
1866                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1867                 dtmf = 1;
1868                 for (co = 0; co < 8; co++) {
1869                         /* read W(n-1) coefficient */
1870                         addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1871                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1872                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1873                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1874                                          | V_ADDR_INC);
1875                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1876                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1877                         if (debug & DEBUG_HFCMULTI_DTMF)
1878                                 printk(" %04x", w_float);
1879
1880                         /* decode float (see chip doc) */
1881                         mantissa = w_float & 0x0fff;
1882                         if (w_float & 0x8000)
1883                                 mantissa |= 0xfffff000;
1884                         exponent = (w_float >> 12) & 0x7;
1885                         if (exponent) {
1886                                 mantissa ^= 0x1000;
1887                                 mantissa <<= (exponent - 1);
1888                         }
1889
1890                         /* store coefficient */
1891                         coeff[co << 1] = mantissa;
1892
1893                         /* read W(n) coefficient */
1894                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1895                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1896                         if (debug & DEBUG_HFCMULTI_DTMF)
1897                                 printk(" %04x", w_float);
1898
1899                         /* decode float (see chip doc) */
1900                         mantissa = w_float & 0x0fff;
1901                         if (w_float & 0x8000)
1902                                 mantissa |= 0xfffff000;
1903                         exponent = (w_float >> 12) & 0x7;
1904                         if (exponent) {
1905                                 mantissa ^= 0x1000;
1906                                 mantissa <<= (exponent - 1);
1907                         }
1908
1909                         /* store coefficient */
1910                         coeff[(co << 1) | 1] = mantissa;
1911                 }
1912                 if (debug & DEBUG_HFCMULTI_DTMF)
1913                         printk(" DTMF ready %08x %08x %08x %08x "
1914                                "%08x %08x %08x %08x\n",
1915                                coeff[0], coeff[1], coeff[2], coeff[3],
1916                                coeff[4], coeff[5], coeff[6], coeff[7]);
1917                 hc->chan[ch].coeff_count++;
1918                 if (hc->chan[ch].coeff_count == 8) {
1919                         hc->chan[ch].coeff_count = 0;
1920                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1921                         if (!skb) {
1922                                 printk(KERN_DEBUG "%s: No memory for skb\n",
1923                                        __func__);
1924                                 continue;
1925                         }
1926                         hh = mISDN_HEAD_P(skb);
1927                         hh->prim = PH_CONTROL_IND;
1928                         hh->id = DTMF_HFC_COEF;
1929                         skb_put_data(skb, hc->chan[ch].coeff, 512);
1930                         recv_Bchannel_skb(bch, skb);
1931                 }
1932         }
1933
1934         /* restart DTMF processing */
1935         hc->dtmf = dtmf;
1936         if (dtmf)
1937                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1938 }
1939
1940
1941 /*
1942  * fill fifo as much as possible
1943  */
1944
1945 static void
1946 hfcmulti_tx(struct hfc_multi *hc, int ch)
1947 {
1948         int i, ii, temp, len = 0;
1949         int Zspace, z1, z2; /* must be int for calculation */
1950         int Fspace, f1, f2;
1951         u_char *d;
1952         int *txpending, slot_tx;
1953         struct  bchannel *bch;
1954         struct  dchannel *dch;
1955         struct  sk_buff **sp = NULL;
1956         int *idxp;
1957
1958         bch = hc->chan[ch].bch;
1959         dch = hc->chan[ch].dch;
1960         if ((!dch) && (!bch))
1961                 return;
1962
1963         txpending = &hc->chan[ch].txpending;
1964         slot_tx = hc->chan[ch].slot_tx;
1965         if (dch) {
1966                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1967                         return;
1968                 sp = &dch->tx_skb;
1969                 idxp = &dch->tx_idx;
1970         } else {
1971                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1972                         return;
1973                 sp = &bch->tx_skb;
1974                 idxp = &bch->tx_idx;
1975         }
1976         if (*sp)
1977                 len = (*sp)->len;
1978
1979         if ((!len) && *txpending != 1)
1980                 return; /* no data */
1981
1982         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1983             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1984             (hc->chan[ch].slot_rx < 0) &&
1985             (hc->chan[ch].slot_tx < 0))
1986                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1987         else
1988                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1989         HFC_wait_nodebug(hc);
1990
1991         if (*txpending == 2) {
1992                 /* reset fifo */
1993                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1994                 HFC_wait_nodebug(hc);
1995                 HFC_outb(hc, A_SUBCH_CFG, 0);
1996                 *txpending = 1;
1997         }
1998 next_frame:
1999         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2000                 f1 = HFC_inb_nodebug(hc, A_F1);
2001                 f2 = HFC_inb_nodebug(hc, A_F2);
2002                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
2003                         if (debug & DEBUG_HFCMULTI_FIFO)
2004                                 printk(KERN_DEBUG
2005                                        "%s(card %d): reread f2 because %d!=%d\n",
2006                                        __func__, hc->id + 1, temp, f2);
2007                         f2 = temp; /* repeat until F2 is equal */
2008                 }
2009                 Fspace = f2 - f1 - 1;
2010                 if (Fspace < 0)
2011                         Fspace += hc->Flen;
2012                 /*
2013                  * Old FIFO handling doesn't give us the current Z2 read
2014                  * pointer, so we cannot send the next frame before the fifo
2015                  * is empty. It makes no difference except for a slightly
2016                  * lower performance.
2017                  */
2018                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
2019                         if (f1 != f2)
2020                                 Fspace = 0;
2021                         else
2022                                 Fspace = 1;
2023                 }
2024                 /* one frame only for ST D-channels, to allow resending */
2025                 if (hc->ctype != HFC_TYPE_E1 && dch) {
2026                         if (f1 != f2)
2027                                 Fspace = 0;
2028                 }
2029                 /* F-counter full condition */
2030                 if (Fspace == 0)
2031                         return;
2032         }
2033         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2034         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2035         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2036                 if (debug & DEBUG_HFCMULTI_FIFO)
2037                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2038                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2039                 z2 = temp; /* repeat unti Z2 is equal */
2040         }
2041         hc->chan[ch].Zfill = z1 - z2;
2042         if (hc->chan[ch].Zfill < 0)
2043                 hc->chan[ch].Zfill += hc->Zlen;
2044         Zspace = z2 - z1;
2045         if (Zspace <= 0)
2046                 Zspace += hc->Zlen;
2047         Zspace -= 4; /* keep not too full, so pointers will not overrun */
2048         /* fill transparent data only to maxinum transparent load (minus 4) */
2049         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2050                 Zspace = Zspace - hc->Zlen + hc->max_trans;
2051         if (Zspace <= 0) /* no space of 4 bytes */
2052                 return;
2053
2054         /* if no data */
2055         if (!len) {
2056                 if (z1 == z2) { /* empty */
2057                         /* if done with FIFO audio data during PCM connection */
2058                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2059                             *txpending && slot_tx >= 0) {
2060                                 if (debug & DEBUG_HFCMULTI_MODE)
2061                                         printk(KERN_DEBUG
2062                                                "%s: reconnecting PCM due to no "
2063                                                "more FIFO data: channel %d "
2064                                                "slot_tx %d\n",
2065                                                __func__, ch, slot_tx);
2066                                 /* connect slot */
2067                                 if (hc->ctype == HFC_TYPE_XHFC)
2068                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2069                                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2070                                 /* Enable FIFO, no interrupt */
2071                                 else
2072                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2073                                                  V_HDLC_TRP | V_IFF);
2074                                 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2075                                 HFC_wait_nodebug(hc);
2076                                 if (hc->ctype == HFC_TYPE_XHFC)
2077                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2078                                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2079                                 /* Enable FIFO, no interrupt */
2080                                 else
2081                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2082                                                  V_HDLC_TRP | V_IFF);
2083                                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2084                                 HFC_wait_nodebug(hc);
2085                         }
2086                         *txpending = 0;
2087                 }
2088                 return; /* no data */
2089         }
2090
2091         /* "fill fifo if empty" feature */
2092         if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2093             && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2094                 if (debug & DEBUG_HFCMULTI_FILL)
2095                         printk(KERN_DEBUG "%s: buffer empty, so we have "
2096                                "underrun\n", __func__);
2097                 /* fill buffer, to prevent future underrun */
2098                 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2099                 Zspace -= (poll >> 1);
2100         }
2101
2102         /* if audio data and connected slot */
2103         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2104             && slot_tx >= 0) {
2105                 if (debug & DEBUG_HFCMULTI_MODE)
2106                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
2107                                "FIFO data: channel %d slot_tx %d\n",
2108                                __func__, ch, slot_tx);
2109                 /* disconnect slot */
2110                 if (hc->ctype == HFC_TYPE_XHFC)
2111                         HFC_outb(hc, A_CON_HDLC, 0x80
2112                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2113                 /* Enable FIFO, no interrupt */
2114                 else
2115                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2116                                  V_HDLC_TRP | V_IFF);
2117                 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2118                 HFC_wait_nodebug(hc);
2119                 if (hc->ctype == HFC_TYPE_XHFC)
2120                         HFC_outb(hc, A_CON_HDLC, 0x80
2121                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2122                 /* Enable FIFO, no interrupt */
2123                 else
2124                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2125                                  V_HDLC_TRP | V_IFF);
2126                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2127                 HFC_wait_nodebug(hc);
2128         }
2129         *txpending = 1;
2130
2131         /* show activity */
2132         if (dch)
2133                 hc->activity_tx |= 1 << hc->chan[ch].port;
2134
2135         /* fill fifo to what we have left */
2136         ii = len;
2137         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2138                 temp = 1;
2139         else
2140                 temp = 0;
2141         i = *idxp;
2142         d = (*sp)->data + i;
2143         if (ii - i > Zspace)
2144                 ii = Zspace + i;
2145         if (debug & DEBUG_HFCMULTI_FIFO)
2146                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2147                        "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2148                        __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2149                        temp ? "HDLC" : "TRANS");
2150
2151         /* Have to prep the audio data */
2152         hc->write_fifo(hc, d, ii - i);
2153         hc->chan[ch].Zfill += ii - i;
2154         *idxp = ii;
2155
2156         /* if not all data has been written */
2157         if (ii != len) {
2158                 /* NOTE: fifo is started by the calling function */
2159                 return;
2160         }
2161
2162         /* if all data has been written, terminate frame */
2163         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2164                 /* increment f-counter */
2165                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2166                 HFC_wait_nodebug(hc);
2167         }
2168
2169         dev_kfree_skb(*sp);
2170         /* check for next frame */
2171         if (bch && get_next_bframe(bch)) {
2172                 len = (*sp)->len;
2173                 goto next_frame;
2174         }
2175         if (dch && get_next_dframe(dch)) {
2176                 len = (*sp)->len;
2177                 goto next_frame;
2178         }
2179
2180         /*
2181          * now we have no more data, so in case of transparent,
2182          * we set the last byte in fifo to 'silence' in case we will get
2183          * no more data at all. this prevents sending an undefined value.
2184          */
2185         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2186                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2187 }
2188
2189
2190 /* NOTE: only called if E1 card is in active state */
2191 static void
2192 hfcmulti_rx(struct hfc_multi *hc, int ch)
2193 {
2194         int temp;
2195         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2196         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2197         int again = 0;
2198         struct  bchannel *bch;
2199         struct  dchannel *dch = NULL;
2200         struct sk_buff  *skb, **sp = NULL;
2201         int     maxlen;
2202
2203         bch = hc->chan[ch].bch;
2204         if (bch) {
2205                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2206                         return;
2207         } else if (hc->chan[ch].dch) {
2208                 dch = hc->chan[ch].dch;
2209                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2210                         return;
2211         } else {
2212                 return;
2213         }
2214 next_frame:
2215         /* on first AND before getting next valid frame, R_FIFO must be written
2216            to. */
2217         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2218             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2219             (hc->chan[ch].slot_rx < 0) &&
2220             (hc->chan[ch].slot_tx < 0))
2221                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2222         else
2223                 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2224         HFC_wait_nodebug(hc);
2225
2226         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2227         if (hc->chan[ch].rx_off) {
2228                 if (bch)
2229                         bch->dropcnt += poll; /* not exact but fair enough */
2230                 return;
2231         }
2232
2233         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2234                 f1 = HFC_inb_nodebug(hc, A_F1);
2235                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2236                         if (debug & DEBUG_HFCMULTI_FIFO)
2237                                 printk(KERN_DEBUG
2238                                        "%s(card %d): reread f1 because %d!=%d\n",
2239                                        __func__, hc->id + 1, temp, f1);
2240                         f1 = temp; /* repeat until F1 is equal */
2241                 }
2242                 f2 = HFC_inb_nodebug(hc, A_F2);
2243         }
2244         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2245         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2246                 if (debug & DEBUG_HFCMULTI_FIFO)
2247                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2248                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2249                 z1 = temp; /* repeat until Z1 is equal */
2250         }
2251         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2252         Zsize = z1 - z2;
2253         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2254                 /* complete hdlc frame */
2255                 Zsize++;
2256         if (Zsize < 0)
2257                 Zsize += hc->Zlen;
2258         /* if buffer is empty */
2259         if (Zsize <= 0)
2260                 return;
2261
2262         if (bch) {
2263                 maxlen = bchannel_get_rxbuf(bch, Zsize);
2264                 if (maxlen < 0) {
2265                         pr_warning("card%d.B%d: No bufferspace for %d bytes\n",
2266                                    hc->id + 1, bch->nr, Zsize);
2267                         return;
2268                 }
2269                 sp = &bch->rx_skb;
2270                 maxlen = bch->maxlen;
2271         } else { /* Dchannel */
2272                 sp = &dch->rx_skb;
2273                 maxlen = dch->maxlen + 3;
2274                 if (*sp == NULL) {
2275                         *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2276                         if (*sp == NULL) {
2277                                 pr_warning("card%d: No mem for dch rx_skb\n",
2278                                            hc->id + 1);
2279                                 return;
2280                         }
2281                 }
2282         }
2283         /* show activity */
2284         if (dch)
2285                 hc->activity_rx |= 1 << hc->chan[ch].port;
2286
2287         /* empty fifo with what we have */
2288         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2289                 if (debug & DEBUG_HFCMULTI_FIFO)
2290                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2291                                "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2292                                "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2293                                Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2294                                f1, f2, Zsize + (*sp)->len, again);
2295                 /* HDLC */
2296                 if ((Zsize + (*sp)->len) > maxlen) {
2297                         if (debug & DEBUG_HFCMULTI_FIFO)
2298                                 printk(KERN_DEBUG
2299                                        "%s(card %d): hdlc-frame too large.\n",
2300                                        __func__, hc->id + 1);
2301                         skb_trim(*sp, 0);
2302                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2303                         HFC_wait_nodebug(hc);
2304                         return;
2305                 }
2306
2307                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2308
2309                 if (f1 != f2) {
2310                         /* increment Z2,F2-counter */
2311                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2312                         HFC_wait_nodebug(hc);
2313                         /* check size */
2314                         if ((*sp)->len < 4) {
2315                                 if (debug & DEBUG_HFCMULTI_FIFO)
2316                                         printk(KERN_DEBUG
2317                                                "%s(card %d): Frame below minimum "
2318                                                "size\n", __func__, hc->id + 1);
2319                                 skb_trim(*sp, 0);
2320                                 goto next_frame;
2321                         }
2322                         /* there is at least one complete frame, check crc */
2323                         if ((*sp)->data[(*sp)->len - 1]) {
2324                                 if (debug & DEBUG_HFCMULTI_CRC)
2325                                         printk(KERN_DEBUG
2326                                                "%s: CRC-error\n", __func__);
2327                                 skb_trim(*sp, 0);
2328                                 goto next_frame;
2329                         }
2330                         skb_trim(*sp, (*sp)->len - 3);
2331                         if ((*sp)->len < MISDN_COPY_SIZE) {
2332                                 skb = *sp;
2333                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2334                                 if (*sp) {
2335                                         skb_put_data(*sp, skb->data, skb->len);
2336                                         skb_trim(skb, 0);
2337                                 } else {
2338                                         printk(KERN_DEBUG "%s: No mem\n",
2339                                                __func__);
2340                                         *sp = skb;
2341                                         skb = NULL;
2342                                 }
2343                         } else {
2344                                 skb = NULL;
2345                         }
2346                         if (debug & DEBUG_HFCMULTI_FIFO) {
2347                                 printk(KERN_DEBUG "%s(card %d):",
2348                                        __func__, hc->id + 1);
2349                                 temp = 0;
2350                                 while (temp < (*sp)->len)
2351                                         printk(" %02x", (*sp)->data[temp++]);
2352                                 printk("\n");
2353                         }
2354                         if (dch)
2355                                 recv_Dchannel(dch);
2356                         else
2357                                 recv_Bchannel(bch, MISDN_ID_ANY, false);
2358                         *sp = skb;
2359                         again++;
2360                         goto next_frame;
2361                 }
2362                 /* there is an incomplete frame */
2363         } else {
2364                 /* transparent */
2365                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2366                 if (debug & DEBUG_HFCMULTI_FIFO)
2367                         printk(KERN_DEBUG
2368                                "%s(card %d): fifo(%d) reading %d bytes "
2369                                "(z1=%04x, z2=%04x) TRANS\n",
2370                                __func__, hc->id + 1, ch, Zsize, z1, z2);
2371                 /* only bch is transparent */
2372                 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2373         }
2374 }
2375
2376
2377 /*
2378  * Interrupt handler
2379  */
2380 static void
2381 signal_state_up(struct dchannel *dch, int info, char *msg)
2382 {
2383         struct sk_buff  *skb;
2384         int             id, data = info;
2385
2386         if (debug & DEBUG_HFCMULTI_STATE)
2387                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2388
2389         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2390
2391         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2392                                GFP_ATOMIC);
2393         if (!skb)
2394                 return;
2395         recv_Dchannel_skb(dch, skb);
2396 }
2397
2398 static inline void
2399 handle_timer_irq(struct hfc_multi *hc)
2400 {
2401         int             ch, temp;
2402         struct dchannel *dch;
2403         u_long          flags;
2404
2405         /* process queued resync jobs */
2406         if (hc->e1_resync) {
2407                 /* lock, so e1_resync gets not changed */
2408                 spin_lock_irqsave(&HFClock, flags);
2409                 if (hc->e1_resync & 1) {
2410                         if (debug & DEBUG_HFCMULTI_PLXSD)
2411                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2412                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2413                         /* disable JATT, if RX_SYNC is set */
2414                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2415                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2416                 }
2417                 if (hc->e1_resync & 2) {
2418                         if (debug & DEBUG_HFCMULTI_PLXSD)
2419                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2420                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2421                 }
2422                 if (hc->e1_resync & 4) {
2423                         if (debug & DEBUG_HFCMULTI_PLXSD)
2424                                 printk(KERN_DEBUG
2425                                        "Enable QUARTZ for HFC-E1\n");
2426                         /* set jatt to quartz */
2427                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2428                                  | V_JATT_OFF);
2429                         /* switch to JATT, in case it is not already */
2430                         HFC_outb(hc, R_SYNC_OUT, 0);
2431                 }
2432                 hc->e1_resync = 0;
2433                 spin_unlock_irqrestore(&HFClock, flags);
2434         }
2435
2436         if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2437                 for (ch = 0; ch <= 31; ch++) {
2438                         if (hc->created[hc->chan[ch].port]) {
2439                                 hfcmulti_tx(hc, ch);
2440                                 /* fifo is started when switching to rx-fifo */
2441                                 hfcmulti_rx(hc, ch);
2442                                 if (hc->chan[ch].dch &&
2443                                     hc->chan[ch].nt_timer > -1) {
2444                                         dch = hc->chan[ch].dch;
2445                                         if (!(--hc->chan[ch].nt_timer)) {
2446                                                 schedule_event(dch,
2447                                                                FLG_PHCHANGE);
2448                                                 if (debug &
2449                                                     DEBUG_HFCMULTI_STATE)
2450                                                         printk(KERN_DEBUG
2451                                                                "%s: nt_timer at "
2452                                                                "state %x\n",
2453                                                                __func__,
2454                                                                dch->state);
2455                                         }
2456                                 }
2457                         }
2458                 }
2459         if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2460                 dch = hc->chan[hc->dnum[0]].dch;
2461                 /* LOS */
2462                 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2463                 hc->chan[hc->dnum[0]].los = temp;
2464                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2465                         if (!temp && hc->chan[hc->dnum[0]].los)
2466                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2467                                                 "LOS detected");
2468                         if (temp && !hc->chan[hc->dnum[0]].los)
2469                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2470                                                 "LOS gone");
2471                 }
2472                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2473                         /* AIS */
2474                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2475                         if (!temp && hc->chan[hc->dnum[0]].ais)
2476                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2477                                                 "AIS detected");
2478                         if (temp && !hc->chan[hc->dnum[0]].ais)
2479                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2480                                                 "AIS gone");
2481                         hc->chan[hc->dnum[0]].ais = temp;
2482                 }
2483                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2484                         /* SLIP */
2485                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2486                         if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2487                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2488                                                 " bit SLIP detected RX");
2489                         hc->chan[hc->dnum[0]].slip_rx = temp;
2490                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2491                         if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2492                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2493                                                 " bit SLIP detected TX");
2494                         hc->chan[hc->dnum[0]].slip_tx = temp;
2495                 }
2496                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2497                         /* RDI */
2498                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2499                         if (!temp && hc->chan[hc->dnum[0]].rdi)
2500                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2501                                                 "RDI detected");
2502                         if (temp && !hc->chan[hc->dnum[0]].rdi)
2503                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2504                                                 "RDI gone");
2505                         hc->chan[hc->dnum[0]].rdi = temp;
2506                 }
2507                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2508                 switch (hc->chan[hc->dnum[0]].sync) {
2509                 case 0:
2510                         if ((temp & 0x60) == 0x60) {
2511                                 if (debug & DEBUG_HFCMULTI_SYNC)
2512                                         printk(KERN_DEBUG
2513                                                "%s: (id=%d) E1 now "
2514                                                "in clock sync\n",
2515                                                __func__, hc->id);
2516                                 HFC_outb(hc, R_RX_OFF,
2517                                     hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2518                                 HFC_outb(hc, R_TX_OFF,
2519                                     hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2520                                 hc->chan[hc->dnum[0]].sync = 1;
2521                                 goto check_framesync;
2522                         }
2523                         break;
2524                 case 1:
2525                         if ((temp & 0x60) != 0x60) {
2526                                 if (debug & DEBUG_HFCMULTI_SYNC)
2527                                         printk(KERN_DEBUG
2528                                                "%s: (id=%d) E1 "
2529                                                "lost clock sync\n",
2530                                                __func__, hc->id);
2531                                 hc->chan[hc->dnum[0]].sync = 0;
2532                                 break;
2533                         }
2534                 check_framesync:
2535                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2536                         if (temp == 0x27) {
2537                                 if (debug & DEBUG_HFCMULTI_SYNC)
2538                                         printk(KERN_DEBUG
2539                                                "%s: (id=%d) E1 "
2540                                                "now in frame sync\n",
2541                                                __func__, hc->id);
2542                                 hc->chan[hc->dnum[0]].sync = 2;
2543                         }
2544                         break;
2545                 case 2:
2546                         if ((temp & 0x60) != 0x60) {
2547                                 if (debug & DEBUG_HFCMULTI_SYNC)
2548                                         printk(KERN_DEBUG
2549                                                "%s: (id=%d) E1 lost "
2550                                                "clock & frame sync\n",
2551                                                __func__, hc->id);
2552                                 hc->chan[hc->dnum[0]].sync = 0;
2553                                 break;
2554                         }
2555                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2556                         if (temp != 0x27) {
2557                                 if (debug & DEBUG_HFCMULTI_SYNC)
2558                                         printk(KERN_DEBUG
2559                                                "%s: (id=%d) E1 "
2560                                                "lost frame sync\n",
2561                                                __func__, hc->id);
2562                                 hc->chan[hc->dnum[0]].sync = 1;
2563                         }
2564                         break;
2565                 }
2566         }
2567
2568         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2569                 hfcmulti_watchdog(hc);
2570
2571         if (hc->leds)
2572                 hfcmulti_leds(hc);
2573 }
2574
2575 static void
2576 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2577 {
2578         struct dchannel *dch;
2579         int             ch;
2580         int             active;
2581         u_char          st_status, temp;
2582
2583         /* state machine */
2584         for (ch = 0; ch <= 31; ch++) {
2585                 if (hc->chan[ch].dch) {
2586                         dch = hc->chan[ch].dch;
2587                         if (r_irq_statech & 1) {
2588                                 HFC_outb_nodebug(hc, R_ST_SEL,
2589                                                  hc->chan[ch].port);
2590                                 /* undocumented: delay after R_ST_SEL */
2591                                 udelay(1);
2592                                 /* undocumented: status changes during read */
2593                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2594                                 while (st_status != (temp =
2595                                                      HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2596                                         if (debug & DEBUG_HFCMULTI_STATE)
2597                                                 printk(KERN_DEBUG "%s: reread "
2598                                                        "STATE because %d!=%d\n",
2599                                                        __func__, temp,
2600                                                        st_status);
2601                                         st_status = temp; /* repeat */
2602                                 }
2603
2604                                 /* Speech Design TE-sync indication */
2605                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2606                                     dch->dev.D.protocol == ISDN_P_TE_S0) {
2607                                         if (st_status & V_FR_SYNC_ST)
2608                                                 hc->syncronized |=
2609                                                         (1 << hc->chan[ch].port);
2610                                         else
2611                                                 hc->syncronized &=
2612                                                         ~(1 << hc->chan[ch].port);
2613                                 }
2614                                 dch->state = st_status & 0x0f;
2615                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2616                                         active = 3;
2617                                 else
2618                                         active = 7;
2619                                 if (dch->state == active) {
2620                                         HFC_outb_nodebug(hc, R_FIFO,
2621                                                          (ch << 1) | 1);
2622                                         HFC_wait_nodebug(hc);
2623                                         HFC_outb_nodebug(hc,
2624                                                          R_INC_RES_FIFO, V_RES_F);
2625                                         HFC_wait_nodebug(hc);
2626                                         dch->tx_idx = 0;
2627                                 }
2628                                 schedule_event(dch, FLG_PHCHANGE);
2629                                 if (debug & DEBUG_HFCMULTI_STATE)
2630                                         printk(KERN_DEBUG
2631                                                "%s: S/T newstate %x port %d\n",
2632                                                __func__, dch->state,
2633                                                hc->chan[ch].port);
2634                         }
2635                         r_irq_statech >>= 1;
2636                 }
2637         }
2638         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2639                 plxsd_checksync(hc, 0);
2640 }
2641
2642 static void
2643 fifo_irq(struct hfc_multi *hc, int block)
2644 {
2645         int     ch, j;
2646         struct dchannel *dch;
2647         struct bchannel *bch;
2648         u_char r_irq_fifo_bl;
2649
2650         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2651         j = 0;
2652         while (j < 8) {
2653                 ch = (block << 2) + (j >> 1);
2654                 dch = hc->chan[ch].dch;
2655                 bch = hc->chan[ch].bch;
2656                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2657                         j += 2;
2658                         continue;
2659                 }
2660                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2661                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2662                         hfcmulti_tx(hc, ch);
2663                         /* start fifo */
2664                         HFC_outb_nodebug(hc, R_FIFO, 0);
2665                         HFC_wait_nodebug(hc);
2666                 }
2667                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2668                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2669                         hfcmulti_tx(hc, ch);
2670                         /* start fifo */
2671                         HFC_outb_nodebug(hc, R_FIFO, 0);
2672                         HFC_wait_nodebug(hc);
2673                 }
2674                 j++;
2675                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2676                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2677                         hfcmulti_rx(hc, ch);
2678                 }
2679                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2680                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2681                         hfcmulti_rx(hc, ch);
2682                 }
2683                 j++;
2684         }
2685 }
2686
2687 #ifdef IRQ_DEBUG
2688 int irqsem;
2689 #endif
2690 static irqreturn_t
2691 hfcmulti_interrupt(int intno, void *dev_id)
2692 {
2693 #ifdef IRQCOUNT_DEBUG
2694         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2695                 iq5 = 0, iq6 = 0, iqcnt = 0;
2696 #endif
2697         struct hfc_multi        *hc = dev_id;
2698         struct dchannel         *dch;
2699         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2700         int                     i;
2701         void __iomem            *plx_acc;
2702         u_short                 wval;
2703         u_char                  e1_syncsta, temp, temp2;
2704         u_long                  flags;
2705
2706         if (!hc) {
2707                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2708                 return IRQ_NONE;
2709         }
2710
2711         spin_lock(&hc->lock);
2712
2713 #ifdef IRQ_DEBUG
2714         if (irqsem)
2715                 printk(KERN_ERR "irq for card %d during irq from "
2716                        "card %d, this is no bug.\n", hc->id + 1, irqsem);
2717         irqsem = hc->id + 1;
2718 #endif
2719 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2720         if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2721                 goto irq_notforus;
2722 #endif
2723         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2724                 spin_lock_irqsave(&plx_lock, flags);
2725                 plx_acc = hc->plx_membase + PLX_INTCSR;
2726                 wval = readw(plx_acc);
2727                 spin_unlock_irqrestore(&plx_lock, flags);
2728                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2729                         goto irq_notforus;
2730         }
2731
2732         status = HFC_inb_nodebug(hc, R_STATUS);
2733         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2734 #ifdef IRQCOUNT_DEBUG
2735         if (r_irq_statech)
2736                 iq1++;
2737         if (status & V_DTMF_STA)
2738                 iq2++;
2739         if (status & V_LOST_STA)
2740                 iq3++;
2741         if (status & V_EXT_IRQSTA)
2742                 iq4++;
2743         if (status & V_MISC_IRQSTA)
2744                 iq5++;
2745         if (status & V_FR_IRQSTA)
2746                 iq6++;
2747         if (iqcnt++ > 5000) {
2748                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2749                        iq1, iq2, iq3, iq4, iq5, iq6);
2750                 iqcnt = 0;
2751         }
2752 #endif
2753
2754         if (!r_irq_statech &&
2755             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2756                         V_MISC_IRQSTA | V_FR_IRQSTA))) {
2757                 /* irq is not for us */
2758                 goto irq_notforus;
2759         }
2760         hc->irqcnt++;
2761         if (r_irq_statech) {
2762                 if (hc->ctype != HFC_TYPE_E1)
2763                         ph_state_irq(hc, r_irq_statech);
2764         }
2765         if (status & V_EXT_IRQSTA)
2766                 ; /* external IRQ */
2767         if (status & V_LOST_STA) {
2768                 /* LOST IRQ */
2769                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2770         }
2771         if (status & V_MISC_IRQSTA) {
2772                 /* misc IRQ */
2773                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2774                 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2775                 if (r_irq_misc & V_STA_IRQ) {
2776                         if (hc->ctype == HFC_TYPE_E1) {
2777                                 /* state machine */
2778                                 dch = hc->chan[hc->dnum[0]].dch;
2779                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2780                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2781                                     && hc->e1_getclock) {
2782                                         if (e1_syncsta & V_FR_SYNC_E1)
2783                                                 hc->syncronized = 1;
2784                                         else
2785                                                 hc->syncronized = 0;
2786                                 }
2787                                 /* undocumented: status changes during read */
2788                                 temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2789                                 while (temp != (temp2 =
2790                                                       HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2791                                         if (debug & DEBUG_HFCMULTI_STATE)
2792                                                 printk(KERN_DEBUG "%s: reread "
2793                                                        "STATE because %d!=%d\n",
2794                                                     __func__, temp, temp2);
2795                                         temp = temp2; /* repeat */
2796                                 }
2797                                 /* broadcast state change to all fragments */
2798                                 if (debug & DEBUG_HFCMULTI_STATE)
2799                                         printk(KERN_DEBUG
2800                                                "%s: E1 (id=%d) newstate %x\n",
2801                                             __func__, hc->id, temp & 0x7);
2802                                 for (i = 0; i < hc->ports; i++) {
2803                                         dch = hc->chan[hc->dnum[i]].dch;
2804                                         dch->state = temp & 0x7;
2805                                         schedule_event(dch, FLG_PHCHANGE);
2806                                 }
2807
2808                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2809                                         plxsd_checksync(hc, 0);
2810                         }
2811                 }
2812                 if (r_irq_misc & V_TI_IRQ) {
2813                         if (hc->iclock_on)
2814                                 mISDN_clock_update(hc->iclock, poll, NULL);
2815                         handle_timer_irq(hc);
2816                 }
2817
2818                 if (r_irq_misc & V_DTMF_IRQ)
2819                         hfcmulti_dtmf(hc);
2820
2821                 if (r_irq_misc & V_IRQ_PROC) {
2822                         static int irq_proc_cnt;
2823                         if (!irq_proc_cnt++)
2824                                 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2825                                        " this should not happen\n", __func__);
2826                 }
2827
2828         }
2829         if (status & V_FR_IRQSTA) {
2830                 /* FIFO IRQ */
2831                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2832                 for (i = 0; i < 8; i++) {
2833                         if (r_irq_oview & (1 << i))
2834                                 fifo_irq(hc, i);
2835                 }
2836         }
2837
2838 #ifdef IRQ_DEBUG
2839         irqsem = 0;
2840 #endif
2841         spin_unlock(&hc->lock);
2842         return IRQ_HANDLED;
2843
2844 irq_notforus:
2845 #ifdef IRQ_DEBUG
2846         irqsem = 0;
2847 #endif
2848         spin_unlock(&hc->lock);
2849         return IRQ_NONE;
2850 }
2851
2852
2853 /*
2854  * timer callback for D-chan busy resolution. Currently no function
2855  */
2856
2857 static void
2858 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2859 {
2860 }
2861
2862
2863 /*
2864  * activate/deactivate hardware for selected channels and mode
2865  *
2866  * configure B-channel with the given protocol
2867  * ch eqals to the HFC-channel (0-31)
2868  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2869  * for S/T, 1-31 for E1)
2870  * the hdlc interrupts will be set/unset
2871  */
2872 static int
2873 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2874               int bank_tx, int slot_rx, int bank_rx)
2875 {
2876         int flow_tx = 0, flow_rx = 0, routing = 0;
2877         int oslot_tx, oslot_rx;
2878         int conf;
2879
2880         if (ch < 0 || ch > 31)
2881                 return -EINVAL;
2882         oslot_tx = hc->chan[ch].slot_tx;
2883         oslot_rx = hc->chan[ch].slot_rx;
2884         conf = hc->chan[ch].conf;
2885
2886         if (debug & DEBUG_HFCMULTI_MODE)
2887                 printk(KERN_DEBUG
2888                        "%s: card %d channel %d protocol %x slot old=%d new=%d "
2889                        "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2890                        __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2891                        bank_tx, oslot_rx, slot_rx, bank_rx);
2892
2893         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2894                 /* remove from slot */
2895                 if (debug & DEBUG_HFCMULTI_MODE)
2896                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2897                                __func__, oslot_tx);
2898                 if (hc->slot_owner[oslot_tx << 1] == ch) {
2899                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2900                         HFC_outb(hc, A_SL_CFG, 0);
2901                         if (hc->ctype != HFC_TYPE_XHFC)
2902                                 HFC_outb(hc, A_CONF, 0);
2903                         hc->slot_owner[oslot_tx << 1] = -1;
2904                 } else {
2905                         if (debug & DEBUG_HFCMULTI_MODE)
2906                                 printk(KERN_DEBUG
2907                                        "%s: we are not owner of this tx slot "
2908                                        "anymore, channel %d is.\n",
2909                                        __func__, hc->slot_owner[oslot_tx << 1]);
2910                 }
2911         }
2912
2913         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2914                 /* remove from slot */
2915                 if (debug & DEBUG_HFCMULTI_MODE)
2916                         printk(KERN_DEBUG
2917                                "%s: remove from slot %d (RX)\n",
2918                                __func__, oslot_rx);
2919                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2920                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2921                         HFC_outb(hc, A_SL_CFG, 0);
2922                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2923                 } else {
2924                         if (debug & DEBUG_HFCMULTI_MODE)
2925                                 printk(KERN_DEBUG
2926                                        "%s: we are not owner of this rx slot "
2927                                        "anymore, channel %d is.\n",
2928                                        __func__,
2929                                        hc->slot_owner[(oslot_rx << 1) | 1]);
2930                 }
2931         }
2932
2933         if (slot_tx < 0) {
2934                 flow_tx = 0x80; /* FIFO->ST */
2935                 /* disable pcm slot */
2936                 hc->chan[ch].slot_tx = -1;
2937                 hc->chan[ch].bank_tx = 0;
2938         } else {
2939                 /* set pcm slot */
2940                 if (hc->chan[ch].txpending)
2941                         flow_tx = 0x80; /* FIFO->ST */
2942                 else
2943                         flow_tx = 0xc0; /* PCM->ST */
2944                 /* put on slot */
2945                 routing = bank_tx ? 0xc0 : 0x80;
2946                 if (conf >= 0 || bank_tx > 1)
2947                         routing = 0x40; /* loop */
2948                 if (debug & DEBUG_HFCMULTI_MODE)
2949                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2950                                " %d flow %02x routing %02x conf %d (TX)\n",
2951                                __func__, ch, slot_tx, bank_tx,
2952                                flow_tx, routing, conf);
2953                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2954                 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2955                 if (hc->ctype != HFC_TYPE_XHFC)
2956                         HFC_outb(hc, A_CONF,
2957                                  (conf < 0) ? 0 : (conf | V_CONF_SL));
2958                 hc->slot_owner[slot_tx << 1] = ch;
2959                 hc->chan[ch].slot_tx = slot_tx;
2960                 hc->chan[ch].bank_tx = bank_tx;
2961         }
2962         if (slot_rx < 0) {
2963                 /* disable pcm slot */
2964                 flow_rx = 0x80; /* ST->FIFO */
2965                 hc->chan[ch].slot_rx = -1;
2966                 hc->chan[ch].bank_rx = 0;
2967         } else {
2968                 /* set pcm slot */
2969                 if (hc->chan[ch].txpending)
2970                         flow_rx = 0x80; /* ST->FIFO */
2971                 else
2972                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2973                 /* put on slot */
2974                 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2975                 if (conf >= 0 || bank_rx > 1)
2976                         routing = 0x40; /* loop */
2977                 if (debug & DEBUG_HFCMULTI_MODE)
2978                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2979                                " %d flow %02x routing %02x conf %d (RX)\n",
2980                                __func__, ch, slot_rx, bank_rx,
2981                                flow_rx, routing, conf);
2982                 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2983                 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2984                 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2985                 hc->chan[ch].slot_rx = slot_rx;
2986                 hc->chan[ch].bank_rx = bank_rx;
2987         }
2988
2989         switch (protocol) {
2990         case (ISDN_P_NONE):
2991                 /* disable TX fifo */
2992                 HFC_outb(hc, R_FIFO, ch << 1);
2993                 HFC_wait(hc);
2994                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2995                 HFC_outb(hc, A_SUBCH_CFG, 0);
2996                 HFC_outb(hc, A_IRQ_MSK, 0);
2997                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2998                 HFC_wait(hc);
2999                 /* disable RX fifo */
3000                 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3001                 HFC_wait(hc);
3002                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
3003                 HFC_outb(hc, A_SUBCH_CFG, 0);
3004                 HFC_outb(hc, A_IRQ_MSK, 0);
3005                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3006                 HFC_wait(hc);
3007                 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
3008                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
3009                                 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
3010                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3011                         /* undocumented: delay after R_ST_SEL */
3012                         udelay(1);
3013                         HFC_outb(hc, A_ST_CTRL0,
3014                                  hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3015                 }
3016                 if (hc->chan[ch].bch) {
3017                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3018                         test_and_clear_bit(FLG_TRANSPARENT,
3019                                            &hc->chan[ch].bch->Flags);
3020                 }
3021                 break;
3022         case (ISDN_P_B_RAW): /* B-channel */
3023
3024                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
3025                     (hc->chan[ch].slot_rx < 0) &&
3026                     (hc->chan[ch].slot_tx < 0)) {
3027
3028                         printk(KERN_DEBUG
3029                                "Setting B-channel %d to echo cancelable "
3030                                "state on PCM slot %d\n", ch,
3031                                ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3032                         printk(KERN_DEBUG
3033                                "Enabling pass through for channel\n");
3034                         vpm_out(hc, ch, ((ch / 4) * 8) +
3035                                 ((ch % 4) * 4) + 1, 0x01);
3036                         /* rx path */
3037                         /* S/T -> PCM */
3038                         HFC_outb(hc, R_FIFO, (ch << 1));
3039                         HFC_wait(hc);
3040                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3041                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3042                                               ((ch % 4) * 4) + 1) << 1);
3043                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3044
3045                         /* PCM -> FIFO */
3046                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3047                         HFC_wait(hc);
3048                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3049                         HFC_outb(hc, A_SUBCH_CFG, 0);
3050                         HFC_outb(hc, A_IRQ_MSK, 0);
3051                         if (hc->chan[ch].protocol != protocol) {
3052                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3053                                 HFC_wait(hc);
3054                         }
3055                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3056                                                ((ch % 4) * 4) + 1) << 1) | 1);
3057                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3058
3059                         /* tx path */
3060                         /* PCM -> S/T */
3061                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3062                         HFC_wait(hc);
3063                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3064                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3065                                                ((ch % 4) * 4)) << 1) | 1);
3066                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3067
3068                         /* FIFO -> PCM */
3069                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3070                         HFC_wait(hc);
3071                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3072                         HFC_outb(hc, A_SUBCH_CFG, 0);
3073                         HFC_outb(hc, A_IRQ_MSK, 0);
3074                         if (hc->chan[ch].protocol != protocol) {
3075                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3076                                 HFC_wait(hc);
3077                         }
3078                         /* tx silence */
3079                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3080                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3081                                               ((ch % 4) * 4)) << 1);
3082                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3083                 } else {
3084                         /* enable TX fifo */
3085                         HFC_outb(hc, R_FIFO, ch << 1);
3086                         HFC_wait(hc);
3087                         if (hc->ctype == HFC_TYPE_XHFC)
3088                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3089                                          V_HDLC_TRP | V_IFF);
3090                         /* Enable FIFO, no interrupt */
3091                         else
3092                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3093                                          V_HDLC_TRP | V_IFF);
3094                         HFC_outb(hc, A_SUBCH_CFG, 0);
3095                         HFC_outb(hc, A_IRQ_MSK, 0);
3096                         if (hc->chan[ch].protocol != protocol) {
3097                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3098                                 HFC_wait(hc);
3099                         }
3100                         /* tx silence */
3101                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3102                         /* enable RX fifo */
3103                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3104                         HFC_wait(hc);
3105                         if (hc->ctype == HFC_TYPE_XHFC)
3106                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3107                                          V_HDLC_TRP);
3108                         /* Enable FIFO, no interrupt*/
3109                         else
3110                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3111                                          V_HDLC_TRP);
3112                         HFC_outb(hc, A_SUBCH_CFG, 0);
3113                         HFC_outb(hc, A_IRQ_MSK, 0);
3114                         if (hc->chan[ch].protocol != protocol) {
3115                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3116                                 HFC_wait(hc);
3117                         }
3118                 }
3119                 if (hc->ctype != HFC_TYPE_E1) {
3120                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3121                                 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3122                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3123                         /* undocumented: delay after R_ST_SEL */
3124                         udelay(1);
3125                         HFC_outb(hc, A_ST_CTRL0,
3126                                  hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3127                 }
3128                 if (hc->chan[ch].bch)
3129                         test_and_set_bit(FLG_TRANSPARENT,
3130                                          &hc->chan[ch].bch->Flags);
3131                 break;
3132         case (ISDN_P_B_HDLC): /* B-channel */
3133         case (ISDN_P_TE_S0): /* D-channel */
3134         case (ISDN_P_NT_S0):
3135         case (ISDN_P_TE_E1):
3136         case (ISDN_P_NT_E1):
3137                 /* enable TX fifo */
3138                 HFC_outb(hc, R_FIFO, ch << 1);
3139                 HFC_wait(hc);
3140                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3141                         /* E1 or B-channel */
3142                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3143                         HFC_outb(hc, A_SUBCH_CFG, 0);
3144                 } else {
3145                         /* D-Channel without HDLC fill flags */
3146                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3147                         HFC_outb(hc, A_SUBCH_CFG, 2);
3148                 }
3149                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3150                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3151                 HFC_wait(hc);
3152                 /* enable RX fifo */
3153                 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3154                 HFC_wait(hc);
3155                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3156                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3157                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3158                 else
3159                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3160                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3161                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3162                 HFC_wait(hc);
3163                 if (hc->chan[ch].bch) {
3164                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3165                         if (hc->ctype != HFC_TYPE_E1) {
3166                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3167                                         ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3168                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3169                                 /* undocumented: delay after R_ST_SEL */
3170                                 udelay(1);
3171                                 HFC_outb(hc, A_ST_CTRL0,
3172                                          hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3173                         }
3174                 }
3175                 break;
3176         default:
3177                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3178                        __func__, protocol);
3179                 hc->chan[ch].protocol = ISDN_P_NONE;
3180                 return -ENOPROTOOPT;
3181         }
3182         hc->chan[ch].protocol = protocol;
3183         return 0;
3184 }
3185
3186
3187 /*
3188  * connect/disconnect PCM
3189  */
3190
3191 static void
3192 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3193              int slot_rx, int bank_rx)
3194 {
3195         if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3196                 /* disable PCM */
3197                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3198                 return;
3199         }
3200
3201         /* enable pcm */
3202         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3203                       slot_rx, bank_rx);
3204 }
3205
3206 /*
3207  * set/disable conference
3208  */
3209
3210 static void
3211 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3212 {
3213         if (num >= 0 && num <= 7)
3214                 hc->chan[ch].conf = num;
3215         else
3216                 hc->chan[ch].conf = -1;
3217         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3218                       hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3219                       hc->chan[ch].bank_rx);
3220 }
3221
3222
3223 /*
3224  * set/disable sample loop
3225  */
3226
3227 /* NOTE: this function is experimental and therefore disabled */
3228
3229 /*
3230  * Layer 1 callback function
3231  */
3232 static int
3233 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3234 {
3235         struct hfc_multi        *hc = dch->hw;
3236         struct sk_buff_head     free_queue;
3237         u_long  flags;
3238
3239         switch (cmd) {
3240         case INFO3_P8:
3241         case INFO3_P10:
3242                 break;
3243         case HW_RESET_REQ:
3244                 /* start activation */
3245                 spin_lock_irqsave(&hc->lock, flags);
3246                 if (hc->ctype == HFC_TYPE_E1) {
3247                         if (debug & DEBUG_HFCMULTI_MSG)
3248                                 printk(KERN_DEBUG
3249                                        "%s: HW_RESET_REQ no BRI\n",
3250                                        __func__);
3251                 } else {
3252                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3253                         /* undocumented: delay after R_ST_SEL */
3254                         udelay(1);
3255                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3256                         udelay(6); /* wait at least 5,21us */
3257                         HFC_outb(hc, A_ST_WR_STATE, 3);
3258                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3259                         /* activate */
3260                 }
3261                 spin_unlock_irqrestore(&hc->lock, flags);
3262                 l1_event(dch->l1, HW_POWERUP_IND);
3263                 break;
3264         case HW_DEACT_REQ:
3265                 __skb_queue_head_init(&free_queue);
3266                 /* start deactivation */
3267                 spin_lock_irqsave(&hc->lock, flags);
3268                 if (hc->ctype == HFC_TYPE_E1) {
3269                         if (debug & DEBUG_HFCMULTI_MSG)
3270                                 printk(KERN_DEBUG
3271                                        "%s: HW_DEACT_REQ no BRI\n",
3272                                        __func__);
3273                 } else {
3274                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3275                         /* undocumented: delay after R_ST_SEL */
3276                         udelay(1);
3277                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3278                         /* deactivate */
3279                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3280                                 hc->syncronized &=
3281                                         ~(1 << hc->chan[dch->slot].port);
3282                                 plxsd_checksync(hc, 0);
3283                         }
3284                 }
3285                 skb_queue_splice_init(&dch->squeue, &free_queue);
3286                 if (dch->tx_skb) {
3287                         __skb_queue_tail(&free_queue, dch->tx_skb);
3288                         dch->tx_skb = NULL;
3289                 }
3290                 dch->tx_idx = 0;
3291                 if (dch->rx_skb) {
3292                         __skb_queue_tail(&free_queue, dch->rx_skb);
3293                         dch->rx_skb = NULL;
3294                 }
3295                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3296                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3297                         del_timer(&dch->timer);
3298                 spin_unlock_irqrestore(&hc->lock, flags);
3299                 __skb_queue_purge(&free_queue);
3300                 break;
3301         case HW_POWERUP_REQ:
3302                 spin_lock_irqsave(&hc->lock, flags);
3303                 if (hc->ctype == HFC_TYPE_E1) {
3304                         if (debug & DEBUG_HFCMULTI_MSG)
3305                                 printk(KERN_DEBUG
3306                                        "%s: HW_POWERUP_REQ no BRI\n",
3307                                        __func__);
3308                 } else {
3309                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3310                         /* undocumented: delay after R_ST_SEL */
3311                         udelay(1);
3312                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3313                         udelay(6); /* wait at least 5,21us */
3314                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3315                 }
3316                 spin_unlock_irqrestore(&hc->lock, flags);
3317                 break;
3318         case PH_ACTIVATE_IND:
3319                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3320                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3321                             GFP_ATOMIC);
3322                 break;
3323         case PH_DEACTIVATE_IND:
3324                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3325                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3326                             GFP_ATOMIC);
3327                 break;
3328         default:
3329                 if (dch->debug & DEBUG_HW)
3330                         printk(KERN_DEBUG "%s: unknown command %x\n",
3331                                __func__, cmd);
3332                 return -1;
3333         }
3334         return 0;
3335 }
3336
3337 /*
3338  * Layer2 -> Layer 1 Transfer
3339  */
3340
3341 static int
3342 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3343 {
3344         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3345         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3346         struct hfc_multi        *hc = dch->hw;
3347         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3348         int                     ret = -EINVAL;
3349         unsigned int            id;
3350         u_long                  flags;
3351
3352         switch (hh->prim) {
3353         case PH_DATA_REQ:
3354                 if (skb->len < 1)
3355                         break;
3356                 spin_lock_irqsave(&hc->lock, flags);
3357                 ret = dchannel_senddata(dch, skb);
3358                 if (ret > 0) { /* direct TX */
3359                         id = hh->id; /* skb can be freed */
3360                         hfcmulti_tx(hc, dch->slot);
3361                         ret = 0;
3362                         /* start fifo */
3363                         HFC_outb(hc, R_FIFO, 0);
3364                         HFC_wait(hc);
3365                         spin_unlock_irqrestore(&hc->lock, flags);
3366                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3367                 } else
3368                         spin_unlock_irqrestore(&hc->lock, flags);
3369                 return ret;
3370         case PH_ACTIVATE_REQ:
3371                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3372                         spin_lock_irqsave(&hc->lock, flags);
3373                         ret = 0;
3374                         if (debug & DEBUG_HFCMULTI_MSG)
3375                                 printk(KERN_DEBUG
3376                                        "%s: PH_ACTIVATE port %d (0..%d)\n",
3377                                        __func__, hc->chan[dch->slot].port,
3378                                        hc->ports - 1);
3379                         /* start activation */
3380                         if (hc->ctype == HFC_TYPE_E1) {
3381                                 ph_state_change(dch);
3382                                 if (debug & DEBUG_HFCMULTI_STATE)
3383                                         printk(KERN_DEBUG
3384                                                "%s: E1 report state %x \n",
3385                                                __func__, dch->state);
3386                         } else {
3387                                 HFC_outb(hc, R_ST_SEL,
3388                                          hc->chan[dch->slot].port);
3389                                 /* undocumented: delay after R_ST_SEL */
3390                                 udelay(1);
3391                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3392                                 /* G1 */
3393                                 udelay(6); /* wait at least 5,21us */
3394                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3395                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3396                                          (V_ST_ACT * 3)); /* activate */
3397                                 dch->state = 1;
3398                         }
3399                         spin_unlock_irqrestore(&hc->lock, flags);
3400                 } else
3401                         ret = l1_event(dch->l1, hh->prim);
3402                 break;
3403         case PH_DEACTIVATE_REQ:
3404                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3405                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3406                         struct sk_buff_head free_queue;
3407
3408                         __skb_queue_head_init(&free_queue);
3409                         spin_lock_irqsave(&hc->lock, flags);
3410                         if (debug & DEBUG_HFCMULTI_MSG)
3411                                 printk(KERN_DEBUG
3412                                        "%s: PH_DEACTIVATE port %d (0..%d)\n",
3413                                        __func__, hc->chan[dch->slot].port,
3414                                        hc->ports - 1);
3415                         /* start deactivation */
3416                         if (hc->ctype == HFC_TYPE_E1) {
3417                                 if (debug & DEBUG_HFCMULTI_MSG)
3418                                         printk(KERN_DEBUG
3419                                                "%s: PH_DEACTIVATE no BRI\n",
3420                                                __func__);
3421                         } else {
3422                                 HFC_outb(hc, R_ST_SEL,
3423                                          hc->chan[dch->slot].port);
3424                                 /* undocumented: delay after R_ST_SEL */
3425                                 udelay(1);
3426                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3427                                 /* deactivate */
3428                                 dch->state = 1;
3429                         }
3430                         skb_queue_splice_init(&dch->squeue, &free_queue);
3431                         if (dch->tx_skb) {
3432                                 __skb_queue_tail(&free_queue, dch->tx_skb);
3433                                 dch->tx_skb = NULL;
3434                         }
3435                         dch->tx_idx = 0;
3436                         if (dch->rx_skb) {
3437                                 __skb_queue_tail(&free_queue, dch->rx_skb);
3438                                 dch->rx_skb = NULL;
3439                         }
3440                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3441                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3442                                 del_timer(&dch->timer);
3443 #ifdef FIXME
3444                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3445                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3446 #endif
3447                         ret = 0;
3448                         spin_unlock_irqrestore(&hc->lock, flags);
3449                         __skb_queue_purge(&free_queue);
3450                 } else
3451                         ret = l1_event(dch->l1, hh->prim);
3452                 break;
3453         }
3454         if (!ret)
3455                 dev_kfree_skb(skb);
3456         return ret;
3457 }
3458
3459 static void
3460 deactivate_bchannel(struct bchannel *bch)
3461 {
3462         struct hfc_multi        *hc = bch->hw;
3463         u_long                  flags;
3464
3465         spin_lock_irqsave(&hc->lock, flags);
3466         mISDN_clear_bchannel(bch);
3467         hc->chan[bch->slot].coeff_count = 0;
3468         hc->chan[bch->slot].rx_off = 0;
3469         hc->chan[bch->slot].conf = -1;
3470         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3471         spin_unlock_irqrestore(&hc->lock, flags);
3472 }
3473
3474 static int
3475 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3476 {
3477         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3478         struct hfc_multi        *hc = bch->hw;
3479         int                     ret = -EINVAL;
3480         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3481         unsigned long           flags;
3482
3483         switch (hh->prim) {
3484         case PH_DATA_REQ:
3485                 if (!skb->len)
3486                         break;
3487                 spin_lock_irqsave(&hc->lock, flags);
3488                 ret = bchannel_senddata(bch, skb);
3489                 if (ret > 0) { /* direct TX */
3490                         hfcmulti_tx(hc, bch->slot);
3491                         ret = 0;
3492                         /* start fifo */
3493                         HFC_outb_nodebug(hc, R_FIFO, 0);
3494                         HFC_wait_nodebug(hc);
3495                 }
3496                 spin_unlock_irqrestore(&hc->lock, flags);
3497                 return ret;
3498         case PH_ACTIVATE_REQ:
3499                 if (debug & DEBUG_HFCMULTI_MSG)
3500                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3501                                __func__, bch->slot);
3502                 spin_lock_irqsave(&hc->lock, flags);
3503                 /* activate B-channel if not already activated */
3504                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3505                         hc->chan[bch->slot].txpending = 0;
3506                         ret = mode_hfcmulti(hc, bch->slot,
3507                                             ch->protocol,
3508                                             hc->chan[bch->slot].slot_tx,
3509                                             hc->chan[bch->slot].bank_tx,
3510                                             hc->chan[bch->slot].slot_rx,
3511                                             hc->chan[bch->slot].bank_rx);
3512                         if (!ret) {
3513                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3514                                     && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3515                                         /* start decoder */
3516                                         hc->dtmf = 1;
3517                                         if (debug & DEBUG_HFCMULTI_DTMF)
3518                                                 printk(KERN_DEBUG
3519                                                        "%s: start dtmf decoder\n",
3520                                                        __func__);
3521                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3522                                                  V_RST_DTMF);
3523                                 }
3524                         }
3525                 } else
3526                         ret = 0;
3527                 spin_unlock_irqrestore(&hc->lock, flags);
3528                 if (!ret)
3529                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3530                                     GFP_KERNEL);
3531                 break;
3532         case PH_CONTROL_REQ:
3533                 spin_lock_irqsave(&hc->lock, flags);
3534                 switch (hh->id) {
3535                 case HFC_SPL_LOOP_ON: /* set sample loop */
3536                         if (debug & DEBUG_HFCMULTI_MSG)
3537                                 printk(KERN_DEBUG
3538                                        "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3539                                        __func__, skb->len);
3540                         ret = 0;
3541                         break;
3542                 case HFC_SPL_LOOP_OFF: /* set silence */
3543                         if (debug & DEBUG_HFCMULTI_MSG)
3544                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3545                                        __func__);
3546                         ret = 0;
3547                         break;
3548                 default:
3549                         printk(KERN_ERR
3550                                "%s: unknown PH_CONTROL_REQ info %x\n",
3551                                __func__, hh->id);
3552                         ret = -EINVAL;
3553                 }
3554                 spin_unlock_irqrestore(&hc->lock, flags);
3555                 break;
3556         case PH_DEACTIVATE_REQ:
3557                 deactivate_bchannel(bch); /* locked there */
3558                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3559                             GFP_KERNEL);
3560                 ret = 0;
3561                 break;
3562         }
3563         if (!ret)
3564                 dev_kfree_skb(skb);
3565         return ret;
3566 }
3567
3568 /*
3569  * bchannel control function
3570  */
3571 static int
3572 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3573 {
3574         int                     ret = 0;
3575         struct dsp_features     *features =
3576                 (struct dsp_features *)(*((u_long *)&cq->p1));
3577         struct hfc_multi        *hc = bch->hw;
3578         int                     slot_tx;
3579         int                     bank_tx;
3580         int                     slot_rx;
3581         int                     bank_rx;
3582         int                     num;
3583
3584         switch (cq->op) {
3585         case MISDN_CTRL_GETOP:
3586                 ret = mISDN_ctrl_bchannel(bch, cq);
3587                 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3588                 break;
3589         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3590                 ret = mISDN_ctrl_bchannel(bch, cq);
3591                 hc->chan[bch->slot].rx_off = !!cq->p1;
3592                 if (!hc->chan[bch->slot].rx_off) {
3593                         /* reset fifo on rx on */
3594                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3595                         HFC_wait_nodebug(hc);
3596                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3597                         HFC_wait_nodebug(hc);
3598                 }
3599                 if (debug & DEBUG_HFCMULTI_MSG)
3600                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3601                                __func__, bch->nr, hc->chan[bch->slot].rx_off);
3602                 break;
3603         case MISDN_CTRL_FILL_EMPTY:
3604                 ret = mISDN_ctrl_bchannel(bch, cq);
3605                 hc->silence = bch->fill[0];
3606                 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3607                 break;
3608         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3609                 if (debug & DEBUG_HFCMULTI_MSG)
3610                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3611                                __func__);
3612                 /* create confirm */
3613                 features->hfc_id = hc->id;
3614                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3615                         features->hfc_dtmf = 1;
3616                 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3617                         features->hfc_conf = 1;
3618                 features->hfc_loops = 0;
3619                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3620                         features->hfc_echocanhw = 1;
3621                 } else {
3622                         features->pcm_id = hc->pcm;
3623                         features->pcm_slots = hc->slots;
3624                         features->pcm_banks = 2;
3625                 }
3626                 break;
3627         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3628                 slot_tx = cq->p1 & 0xff;
3629                 bank_tx = cq->p1 >> 8;
3630                 slot_rx = cq->p2 & 0xff;
3631                 bank_rx = cq->p2 >> 8;
3632                 if (debug & DEBUG_HFCMULTI_MSG)
3633                         printk(KERN_DEBUG
3634                                "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3635                                "slot %d bank %d (RX)\n",
3636                                __func__, slot_tx, bank_tx,
3637                                slot_rx, bank_rx);
3638                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3639                     slot_rx < hc->slots && bank_rx <= 2)
3640                         hfcmulti_pcm(hc, bch->slot,
3641                                      slot_tx, bank_tx, slot_rx, bank_rx);
3642                 else {
3643                         printk(KERN_WARNING
3644                                "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3645                                "slot %d bank %d (RX) out of range\n",
3646                                __func__, slot_tx, bank_tx,
3647                                slot_rx, bank_rx);
3648                         ret = -EINVAL;
3649                 }
3650                 break;
3651         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3652                 if (debug & DEBUG_HFCMULTI_MSG)
3653                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3654                                __func__);
3655                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3656                 break;
3657         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3658                 num = cq->p1 & 0xff;
3659                 if (debug & DEBUG_HFCMULTI_MSG)
3660                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3661                                __func__, num);
3662                 if (num <= 7)
3663                         hfcmulti_conf(hc, bch->slot, num);
3664                 else {
3665                         printk(KERN_WARNING
3666                                "%s: HW_CONF_JOIN conf %d out of range\n",
3667                                __func__, num);
3668                         ret = -EINVAL;
3669                 }
3670                 break;
3671         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3672                 if (debug & DEBUG_HFCMULTI_MSG)
3673                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3674                 hfcmulti_conf(hc, bch->slot, -1);
3675                 break;
3676         case MISDN_CTRL_HFC_ECHOCAN_ON:
3677                 if (debug & DEBUG_HFCMULTI_MSG)
3678                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3679                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3680                         vpm_echocan_on(hc, bch->slot, cq->p1);
3681                 else
3682                         ret = -EINVAL;
3683                 break;
3684
3685         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3686                 if (debug & DEBUG_HFCMULTI_MSG)
3687                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3688                                __func__);
3689                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3690                         vpm_echocan_off(hc, bch->slot);
3691                 else
3692                         ret = -EINVAL;
3693                 break;
3694         default:
3695                 ret = mISDN_ctrl_bchannel(bch, cq);
3696                 break;
3697         }
3698         return ret;
3699 }
3700
3701 static int
3702 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3703 {
3704         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3705         struct hfc_multi        *hc = bch->hw;
3706         int                     err = -EINVAL;
3707         u_long  flags;
3708
3709         if (bch->debug & DEBUG_HW)
3710                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3711                        __func__, cmd, arg);
3712         switch (cmd) {
3713         case CLOSE_CHANNEL:
3714                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3715                 deactivate_bchannel(bch); /* locked there */
3716                 ch->protocol = ISDN_P_NONE;
3717                 ch->peer = NULL;
3718                 module_put(THIS_MODULE);
3719                 err = 0;
3720                 break;
3721         case CONTROL_CHANNEL:
3722                 spin_lock_irqsave(&hc->lock, flags);
3723                 err = channel_bctrl(bch, arg);
3724                 spin_unlock_irqrestore(&hc->lock, flags);
3725                 break;
3726         default:
3727                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3728                        __func__, cmd);
3729         }
3730         return err;
3731 }
3732
3733 /*
3734  * handle D-channel events
3735  *
3736  * handle state change event
3737  */
3738 static void
3739 ph_state_change(struct dchannel *dch)
3740 {
3741         struct hfc_multi *hc;
3742         int ch, i;
3743
3744         if (!dch) {
3745                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3746                 return;
3747         }
3748         hc = dch->hw;
3749         ch = dch->slot;
3750
3751         if (hc->ctype == HFC_TYPE_E1) {
3752                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3753                         if (debug & DEBUG_HFCMULTI_STATE)
3754                                 printk(KERN_DEBUG
3755                                        "%s: E1 TE (id=%d) newstate %x\n",
3756                                        __func__, hc->id, dch->state);
3757                 } else {
3758                         if (debug & DEBUG_HFCMULTI_STATE)
3759                                 printk(KERN_DEBUG
3760                                        "%s: E1 NT (id=%d) newstate %x\n",
3761                                        __func__, hc->id, dch->state);
3762                 }
3763                 switch (dch->state) {
3764                 case (1):
3765                         if (hc->e1_state != 1) {
3766                                 for (i = 1; i <= 31; i++) {
3767                                         /* reset fifos on e1 activation */
3768                                         HFC_outb_nodebug(hc, R_FIFO,
3769                                                          (i << 1) | 1);
3770                                         HFC_wait_nodebug(hc);
3771                                         HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3772                                                          V_RES_F);
3773                                         HFC_wait_nodebug(hc);
3774                                 }
3775                         }
3776                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3777                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3778                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3779                         break;
3780
3781                 default:
3782                         if (hc->e1_state != 1)
3783                                 return;
3784                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3785                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3786                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3787                 }
3788                 hc->e1_state = dch->state;
3789         } else {
3790                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3791                         if (debug & DEBUG_HFCMULTI_STATE)
3792                                 printk(KERN_DEBUG
3793                                        "%s: S/T TE newstate %x\n",
3794                                        __func__, dch->state);
3795                         switch (dch->state) {
3796                         case (0):
3797                                 l1_event(dch->l1, HW_RESET_IND);
3798                                 break;
3799                         case (3):
3800                                 l1_event(dch->l1, HW_DEACT_IND);
3801                                 break;
3802                         case (5):
3803                         case (8):
3804                                 l1_event(dch->l1, ANYSIGNAL);
3805                                 break;
3806                         case (6):
3807                                 l1_event(dch->l1, INFO2);
3808                                 break;
3809                         case (7):
3810                                 l1_event(dch->l1, INFO4_P8);
3811                                 break;
3812                         }
3813                 } else {
3814                         if (debug & DEBUG_HFCMULTI_STATE)
3815                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3816                                        __func__, dch->state);
3817                         switch (dch->state) {
3818                         case (2):
3819                                 if (hc->chan[ch].nt_timer == 0) {
3820                                         hc->chan[ch].nt_timer = -1;
3821                                         HFC_outb(hc, R_ST_SEL,
3822                                                  hc->chan[ch].port);
3823                                         /* undocumented: delay after R_ST_SEL */
3824                                         udelay(1);
3825                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3826                                                  V_ST_LD_STA); /* G4 */
3827                                         udelay(6); /* wait at least 5,21us */
3828                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3829                                         dch->state = 4;
3830                                 } else {
3831                                         /* one extra count for the next event */
3832                                         hc->chan[ch].nt_timer =
3833                                                 nt_t1_count[poll_timer] + 1;
3834                                         HFC_outb(hc, R_ST_SEL,
3835                                                  hc->chan[ch].port);
3836                                         /* undocumented: delay after R_ST_SEL */
3837                                         udelay(1);
3838                                         /* allow G2 -> G3 transition */
3839                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3840                                                  V_SET_G2_G3);
3841                                 }
3842                                 break;
3843                         case (1):
3844                                 hc->chan[ch].nt_timer = -1;
3845                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3846                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3847                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3848                                 break;
3849                         case (4):
3850                                 hc->chan[ch].nt_timer = -1;
3851                                 break;
3852                         case (3):
3853                                 hc->chan[ch].nt_timer = -1;
3854                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3855                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3856                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3857                                 break;
3858                         }
3859                 }
3860         }
3861 }
3862
3863 /*
3864  * called for card mode init message
3865  */
3866
3867 static void
3868 hfcmulti_initmode(struct dchannel *dch)
3869 {
3870         struct hfc_multi *hc = dch->hw;
3871         u_char          a_st_wr_state, r_e1_wr_sta;
3872         int             i, pt;
3873
3874         if (debug & DEBUG_HFCMULTI_INIT)
3875                 printk(KERN_DEBUG "%s: entered\n", __func__);
3876
3877         i = dch->slot;
3878         pt = hc->chan[i].port;
3879         if (hc->ctype == HFC_TYPE_E1) {
3880                 /* E1 */
3881                 hc->chan[hc->dnum[pt]].slot_tx = -1;
3882                 hc->chan[hc->dnum[pt]].slot_rx = -1;
3883                 hc->chan[hc->dnum[pt]].conf = -1;
3884                 if (hc->dnum[pt]) {
3885                         mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
3886                                       -1, 0, -1, 0);
3887                         setup_timer(&dch->timer, (void *)hfcmulti_dbusy_timer,
3888                                     (long)dch);
3889                 }
3890                 for (i = 1; i <= 31; i++) {
3891                         if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3892                                 continue;
3893                         hc->chan[i].slot_tx = -1;
3894                         hc->chan[i].slot_rx = -1;
3895                         hc->chan[i].conf = -1;
3896                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3897                 }
3898         }
3899         if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3900                 /* E1, port 0 */
3901                 dch = hc->chan[hc->dnum[0]].dch;
3902                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3903                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3904                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3905                 }
3906                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3907                         HFC_outb(hc, R_RX0, 0);
3908                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3909                 } else {
3910                         HFC_outb(hc, R_RX0, 1);
3911                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3912                 }
3913                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3914                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3915                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3916                 HFC_outb(hc, R_TX_FR0, 0x00);
3917                 HFC_outb(hc, R_TX_FR1, 0xf8);
3918
3919                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3920                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3921
3922                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3923
3924                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3925                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3926
3927                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3928                         if (debug & DEBUG_HFCMULTI_INIT)
3929                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3930                                        __func__);
3931                         r_e1_wr_sta = 0; /* G0 */
3932                         hc->e1_getclock = 0;
3933                 } else {
3934                         if (debug & DEBUG_HFCMULTI_INIT)
3935                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3936                                        __func__);
3937                         r_e1_wr_sta = 0; /* F0 */
3938                         hc->e1_getclock = 1;
3939                 }
3940                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3941                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3942                 else
3943                         HFC_outb(hc, R_SYNC_OUT, 0);
3944                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3945                         hc->e1_getclock = 1;
3946                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3947                         hc->e1_getclock = 0;
3948                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3949                         /* SLAVE (clock master) */
3950                         if (debug & DEBUG_HFCMULTI_INIT)
3951                                 printk(KERN_DEBUG
3952                                        "%s: E1 port is clock master "
3953                                        "(clock from PCM)\n", __func__);
3954                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3955                 } else {
3956                         if (hc->e1_getclock) {
3957                                 /* MASTER (clock slave) */
3958                                 if (debug & DEBUG_HFCMULTI_INIT)
3959                                         printk(KERN_DEBUG
3960                                                "%s: E1 port is clock slave "
3961                                                "(clock to PCM)\n", __func__);
3962                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3963                         } else {
3964                                 /* MASTER (clock master) */
3965                                 if (debug & DEBUG_HFCMULTI_INIT)
3966                                         printk(KERN_DEBUG "%s: E1 port is "
3967                                                "clock master "
3968                                                "(clock from QUARTZ)\n",
3969                                                __func__);
3970                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3971                                          V_PCM_SYNC | V_JATT_OFF);
3972                                 HFC_outb(hc, R_SYNC_OUT, 0);
3973                         }
3974                 }
3975                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3976                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3977                 HFC_outb(hc, R_PWM0, 0x50);
3978                 HFC_outb(hc, R_PWM1, 0xff);
3979                 /* state machine setup */
3980                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3981                 udelay(6); /* wait at least 5,21us */
3982                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3983                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3984                         hc->syncronized = 0;
3985                         plxsd_checksync(hc, 0);
3986                 }
3987         }
3988         if (hc->ctype != HFC_TYPE_E1) {
3989                 /* ST */
3990                 hc->chan[i].slot_tx = -1;
3991                 hc->chan[i].slot_rx = -1;
3992                 hc->chan[i].conf = -1;
3993                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3994                 setup_timer(&dch->timer, (void *)hfcmulti_dbusy_timer,
3995                             (long)dch);
3996                 hc->chan[i - 2].slot_tx = -1;
3997                 hc->chan[i - 2].slot_rx = -1;
3998                 hc->chan[i - 2].conf = -1;
3999                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
4000                 hc->chan[i - 1].slot_tx = -1;
4001                 hc->chan[i - 1].slot_rx = -1;
4002                 hc->chan[i - 1].conf = -1;
4003                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
4004                 /* select interface */
4005                 HFC_outb(hc, R_ST_SEL, pt);
4006                 /* undocumented: delay after R_ST_SEL */
4007                 udelay(1);
4008                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
4009                         if (debug & DEBUG_HFCMULTI_INIT)
4010                                 printk(KERN_DEBUG
4011                                        "%s: ST port %d is NT-mode\n",
4012                                        __func__, pt);
4013                         /* clock delay */
4014                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
4015                         a_st_wr_state = 1; /* G1 */
4016                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
4017                 } else {
4018                         if (debug & DEBUG_HFCMULTI_INIT)
4019                                 printk(KERN_DEBUG
4020                                        "%s: ST port %d is TE-mode\n",
4021                                        __func__, pt);
4022                         /* clock delay */
4023                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
4024                         a_st_wr_state = 2; /* F2 */
4025                         hc->hw.a_st_ctrl0[pt] = 0;
4026                 }
4027                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4028                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
4029                 if (hc->ctype == HFC_TYPE_XHFC) {
4030                         hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4031                         HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4032                                  0x7c << 1 /* V_ST_PULSE */);
4033                 }
4034                 /* line setup */
4035                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
4036                 /* disable E-channel */
4037                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4038                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4039                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4040                 else
4041                         HFC_outb(hc, A_ST_CTRL1, 0);
4042                 /* enable B-channel receive */
4043                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
4044                 /* state machine setup */
4045                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4046                 udelay(6); /* wait at least 5,21us */
4047                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4048                 hc->hw.r_sci_msk |= 1 << pt;
4049                 /* state machine interrupts */
4050                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4051                 /* unset sync on port */
4052                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4053                         hc->syncronized &=
4054                                 ~(1 << hc->chan[dch->slot].port);
4055                         plxsd_checksync(hc, 0);
4056                 }
4057         }
4058         if (debug & DEBUG_HFCMULTI_INIT)
4059                 printk("%s: done\n", __func__);
4060 }
4061
4062
4063 static int
4064 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4065               struct channel_req *rq)
4066 {
4067         int     err = 0;
4068         u_long  flags;
4069
4070         if (debug & DEBUG_HW_OPEN)
4071                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4072                        dch->dev.id, __builtin_return_address(0));
4073         if (rq->protocol == ISDN_P_NONE)
4074                 return -EINVAL;
4075         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4076             (dch->dev.D.protocol != rq->protocol)) {
4077                 if (debug & DEBUG_HFCMULTI_MODE)
4078                         printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4079                                __func__, dch->dev.D.protocol, rq->protocol);
4080         }
4081         if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4082             (rq->protocol != ISDN_P_TE_S0))
4083                 l1_event(dch->l1, CLOSE_CHANNEL);
4084         if (dch->dev.D.protocol != rq->protocol) {
4085                 if (rq->protocol == ISDN_P_TE_S0) {
4086                         err = create_l1(dch, hfcm_l1callback);
4087                         if (err)
4088                                 return err;
4089                 }
4090                 dch->dev.D.protocol = rq->protocol;
4091                 spin_lock_irqsave(&hc->lock, flags);
4092                 hfcmulti_initmode(dch);
4093                 spin_unlock_irqrestore(&hc->lock, flags);
4094         }
4095         if (test_bit(FLG_ACTIVE, &dch->Flags))
4096                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4097                             0, NULL, GFP_KERNEL);
4098         rq->ch = &dch->dev.D;
4099         if (!try_module_get(THIS_MODULE))
4100                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4101         return 0;
4102 }
4103
4104 static int
4105 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4106               struct channel_req *rq)
4107 {
4108         struct bchannel *bch;
4109         int             ch;
4110
4111         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4112                 return -EINVAL;
4113         if (rq->protocol == ISDN_P_NONE)
4114                 return -EINVAL;
4115         if (hc->ctype == HFC_TYPE_E1)
4116                 ch = rq->adr.channel;
4117         else
4118                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4119         bch = hc->chan[ch].bch;
4120         if (!bch) {
4121                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4122                        __func__, ch);
4123                 return -EINVAL;
4124         }
4125         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4126                 return -EBUSY; /* b-channel can be only open once */
4127         bch->ch.protocol = rq->protocol;
4128         hc->chan[ch].rx_off = 0;
4129         rq->ch = &bch->ch;
4130         if (!try_module_get(THIS_MODULE))
4131                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4132         return 0;
4133 }
4134
4135 /*
4136  * device control function
4137  */
4138 static int
4139 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4140 {
4141         struct hfc_multi        *hc = dch->hw;
4142         int     ret = 0;
4143         int     wd_mode, wd_cnt;
4144
4145         switch (cq->op) {
4146         case MISDN_CTRL_GETOP:
4147                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4148                 break;
4149         case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4150                 wd_cnt = cq->p1 & 0xf;
4151                 wd_mode = !!(cq->p1 >> 4);
4152                 if (debug & DEBUG_HFCMULTI_MSG)
4153                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4154                                ", counter 0x%x\n", __func__,
4155                                wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4156                 /* set the watchdog timer */
4157                 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4158                 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4159                 if (hc->ctype == HFC_TYPE_XHFC)
4160                         hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4161                 /* init the watchdog register and reset the counter */
4162                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4163                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4164                         /* enable the watchdog output for Speech-Design */
4165                         HFC_outb(hc, R_GPIO_SEL,  V_GPIO_SEL7);
4166                         HFC_outb(hc, R_GPIO_EN1,  V_GPIO_EN15);
4167                         HFC_outb(hc, R_GPIO_OUT1, 0);
4168                         HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4169                 }
4170                 break;
4171         case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4172                 if (debug & DEBUG_HFCMULTI_MSG)
4173                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4174                                __func__);
4175                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4176                 break;
4177         case MISDN_CTRL_L1_TIMER3:
4178                 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4179                 break;
4180         default:
4181                 printk(KERN_WARNING "%s: unknown Op %x\n",
4182                        __func__, cq->op);
4183                 ret = -EINVAL;
4184                 break;
4185         }
4186         return ret;
4187 }
4188
4189 static int
4190 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4191 {
4192         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4193         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4194         struct hfc_multi        *hc = dch->hw;
4195         struct channel_req      *rq;
4196         int                     err = 0;
4197         u_long                  flags;
4198
4199         if (dch->debug & DEBUG_HW)
4200                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4201                        __func__, cmd, arg);
4202         switch (cmd) {
4203         case OPEN_CHANNEL:
4204                 rq = arg;
4205                 switch (rq->protocol) {
4206                 case ISDN_P_TE_S0:
4207                 case ISDN_P_NT_S0:
4208                         if (hc->ctype == HFC_TYPE_E1) {
4209                                 err = -EINVAL;
4210                                 break;
4211                         }
4212                         err = open_dchannel(hc, dch, rq); /* locked there */
4213                         break;
4214                 case ISDN_P_TE_E1:
4215                 case ISDN_P_NT_E1:
4216                         if (hc->ctype != HFC_TYPE_E1) {
4217                                 err = -EINVAL;
4218                                 break;
4219                         }
4220                         err = open_dchannel(hc, dch, rq); /* locked there */
4221                         break;
4222                 default:
4223                         spin_lock_irqsave(&hc->lock, flags);
4224                         err = open_bchannel(hc, dch, rq);
4225                         spin_unlock_irqrestore(&hc->lock, flags);
4226                 }
4227                 break;
4228         case CLOSE_CHANNEL:
4229                 if (debug & DEBUG_HW_OPEN)
4230                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4231                                __func__, dch->dev.id,
4232                                __builtin_return_address(0));
4233                 module_put(THIS_MODULE);
4234                 break;
4235         case CONTROL_CHANNEL:
4236                 spin_lock_irqsave(&hc->lock, flags);
4237                 err = channel_dctrl(dch, arg);
4238                 spin_unlock_irqrestore(&hc->lock, flags);
4239                 break;
4240         default:
4241                 if (dch->debug & DEBUG_HW)
4242                         printk(KERN_DEBUG "%s: unknown command %x\n",
4243                                __func__, cmd);
4244                 err = -EINVAL;
4245         }
4246         return err;
4247 }
4248
4249 static int
4250 clockctl(void *priv, int enable)
4251 {
4252         struct hfc_multi *hc = priv;
4253
4254         hc->iclock_on = enable;
4255         return 0;
4256 }
4257
4258 /*
4259  * initialize the card
4260  */
4261
4262 /*
4263  * start timer irq, wait some time and check if we have interrupts.
4264  * if not, reset chip and try again.
4265  */
4266 static int
4267 init_card(struct hfc_multi *hc)
4268 {
4269         int     err = -EIO;
4270         u_long  flags;
4271         void    __iomem *plx_acc;
4272         u_long  plx_flags;
4273
4274         if (debug & DEBUG_HFCMULTI_INIT)
4275                 printk(KERN_DEBUG "%s: entered\n", __func__);
4276
4277         spin_lock_irqsave(&hc->lock, flags);
4278         /* set interrupts but leave global interrupt disabled */
4279         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4280         disable_hwirq(hc);
4281         spin_unlock_irqrestore(&hc->lock, flags);
4282
4283         if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4284                         "HFC-multi", hc)) {
4285                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4286                        hc->irq);
4287                 hc->irq = 0;
4288                 return -EIO;
4289         }
4290
4291         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4292                 spin_lock_irqsave(&plx_lock, plx_flags);
4293                 plx_acc = hc->plx_membase + PLX_INTCSR;
4294                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4295                        plx_acc); /* enable PCI & LINT1 irq */
4296                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4297         }
4298
4299         if (debug & DEBUG_HFCMULTI_INIT)
4300                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4301                        __func__, hc->irq, hc->irqcnt);
4302         err = init_chip(hc);
4303         if (err)
4304                 goto error;
4305         /*
4306          * Finally enable IRQ output
4307          * this is only allowed, if an IRQ routine is already
4308          * established for this HFC, so don't do that earlier
4309          */
4310         spin_lock_irqsave(&hc->lock, flags);
4311         enable_hwirq(hc);
4312         spin_unlock_irqrestore(&hc->lock, flags);
4313         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4314         set_current_state(TASK_UNINTERRUPTIBLE);
4315         schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4316         /* turn IRQ off until chip is completely initialized */
4317         spin_lock_irqsave(&hc->lock, flags);
4318         disable_hwirq(hc);
4319         spin_unlock_irqrestore(&hc->lock, flags);
4320         if (debug & DEBUG_HFCMULTI_INIT)
4321                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4322                        __func__, hc->irq, hc->irqcnt);
4323         if (hc->irqcnt) {
4324                 if (debug & DEBUG_HFCMULTI_INIT)
4325                         printk(KERN_DEBUG "%s: done\n", __func__);
4326
4327                 return 0;
4328         }
4329         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4330                 printk(KERN_INFO "ignoring missing interrupts\n");
4331                 return 0;
4332         }
4333
4334         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4335                hc->irq);
4336
4337         err = -EIO;
4338
4339 error:
4340         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4341                 spin_lock_irqsave(&plx_lock, plx_flags);
4342                 plx_acc = hc->plx_membase + PLX_INTCSR;
4343                 writew(0x00, plx_acc); /*disable IRQs*/
4344                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4345         }
4346
4347         if (debug & DEBUG_HFCMULTI_INIT)
4348                 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4349         if (hc->irq) {
4350                 free_irq(hc->irq, hc);
4351                 hc->irq = 0;
4352         }
4353
4354         if (debug & DEBUG_HFCMULTI_INIT)
4355                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4356         return err;
4357 }
4358
4359 /*
4360  * find pci device and set it up
4361  */
4362
4363 static int
4364 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4365           const struct pci_device_id *ent)
4366 {
4367         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4368
4369         printk(KERN_INFO
4370                "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4371                m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4372
4373         hc->pci_dev = pdev;
4374         if (m->clock2)
4375                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4376
4377         if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4378             ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
4379                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4380                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4381                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4382                 hc->slots = 32;
4383         }
4384
4385         if (hc->pci_dev->irq <= 0) {
4386                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4387                 return -EIO;
4388         }
4389         if (pci_enable_device(hc->pci_dev)) {
4390                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4391                 return -EIO;
4392         }
4393         hc->leds = m->leds;
4394         hc->ledstate = 0xAFFEAFFE;
4395         hc->opticalsupport = m->opticalsupport;
4396
4397         hc->pci_iobase = 0;
4398         hc->pci_membase = NULL;
4399         hc->plx_membase = NULL;
4400
4401         /* set memory access methods */
4402         if (m->io_mode) /* use mode from card config */
4403                 hc->io_mode = m->io_mode;
4404         switch (hc->io_mode) {
4405         case HFC_IO_MODE_PLXSD:
4406                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4407                 hc->slots = 128; /* required */
4408                 hc->HFC_outb = HFC_outb_pcimem;
4409                 hc->HFC_inb = HFC_inb_pcimem;
4410                 hc->HFC_inw = HFC_inw_pcimem;
4411                 hc->HFC_wait = HFC_wait_pcimem;
4412                 hc->read_fifo = read_fifo_pcimem;
4413                 hc->write_fifo = write_fifo_pcimem;
4414                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4415                 /* MEMBASE 1 is PLX PCI Bridge */
4416
4417                 if (!hc->plx_origmembase) {
4418                         printk(KERN_WARNING
4419                                "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4420                         pci_disable_device(hc->pci_dev);
4421                         return -EIO;
4422                 }
4423
4424                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4425                 if (!hc->plx_membase) {
4426                         printk(KERN_WARNING
4427                                "HFC-multi: failed to remap plx address space. "
4428                                "(internal error)\n");
4429                         pci_disable_device(hc->pci_dev);
4430                         return -EIO;
4431                 }
4432                 printk(KERN_INFO
4433                        "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4434                        (u_long)hc->plx_membase, hc->plx_origmembase);
4435
4436                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4437                 /* MEMBASE 1 is PLX PCI Bridge */
4438                 if (!hc->pci_origmembase) {
4439                         printk(KERN_WARNING
4440                                "HFC-multi: No IO-Memory for PCI card found\n");
4441                         pci_disable_device(hc->pci_dev);
4442                         return -EIO;
4443                 }
4444
4445                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4446                 if (!hc->pci_membase) {
4447                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4448                                "address space. (internal error)\n");
4449                         pci_disable_device(hc->pci_dev);
4450                         return -EIO;
4451                 }
4452
4453                 printk(KERN_INFO
4454                        "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4455                        "leds-type %d\n",
4456                        hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4457                        hc->pci_dev->irq, HZ, hc->leds);
4458                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4459                 break;
4460         case HFC_IO_MODE_PCIMEM:
4461                 hc->HFC_outb = HFC_outb_pcimem;
4462                 hc->HFC_inb = HFC_inb_pcimem;
4463                 hc->HFC_inw = HFC_inw_pcimem;
4464                 hc->HFC_wait = HFC_wait_pcimem;
4465                 hc->read_fifo = read_fifo_pcimem;
4466                 hc->write_fifo = write_fifo_pcimem;
4467                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4468                 if (!hc->pci_origmembase) {
4469                         printk(KERN_WARNING
4470                                "HFC-multi: No IO-Memory for PCI card found\n");
4471                         pci_disable_device(hc->pci_dev);
4472                         return -EIO;
4473                 }
4474
4475                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4476                 if (!hc->pci_membase) {
4477                         printk(KERN_WARNING
4478                                "HFC-multi: failed to remap io address space. "
4479                                "(internal error)\n");
4480                         pci_disable_device(hc->pci_dev);
4481                         return -EIO;
4482                 }
4483                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4484                        "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4485                        hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4486                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4487                 break;
4488         case HFC_IO_MODE_REGIO:
4489                 hc->HFC_outb = HFC_outb_regio;
4490                 hc->HFC_inb = HFC_inb_regio;
4491                 hc->HFC_inw = HFC_inw_regio;
4492                 hc->HFC_wait = HFC_wait_regio;
4493                 hc->read_fifo = read_fifo_regio;
4494                 hc->write_fifo = write_fifo_regio;
4495                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4496                 if (!hc->pci_iobase) {
4497                         printk(KERN_WARNING
4498                                "HFC-multi: No IO for PCI card found\n");
4499                         pci_disable_device(hc->pci_dev);
4500                         return -EIO;
4501                 }
4502
4503                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4504                         printk(KERN_WARNING "HFC-multi: failed to request "
4505                                "address space at 0x%08lx (internal error)\n",
4506                                hc->pci_iobase);
4507                         pci_disable_device(hc->pci_dev);
4508                         return -EIO;
4509                 }
4510
4511                 printk(KERN_INFO
4512                        "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4513                        m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4514                        hc->pci_dev->irq, HZ, hc->leds);
4515                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4516                 break;
4517         default:
4518                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4519                 pci_disable_device(hc->pci_dev);
4520                 return -EIO;
4521         }
4522
4523         pci_set_drvdata(hc->pci_dev, hc);
4524
4525         /* At this point the needed PCI config is done */
4526         /* fifos are still not enabled */
4527         return 0;
4528 }
4529
4530
4531 /*
4532  * remove port
4533  */
4534
4535 static void
4536 release_port(struct hfc_multi *hc, struct dchannel *dch)
4537 {
4538         int     pt, ci, i = 0;
4539         u_long  flags;
4540         struct bchannel *pb;
4541
4542         ci = dch->slot;
4543         pt = hc->chan[ci].port;
4544
4545         if (debug & DEBUG_HFCMULTI_INIT)
4546                 printk(KERN_DEBUG "%s: entered for port %d\n",
4547                        __func__, pt + 1);
4548
4549         if (pt >= hc->ports) {
4550                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4551                        __func__, pt + 1);
4552                 return;
4553         }
4554
4555         if (debug & DEBUG_HFCMULTI_INIT)
4556                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4557                        __func__, pt + 1);
4558
4559         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4560                 l1_event(dch->l1, CLOSE_CHANNEL);
4561
4562         hc->chan[ci].dch = NULL;
4563
4564         if (hc->created[pt]) {
4565                 hc->created[pt] = 0;
4566                 mISDN_unregister_device(&dch->dev);
4567         }
4568
4569         spin_lock_irqsave(&hc->lock, flags);
4570
4571         if (dch->timer.function) {
4572                 del_timer(&dch->timer);
4573                 dch->timer.function = NULL;
4574         }
4575
4576         if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4577                 /* remove sync */
4578                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4579                         hc->syncronized = 0;
4580                         plxsd_checksync(hc, 1);
4581                 }
4582                 /* free channels */
4583                 for (i = 0; i <= 31; i++) {
4584                         if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4585                                 continue;
4586                         if (hc->chan[i].bch) {
4587                                 if (debug & DEBUG_HFCMULTI_INIT)
4588                                         printk(KERN_DEBUG
4589                                                "%s: free port %d channel %d\n",
4590                                                __func__, hc->chan[i].port + 1, i);
4591                                 pb = hc->chan[i].bch;
4592                                 hc->chan[i].bch = NULL;
4593                                 spin_unlock_irqrestore(&hc->lock, flags);
4594                                 mISDN_freebchannel(pb);
4595                                 kfree(pb);
4596                                 kfree(hc->chan[i].coeff);
4597                                 spin_lock_irqsave(&hc->lock, flags);
4598                         }
4599                 }
4600         } else {
4601                 /* remove sync */
4602                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4603                         hc->syncronized &=
4604                                 ~(1 << hc->chan[ci].port);
4605                         plxsd_checksync(hc, 1);
4606                 }
4607                 /* free channels */
4608                 if (hc->chan[ci - 2].bch) {
4609                         if (debug & DEBUG_HFCMULTI_INIT)
4610                                 printk(KERN_DEBUG
4611                                        "%s: free port %d channel %d\n",
4612                                        __func__, hc->chan[ci - 2].port + 1,
4613                                        ci - 2);
4614                         pb = hc->chan[ci - 2].bch;
4615                         hc->chan[ci - 2].bch = NULL;
4616                         spin_unlock_irqrestore(&hc->lock, flags);
4617                         mISDN_freebchannel(pb);
4618                         kfree(pb);
4619                         kfree(hc->chan[ci - 2].coeff);
4620                         spin_lock_irqsave(&hc->lock, flags);
4621                 }
4622                 if (hc->chan[ci - 1].bch) {
4623                         if (debug & DEBUG_HFCMULTI_INIT)
4624                                 printk(KERN_DEBUG
4625                                        "%s: free port %d channel %d\n",
4626                                        __func__, hc->chan[ci - 1].port + 1,
4627                                        ci - 1);
4628                         pb = hc->chan[ci - 1].bch;
4629                         hc->chan[ci - 1].bch = NULL;
4630                         spin_unlock_irqrestore(&hc->lock, flags);
4631                         mISDN_freebchannel(pb);
4632                         kfree(pb);
4633                         kfree(hc->chan[ci - 1].coeff);
4634                         spin_lock_irqsave(&hc->lock, flags);
4635                 }
4636         }
4637
4638         spin_unlock_irqrestore(&hc->lock, flags);
4639
4640         if (debug & DEBUG_HFCMULTI_INIT)
4641                 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4642                         pt+1, ci);
4643         mISDN_freedchannel(dch);
4644         kfree(dch);
4645
4646         if (debug & DEBUG_HFCMULTI_INIT)
4647                 printk(KERN_DEBUG "%s: done!\n", __func__);
4648 }
4649
4650 static void
4651 release_card(struct hfc_multi *hc)
4652 {
4653         u_long  flags;
4654         int     ch;
4655
4656         if (debug & DEBUG_HFCMULTI_INIT)
4657                 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4658                        __func__, hc->id);
4659
4660         /* unregister clock source */
4661         if (hc->iclock)
4662                 mISDN_unregister_clock(hc->iclock);
4663
4664         /* disable and free irq */
4665         spin_lock_irqsave(&hc->lock, flags);
4666         disable_hwirq(hc);
4667         spin_unlock_irqrestore(&hc->lock, flags);
4668         udelay(1000);
4669         if (hc->irq) {
4670                 if (debug & DEBUG_HFCMULTI_INIT)
4671                         printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4672                             __func__, hc->irq, hc);
4673                 free_irq(hc->irq, hc);
4674                 hc->irq = 0;
4675
4676         }
4677
4678         /* disable D-channels & B-channels */
4679         if (debug & DEBUG_HFCMULTI_INIT)
4680                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4681                        __func__);
4682         for (ch = 0; ch <= 31; ch++) {
4683                 if (hc->chan[ch].dch)
4684                         release_port(hc, hc->chan[ch].dch);
4685         }
4686
4687         /* dimm leds */
4688         if (hc->leds)
4689                 hfcmulti_leds(hc);
4690
4691         /* release hardware */
4692         release_io_hfcmulti(hc);
4693
4694         if (debug & DEBUG_HFCMULTI_INIT)
4695                 printk(KERN_DEBUG "%s: remove instance from list\n",
4696                        __func__);
4697         list_del(&hc->list);
4698
4699         if (debug & DEBUG_HFCMULTI_INIT)
4700                 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4701         if (hc == syncmaster)
4702                 syncmaster = NULL;
4703         kfree(hc);
4704         if (debug & DEBUG_HFCMULTI_INIT)
4705                 printk(KERN_DEBUG "%s: card successfully removed\n",
4706                        __func__);
4707 }
4708
4709 static void
4710 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
4711 {
4712         /* set optical line type */
4713         if (port[Port_cnt] & 0x001) {
4714                 if (!m->opticalsupport)  {
4715                         printk(KERN_INFO
4716                                "This board has no optical "
4717                                "support\n");
4718                 } else {
4719                         if (debug & DEBUG_HFCMULTI_INIT)
4720                                 printk(KERN_DEBUG
4721                                        "%s: PORT set optical "
4722                                        "interfacs: card(%d) "
4723                                        "port(%d)\n",
4724                                        __func__,
4725                                        HFC_cnt + 1, 1);
4726                         test_and_set_bit(HFC_CFG_OPTICAL,
4727                             &hc->chan[hc->dnum[0]].cfg);
4728                 }
4729         }
4730         /* set LOS report */
4731         if (port[Port_cnt] & 0x004) {
4732                 if (debug & DEBUG_HFCMULTI_INIT)
4733                         printk(KERN_DEBUG "%s: PORT set "
4734                                "LOS report: card(%d) port(%d)\n",
4735                                __func__, HFC_cnt + 1, 1);
4736                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4737                     &hc->chan[hc->dnum[0]].cfg);
4738         }
4739         /* set AIS report */
4740         if (port[Port_cnt] & 0x008) {
4741                 if (debug & DEBUG_HFCMULTI_INIT)
4742                         printk(KERN_DEBUG "%s: PORT set "
4743                                "AIS report: card(%d) port(%d)\n",
4744                                __func__, HFC_cnt + 1, 1);
4745                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4746                     &hc->chan[hc->dnum[0]].cfg);
4747         }
4748         /* set SLIP report */
4749         if (port[Port_cnt] & 0x010) {
4750                 if (debug & DEBUG_HFCMULTI_INIT)
4751                         printk(KERN_DEBUG
4752                                "%s: PORT set SLIP report: "
4753                                "card(%d) port(%d)\n",
4754                                __func__, HFC_cnt + 1, 1);
4755                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4756                     &hc->chan[hc->dnum[0]].cfg);
4757         }
4758         /* set RDI report */
4759         if (port[Port_cnt] & 0x020) {
4760                 if (debug & DEBUG_HFCMULTI_INIT)
4761                         printk(KERN_DEBUG
4762                                "%s: PORT set RDI report: "
4763                                "card(%d) port(%d)\n",
4764                                __func__, HFC_cnt + 1, 1);
4765                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4766                     &hc->chan[hc->dnum[0]].cfg);
4767         }
4768         /* set CRC-4 Mode */
4769         if (!(port[Port_cnt] & 0x100)) {
4770                 if (debug & DEBUG_HFCMULTI_INIT)
4771                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4772                                " card(%d) port(%d)\n",
4773                                __func__, HFC_cnt + 1, 1);
4774                 test_and_set_bit(HFC_CFG_CRC4,
4775                     &hc->chan[hc->dnum[0]].cfg);
4776         } else {
4777                 if (debug & DEBUG_HFCMULTI_INIT)
4778                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4779                                " report: card(%d) port(%d)\n",
4780                                __func__, HFC_cnt + 1, 1);
4781         }
4782         /* set forced clock */
4783         if (port[Port_cnt] & 0x0200) {
4784                 if (debug & DEBUG_HFCMULTI_INIT)
4785                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4786                                "E1: card(%d) port(%d)\n",
4787                                __func__, HFC_cnt + 1, 1);
4788                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4789         } else
4790                 if (port[Port_cnt] & 0x0400) {
4791                         if (debug & DEBUG_HFCMULTI_INIT)
4792                                 printk(KERN_DEBUG "%s: PORT force putting clock to "
4793                                        "E1: card(%d) port(%d)\n",
4794                                        __func__, HFC_cnt + 1, 1);
4795                         test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4796                 }
4797         /* set JATT PLL */
4798         if (port[Port_cnt] & 0x0800) {
4799                 if (debug & DEBUG_HFCMULTI_INIT)
4800                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4801                                "E1: card(%d) port(%d)\n",
4802                                __func__, HFC_cnt + 1, 1);
4803                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4804         }
4805         /* set elastic jitter buffer */
4806         if (port[Port_cnt] & 0x3000) {
4807                 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4808                 if (debug & DEBUG_HFCMULTI_INIT)
4809                         printk(KERN_DEBUG
4810                                "%s: PORT set elastic "
4811                                "buffer to %d: card(%d) port(%d)\n",
4812                             __func__, hc->chan[hc->dnum[0]].jitter,
4813                                HFC_cnt + 1, 1);
4814         } else
4815                 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4816 }
4817
4818 static int
4819 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4820 {
4821         struct dchannel *dch;
4822         struct bchannel *bch;
4823         int             ch, ret = 0;
4824         char            name[MISDN_MAX_IDLEN];
4825         int             bcount = 0;
4826
4827         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4828         if (!dch)
4829                 return -ENOMEM;
4830         dch->debug = debug;
4831         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4832         dch->hw = hc;
4833         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4834         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4835             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4836         dch->dev.D.send = handle_dmsg;
4837         dch->dev.D.ctrl = hfcm_dctrl;
4838         dch->slot = hc->dnum[pt];
4839         hc->chan[hc->dnum[pt]].dch = dch;
4840         hc->chan[hc->dnum[pt]].port = pt;
4841         hc->chan[hc->dnum[pt]].nt_timer = -1;
4842         for (ch = 1; ch <= 31; ch++) {
4843                 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4844                         continue;
4845                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4846                 if (!bch) {
4847                         printk(KERN_ERR "%s: no memory for bchannel\n",
4848                             __func__);
4849                         ret = -ENOMEM;
4850                         goto free_chan;
4851                 }
4852                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4853                 if (!hc->chan[ch].coeff) {
4854                         printk(KERN_ERR "%s: no memory for coeffs\n",
4855                             __func__);
4856                         ret = -ENOMEM;
4857                         kfree(bch);
4858                         goto free_chan;
4859                 }
4860                 bch->nr = ch;
4861                 bch->slot = ch;
4862                 bch->debug = debug;
4863                 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4864                 bch->hw = hc;
4865                 bch->ch.send = handle_bmsg;
4866                 bch->ch.ctrl = hfcm_bctrl;
4867                 bch->ch.nr = ch;
4868                 list_add(&bch->ch.list, &dch->dev.bchannels);
4869                 hc->chan[ch].bch = bch;
4870                 hc->chan[ch].port = pt;
4871                 set_channelmap(bch->nr, dch->dev.channelmap);
4872                 bcount++;
4873         }
4874         dch->dev.nrbchan = bcount;
4875         if (pt == 0)
4876                 init_e1_port_hw(hc, m);
4877         if (hc->ports > 1)
4878                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4879                                 HFC_cnt + 1, pt+1);
4880         else
4881                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4882         ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4883         if (ret)
4884                 goto free_chan;
4885         hc->created[pt] = 1;
4886         return ret;
4887 free_chan:
4888         release_port(hc, dch);
4889         return ret;
4890 }
4891
4892 static int
4893 init_multi_port(struct hfc_multi *hc, int pt)
4894 {
4895         struct dchannel *dch;
4896         struct bchannel *bch;
4897         int             ch, i, ret = 0;
4898         char            name[MISDN_MAX_IDLEN];
4899
4900         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4901         if (!dch)
4902                 return -ENOMEM;
4903         dch->debug = debug;
4904         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4905         dch->hw = hc;
4906         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4907         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4908                 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4909         dch->dev.D.send = handle_dmsg;
4910         dch->dev.D.ctrl = hfcm_dctrl;
4911         dch->dev.nrbchan = 2;
4912         i = pt << 2;
4913         dch->slot = i + 2;
4914         hc->chan[i + 2].dch = dch;
4915         hc->chan[i + 2].port = pt;
4916         hc->chan[i + 2].nt_timer = -1;
4917         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4918                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4919                 if (!bch) {
4920                         printk(KERN_ERR "%s: no memory for bchannel\n",
4921                                __func__);
4922                         ret = -ENOMEM;
4923                         goto free_chan;
4924                 }
4925                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4926                 if (!hc->chan[i + ch].coeff) {
4927                         printk(KERN_ERR "%s: no memory for coeffs\n",
4928                                __func__);
4929                         ret = -ENOMEM;
4930                         kfree(bch);
4931                         goto free_chan;
4932                 }
4933                 bch->nr = ch + 1;
4934                 bch->slot = i + ch;
4935                 bch->debug = debug;
4936                 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4937                 bch->hw = hc;
4938                 bch->ch.send = handle_bmsg;
4939                 bch->ch.ctrl = hfcm_bctrl;
4940                 bch->ch.nr = ch + 1;
4941                 list_add(&bch->ch.list, &dch->dev.bchannels);
4942                 hc->chan[i + ch].bch = bch;
4943                 hc->chan[i + ch].port = pt;
4944                 set_channelmap(bch->nr, dch->dev.channelmap);
4945         }
4946         /* set master clock */
4947         if (port[Port_cnt] & 0x001) {
4948                 if (debug & DEBUG_HFCMULTI_INIT)
4949                         printk(KERN_DEBUG
4950                                "%s: PROTOCOL set master clock: "
4951                                "card(%d) port(%d)\n",
4952                                __func__, HFC_cnt + 1, pt + 1);
4953                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4954                         printk(KERN_ERR "Error: Master clock "
4955                                "for port(%d) of card(%d) is only"
4956                                " possible with TE-mode\n",
4957                                pt + 1, HFC_cnt + 1);
4958                         ret = -EINVAL;
4959                         goto free_chan;
4960                 }
4961                 if (hc->masterclk >= 0) {
4962                         printk(KERN_ERR "Error: Master clock "
4963                                "for port(%d) of card(%d) already "
4964                                "defined for port(%d)\n",
4965                                pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4966                         ret = -EINVAL;
4967                         goto free_chan;
4968                 }
4969                 hc->masterclk = pt;
4970         }
4971         /* set transmitter line to non capacitive */
4972         if (port[Port_cnt] & 0x002) {
4973                 if (debug & DEBUG_HFCMULTI_INIT)
4974                         printk(KERN_DEBUG
4975                                "%s: PROTOCOL set non capacitive "
4976                                "transmitter: card(%d) port(%d)\n",
4977                                __func__, HFC_cnt + 1, pt + 1);
4978                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4979                                  &hc->chan[i + 2].cfg);
4980         }
4981         /* disable E-channel */
4982         if (port[Port_cnt] & 0x004) {
4983                 if (debug & DEBUG_HFCMULTI_INIT)
4984                         printk(KERN_DEBUG
4985                                "%s: PROTOCOL disable E-channel: "
4986                                "card(%d) port(%d)\n",
4987                                __func__, HFC_cnt + 1, pt + 1);
4988                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4989                                  &hc->chan[i + 2].cfg);
4990         }
4991         if (hc->ctype == HFC_TYPE_XHFC) {
4992                 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4993                          HFC_cnt + 1, pt + 1);
4994                 ret = mISDN_register_device(&dch->dev, NULL, name);
4995         } else {
4996                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4997                          hc->ctype, HFC_cnt + 1, pt + 1);
4998                 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4999         }
5000         if (ret)
5001                 goto free_chan;
5002         hc->created[pt] = 1;
5003         return ret;
5004 free_chan:
5005         release_port(hc, dch);
5006         return ret;
5007 }
5008
5009 static int
5010 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
5011               const struct pci_device_id *ent)
5012 {
5013         int             ret_err = 0;
5014         int             pt;
5015         struct hfc_multi        *hc;
5016         u_long          flags;
5017         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
5018         int             i, ch;
5019         u_int           maskcheck;
5020
5021         if (HFC_cnt >= MAX_CARDS) {
5022                 printk(KERN_ERR "too many cards (max=%d).\n",
5023                        MAX_CARDS);
5024                 return -EINVAL;
5025         }
5026         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
5027                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
5028                        "type[%d] %d was supplied as module parameter\n",
5029                        m->vendor_name, m->card_name, m->type, HFC_cnt,
5030                        type[HFC_cnt] & 0xff);
5031                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
5032                        "first, to see cards and their types.");
5033                 return -EINVAL;
5034         }
5035         if (debug & DEBUG_HFCMULTI_INIT)
5036                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
5037                        __func__, m->vendor_name, m->card_name, m->type,
5038                        type[HFC_cnt]);
5039
5040         /* allocate card+fifo structure */
5041         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5042         if (!hc) {
5043                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5044                 return -ENOMEM;
5045         }
5046         spin_lock_init(&hc->lock);
5047         hc->mtyp = m;
5048         hc->ctype =  m->type;
5049         hc->ports = m->ports;
5050         hc->id = HFC_cnt;
5051         hc->pcm = pcm[HFC_cnt];
5052         hc->io_mode = iomode[HFC_cnt];
5053         if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5054                 /* fragment card */
5055                 pt = 0;
5056                 maskcheck = 0;
5057                 for (ch = 0; ch <= 31; ch++) {
5058                         if (!((1 << ch) & dmask[E1_cnt]))
5059                                 continue;
5060                         hc->dnum[pt] = ch;
5061                         hc->bmask[pt] = bmask[bmask_cnt++];
5062                         if ((maskcheck & hc->bmask[pt])
5063                          || (dmask[E1_cnt] & hc->bmask[pt])) {
5064                                 printk(KERN_INFO
5065                                        "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5066                                        E1_cnt + 1, pt);
5067                                 kfree(hc);
5068                                 return -EINVAL;
5069                         }
5070                         maskcheck |= hc->bmask[pt];
5071                         printk(KERN_INFO
5072                                "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5073                                 E1_cnt + 1, ch, hc->bmask[pt]);
5074                         pt++;
5075                 }
5076                 hc->ports = pt;
5077         }
5078         if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5079                 /* default card layout */
5080                 hc->dnum[0] = 16;
5081                 hc->bmask[0] = 0xfffefffe;
5082                 hc->ports = 1;
5083         }
5084
5085         /* set chip specific features */
5086         hc->masterclk = -1;
5087         if (type[HFC_cnt] & 0x100) {
5088                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5089                 hc->silence = 0xff; /* ulaw silence */
5090         } else
5091                 hc->silence = 0x2a; /* alaw silence */
5092         if ((poll >> 1) > sizeof(hc->silence_data)) {
5093                 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5094                        "please fix\n");
5095                 kfree(hc);
5096                 return -EINVAL;
5097         }
5098         for (i = 0; i < (poll >> 1); i++)
5099                 hc->silence_data[i] = hc->silence;
5100
5101         if (hc->ctype != HFC_TYPE_XHFC) {
5102                 if (!(type[HFC_cnt] & 0x200))
5103                         test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5104                 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5105         }
5106
5107         if (type[HFC_cnt] & 0x800)
5108                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5109         if (type[HFC_cnt] & 0x1000) {
5110                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5111                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5112         }
5113         if (type[HFC_cnt] & 0x4000)
5114                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5115         if (type[HFC_cnt] & 0x8000)
5116                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5117         hc->slots = 32;
5118         if (type[HFC_cnt] & 0x10000)
5119                 hc->slots = 64;
5120         if (type[HFC_cnt] & 0x20000)
5121                 hc->slots = 128;
5122         if (type[HFC_cnt] & 0x80000) {
5123                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5124                 hc->wdcount = 0;
5125                 hc->wdbyte = V_GPIO_OUT2;
5126                 printk(KERN_NOTICE "Watchdog enabled\n");
5127         }
5128
5129         if (pdev && ent)
5130                 /* setup pci, hc->slots may change due to PLXSD */
5131                 ret_err = setup_pci(hc, pdev, ent);
5132         else
5133 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5134                 ret_err = setup_embedded(hc, m);
5135 #else
5136         {
5137                 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5138                 ret_err = -EIO;
5139         }
5140 #endif
5141         if (ret_err) {
5142                 if (hc == syncmaster)
5143                         syncmaster = NULL;
5144                 kfree(hc);
5145                 return ret_err;
5146         }
5147
5148         hc->HFC_outb_nodebug = hc->HFC_outb;
5149         hc->HFC_inb_nodebug = hc->HFC_inb;
5150         hc->HFC_inw_nodebug = hc->HFC_inw;
5151         hc->HFC_wait_nodebug = hc->HFC_wait;
5152 #ifdef HFC_REGISTER_DEBUG
5153         hc->HFC_outb = HFC_outb_debug;
5154         hc->HFC_inb = HFC_inb_debug;
5155         hc->HFC_inw = HFC_inw_debug;
5156         hc->HFC_wait = HFC_wait_debug;
5157 #endif
5158         /* create channels */
5159         for (pt = 0; pt < hc->ports; pt++) {
5160                 if (Port_cnt >= MAX_PORTS) {
5161                         printk(KERN_ERR "too many ports (max=%d).\n",
5162                                MAX_PORTS);
5163                         ret_err = -EINVAL;
5164                         goto free_card;
5165                 }
5166                 if (hc->ctype == HFC_TYPE_E1)
5167                         ret_err = init_e1_port(hc, m, pt);
5168                 else
5169                         ret_err = init_multi_port(hc, pt);
5170                 if (debug & DEBUG_HFCMULTI_INIT)
5171                         printk(KERN_DEBUG
5172                             "%s: Registering D-channel, card(%d) port(%d) "
5173                                "result %d\n",
5174                             __func__, HFC_cnt + 1, pt + 1, ret_err);
5175
5176                 if (ret_err) {
5177                         while (pt) { /* release already registered ports */
5178                                 pt--;
5179                                 if (hc->ctype == HFC_TYPE_E1)
5180                                         release_port(hc,
5181                                                 hc->chan[hc->dnum[pt]].dch);
5182                                 else
5183                                         release_port(hc,
5184                                                 hc->chan[(pt << 2) + 2].dch);
5185                         }
5186                         goto free_card;
5187                 }
5188                 if (hc->ctype != HFC_TYPE_E1)
5189                         Port_cnt++; /* for each S0 port */
5190         }
5191         if (hc->ctype == HFC_TYPE_E1) {
5192                 Port_cnt++; /* for each E1 port */
5193                 E1_cnt++;
5194         }
5195
5196         /* disp switches */
5197         switch (m->dip_type) {
5198         case DIP_4S:
5199                 /*
5200                  * Get DIP setting for beroNet 1S/2S/4S cards
5201                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5202                  * GPI 19/23 (R_GPI_IN2))
5203                  */
5204                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5205                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5206                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5207
5208                 /* Port mode (TE/NT) jumpers */
5209                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
5210
5211                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5212                         pmj = ~pmj & 0xf;
5213
5214                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5215                        m->vendor_name, m->card_name, dips, pmj);
5216                 break;
5217         case DIP_8S:
5218                 /*
5219                  * Get DIP Setting for beroNet 8S0+ cards
5220                  * Enable PCI auxbridge function
5221                  */
5222                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5223                 /* prepare access to auxport */
5224                 outw(0x4000, hc->pci_iobase + 4);
5225                 /*
5226                  * some dummy reads are required to
5227                  * read valid DIP switch data
5228                  */
5229                 dips = inb(hc->pci_iobase);
5230                 dips = inb(hc->pci_iobase);
5231                 dips = inb(hc->pci_iobase);
5232                 dips = ~inb(hc->pci_iobase) & 0x3F;
5233                 outw(0x0, hc->pci_iobase + 4);
5234                 /* disable PCI auxbridge function */
5235                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5236                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5237                        m->vendor_name, m->card_name, dips);
5238                 break;
5239         case DIP_E1:
5240                 /*
5241                  * get DIP Setting for beroNet E1 cards
5242                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5243                  */
5244                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5245                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5246                        m->vendor_name, m->card_name, dips);
5247                 break;
5248         }
5249
5250         /* add to list */
5251         spin_lock_irqsave(&HFClock, flags);
5252         list_add_tail(&hc->list, &HFClist);
5253         spin_unlock_irqrestore(&HFClock, flags);
5254
5255         /* use as clock source */
5256         if (clock == HFC_cnt + 1)
5257                 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5258
5259         /* initialize hardware */
5260         hc->irq = (m->irq) ? : hc->pci_dev->irq;
5261         ret_err = init_card(hc);
5262         if (ret_err) {
5263                 printk(KERN_ERR "init card returns %d\n", ret_err);
5264                 release_card(hc);
5265                 return ret_err;
5266         }
5267
5268         /* start IRQ and return */
5269         spin_lock_irqsave(&hc->lock, flags);
5270         enable_hwirq(hc);
5271         spin_unlock_irqrestore(&hc->lock, flags);
5272         return 0;
5273
5274 free_card:
5275         release_io_hfcmulti(hc);
5276         if (hc == syncmaster)
5277                 syncmaster = NULL;
5278         kfree(hc);
5279         return ret_err;
5280 }
5281
5282 static void hfc_remove_pci(struct pci_dev *pdev)
5283 {
5284         struct hfc_multi        *card = pci_get_drvdata(pdev);
5285         u_long                  flags;
5286
5287         if (debug)
5288                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5289                        "device:%x subvendor:%x subdevice:%x\n",
5290                        pdev->vendor, pdev->device,
5291                        pdev->subsystem_vendor, pdev->subsystem_device);
5292
5293         if (card) {
5294                 spin_lock_irqsave(&HFClock, flags);
5295                 release_card(card);
5296                 spin_unlock_irqrestore(&HFClock, flags);
5297         }  else {
5298                 if (debug)
5299                         printk(KERN_DEBUG "%s: drvdata already removed\n",
5300                                __func__);
5301         }
5302 }
5303
5304 #define VENDOR_CCD      "Cologne Chip AG"
5305 #define VENDOR_BN       "beroNet GmbH"
5306 #define VENDOR_DIG      "Digium Inc."
5307 #define VENDOR_JH       "Junghanns.NET GmbH"
5308 #define VENDOR_PRIM     "PrimuX"
5309
5310 static const struct hm_map hfcm_map[] = {
5311         /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5312         /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5313         /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5314         /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5315         /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5316         /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5317         /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5318         /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5319         /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5320         /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5321         /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5322         /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5323
5324         /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5325         /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5326                  HFC_IO_MODE_REGIO, 0},
5327         /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5328         /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5329
5330         /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5331         /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5332         /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5333
5334         /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5335         /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5336         /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5337         /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5338
5339         /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5340         /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5341         /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5342
5343         /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5344                  HFC_IO_MODE_PLXSD, 0},
5345         /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5346                  HFC_IO_MODE_PLXSD, 0},
5347         /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5348         /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5349         /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5350         /*31*/  {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5351                  HFC_IO_MODE_EMBSD, XHFC_IRQ},
5352         /*32*/  {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5353         /*33*/  {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5354         /*34*/  {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5355 };
5356
5357 #undef H
5358 #define H(x)    ((unsigned long)&hfcm_map[x])
5359 static const struct pci_device_id hfmultipci_ids[] = {
5360
5361         /* Cards with HFC-4S Chip */
5362         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5363           PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5364         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5365           PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5366         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5367           PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5368         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5369           PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5370         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5371           PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5372         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5373           PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5374         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5375           PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5376         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5377           PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5378         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5379           PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5380         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5381           PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5382         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5383           PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5384         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5385           PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5386         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5387           PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5388         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5389           PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5390         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5391           0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5392         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5393           0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5394
5395         /* Cards with HFC-8S Chip */
5396         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5397           PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5398         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5399           PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5400         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5401           PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5402         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5403           PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5404         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5405           PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5406         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5407           PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5408         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5409           PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5410         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5411           PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5412         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5413           PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S  */
5414
5415
5416         /* Cards with HFC-E1 Chip */
5417         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5418           PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5419         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5420           PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5421         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5422           PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5423         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5424           PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5425
5426         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5427           PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5428         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5429           PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5430         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5431           PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5432
5433         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5434           PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5435         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5436           PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5437
5438         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5439           PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5440
5441         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5442         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5443         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5444         {0, }
5445 };
5446 #undef H
5447
5448 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5449
5450 static int
5451 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5452 {
5453         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5454         int             ret;
5455
5456         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5457                     ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5458                     ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5459                     ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5460                 printk(KERN_ERR
5461                        "Unknown HFC multiport controller (vendor:%04x device:%04x "
5462                        "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5463                        pdev->device, pdev->subsystem_vendor,
5464                        pdev->subsystem_device);
5465                 printk(KERN_ERR
5466                        "Please contact the driver maintainer for support.\n");
5467                 return -ENODEV;
5468         }
5469         ret = hfcmulti_init(m, pdev, ent);
5470         if (ret)
5471                 return ret;
5472         HFC_cnt++;
5473         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5474         return 0;
5475 }
5476
5477 static struct pci_driver hfcmultipci_driver = {
5478         .name           = "hfc_multi",
5479         .probe          = hfcmulti_probe,
5480         .remove         = hfc_remove_pci,
5481         .id_table       = hfmultipci_ids,
5482 };
5483
5484 static void __exit
5485 HFCmulti_cleanup(void)
5486 {
5487         struct hfc_multi *card, *next;
5488
5489         /* get rid of all devices of this driver */
5490         list_for_each_entry_safe(card, next, &HFClist, list)
5491                 release_card(card);
5492         pci_unregister_driver(&hfcmultipci_driver);
5493 }
5494
5495 static int __init
5496 HFCmulti_init(void)
5497 {
5498         int err;
5499         int i, xhfc = 0;
5500         struct hm_map m;
5501
5502         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5503
5504 #ifdef IRQ_DEBUG
5505         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5506 #endif
5507
5508         spin_lock_init(&HFClock);
5509         spin_lock_init(&plx_lock);
5510
5511         if (debug & DEBUG_HFCMULTI_INIT)
5512                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5513
5514         switch (poll) {
5515         case 0:
5516                 poll_timer = 6;
5517                 poll = 128;
5518                 break;
5519         case 8:
5520                 poll_timer = 2;
5521                 break;
5522         case 16:
5523                 poll_timer = 3;
5524                 break;
5525         case 32:
5526                 poll_timer = 4;
5527                 break;
5528         case 64:
5529                 poll_timer = 5;
5530                 break;
5531         case 128:
5532                 poll_timer = 6;
5533                 break;
5534         case 256:
5535                 poll_timer = 7;
5536                 break;
5537         default:
5538                 printk(KERN_ERR
5539                        "%s: Wrong poll value (%d).\n", __func__, poll);
5540                 err = -EINVAL;
5541                 return err;
5542
5543         }
5544
5545         if (!clock)
5546                 clock = 1;
5547
5548         /* Register the embedded devices.
5549          * This should be done before the PCI cards registration */
5550         switch (hwid) {
5551         case HWID_MINIP4:
5552                 xhfc = 1;
5553                 m = hfcm_map[31];
5554                 break;
5555         case HWID_MINIP8:
5556                 xhfc = 2;
5557                 m = hfcm_map[31];
5558                 break;
5559         case HWID_MINIP16:
5560                 xhfc = 4;
5561                 m = hfcm_map[31];
5562                 break;
5563         default:
5564                 xhfc = 0;
5565         }
5566
5567         for (i = 0; i < xhfc; ++i) {
5568                 err = hfcmulti_init(&m, NULL, NULL);
5569                 if (err) {
5570                         printk(KERN_ERR "error registering embedded driver: "
5571                                "%x\n", err);
5572                         return err;
5573                 }
5574                 HFC_cnt++;
5575                 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5576         }
5577
5578         /* Register the PCI cards */
5579         err = pci_register_driver(&hfcmultipci_driver);
5580         if (err < 0) {
5581                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5582                 return err;
5583         }
5584
5585         return 0;
5586 }
5587
5588
5589 module_init(HFCmulti_init);
5590 module_exit(HFCmulti_cleanup);