2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Thanks to Cologne Chip AG for this great controller!
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
80 * (all other bits are reserved and shall be 0)
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
107 * NOTE: One dmask value must be given for every HFC-E1 card.
108 * If omitted, the E1 card has D-channel on time slot 16, which is default.
109 * dmask is a 32 bit mask. The bit must be set for an alternate time slot.
110 * If multiple bits are set, multiple virtual card fragments are created.
111 * For each bit set, a bmask value must be given. Each bit on the bmask
112 * value stands for a B-channel. The bmask may not overlap with dmask or
113 * with other bmask values for that card.
114 * Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
115 * This will create one fragment with D-channel on slot 1 with
116 * B-channels on slots 2..15, and a second fragment with D-channel
117 * on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
118 * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
120 * Example: dmask=0x00000001 bmask=0xfffffffe
121 * This will create a port with all 31 usable timeslots as
123 * If no bits are set on bmask, no B-channel is created for that fragment.
124 * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
125 * This will create 31 ports with one D-channel only.
126 * If you don't know how to use it, you don't need it!
129 * NOTE: only one mode value must be given for every card.
130 * -> See hfc_multi.h for HFC_IO_MODE_* values
131 * By default, the IO mode is pci memory IO (MEMIO).
132 * Some cards require specific IO mode, so it cannot be changed.
133 * It may be useful to set IO mode to register io (REGIO) to solve
134 * PCI bridge problems.
135 * If unsure, don't give this parameter.
138 * NOTE: only one clockdelay_nt value must be given once for all cards.
139 * Give the value of the clock control register (A_ST_CLK_DLY)
140 * of the S/T interfaces in NT mode.
141 * This register is needed for the TBR3 certification, so don't change it.
144 * NOTE: only one clockdelay_te value must be given once
145 * Give the value of the clock control register (A_ST_CLK_DLY)
146 * of the S/T interfaces in TE mode.
147 * This register is needed for the TBR3 certification, so don't change it.
150 * NOTE: only one clock value must be given once
151 * Selects interface with clock source for mISDN and applications.
152 * Set to card number starting with 1. Set to -1 to disable.
153 * By default, the first card is used as clock source.
156 * NOTE: only one hwid value must be given once
157 * Enable special embedded devices with XHFC controllers.
161 * debug register access (never use this, it will flood your system log)
162 * #define HFC_REGISTER_DEBUG
165 #define HFC_MULTI_VERSION "2.03"
167 #include <linux/interrupt.h>
168 #include <linux/module.h>
169 #include <linux/slab.h>
170 #include <linux/pci.h>
171 #include <linux/delay.h>
172 #include <linux/mISDNhw.h>
173 #include <linux/mISDNdsp.h>
176 #define IRQCOUNT_DEBUG
180 #include "hfc_multi.h"
186 #define MAX_PORTS (8 * MAX_CARDS)
187 #define MAX_FRAGS (32 * MAX_CARDS)
189 static LIST_HEAD(HFClist);
190 static spinlock_t HFClock; /* global hfc list lock */
192 static void ph_state_change(struct dchannel *);
194 static struct hfc_multi *syncmaster;
195 static int plxsd_master; /* if we have a master card (yet) */
196 static spinlock_t plx_lock; /* may not acquire other lock inside */
202 static int poll_timer = 6; /* default = 128 samples = 16ms */
203 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
204 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
205 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
206 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
207 (0x60 MUST be included!) */
209 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
210 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
211 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
217 static uint type[MAX_CARDS];
218 static int pcm[MAX_CARDS];
219 static uint dmask[MAX_CARDS];
220 static uint bmask[MAX_FRAGS];
221 static uint iomode[MAX_CARDS];
222 static uint port[MAX_PORTS];
227 static uint clockdelay_te = CLKDEL_TE;
228 static uint clockdelay_nt = CLKDEL_NT;
230 #define HWID_MINIP4 1
231 #define HWID_MINIP8 2
232 #define HWID_MINIP16 3
233 static uint hwid = HWID_NONE;
235 static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
237 MODULE_AUTHOR("Andreas Eversberg");
238 MODULE_LICENSE("GPL");
239 MODULE_VERSION(HFC_MULTI_VERSION);
240 module_param(debug, uint, S_IRUGO | S_IWUSR);
241 module_param(poll, uint, S_IRUGO | S_IWUSR);
242 module_param(clock, int, S_IRUGO | S_IWUSR);
243 module_param(timer, uint, S_IRUGO | S_IWUSR);
244 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
245 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
246 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
247 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
248 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
249 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
250 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
251 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
252 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
254 #ifdef HFC_REGISTER_DEBUG
255 #define HFC_outb(hc, reg, val) \
256 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
257 #define HFC_outb_nodebug(hc, reg, val) \
258 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
259 #define HFC_inb(hc, reg) \
260 (hc->HFC_inb(hc, reg, __func__, __LINE__))
261 #define HFC_inb_nodebug(hc, reg) \
262 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
263 #define HFC_inw(hc, reg) \
264 (hc->HFC_inw(hc, reg, __func__, __LINE__))
265 #define HFC_inw_nodebug(hc, reg) \
266 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
267 #define HFC_wait(hc) \
268 (hc->HFC_wait(hc, __func__, __LINE__))
269 #define HFC_wait_nodebug(hc) \
270 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
272 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
273 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
274 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
275 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
276 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
277 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
278 #define HFC_wait(hc) (hc->HFC_wait(hc))
279 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
282 #ifdef CONFIG_MISDN_HFCMULTI_8xx
283 #include "hfc_multi_8xx.h"
286 /* HFC_IO_MODE_PCIMEM */
288 #ifdef HFC_REGISTER_DEBUG
289 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
290 const char *function, int line)
292 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
295 writeb(val, hc->pci_membase + reg);
298 #ifdef HFC_REGISTER_DEBUG
299 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
301 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
304 return readb(hc->pci_membase + reg);
307 #ifdef HFC_REGISTER_DEBUG
308 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
310 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
313 return readw(hc->pci_membase + reg);
316 #ifdef HFC_REGISTER_DEBUG
317 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
319 HFC_wait_pcimem(struct hfc_multi *hc)
322 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
326 /* HFC_IO_MODE_REGIO */
328 #ifdef HFC_REGISTER_DEBUG
329 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
330 const char *function, int line)
332 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
335 outb(reg, hc->pci_iobase + 4);
336 outb(val, hc->pci_iobase);
339 #ifdef HFC_REGISTER_DEBUG
340 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
342 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
345 outb(reg, hc->pci_iobase + 4);
346 return inb(hc->pci_iobase);
349 #ifdef HFC_REGISTER_DEBUG
350 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
352 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
355 outb(reg, hc->pci_iobase + 4);
356 return inw(hc->pci_iobase);
359 #ifdef HFC_REGISTER_DEBUG
360 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
362 HFC_wait_regio(struct hfc_multi *hc)
365 outb(R_STATUS, hc->pci_iobase + 4);
366 while (inb(hc->pci_iobase) & V_BUSY)
370 #ifdef HFC_REGISTER_DEBUG
372 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
373 const char *function, int line)
375 char regname[256] = "", bits[9] = "xxxxxxxx";
379 while (hfc_register_names[++i].name) {
380 if (hfc_register_names[i].reg == reg)
381 strcat(regname, hfc_register_names[i].name);
383 if (regname[0] == '\0')
384 strcpy(regname, "register");
386 bits[7] = '0' + (!!(val & 1));
387 bits[6] = '0' + (!!(val & 2));
388 bits[5] = '0' + (!!(val & 4));
389 bits[4] = '0' + (!!(val & 8));
390 bits[3] = '0' + (!!(val & 16));
391 bits[2] = '0' + (!!(val & 32));
392 bits[1] = '0' + (!!(val & 64));
393 bits[0] = '0' + (!!(val & 128));
395 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
396 hc->id, reg, regname, val, bits, function, line);
397 HFC_outb_nodebug(hc, reg, val);
400 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
402 char regname[256] = "", bits[9] = "xxxxxxxx";
403 u_char val = HFC_inb_nodebug(hc, reg);
407 while (hfc_register_names[i++].name)
409 while (hfc_register_names[++i].name) {
410 if (hfc_register_names[i].reg == reg)
411 strcat(regname, hfc_register_names[i].name);
413 if (regname[0] == '\0')
414 strcpy(regname, "register");
416 bits[7] = '0' + (!!(val & 1));
417 bits[6] = '0' + (!!(val & 2));
418 bits[5] = '0' + (!!(val & 4));
419 bits[4] = '0' + (!!(val & 8));
420 bits[3] = '0' + (!!(val & 16));
421 bits[2] = '0' + (!!(val & 32));
422 bits[1] = '0' + (!!(val & 64));
423 bits[0] = '0' + (!!(val & 128));
425 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
426 hc->id, reg, regname, val, bits, function, line);
430 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
432 char regname[256] = "";
433 u_short val = HFC_inw_nodebug(hc, reg);
437 while (hfc_register_names[i++].name)
439 while (hfc_register_names[++i].name) {
440 if (hfc_register_names[i].reg == reg)
441 strcat(regname, hfc_register_names[i].name);
443 if (regname[0] == '\0')
444 strcpy(regname, "register");
447 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
448 hc->id, reg, regname, val, function, line);
452 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
454 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
455 hc->id, function, line);
456 HFC_wait_nodebug(hc);
460 /* write fifo data (REGIO) */
462 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
464 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
466 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
471 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
476 outb(*data, hc->pci_iobase);
481 /* write fifo data (PCIMEM) */
483 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
486 writel(cpu_to_le32(*(u32 *)data),
487 hc->pci_membase + A_FIFO_DATA0);
492 writew(cpu_to_le16(*(u16 *)data),
493 hc->pci_membase + A_FIFO_DATA0);
498 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
504 /* read fifo data (REGIO) */
506 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
508 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
510 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
515 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
520 *data = inb(hc->pci_iobase);
526 /* read fifo data (PCIMEM) */
528 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
532 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
538 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
543 *data = readb(hc->pci_membase + A_FIFO_DATA0);
550 enable_hwirq(struct hfc_multi *hc)
552 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
553 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
557 disable_hwirq(struct hfc_multi *hc)
559 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
560 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
564 #define MAX_TDM_CHAN 32
568 enablepcibridge(struct hfc_multi *c)
570 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
574 disablepcibridge(struct hfc_multi *c)
576 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
579 static inline unsigned char
580 readpcibridge(struct hfc_multi *hc, unsigned char address)
588 /* slow down a PCI read access by 1 PCI clock cycle */
589 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
596 /* select local bridge port address by writing to CIP port */
597 /* data = HFC_inb(c, cipv); * was _io before */
598 outw(cipv, hc->pci_iobase + 4);
599 data = inb(hc->pci_iobase);
601 /* restore R_CTRL for normal PCI read cycle speed */
602 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
608 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
621 /* select local bridge port address by writing to CIP port */
622 outw(cipv, hc->pci_iobase + 4);
623 /* define a 32 bit dword with 4 identical bytes for write sequence */
624 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
625 ((__u32) data << 24);
628 * write this 32 bit dword to the bridge data port
629 * this will initiate a write sequence of up to 4 writes to the same
630 * address on the local bus interface the number of write accesses
631 * is undefined but >=1 and depends on the next PCI transaction
632 * during write sequence on the local bus
634 outl(datav, hc->pci_iobase);
638 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
640 /* Do data pin read low byte */
641 HFC_outb(hc, R_GPIO_OUT1, reg);
645 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
647 cpld_set_reg(hc, reg);
650 writepcibridge(hc, 1, val);
651 disablepcibridge(hc);
656 static inline unsigned char
657 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
659 unsigned char bytein;
661 cpld_set_reg(hc, reg);
663 /* Do data pin read low byte */
664 HFC_outb(hc, R_GPIO_OUT1, reg);
667 bytein = readpcibridge(hc, 1);
668 disablepcibridge(hc);
674 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
676 cpld_write_reg(hc, 0, 0xff & addr);
677 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
680 static inline unsigned short
681 vpm_read_address(struct hfc_multi *c)
684 unsigned short highbit;
686 addr = cpld_read_reg(c, 0);
687 highbit = cpld_read_reg(c, 1);
689 addr = addr | (highbit << 8);
694 static inline unsigned char
695 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
699 vpm_write_address(c, addr);
707 res = readpcibridge(c, 1);
716 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
719 vpm_write_address(c, addr);
728 writepcibridge(c, 1, data);
736 regin = vpm_in(c, which, addr);
738 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
739 "0x%x\n", data, addr, regin);
746 vpm_init(struct hfc_multi *wc)
750 unsigned int i, x, y;
753 for (x = 0; x < NUM_EC; x++) {
756 ver = vpm_in(wc, x, 0x1a0);
757 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
760 for (y = 0; y < 4; y++) {
761 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
762 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
763 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
766 /* Setup TDM path - sets fsync and tdm_clk as inputs */
767 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
768 vpm_out(wc, x, 0x1a3, reg & ~2);
770 /* Setup Echo length (256 taps) */
771 vpm_out(wc, x, 0x022, 1);
772 vpm_out(wc, x, 0x023, 0xff);
774 /* Setup timeslots */
775 vpm_out(wc, x, 0x02f, 0x00);
776 mask = 0x02020202 << (x * 4);
778 /* Setup the tdm channel masks for all chips */
779 for (i = 0; i < 4; i++)
780 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
782 /* Setup convergence rate */
783 printk(KERN_DEBUG "VPM: A-law mode\n");
784 reg = 0x00 | 0x10 | 0x01;
785 vpm_out(wc, x, 0x20, reg);
786 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
787 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
789 vpm_out(wc, x, 0x24, 0x02);
790 reg = vpm_in(wc, x, 0x24);
791 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
793 /* Initialize echo cans */
794 for (i = 0; i < MAX_TDM_CHAN; i++) {
795 if (mask & (0x00000001 << i))
796 vpm_out(wc, x, i, 0x00);
800 * ARM arch at least disallows a udelay of
801 * more than 2ms... it gives a fake "__bad_udelay"
802 * reference at link-time.
803 * long delays in kernel code are pretty sucky anyway
804 * for now work around it using 5 x 2ms instead of 1 x 10ms
813 /* Put in bypass mode */
814 for (i = 0; i < MAX_TDM_CHAN; i++) {
815 if (mask & (0x00000001 << i))
816 vpm_out(wc, x, i, 0x01);
820 for (i = 0; i < MAX_TDM_CHAN; i++) {
821 if (mask & (0x00000001 << i))
822 vpm_out(wc, x, 0x78 + i, 0x01);
830 vpm_check(struct hfc_multi *hctmp)
834 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
836 if ((gpi2 & 0x3) != 0x3)
837 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
843 * Interface to enable/disable the HW Echocan
845 * these functions are called within a spin_lock_irqsave on
846 * the channel instance lock, so we are not disturbed by irqs
848 * we can later easily change the interface to make other
849 * things configurable, for now we configure the taps
854 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
856 unsigned int timeslot;
858 struct bchannel *bch = hc->chan[ch].bch;
863 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
870 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
871 sizeof(int), &txadj, GFP_ATOMIC);
873 recv_Bchannel_skb(bch, skb);
876 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
879 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
882 vpm_out(hc, unit, timeslot, 0x7e);
886 vpm_echocan_off(struct hfc_multi *hc, int ch)
888 unsigned int timeslot;
890 struct bchannel *bch = hc->chan[ch].bch;
896 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
903 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
904 sizeof(int), &txadj, GFP_ATOMIC);
906 recv_Bchannel_skb(bch, skb);
909 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
912 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
915 vpm_out(hc, unit, timeslot, 0x01);
920 * Speech Design resync feature
921 * NOTE: This is called sometimes outside interrupt handler.
922 * We must lock irqsave, so no other interrupt (other card) will occur!
923 * Also multiple interrupts may nest, so must lock each access (lists, card)!
926 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
928 struct hfc_multi *hc, *next, *pcmmaster = NULL;
929 void __iomem *plx_acc_32;
933 spin_lock_irqsave(&HFClock, flags);
934 spin_lock(&plx_lock); /* must be locked inside other locks */
936 if (debug & DEBUG_HFCMULTI_PLXSD)
937 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
938 __func__, syncmaster);
940 /* select new master */
942 if (debug & DEBUG_HFCMULTI_PLXSD)
943 printk(KERN_DEBUG "using provided controller\n");
945 list_for_each_entry_safe(hc, next, &HFClist, list) {
946 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
947 if (hc->syncronized) {
955 /* Disable sync of all cards */
956 list_for_each_entry_safe(hc, next, &HFClist, list) {
957 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
958 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
959 pv = readl(plx_acc_32);
960 pv &= ~PLX_SYNC_O_EN;
961 writel(pv, plx_acc_32);
962 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
964 if (hc->ctype == HFC_TYPE_E1) {
965 if (debug & DEBUG_HFCMULTI_PLXSD)
967 "Schedule SYNC_I\n");
968 hc->e1_resync |= 1; /* get SYNC_I */
976 if (debug & DEBUG_HFCMULTI_PLXSD)
977 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
978 "interface.\n", hc->id, hc);
979 /* Enable new sync master */
980 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
981 pv = readl(plx_acc_32);
983 writel(pv, plx_acc_32);
984 /* switch to jatt PLL, if not disabled by RX_SYNC */
985 if (hc->ctype == HFC_TYPE_E1
986 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
987 if (debug & DEBUG_HFCMULTI_PLXSD)
988 printk(KERN_DEBUG "Schedule jatt PLL\n");
989 hc->e1_resync |= 2; /* switch to jatt */
994 if (debug & DEBUG_HFCMULTI_PLXSD)
996 "id=%d (0x%p) = PCM master syncronized "
997 "with QUARTZ\n", hc->id, hc);
998 if (hc->ctype == HFC_TYPE_E1) {
999 /* Use the crystal clock for the PCM
1001 if (debug & DEBUG_HFCMULTI_PLXSD)
1003 "Schedule QUARTZ for HFC-E1\n");
1004 hc->e1_resync |= 4; /* switch quartz */
1006 if (debug & DEBUG_HFCMULTI_PLXSD)
1008 "QUARTZ is automatically "
1009 "enabled by HFC-%dS\n", hc->ctype);
1011 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1012 pv = readl(plx_acc_32);
1013 pv |= PLX_SYNC_O_EN;
1014 writel(pv, plx_acc_32);
1017 printk(KERN_ERR "%s no pcm master, this MUST "
1018 "not happen!\n", __func__);
1020 syncmaster = newmaster;
1022 spin_unlock(&plx_lock);
1023 spin_unlock_irqrestore(&HFClock, flags);
1026 /* This must be called AND hc must be locked irqsave!!! */
1028 plxsd_checksync(struct hfc_multi *hc, int rm)
1030 if (hc->syncronized) {
1031 if (syncmaster == NULL) {
1032 if (debug & DEBUG_HFCMULTI_PLXSD)
1033 printk(KERN_DEBUG "%s: GOT sync on card %d"
1034 " (id=%d)\n", __func__, hc->id + 1,
1036 hfcmulti_resync(hc, hc, rm);
1039 if (syncmaster == hc) {
1040 if (debug & DEBUG_HFCMULTI_PLXSD)
1041 printk(KERN_DEBUG "%s: LOST sync on card %d"
1042 " (id=%d)\n", __func__, hc->id + 1,
1044 hfcmulti_resync(hc, NULL, rm);
1051 * free hardware resources used by driver
1054 release_io_hfcmulti(struct hfc_multi *hc)
1056 void __iomem *plx_acc_32;
1060 if (debug & DEBUG_HFCMULTI_INIT)
1061 printk(KERN_DEBUG "%s: entered\n", __func__);
1063 /* soft reset also masks all interrupts */
1064 hc->hw.r_cirm |= V_SRES;
1065 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1067 hc->hw.r_cirm &= ~V_SRES;
1068 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1069 udelay(1000); /* instead of 'wait' that may cause locking */
1071 /* release Speech Design card, if PLX was initialized */
1072 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1073 if (debug & DEBUG_HFCMULTI_PLXSD)
1074 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1075 __func__, hc->id + 1);
1076 spin_lock_irqsave(&plx_lock, plx_flags);
1077 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1078 writel(PLX_GPIOC_INIT, plx_acc_32);
1079 pv = readl(plx_acc_32);
1080 /* Termination off */
1082 /* Disconnect the PCM */
1083 pv |= PLX_SLAVE_EN_N;
1084 pv &= ~PLX_MASTER_EN;
1085 pv &= ~PLX_SYNC_O_EN;
1086 /* Put the DSP in Reset */
1087 pv &= ~PLX_DSP_RES_N;
1088 writel(pv, plx_acc_32);
1089 if (debug & DEBUG_HFCMULTI_INIT)
1090 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1092 spin_unlock_irqrestore(&plx_lock, plx_flags);
1095 /* disable memory mapped ports / io ports */
1096 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1098 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1099 if (hc->pci_membase)
1100 iounmap(hc->pci_membase);
1101 if (hc->plx_membase)
1102 iounmap(hc->plx_membase);
1104 release_region(hc->pci_iobase, 8);
1105 if (hc->xhfc_membase)
1106 iounmap((void *)hc->xhfc_membase);
1109 pci_disable_device(hc->pci_dev);
1110 pci_set_drvdata(hc->pci_dev, NULL);
1112 if (debug & DEBUG_HFCMULTI_INIT)
1113 printk(KERN_DEBUG "%s: done\n", __func__);
1117 * function called to reset the HFC chip. A complete software reset of chip
1118 * and fifos is done. All configuration of the chip is done.
1122 init_chip(struct hfc_multi *hc)
1124 u_long flags, val, val2 = 0, rev;
1126 u_char r_conf_en, rval;
1127 void __iomem *plx_acc_32;
1129 u_long plx_flags, hfc_flags;
1131 struct hfc_multi *pos, *next, *plx_last_hc;
1133 spin_lock_irqsave(&hc->lock, flags);
1134 /* reset all registers */
1135 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1137 /* revision check */
1138 if (debug & DEBUG_HFCMULTI_INIT)
1139 printk(KERN_DEBUG "%s: entered\n", __func__);
1140 val = HFC_inb(hc, R_CHIP_ID);
1141 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1142 (val >> 1) != 0x31) {
1143 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1147 rev = HFC_inb(hc, R_CHIP_RV);
1149 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1150 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1151 " (old FIFO handling)" : "");
1152 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1153 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1155 "HFC_multi: NOTE: Your chip is revision 0, "
1156 "ask Cologne Chip for update. Newer chips "
1157 "have a better FIFO handling. Old chips "
1158 "still work but may have slightly lower "
1159 "HDLC transmit performance.\n");
1162 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1163 "consider chip revision = %ld. The chip / "
1164 "bridge may not work.\n", rev);
1167 /* set s-ram size */
1171 hc->DTMFbase = 0x1000;
1172 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1173 if (debug & DEBUG_HFCMULTI_INIT)
1174 printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
1176 hc->hw.r_ctrl |= V_EXT_RAM;
1177 hc->hw.r_ram_sz = 1;
1181 hc->DTMFbase = 0x2000;
1183 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1184 if (debug & DEBUG_HFCMULTI_INIT)
1185 printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
1187 hc->hw.r_ctrl |= V_EXT_RAM;
1188 hc->hw.r_ram_sz = 2;
1192 hc->DTMFbase = 0x2000;
1194 if (hc->ctype == HFC_TYPE_XHFC) {
1200 hc->max_trans = poll << 1;
1201 if (hc->max_trans > hc->Zlen)
1202 hc->max_trans = hc->Zlen;
1204 /* Speech Design PLX bridge */
1205 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1206 if (debug & DEBUG_HFCMULTI_PLXSD)
1207 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1208 __func__, hc->id + 1);
1209 spin_lock_irqsave(&plx_lock, plx_flags);
1210 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1211 writel(PLX_GPIOC_INIT, plx_acc_32);
1212 pv = readl(plx_acc_32);
1213 /* The first and the last cards are terminating the PCM bus */
1214 pv |= PLX_TERM_ON; /* hc is currently the last */
1215 /* Disconnect the PCM */
1216 pv |= PLX_SLAVE_EN_N;
1217 pv &= ~PLX_MASTER_EN;
1218 pv &= ~PLX_SYNC_O_EN;
1219 /* Put the DSP in Reset */
1220 pv &= ~PLX_DSP_RES_N;
1221 writel(pv, plx_acc_32);
1222 spin_unlock_irqrestore(&plx_lock, plx_flags);
1223 if (debug & DEBUG_HFCMULTI_INIT)
1224 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1227 * If we are the 3rd PLXSD card or higher, we must turn
1228 * termination of last PLXSD card off.
1230 spin_lock_irqsave(&HFClock, hfc_flags);
1233 list_for_each_entry_safe(pos, next, &HFClist, list) {
1234 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1240 if (plx_count >= 3) {
1241 if (debug & DEBUG_HFCMULTI_PLXSD)
1242 printk(KERN_DEBUG "%s: card %d is between, so "
1243 "we disable termination\n",
1244 __func__, plx_last_hc->id + 1);
1245 spin_lock_irqsave(&plx_lock, plx_flags);
1246 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1247 pv = readl(plx_acc_32);
1249 writel(pv, plx_acc_32);
1250 spin_unlock_irqrestore(&plx_lock, plx_flags);
1251 if (debug & DEBUG_HFCMULTI_INIT)
1253 "%s: term off: PLX_GPIO=%x\n",
1256 spin_unlock_irqrestore(&HFClock, hfc_flags);
1257 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1260 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1261 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1263 /* we only want the real Z2 read-pointer for revision > 0 */
1264 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1265 hc->hw.r_ram_sz |= V_FZ_MD;
1267 /* select pcm mode */
1268 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1269 if (debug & DEBUG_HFCMULTI_INIT)
1270 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1273 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1274 if (debug & DEBUG_HFCMULTI_INIT)
1275 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1277 hc->hw.r_pcm_md0 |= V_PCM_MD;
1279 if (debug & DEBUG_HFCMULTI_INIT)
1280 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1285 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1286 if (hc->ctype == HFC_TYPE_XHFC)
1287 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1288 0x11 /* 16 Bytes TX/RX */);
1290 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1291 HFC_outb(hc, R_FIFO_MD, 0);
1292 if (hc->ctype == HFC_TYPE_XHFC)
1293 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1295 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1297 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1300 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1302 if (hc->ctype != HFC_TYPE_XHFC)
1303 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1305 /* Speech Design PLX bridge pcm and sync mode */
1306 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1307 spin_lock_irqsave(&plx_lock, plx_flags);
1308 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1309 pv = readl(plx_acc_32);
1311 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1312 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1313 pv |= PLX_SYNC_O_EN;
1314 if (debug & DEBUG_HFCMULTI_INIT)
1315 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1318 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1319 pv &= ~PLX_SYNC_O_EN;
1320 if (debug & DEBUG_HFCMULTI_INIT)
1321 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1324 writel(pv, plx_acc_32);
1325 spin_unlock_irqrestore(&plx_lock, plx_flags);
1329 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1330 if (hc->slots == 32)
1331 HFC_outb(hc, R_PCM_MD1, 0x00);
1332 if (hc->slots == 64)
1333 HFC_outb(hc, R_PCM_MD1, 0x10);
1334 if (hc->slots == 128)
1335 HFC_outb(hc, R_PCM_MD1, 0x20);
1336 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1337 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1338 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1339 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1340 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1342 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1343 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1344 for (i = 0; i < 256; i++) {
1345 HFC_outb_nodebug(hc, R_SLOT, i);
1346 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1347 if (hc->ctype != HFC_TYPE_XHFC)
1348 HFC_outb_nodebug(hc, A_CONF, 0);
1349 hc->slot_owner[i] = -1;
1352 /* set clock speed */
1353 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1354 if (debug & DEBUG_HFCMULTI_INIT)
1356 "%s: setting double clock\n", __func__);
1357 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1360 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1361 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1364 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1365 printk(KERN_NOTICE "Setting GPIOs\n");
1366 HFC_outb(hc, R_GPIO_SEL, 0x30);
1367 HFC_outb(hc, R_GPIO_EN1, 0x3);
1369 printk(KERN_NOTICE "calling vpm_init\n");
1373 /* check if R_F0_CNT counts (8 kHz frame count) */
1374 val = HFC_inb(hc, R_F0_CNTL);
1375 val += HFC_inb(hc, R_F0_CNTH) << 8;
1376 if (debug & DEBUG_HFCMULTI_INIT)
1378 "HFC_multi F0_CNT %ld after reset\n", val);
1379 spin_unlock_irqrestore(&hc->lock, flags);
1380 set_current_state(TASK_UNINTERRUPTIBLE);
1381 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1382 spin_lock_irqsave(&hc->lock, flags);
1383 val2 = HFC_inb(hc, R_F0_CNTL);
1384 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1385 if (debug & DEBUG_HFCMULTI_INIT)
1387 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1389 if (val2 >= val + 8) { /* 1 ms */
1390 /* it counts, so we keep the pcm mode */
1391 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1392 printk(KERN_INFO "controller is PCM bus MASTER\n");
1394 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1395 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1397 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1398 printk(KERN_INFO "controller is PCM bus SLAVE "
1399 "(auto detected)\n");
1402 /* does not count */
1403 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1405 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1406 "pulse. Seems that controller fails.\n");
1410 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1411 printk(KERN_INFO "controller is PCM bus SLAVE "
1412 "(ignoring missing PCM clock)\n");
1414 /* only one pcm master */
1415 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1417 printk(KERN_ERR "HFC_multi ERROR, no clock "
1418 "on another Speech Design card found. "
1419 "Please be sure to connect PCM cable.\n");
1423 /* retry with master clock */
1424 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1425 spin_lock_irqsave(&plx_lock, plx_flags);
1426 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1427 pv = readl(plx_acc_32);
1428 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1429 pv |= PLX_SYNC_O_EN;
1430 writel(pv, plx_acc_32);
1431 spin_unlock_irqrestore(&plx_lock, plx_flags);
1432 if (debug & DEBUG_HFCMULTI_INIT)
1433 printk(KERN_DEBUG "%s: master: "
1434 "PLX_GPIO=%x\n", __func__, pv);
1436 hc->hw.r_pcm_md0 |= V_PCM_MD;
1437 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1438 spin_unlock_irqrestore(&hc->lock, flags);
1439 set_current_state(TASK_UNINTERRUPTIBLE);
1440 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1441 spin_lock_irqsave(&hc->lock, flags);
1442 val2 = HFC_inb(hc, R_F0_CNTL);
1443 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1444 if (debug & DEBUG_HFCMULTI_INIT)
1445 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1446 "10 ms (2nd try)\n", val2);
1447 if (val2 >= val + 8) { /* 1 ms */
1448 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1450 printk(KERN_INFO "controller is PCM bus MASTER "
1451 "(auto detected)\n");
1453 goto controller_fail;
1457 /* Release the DSP Reset */
1458 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1459 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1461 spin_lock_irqsave(&plx_lock, plx_flags);
1462 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1463 pv = readl(plx_acc_32);
1464 pv |= PLX_DSP_RES_N;
1465 writel(pv, plx_acc_32);
1466 spin_unlock_irqrestore(&plx_lock, plx_flags);
1467 if (debug & DEBUG_HFCMULTI_INIT)
1468 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1474 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1477 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1478 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1479 PCM_cnt++; /* SD has proprietary bridging */
1482 printk(KERN_INFO "controller has PCM BUS ID %d "
1483 "(auto selected)\n", hc->pcm);
1487 HFC_outb(hc, R_TI_WD, poll_timer);
1488 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1490 /* set E1 state machine IRQ */
1491 if (hc->ctype == HFC_TYPE_E1)
1492 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1494 /* set DTMF detection */
1495 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1496 if (debug & DEBUG_HFCMULTI_INIT)
1497 printk(KERN_DEBUG "%s: enabling DTMF detection "
1498 "for all B-channel\n", __func__);
1499 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1500 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1501 hc->hw.r_dtmf |= V_ULAW_SEL;
1502 HFC_outb(hc, R_DTMF_N, 102 - 1);
1503 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1506 /* conference engine */
1507 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1508 r_conf_en = V_CONF_EN | V_ULAW;
1510 r_conf_en = V_CONF_EN;
1511 if (hc->ctype != HFC_TYPE_XHFC)
1512 HFC_outb(hc, R_CONF_EN, r_conf_en);
1516 case 1: /* HFC-E1 OEM */
1517 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1518 HFC_outb(hc, R_GPIO_SEL, 0x32);
1520 HFC_outb(hc, R_GPIO_SEL, 0x30);
1522 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1523 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1525 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1528 case 2: /* HFC-4S OEM */
1530 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1531 HFC_outb(hc, R_GPIO_EN1, 0xff);
1532 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1536 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1537 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1538 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1541 /* set master clock */
1542 if (hc->masterclk >= 0) {
1543 if (debug & DEBUG_HFCMULTI_INIT)
1544 printk(KERN_DEBUG "%s: setting ST master clock "
1545 "to port %d (0..%d)\n",
1546 __func__, hc->masterclk, hc->ports - 1);
1547 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1548 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1553 /* setting misc irq */
1554 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1555 if (debug & DEBUG_HFCMULTI_INIT)
1556 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1557 hc->hw.r_irqmsk_misc);
1559 /* RAM access test */
1560 HFC_outb(hc, R_RAM_ADDR0, 0);
1561 HFC_outb(hc, R_RAM_ADDR1, 0);
1562 HFC_outb(hc, R_RAM_ADDR2, 0);
1563 for (i = 0; i < 256; i++) {
1564 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1565 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1567 for (i = 0; i < 256; i++) {
1568 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1569 HFC_inb_nodebug(hc, R_RAM_DATA);
1570 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1571 if (rval != ((i * 3) & 0xff)) {
1573 "addr:%x val:%x should:%x\n", i, rval,
1579 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1584 if (debug & DEBUG_HFCMULTI_INIT)
1585 printk(KERN_DEBUG "%s: done\n", __func__);
1587 spin_unlock_irqrestore(&hc->lock, flags);
1593 * control the watchdog
1596 hfcmulti_watchdog(struct hfc_multi *hc)
1600 if (hc->wdcount > 10) {
1602 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1603 V_GPIO_OUT3 : V_GPIO_OUT2;
1605 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1606 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1607 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1617 hfcmulti_leds(struct hfc_multi *hc)
1620 unsigned long leddw;
1621 int i, state, active, leds;
1622 struct dchannel *dch;
1626 case 1: /* HFC-E1 OEM */
1627 /* 2 red steady: LOS
1628 * 1 red steady: L1 not active
1629 * 2 green steady: L1 active
1630 * 1st green flashing: activity on TX
1631 * 2nd green flashing: activity on RX
1637 dch = hc->chan[hc->dnum[0]].dch;
1639 if (hc->chan[hc->dnum[0]].los)
1641 if (hc->e1_state != 1) {
1648 if (!hc->flash[2] && hc->activity_tx)
1649 hc->flash[2] = poll;
1650 if (!hc->flash[3] && hc->activity_rx)
1651 hc->flash[3] = poll;
1652 if (hc->flash[2] && hc->flash[2] < 1024)
1654 if (hc->flash[3] && hc->flash[3] < 1024)
1656 if (hc->flash[2] >= 2048)
1658 if (hc->flash[3] >= 2048)
1661 hc->flash[2] += poll;
1663 hc->flash[3] += poll;
1666 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1667 /* leds are inverted */
1668 if (leds != (int)hc->ledstate) {
1669 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1670 hc->ledstate = leds;
1674 case 2: /* HFC-4S OEM */
1675 /* red steady: PH_DEACTIVATE
1676 * green steady: PH_ACTIVATE
1677 * green flashing: activity on TX
1679 for (i = 0; i < 4; i++) {
1682 dch = hc->chan[(i << 2) | 2].dch;
1685 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1691 if (state == active) {
1692 led[i] = 1; /* led green */
1693 hc->activity_tx |= hc->activity_rx;
1694 if (!hc->flash[i] &&
1695 (hc->activity_tx & (1 << i)))
1696 hc->flash[i] = poll;
1697 if (hc->flash[i] && hc->flash[i] < 1024)
1698 led[i] = 0; /* led off */
1699 if (hc->flash[i] >= 2048)
1702 hc->flash[i] += poll;
1704 led[i] = 2; /* led red */
1708 led[i] = 0; /* led off */
1710 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1712 for (i = 0; i < 4; i++) {
1715 leds |= (0x2 << (i * 2));
1716 } else if (led[i] == 2) {
1718 leds |= (0x1 << (i * 2));
1721 if (leds != (int)hc->ledstate) {
1722 vpm_out(hc, 0, 0x1a8 + 3, leds);
1723 hc->ledstate = leds;
1726 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1727 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1728 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1729 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1730 if (leds != (int)hc->ledstate) {
1731 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1732 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1733 hc->ledstate = leds;
1738 case 3: /* HFC 1S/2S Beronet */
1739 /* red steady: PH_DEACTIVATE
1740 * green steady: PH_ACTIVATE
1741 * green flashing: activity on TX
1743 for (i = 0; i < 2; i++) {
1746 dch = hc->chan[(i << 2) | 2].dch;
1749 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1755 if (state == active) {
1756 led[i] = 1; /* led green */
1757 hc->activity_tx |= hc->activity_rx;
1758 if (!hc->flash[i] &&
1759 (hc->activity_tx & (1 << i)))
1760 hc->flash[i] = poll;
1761 if (hc->flash[i] < 1024)
1762 led[i] = 0; /* led off */
1763 if (hc->flash[i] >= 2048)
1766 hc->flash[i] += poll;
1768 led[i] = 2; /* led red */
1772 led[i] = 0; /* led off */
1774 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1775 | ((led[1]&1) << 3);
1776 if (leds != (int)hc->ledstate) {
1777 HFC_outb_nodebug(hc, R_GPIO_EN1,
1778 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1779 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1780 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1781 hc->ledstate = leds;
1784 case 8: /* HFC 8S+ Beronet */
1785 /* off: PH_DEACTIVATE
1786 * steady: PH_ACTIVATE
1787 * flashing: activity on TX
1789 lled = 0xff; /* leds off */
1790 for (i = 0; i < 8; i++) {
1793 dch = hc->chan[(i << 2) | 2].dch;
1796 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1802 if (state == active) {
1803 lled &= ~(1 << i); /* led on */
1804 hc->activity_tx |= hc->activity_rx;
1805 if (!hc->flash[i] &&
1806 (hc->activity_tx & (1 << i)))
1807 hc->flash[i] = poll;
1808 if (hc->flash[i] < 1024)
1809 lled |= 1 << i; /* led off */
1810 if (hc->flash[i] >= 2048)
1813 hc->flash[i] += poll;
1818 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1819 if (leddw != hc->ledstate) {
1820 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1821 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1822 /* was _io before */
1823 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1824 outw(0x4000, hc->pci_iobase + 4);
1825 outl(leddw, hc->pci_iobase);
1826 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1827 hc->ledstate = leddw;
1831 hc->activity_tx = 0;
1832 hc->activity_rx = 0;
1835 * read dtmf coefficients
1839 hfcmulti_dtmf(struct hfc_multi *hc)
1844 struct bchannel *bch = NULL;
1849 struct sk_buff *skb;
1850 struct mISDNhead *hh;
1852 if (debug & DEBUG_HFCMULTI_DTMF)
1853 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1854 for (ch = 0; ch <= 31; ch++) {
1855 /* only process enabled B-channels */
1856 bch = hc->chan[ch].bch;
1859 if (!hc->created[hc->chan[ch].port])
1861 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1863 if (debug & DEBUG_HFCMULTI_DTMF)
1864 printk(KERN_DEBUG "%s: dtmf channel %d:",
1866 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1868 for (co = 0; co < 8; co++) {
1869 /* read W(n-1) coefficient */
1870 addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1871 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1872 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1873 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1875 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1876 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1877 if (debug & DEBUG_HFCMULTI_DTMF)
1878 printk(" %04x", w_float);
1880 /* decode float (see chip doc) */
1881 mantissa = w_float & 0x0fff;
1882 if (w_float & 0x8000)
1883 mantissa |= 0xfffff000;
1884 exponent = (w_float >> 12) & 0x7;
1887 mantissa <<= (exponent - 1);
1890 /* store coefficient */
1891 coeff[co << 1] = mantissa;
1893 /* read W(n) coefficient */
1894 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1895 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1896 if (debug & DEBUG_HFCMULTI_DTMF)
1897 printk(" %04x", w_float);
1899 /* decode float (see chip doc) */
1900 mantissa = w_float & 0x0fff;
1901 if (w_float & 0x8000)
1902 mantissa |= 0xfffff000;
1903 exponent = (w_float >> 12) & 0x7;
1906 mantissa <<= (exponent - 1);
1909 /* store coefficient */
1910 coeff[(co << 1) | 1] = mantissa;
1912 if (debug & DEBUG_HFCMULTI_DTMF)
1913 printk(" DTMF ready %08x %08x %08x %08x "
1914 "%08x %08x %08x %08x\n",
1915 coeff[0], coeff[1], coeff[2], coeff[3],
1916 coeff[4], coeff[5], coeff[6], coeff[7]);
1917 hc->chan[ch].coeff_count++;
1918 if (hc->chan[ch].coeff_count == 8) {
1919 hc->chan[ch].coeff_count = 0;
1920 skb = mI_alloc_skb(512, GFP_ATOMIC);
1922 printk(KERN_DEBUG "%s: No memory for skb\n",
1926 hh = mISDN_HEAD_P(skb);
1927 hh->prim = PH_CONTROL_IND;
1928 hh->id = DTMF_HFC_COEF;
1929 skb_put_data(skb, hc->chan[ch].coeff, 512);
1930 recv_Bchannel_skb(bch, skb);
1934 /* restart DTMF processing */
1937 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1942 * fill fifo as much as possible
1946 hfcmulti_tx(struct hfc_multi *hc, int ch)
1948 int i, ii, temp, len = 0;
1949 int Zspace, z1, z2; /* must be int for calculation */
1952 int *txpending, slot_tx;
1953 struct bchannel *bch;
1954 struct dchannel *dch;
1955 struct sk_buff **sp = NULL;
1958 bch = hc->chan[ch].bch;
1959 dch = hc->chan[ch].dch;
1960 if ((!dch) && (!bch))
1963 txpending = &hc->chan[ch].txpending;
1964 slot_tx = hc->chan[ch].slot_tx;
1966 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1969 idxp = &dch->tx_idx;
1971 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1974 idxp = &bch->tx_idx;
1979 if ((!len) && *txpending != 1)
1980 return; /* no data */
1982 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1983 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1984 (hc->chan[ch].slot_rx < 0) &&
1985 (hc->chan[ch].slot_tx < 0))
1986 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1988 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1989 HFC_wait_nodebug(hc);
1991 if (*txpending == 2) {
1993 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1994 HFC_wait_nodebug(hc);
1995 HFC_outb(hc, A_SUBCH_CFG, 0);
1999 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2000 f1 = HFC_inb_nodebug(hc, A_F1);
2001 f2 = HFC_inb_nodebug(hc, A_F2);
2002 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
2003 if (debug & DEBUG_HFCMULTI_FIFO)
2005 "%s(card %d): reread f2 because %d!=%d\n",
2006 __func__, hc->id + 1, temp, f2);
2007 f2 = temp; /* repeat until F2 is equal */
2009 Fspace = f2 - f1 - 1;
2013 * Old FIFO handling doesn't give us the current Z2 read
2014 * pointer, so we cannot send the next frame before the fifo
2015 * is empty. It makes no difference except for a slightly
2016 * lower performance.
2018 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
2024 /* one frame only for ST D-channels, to allow resending */
2025 if (hc->ctype != HFC_TYPE_E1 && dch) {
2029 /* F-counter full condition */
2033 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2034 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2035 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2036 if (debug & DEBUG_HFCMULTI_FIFO)
2037 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2038 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2039 z2 = temp; /* repeat unti Z2 is equal */
2041 hc->chan[ch].Zfill = z1 - z2;
2042 if (hc->chan[ch].Zfill < 0)
2043 hc->chan[ch].Zfill += hc->Zlen;
2047 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2048 /* fill transparent data only to maxinum transparent load (minus 4) */
2049 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2050 Zspace = Zspace - hc->Zlen + hc->max_trans;
2051 if (Zspace <= 0) /* no space of 4 bytes */
2056 if (z1 == z2) { /* empty */
2057 /* if done with FIFO audio data during PCM connection */
2058 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2059 *txpending && slot_tx >= 0) {
2060 if (debug & DEBUG_HFCMULTI_MODE)
2062 "%s: reconnecting PCM due to no "
2063 "more FIFO data: channel %d "
2065 __func__, ch, slot_tx);
2067 if (hc->ctype == HFC_TYPE_XHFC)
2068 HFC_outb(hc, A_CON_HDLC, 0xc0
2069 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2070 /* Enable FIFO, no interrupt */
2072 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2073 V_HDLC_TRP | V_IFF);
2074 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2075 HFC_wait_nodebug(hc);
2076 if (hc->ctype == HFC_TYPE_XHFC)
2077 HFC_outb(hc, A_CON_HDLC, 0xc0
2078 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2079 /* Enable FIFO, no interrupt */
2081 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2082 V_HDLC_TRP | V_IFF);
2083 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2084 HFC_wait_nodebug(hc);
2088 return; /* no data */
2091 /* "fill fifo if empty" feature */
2092 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2093 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2094 if (debug & DEBUG_HFCMULTI_FILL)
2095 printk(KERN_DEBUG "%s: buffer empty, so we have "
2096 "underrun\n", __func__);
2097 /* fill buffer, to prevent future underrun */
2098 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2099 Zspace -= (poll >> 1);
2102 /* if audio data and connected slot */
2103 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2105 if (debug & DEBUG_HFCMULTI_MODE)
2106 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2107 "FIFO data: channel %d slot_tx %d\n",
2108 __func__, ch, slot_tx);
2109 /* disconnect slot */
2110 if (hc->ctype == HFC_TYPE_XHFC)
2111 HFC_outb(hc, A_CON_HDLC, 0x80
2112 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2113 /* Enable FIFO, no interrupt */
2115 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2116 V_HDLC_TRP | V_IFF);
2117 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2118 HFC_wait_nodebug(hc);
2119 if (hc->ctype == HFC_TYPE_XHFC)
2120 HFC_outb(hc, A_CON_HDLC, 0x80
2121 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2122 /* Enable FIFO, no interrupt */
2124 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2125 V_HDLC_TRP | V_IFF);
2126 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2127 HFC_wait_nodebug(hc);
2133 hc->activity_tx |= 1 << hc->chan[ch].port;
2135 /* fill fifo to what we have left */
2137 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2142 d = (*sp)->data + i;
2143 if (ii - i > Zspace)
2145 if (debug & DEBUG_HFCMULTI_FIFO)
2146 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2147 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2148 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2149 temp ? "HDLC" : "TRANS");
2151 /* Have to prep the audio data */
2152 hc->write_fifo(hc, d, ii - i);
2153 hc->chan[ch].Zfill += ii - i;
2156 /* if not all data has been written */
2158 /* NOTE: fifo is started by the calling function */
2162 /* if all data has been written, terminate frame */
2163 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2164 /* increment f-counter */
2165 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2166 HFC_wait_nodebug(hc);
2170 /* check for next frame */
2171 if (bch && get_next_bframe(bch)) {
2175 if (dch && get_next_dframe(dch)) {
2181 * now we have no more data, so in case of transparent,
2182 * we set the last byte in fifo to 'silence' in case we will get
2183 * no more data at all. this prevents sending an undefined value.
2185 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2186 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2190 /* NOTE: only called if E1 card is in active state */
2192 hfcmulti_rx(struct hfc_multi *hc, int ch)
2195 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2196 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2198 struct bchannel *bch;
2199 struct dchannel *dch = NULL;
2200 struct sk_buff *skb, **sp = NULL;
2203 bch = hc->chan[ch].bch;
2205 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2207 } else if (hc->chan[ch].dch) {
2208 dch = hc->chan[ch].dch;
2209 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2215 /* on first AND before getting next valid frame, R_FIFO must be written
2217 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2218 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2219 (hc->chan[ch].slot_rx < 0) &&
2220 (hc->chan[ch].slot_tx < 0))
2221 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2223 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2224 HFC_wait_nodebug(hc);
2226 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2227 if (hc->chan[ch].rx_off) {
2229 bch->dropcnt += poll; /* not exact but fair enough */
2233 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2234 f1 = HFC_inb_nodebug(hc, A_F1);
2235 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2236 if (debug & DEBUG_HFCMULTI_FIFO)
2238 "%s(card %d): reread f1 because %d!=%d\n",
2239 __func__, hc->id + 1, temp, f1);
2240 f1 = temp; /* repeat until F1 is equal */
2242 f2 = HFC_inb_nodebug(hc, A_F2);
2244 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2245 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2246 if (debug & DEBUG_HFCMULTI_FIFO)
2247 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2248 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2249 z1 = temp; /* repeat until Z1 is equal */
2251 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2253 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2254 /* complete hdlc frame */
2258 /* if buffer is empty */
2263 maxlen = bchannel_get_rxbuf(bch, Zsize);
2265 pr_warning("card%d.B%d: No bufferspace for %d bytes\n",
2266 hc->id + 1, bch->nr, Zsize);
2270 maxlen = bch->maxlen;
2271 } else { /* Dchannel */
2273 maxlen = dch->maxlen + 3;
2275 *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2277 pr_warning("card%d: No mem for dch rx_skb\n",
2285 hc->activity_rx |= 1 << hc->chan[ch].port;
2287 /* empty fifo with what we have */
2288 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2289 if (debug & DEBUG_HFCMULTI_FIFO)
2290 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2291 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2292 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2293 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2294 f1, f2, Zsize + (*sp)->len, again);
2296 if ((Zsize + (*sp)->len) > maxlen) {
2297 if (debug & DEBUG_HFCMULTI_FIFO)
2299 "%s(card %d): hdlc-frame too large.\n",
2300 __func__, hc->id + 1);
2302 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2303 HFC_wait_nodebug(hc);
2307 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2310 /* increment Z2,F2-counter */
2311 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2312 HFC_wait_nodebug(hc);
2314 if ((*sp)->len < 4) {
2315 if (debug & DEBUG_HFCMULTI_FIFO)
2317 "%s(card %d): Frame below minimum "
2318 "size\n", __func__, hc->id + 1);
2322 /* there is at least one complete frame, check crc */
2323 if ((*sp)->data[(*sp)->len - 1]) {
2324 if (debug & DEBUG_HFCMULTI_CRC)
2326 "%s: CRC-error\n", __func__);
2330 skb_trim(*sp, (*sp)->len - 3);
2331 if ((*sp)->len < MISDN_COPY_SIZE) {
2333 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2335 skb_put_data(*sp, skb->data, skb->len);
2338 printk(KERN_DEBUG "%s: No mem\n",
2346 if (debug & DEBUG_HFCMULTI_FIFO) {
2347 printk(KERN_DEBUG "%s(card %d):",
2348 __func__, hc->id + 1);
2350 while (temp < (*sp)->len)
2351 printk(" %02x", (*sp)->data[temp++]);
2357 recv_Bchannel(bch, MISDN_ID_ANY, false);
2362 /* there is an incomplete frame */
2365 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2366 if (debug & DEBUG_HFCMULTI_FIFO)
2368 "%s(card %d): fifo(%d) reading %d bytes "
2369 "(z1=%04x, z2=%04x) TRANS\n",
2370 __func__, hc->id + 1, ch, Zsize, z1, z2);
2371 /* only bch is transparent */
2372 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2381 signal_state_up(struct dchannel *dch, int info, char *msg)
2383 struct sk_buff *skb;
2384 int id, data = info;
2386 if (debug & DEBUG_HFCMULTI_STATE)
2387 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2389 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2391 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2395 recv_Dchannel_skb(dch, skb);
2399 handle_timer_irq(struct hfc_multi *hc)
2402 struct dchannel *dch;
2405 /* process queued resync jobs */
2406 if (hc->e1_resync) {
2407 /* lock, so e1_resync gets not changed */
2408 spin_lock_irqsave(&HFClock, flags);
2409 if (hc->e1_resync & 1) {
2410 if (debug & DEBUG_HFCMULTI_PLXSD)
2411 printk(KERN_DEBUG "Enable SYNC_I\n");
2412 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2413 /* disable JATT, if RX_SYNC is set */
2414 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2415 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2417 if (hc->e1_resync & 2) {
2418 if (debug & DEBUG_HFCMULTI_PLXSD)
2419 printk(KERN_DEBUG "Enable jatt PLL\n");
2420 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2422 if (hc->e1_resync & 4) {
2423 if (debug & DEBUG_HFCMULTI_PLXSD)
2425 "Enable QUARTZ for HFC-E1\n");
2426 /* set jatt to quartz */
2427 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2429 /* switch to JATT, in case it is not already */
2430 HFC_outb(hc, R_SYNC_OUT, 0);
2433 spin_unlock_irqrestore(&HFClock, flags);
2436 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2437 for (ch = 0; ch <= 31; ch++) {
2438 if (hc->created[hc->chan[ch].port]) {
2439 hfcmulti_tx(hc, ch);
2440 /* fifo is started when switching to rx-fifo */
2441 hfcmulti_rx(hc, ch);
2442 if (hc->chan[ch].dch &&
2443 hc->chan[ch].nt_timer > -1) {
2444 dch = hc->chan[ch].dch;
2445 if (!(--hc->chan[ch].nt_timer)) {
2449 DEBUG_HFCMULTI_STATE)
2459 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2460 dch = hc->chan[hc->dnum[0]].dch;
2462 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2463 hc->chan[hc->dnum[0]].los = temp;
2464 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2465 if (!temp && hc->chan[hc->dnum[0]].los)
2466 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2468 if (temp && !hc->chan[hc->dnum[0]].los)
2469 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2472 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2474 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2475 if (!temp && hc->chan[hc->dnum[0]].ais)
2476 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2478 if (temp && !hc->chan[hc->dnum[0]].ais)
2479 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2481 hc->chan[hc->dnum[0]].ais = temp;
2483 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2485 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2486 if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2487 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2488 " bit SLIP detected RX");
2489 hc->chan[hc->dnum[0]].slip_rx = temp;
2490 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2491 if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2492 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2493 " bit SLIP detected TX");
2494 hc->chan[hc->dnum[0]].slip_tx = temp;
2496 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2498 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2499 if (!temp && hc->chan[hc->dnum[0]].rdi)
2500 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2502 if (temp && !hc->chan[hc->dnum[0]].rdi)
2503 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2505 hc->chan[hc->dnum[0]].rdi = temp;
2507 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2508 switch (hc->chan[hc->dnum[0]].sync) {
2510 if ((temp & 0x60) == 0x60) {
2511 if (debug & DEBUG_HFCMULTI_SYNC)
2513 "%s: (id=%d) E1 now "
2516 HFC_outb(hc, R_RX_OFF,
2517 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2518 HFC_outb(hc, R_TX_OFF,
2519 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2520 hc->chan[hc->dnum[0]].sync = 1;
2521 goto check_framesync;
2525 if ((temp & 0x60) != 0x60) {
2526 if (debug & DEBUG_HFCMULTI_SYNC)
2529 "lost clock sync\n",
2531 hc->chan[hc->dnum[0]].sync = 0;
2535 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2537 if (debug & DEBUG_HFCMULTI_SYNC)
2540 "now in frame sync\n",
2542 hc->chan[hc->dnum[0]].sync = 2;
2546 if ((temp & 0x60) != 0x60) {
2547 if (debug & DEBUG_HFCMULTI_SYNC)
2549 "%s: (id=%d) E1 lost "
2550 "clock & frame sync\n",
2552 hc->chan[hc->dnum[0]].sync = 0;
2555 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2557 if (debug & DEBUG_HFCMULTI_SYNC)
2560 "lost frame sync\n",
2562 hc->chan[hc->dnum[0]].sync = 1;
2568 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2569 hfcmulti_watchdog(hc);
2576 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2578 struct dchannel *dch;
2581 u_char st_status, temp;
2584 for (ch = 0; ch <= 31; ch++) {
2585 if (hc->chan[ch].dch) {
2586 dch = hc->chan[ch].dch;
2587 if (r_irq_statech & 1) {
2588 HFC_outb_nodebug(hc, R_ST_SEL,
2590 /* undocumented: delay after R_ST_SEL */
2592 /* undocumented: status changes during read */
2593 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2594 while (st_status != (temp =
2595 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2596 if (debug & DEBUG_HFCMULTI_STATE)
2597 printk(KERN_DEBUG "%s: reread "
2598 "STATE because %d!=%d\n",
2601 st_status = temp; /* repeat */
2604 /* Speech Design TE-sync indication */
2605 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2606 dch->dev.D.protocol == ISDN_P_TE_S0) {
2607 if (st_status & V_FR_SYNC_ST)
2609 (1 << hc->chan[ch].port);
2612 ~(1 << hc->chan[ch].port);
2614 dch->state = st_status & 0x0f;
2615 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2619 if (dch->state == active) {
2620 HFC_outb_nodebug(hc, R_FIFO,
2622 HFC_wait_nodebug(hc);
2623 HFC_outb_nodebug(hc,
2624 R_INC_RES_FIFO, V_RES_F);
2625 HFC_wait_nodebug(hc);
2628 schedule_event(dch, FLG_PHCHANGE);
2629 if (debug & DEBUG_HFCMULTI_STATE)
2631 "%s: S/T newstate %x port %d\n",
2632 __func__, dch->state,
2635 r_irq_statech >>= 1;
2638 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2639 plxsd_checksync(hc, 0);
2643 fifo_irq(struct hfc_multi *hc, int block)
2646 struct dchannel *dch;
2647 struct bchannel *bch;
2648 u_char r_irq_fifo_bl;
2650 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2653 ch = (block << 2) + (j >> 1);
2654 dch = hc->chan[ch].dch;
2655 bch = hc->chan[ch].bch;
2656 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2660 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2661 test_bit(FLG_ACTIVE, &dch->Flags)) {
2662 hfcmulti_tx(hc, ch);
2664 HFC_outb_nodebug(hc, R_FIFO, 0);
2665 HFC_wait_nodebug(hc);
2667 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2668 test_bit(FLG_ACTIVE, &bch->Flags)) {
2669 hfcmulti_tx(hc, ch);
2671 HFC_outb_nodebug(hc, R_FIFO, 0);
2672 HFC_wait_nodebug(hc);
2675 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2676 test_bit(FLG_ACTIVE, &dch->Flags)) {
2677 hfcmulti_rx(hc, ch);
2679 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2680 test_bit(FLG_ACTIVE, &bch->Flags)) {
2681 hfcmulti_rx(hc, ch);
2691 hfcmulti_interrupt(int intno, void *dev_id)
2693 #ifdef IRQCOUNT_DEBUG
2694 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2695 iq5 = 0, iq6 = 0, iqcnt = 0;
2697 struct hfc_multi *hc = dev_id;
2698 struct dchannel *dch;
2699 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2701 void __iomem *plx_acc;
2703 u_char e1_syncsta, temp, temp2;
2707 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2711 spin_lock(&hc->lock);
2715 printk(KERN_ERR "irq for card %d during irq from "
2716 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2717 irqsem = hc->id + 1;
2719 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2720 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2723 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2724 spin_lock_irqsave(&plx_lock, flags);
2725 plx_acc = hc->plx_membase + PLX_INTCSR;
2726 wval = readw(plx_acc);
2727 spin_unlock_irqrestore(&plx_lock, flags);
2728 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2732 status = HFC_inb_nodebug(hc, R_STATUS);
2733 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2734 #ifdef IRQCOUNT_DEBUG
2737 if (status & V_DTMF_STA)
2739 if (status & V_LOST_STA)
2741 if (status & V_EXT_IRQSTA)
2743 if (status & V_MISC_IRQSTA)
2745 if (status & V_FR_IRQSTA)
2747 if (iqcnt++ > 5000) {
2748 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2749 iq1, iq2, iq3, iq4, iq5, iq6);
2754 if (!r_irq_statech &&
2755 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2756 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2757 /* irq is not for us */
2761 if (r_irq_statech) {
2762 if (hc->ctype != HFC_TYPE_E1)
2763 ph_state_irq(hc, r_irq_statech);
2765 if (status & V_EXT_IRQSTA)
2766 ; /* external IRQ */
2767 if (status & V_LOST_STA) {
2769 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2771 if (status & V_MISC_IRQSTA) {
2773 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2774 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2775 if (r_irq_misc & V_STA_IRQ) {
2776 if (hc->ctype == HFC_TYPE_E1) {
2778 dch = hc->chan[hc->dnum[0]].dch;
2779 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2780 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2781 && hc->e1_getclock) {
2782 if (e1_syncsta & V_FR_SYNC_E1)
2783 hc->syncronized = 1;
2785 hc->syncronized = 0;
2787 /* undocumented: status changes during read */
2788 temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2789 while (temp != (temp2 =
2790 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2791 if (debug & DEBUG_HFCMULTI_STATE)
2792 printk(KERN_DEBUG "%s: reread "
2793 "STATE because %d!=%d\n",
2794 __func__, temp, temp2);
2795 temp = temp2; /* repeat */
2797 /* broadcast state change to all fragments */
2798 if (debug & DEBUG_HFCMULTI_STATE)
2800 "%s: E1 (id=%d) newstate %x\n",
2801 __func__, hc->id, temp & 0x7);
2802 for (i = 0; i < hc->ports; i++) {
2803 dch = hc->chan[hc->dnum[i]].dch;
2804 dch->state = temp & 0x7;
2805 schedule_event(dch, FLG_PHCHANGE);
2808 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2809 plxsd_checksync(hc, 0);
2812 if (r_irq_misc & V_TI_IRQ) {
2814 mISDN_clock_update(hc->iclock, poll, NULL);
2815 handle_timer_irq(hc);
2818 if (r_irq_misc & V_DTMF_IRQ)
2821 if (r_irq_misc & V_IRQ_PROC) {
2822 static int irq_proc_cnt;
2823 if (!irq_proc_cnt++)
2824 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2825 " this should not happen\n", __func__);
2829 if (status & V_FR_IRQSTA) {
2831 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2832 for (i = 0; i < 8; i++) {
2833 if (r_irq_oview & (1 << i))
2841 spin_unlock(&hc->lock);
2848 spin_unlock(&hc->lock);
2854 * timer callback for D-chan busy resolution. Currently no function
2858 hfcmulti_dbusy_timer(struct timer_list *t)
2864 * activate/deactivate hardware for selected channels and mode
2866 * configure B-channel with the given protocol
2867 * ch eqals to the HFC-channel (0-31)
2868 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2869 * for S/T, 1-31 for E1)
2870 * the hdlc interrupts will be set/unset
2873 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2874 int bank_tx, int slot_rx, int bank_rx)
2876 int flow_tx = 0, flow_rx = 0, routing = 0;
2877 int oslot_tx, oslot_rx;
2880 if (ch < 0 || ch > 31)
2882 oslot_tx = hc->chan[ch].slot_tx;
2883 oslot_rx = hc->chan[ch].slot_rx;
2884 conf = hc->chan[ch].conf;
2886 if (debug & DEBUG_HFCMULTI_MODE)
2888 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2889 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2890 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2891 bank_tx, oslot_rx, slot_rx, bank_rx);
2893 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2894 /* remove from slot */
2895 if (debug & DEBUG_HFCMULTI_MODE)
2896 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2897 __func__, oslot_tx);
2898 if (hc->slot_owner[oslot_tx << 1] == ch) {
2899 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2900 HFC_outb(hc, A_SL_CFG, 0);
2901 if (hc->ctype != HFC_TYPE_XHFC)
2902 HFC_outb(hc, A_CONF, 0);
2903 hc->slot_owner[oslot_tx << 1] = -1;
2905 if (debug & DEBUG_HFCMULTI_MODE)
2907 "%s: we are not owner of this tx slot "
2908 "anymore, channel %d is.\n",
2909 __func__, hc->slot_owner[oslot_tx << 1]);
2913 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2914 /* remove from slot */
2915 if (debug & DEBUG_HFCMULTI_MODE)
2917 "%s: remove from slot %d (RX)\n",
2918 __func__, oslot_rx);
2919 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2920 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2921 HFC_outb(hc, A_SL_CFG, 0);
2922 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2924 if (debug & DEBUG_HFCMULTI_MODE)
2926 "%s: we are not owner of this rx slot "
2927 "anymore, channel %d is.\n",
2929 hc->slot_owner[(oslot_rx << 1) | 1]);
2934 flow_tx = 0x80; /* FIFO->ST */
2935 /* disable pcm slot */
2936 hc->chan[ch].slot_tx = -1;
2937 hc->chan[ch].bank_tx = 0;
2940 if (hc->chan[ch].txpending)
2941 flow_tx = 0x80; /* FIFO->ST */
2943 flow_tx = 0xc0; /* PCM->ST */
2945 routing = bank_tx ? 0xc0 : 0x80;
2946 if (conf >= 0 || bank_tx > 1)
2947 routing = 0x40; /* loop */
2948 if (debug & DEBUG_HFCMULTI_MODE)
2949 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2950 " %d flow %02x routing %02x conf %d (TX)\n",
2951 __func__, ch, slot_tx, bank_tx,
2952 flow_tx, routing, conf);
2953 HFC_outb(hc, R_SLOT, slot_tx << 1);
2954 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2955 if (hc->ctype != HFC_TYPE_XHFC)
2956 HFC_outb(hc, A_CONF,
2957 (conf < 0) ? 0 : (conf | V_CONF_SL));
2958 hc->slot_owner[slot_tx << 1] = ch;
2959 hc->chan[ch].slot_tx = slot_tx;
2960 hc->chan[ch].bank_tx = bank_tx;
2963 /* disable pcm slot */
2964 flow_rx = 0x80; /* ST->FIFO */
2965 hc->chan[ch].slot_rx = -1;
2966 hc->chan[ch].bank_rx = 0;
2969 if (hc->chan[ch].txpending)
2970 flow_rx = 0x80; /* ST->FIFO */
2972 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2974 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2975 if (conf >= 0 || bank_rx > 1)
2976 routing = 0x40; /* loop */
2977 if (debug & DEBUG_HFCMULTI_MODE)
2978 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2979 " %d flow %02x routing %02x conf %d (RX)\n",
2980 __func__, ch, slot_rx, bank_rx,
2981 flow_rx, routing, conf);
2982 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2983 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2984 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2985 hc->chan[ch].slot_rx = slot_rx;
2986 hc->chan[ch].bank_rx = bank_rx;
2991 /* disable TX fifo */
2992 HFC_outb(hc, R_FIFO, ch << 1);
2994 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2995 HFC_outb(hc, A_SUBCH_CFG, 0);
2996 HFC_outb(hc, A_IRQ_MSK, 0);
2997 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2999 /* disable RX fifo */
3000 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3002 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
3003 HFC_outb(hc, A_SUBCH_CFG, 0);
3004 HFC_outb(hc, A_IRQ_MSK, 0);
3005 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3007 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
3008 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
3009 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
3010 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3011 /* undocumented: delay after R_ST_SEL */
3013 HFC_outb(hc, A_ST_CTRL0,
3014 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3016 if (hc->chan[ch].bch) {
3017 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3018 test_and_clear_bit(FLG_TRANSPARENT,
3019 &hc->chan[ch].bch->Flags);
3022 case (ISDN_P_B_RAW): /* B-channel */
3024 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
3025 (hc->chan[ch].slot_rx < 0) &&
3026 (hc->chan[ch].slot_tx < 0)) {
3029 "Setting B-channel %d to echo cancelable "
3030 "state on PCM slot %d\n", ch,
3031 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3033 "Enabling pass through for channel\n");
3034 vpm_out(hc, ch, ((ch / 4) * 8) +
3035 ((ch % 4) * 4) + 1, 0x01);
3038 HFC_outb(hc, R_FIFO, (ch << 1));
3040 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3041 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3042 ((ch % 4) * 4) + 1) << 1);
3043 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3046 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3048 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3049 HFC_outb(hc, A_SUBCH_CFG, 0);
3050 HFC_outb(hc, A_IRQ_MSK, 0);
3051 if (hc->chan[ch].protocol != protocol) {
3052 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3055 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3056 ((ch % 4) * 4) + 1) << 1) | 1);
3057 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3061 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3063 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3064 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3065 ((ch % 4) * 4)) << 1) | 1);
3066 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3069 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3071 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3072 HFC_outb(hc, A_SUBCH_CFG, 0);
3073 HFC_outb(hc, A_IRQ_MSK, 0);
3074 if (hc->chan[ch].protocol != protocol) {
3075 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3079 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3080 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3081 ((ch % 4) * 4)) << 1);
3082 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3084 /* enable TX fifo */
3085 HFC_outb(hc, R_FIFO, ch << 1);
3087 if (hc->ctype == HFC_TYPE_XHFC)
3088 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3089 V_HDLC_TRP | V_IFF);
3090 /* Enable FIFO, no interrupt */
3092 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3093 V_HDLC_TRP | V_IFF);
3094 HFC_outb(hc, A_SUBCH_CFG, 0);
3095 HFC_outb(hc, A_IRQ_MSK, 0);
3096 if (hc->chan[ch].protocol != protocol) {
3097 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3101 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3102 /* enable RX fifo */
3103 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3105 if (hc->ctype == HFC_TYPE_XHFC)
3106 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3108 /* Enable FIFO, no interrupt*/
3110 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3112 HFC_outb(hc, A_SUBCH_CFG, 0);
3113 HFC_outb(hc, A_IRQ_MSK, 0);
3114 if (hc->chan[ch].protocol != protocol) {
3115 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3119 if (hc->ctype != HFC_TYPE_E1) {
3120 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3121 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3122 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3123 /* undocumented: delay after R_ST_SEL */
3125 HFC_outb(hc, A_ST_CTRL0,
3126 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3128 if (hc->chan[ch].bch)
3129 test_and_set_bit(FLG_TRANSPARENT,
3130 &hc->chan[ch].bch->Flags);
3132 case (ISDN_P_B_HDLC): /* B-channel */
3133 case (ISDN_P_TE_S0): /* D-channel */
3134 case (ISDN_P_NT_S0):
3135 case (ISDN_P_TE_E1):
3136 case (ISDN_P_NT_E1):
3137 /* enable TX fifo */
3138 HFC_outb(hc, R_FIFO, ch << 1);
3140 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3141 /* E1 or B-channel */
3142 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3143 HFC_outb(hc, A_SUBCH_CFG, 0);
3145 /* D-Channel without HDLC fill flags */
3146 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3147 HFC_outb(hc, A_SUBCH_CFG, 2);
3149 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3150 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3152 /* enable RX fifo */
3153 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3155 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3156 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3157 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3159 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3160 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3161 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3163 if (hc->chan[ch].bch) {
3164 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3165 if (hc->ctype != HFC_TYPE_E1) {
3166 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3167 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3168 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3169 /* undocumented: delay after R_ST_SEL */
3171 HFC_outb(hc, A_ST_CTRL0,
3172 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3177 printk(KERN_DEBUG "%s: protocol not known %x\n",
3178 __func__, protocol);
3179 hc->chan[ch].protocol = ISDN_P_NONE;
3180 return -ENOPROTOOPT;
3182 hc->chan[ch].protocol = protocol;
3188 * connect/disconnect PCM
3192 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3193 int slot_rx, int bank_rx)
3195 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3197 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3202 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3207 * set/disable conference
3211 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3213 if (num >= 0 && num <= 7)
3214 hc->chan[ch].conf = num;
3216 hc->chan[ch].conf = -1;
3217 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3218 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3219 hc->chan[ch].bank_rx);
3224 * set/disable sample loop
3227 /* NOTE: this function is experimental and therefore disabled */
3230 * Layer 1 callback function
3233 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3235 struct hfc_multi *hc = dch->hw;
3236 struct sk_buff_head free_queue;
3244 /* start activation */
3245 spin_lock_irqsave(&hc->lock, flags);
3246 if (hc->ctype == HFC_TYPE_E1) {
3247 if (debug & DEBUG_HFCMULTI_MSG)
3249 "%s: HW_RESET_REQ no BRI\n",
3252 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3253 /* undocumented: delay after R_ST_SEL */
3255 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3256 udelay(6); /* wait at least 5,21us */
3257 HFC_outb(hc, A_ST_WR_STATE, 3);
3258 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3261 spin_unlock_irqrestore(&hc->lock, flags);
3262 l1_event(dch->l1, HW_POWERUP_IND);
3265 __skb_queue_head_init(&free_queue);
3266 /* start deactivation */
3267 spin_lock_irqsave(&hc->lock, flags);
3268 if (hc->ctype == HFC_TYPE_E1) {
3269 if (debug & DEBUG_HFCMULTI_MSG)
3271 "%s: HW_DEACT_REQ no BRI\n",
3274 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3275 /* undocumented: delay after R_ST_SEL */
3277 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3279 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3281 ~(1 << hc->chan[dch->slot].port);
3282 plxsd_checksync(hc, 0);
3285 skb_queue_splice_init(&dch->squeue, &free_queue);
3287 __skb_queue_tail(&free_queue, dch->tx_skb);
3292 __skb_queue_tail(&free_queue, dch->rx_skb);
3295 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3296 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3297 del_timer(&dch->timer);
3298 spin_unlock_irqrestore(&hc->lock, flags);
3299 __skb_queue_purge(&free_queue);
3301 case HW_POWERUP_REQ:
3302 spin_lock_irqsave(&hc->lock, flags);
3303 if (hc->ctype == HFC_TYPE_E1) {
3304 if (debug & DEBUG_HFCMULTI_MSG)
3306 "%s: HW_POWERUP_REQ no BRI\n",
3309 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3310 /* undocumented: delay after R_ST_SEL */
3312 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3313 udelay(6); /* wait at least 5,21us */
3314 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3316 spin_unlock_irqrestore(&hc->lock, flags);
3318 case PH_ACTIVATE_IND:
3319 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3320 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3323 case PH_DEACTIVATE_IND:
3324 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3325 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3329 if (dch->debug & DEBUG_HW)
3330 printk(KERN_DEBUG "%s: unknown command %x\n",
3338 * Layer2 -> Layer 1 Transfer
3342 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3344 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3345 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3346 struct hfc_multi *hc = dch->hw;
3347 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3356 spin_lock_irqsave(&hc->lock, flags);
3357 ret = dchannel_senddata(dch, skb);
3358 if (ret > 0) { /* direct TX */
3359 id = hh->id; /* skb can be freed */
3360 hfcmulti_tx(hc, dch->slot);
3363 HFC_outb(hc, R_FIFO, 0);
3365 spin_unlock_irqrestore(&hc->lock, flags);
3366 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3368 spin_unlock_irqrestore(&hc->lock, flags);
3370 case PH_ACTIVATE_REQ:
3371 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3372 spin_lock_irqsave(&hc->lock, flags);
3374 if (debug & DEBUG_HFCMULTI_MSG)
3376 "%s: PH_ACTIVATE port %d (0..%d)\n",
3377 __func__, hc->chan[dch->slot].port,
3379 /* start activation */
3380 if (hc->ctype == HFC_TYPE_E1) {
3381 ph_state_change(dch);
3382 if (debug & DEBUG_HFCMULTI_STATE)
3384 "%s: E1 report state %x \n",
3385 __func__, dch->state);
3387 HFC_outb(hc, R_ST_SEL,
3388 hc->chan[dch->slot].port);
3389 /* undocumented: delay after R_ST_SEL */
3391 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3393 udelay(6); /* wait at least 5,21us */
3394 HFC_outb(hc, A_ST_WR_STATE, 1);
3395 HFC_outb(hc, A_ST_WR_STATE, 1 |
3396 (V_ST_ACT * 3)); /* activate */
3399 spin_unlock_irqrestore(&hc->lock, flags);
3401 ret = l1_event(dch->l1, hh->prim);
3403 case PH_DEACTIVATE_REQ:
3404 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3405 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3406 struct sk_buff_head free_queue;
3408 __skb_queue_head_init(&free_queue);
3409 spin_lock_irqsave(&hc->lock, flags);
3410 if (debug & DEBUG_HFCMULTI_MSG)
3412 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3413 __func__, hc->chan[dch->slot].port,
3415 /* start deactivation */
3416 if (hc->ctype == HFC_TYPE_E1) {
3417 if (debug & DEBUG_HFCMULTI_MSG)
3419 "%s: PH_DEACTIVATE no BRI\n",
3422 HFC_outb(hc, R_ST_SEL,
3423 hc->chan[dch->slot].port);
3424 /* undocumented: delay after R_ST_SEL */
3426 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3430 skb_queue_splice_init(&dch->squeue, &free_queue);
3432 __skb_queue_tail(&free_queue, dch->tx_skb);
3437 __skb_queue_tail(&free_queue, dch->rx_skb);
3440 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3441 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3442 del_timer(&dch->timer);
3444 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3445 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3448 spin_unlock_irqrestore(&hc->lock, flags);
3449 __skb_queue_purge(&free_queue);
3451 ret = l1_event(dch->l1, hh->prim);
3460 deactivate_bchannel(struct bchannel *bch)
3462 struct hfc_multi *hc = bch->hw;
3465 spin_lock_irqsave(&hc->lock, flags);
3466 mISDN_clear_bchannel(bch);
3467 hc->chan[bch->slot].coeff_count = 0;
3468 hc->chan[bch->slot].rx_off = 0;
3469 hc->chan[bch->slot].conf = -1;
3470 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3471 spin_unlock_irqrestore(&hc->lock, flags);
3475 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3477 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3478 struct hfc_multi *hc = bch->hw;
3480 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3481 unsigned long flags;
3487 spin_lock_irqsave(&hc->lock, flags);
3488 ret = bchannel_senddata(bch, skb);
3489 if (ret > 0) { /* direct TX */
3490 hfcmulti_tx(hc, bch->slot);
3493 HFC_outb_nodebug(hc, R_FIFO, 0);
3494 HFC_wait_nodebug(hc);
3496 spin_unlock_irqrestore(&hc->lock, flags);
3498 case PH_ACTIVATE_REQ:
3499 if (debug & DEBUG_HFCMULTI_MSG)
3500 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3501 __func__, bch->slot);
3502 spin_lock_irqsave(&hc->lock, flags);
3503 /* activate B-channel if not already activated */
3504 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3505 hc->chan[bch->slot].txpending = 0;
3506 ret = mode_hfcmulti(hc, bch->slot,
3508 hc->chan[bch->slot].slot_tx,
3509 hc->chan[bch->slot].bank_tx,
3510 hc->chan[bch->slot].slot_rx,
3511 hc->chan[bch->slot].bank_rx);
3513 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3514 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3517 if (debug & DEBUG_HFCMULTI_DTMF)
3519 "%s: start dtmf decoder\n",
3521 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3527 spin_unlock_irqrestore(&hc->lock, flags);
3529 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3532 case PH_CONTROL_REQ:
3533 spin_lock_irqsave(&hc->lock, flags);
3535 case HFC_SPL_LOOP_ON: /* set sample loop */
3536 if (debug & DEBUG_HFCMULTI_MSG)
3538 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3539 __func__, skb->len);
3542 case HFC_SPL_LOOP_OFF: /* set silence */
3543 if (debug & DEBUG_HFCMULTI_MSG)
3544 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3550 "%s: unknown PH_CONTROL_REQ info %x\n",
3554 spin_unlock_irqrestore(&hc->lock, flags);
3556 case PH_DEACTIVATE_REQ:
3557 deactivate_bchannel(bch); /* locked there */
3558 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3569 * bchannel control function
3572 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3575 struct dsp_features *features =
3576 (struct dsp_features *)(*((u_long *)&cq->p1));
3577 struct hfc_multi *hc = bch->hw;
3585 case MISDN_CTRL_GETOP:
3586 ret = mISDN_ctrl_bchannel(bch, cq);
3587 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3589 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3590 ret = mISDN_ctrl_bchannel(bch, cq);
3591 hc->chan[bch->slot].rx_off = !!cq->p1;
3592 if (!hc->chan[bch->slot].rx_off) {
3593 /* reset fifo on rx on */
3594 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3595 HFC_wait_nodebug(hc);
3596 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3597 HFC_wait_nodebug(hc);
3599 if (debug & DEBUG_HFCMULTI_MSG)
3600 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3601 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3603 case MISDN_CTRL_FILL_EMPTY:
3604 ret = mISDN_ctrl_bchannel(bch, cq);
3605 hc->silence = bch->fill[0];
3606 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3608 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3609 if (debug & DEBUG_HFCMULTI_MSG)
3610 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3612 /* create confirm */
3613 features->hfc_id = hc->id;
3614 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3615 features->hfc_dtmf = 1;
3616 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3617 features->hfc_conf = 1;
3618 features->hfc_loops = 0;
3619 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3620 features->hfc_echocanhw = 1;
3622 features->pcm_id = hc->pcm;
3623 features->pcm_slots = hc->slots;
3624 features->pcm_banks = 2;
3627 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3628 slot_tx = cq->p1 & 0xff;
3629 bank_tx = cq->p1 >> 8;
3630 slot_rx = cq->p2 & 0xff;
3631 bank_rx = cq->p2 >> 8;
3632 if (debug & DEBUG_HFCMULTI_MSG)
3634 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3635 "slot %d bank %d (RX)\n",
3636 __func__, slot_tx, bank_tx,
3638 if (slot_tx < hc->slots && bank_tx <= 2 &&
3639 slot_rx < hc->slots && bank_rx <= 2)
3640 hfcmulti_pcm(hc, bch->slot,
3641 slot_tx, bank_tx, slot_rx, bank_rx);
3644 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3645 "slot %d bank %d (RX) out of range\n",
3646 __func__, slot_tx, bank_tx,
3651 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3652 if (debug & DEBUG_HFCMULTI_MSG)
3653 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3655 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3657 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3658 num = cq->p1 & 0xff;
3659 if (debug & DEBUG_HFCMULTI_MSG)
3660 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3663 hfcmulti_conf(hc, bch->slot, num);
3666 "%s: HW_CONF_JOIN conf %d out of range\n",
3671 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3672 if (debug & DEBUG_HFCMULTI_MSG)
3673 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3674 hfcmulti_conf(hc, bch->slot, -1);
3676 case MISDN_CTRL_HFC_ECHOCAN_ON:
3677 if (debug & DEBUG_HFCMULTI_MSG)
3678 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3679 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3680 vpm_echocan_on(hc, bch->slot, cq->p1);
3685 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3686 if (debug & DEBUG_HFCMULTI_MSG)
3687 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3689 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3690 vpm_echocan_off(hc, bch->slot);
3695 ret = mISDN_ctrl_bchannel(bch, cq);
3702 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3704 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3705 struct hfc_multi *hc = bch->hw;
3709 if (bch->debug & DEBUG_HW)
3710 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3711 __func__, cmd, arg);
3714 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3715 deactivate_bchannel(bch); /* locked there */
3716 ch->protocol = ISDN_P_NONE;
3718 module_put(THIS_MODULE);
3721 case CONTROL_CHANNEL:
3722 spin_lock_irqsave(&hc->lock, flags);
3723 err = channel_bctrl(bch, arg);
3724 spin_unlock_irqrestore(&hc->lock, flags);
3727 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3734 * handle D-channel events
3736 * handle state change event
3739 ph_state_change(struct dchannel *dch)
3741 struct hfc_multi *hc;
3745 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3751 if (hc->ctype == HFC_TYPE_E1) {
3752 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3753 if (debug & DEBUG_HFCMULTI_STATE)
3755 "%s: E1 TE (id=%d) newstate %x\n",
3756 __func__, hc->id, dch->state);
3758 if (debug & DEBUG_HFCMULTI_STATE)
3760 "%s: E1 NT (id=%d) newstate %x\n",
3761 __func__, hc->id, dch->state);
3763 switch (dch->state) {
3765 if (hc->e1_state != 1) {
3766 for (i = 1; i <= 31; i++) {
3767 /* reset fifos on e1 activation */
3768 HFC_outb_nodebug(hc, R_FIFO,
3770 HFC_wait_nodebug(hc);
3771 HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3773 HFC_wait_nodebug(hc);
3776 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3777 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3778 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3782 if (hc->e1_state != 1)
3784 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3785 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3786 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3788 hc->e1_state = dch->state;
3790 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3791 if (debug & DEBUG_HFCMULTI_STATE)
3793 "%s: S/T TE newstate %x\n",
3794 __func__, dch->state);
3795 switch (dch->state) {
3797 l1_event(dch->l1, HW_RESET_IND);
3800 l1_event(dch->l1, HW_DEACT_IND);
3804 l1_event(dch->l1, ANYSIGNAL);
3807 l1_event(dch->l1, INFO2);
3810 l1_event(dch->l1, INFO4_P8);
3814 if (debug & DEBUG_HFCMULTI_STATE)
3815 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3816 __func__, dch->state);
3817 switch (dch->state) {
3819 if (hc->chan[ch].nt_timer == 0) {
3820 hc->chan[ch].nt_timer = -1;
3821 HFC_outb(hc, R_ST_SEL,
3823 /* undocumented: delay after R_ST_SEL */
3825 HFC_outb(hc, A_ST_WR_STATE, 4 |
3826 V_ST_LD_STA); /* G4 */
3827 udelay(6); /* wait at least 5,21us */
3828 HFC_outb(hc, A_ST_WR_STATE, 4);
3831 /* one extra count for the next event */
3832 hc->chan[ch].nt_timer =
3833 nt_t1_count[poll_timer] + 1;
3834 HFC_outb(hc, R_ST_SEL,
3836 /* undocumented: delay after R_ST_SEL */
3838 /* allow G2 -> G3 transition */
3839 HFC_outb(hc, A_ST_WR_STATE, 2 |
3844 hc->chan[ch].nt_timer = -1;
3845 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3846 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3847 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3850 hc->chan[ch].nt_timer = -1;
3853 hc->chan[ch].nt_timer = -1;
3854 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3855 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3856 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3864 * called for card mode init message
3868 hfcmulti_initmode(struct dchannel *dch)
3870 struct hfc_multi *hc = dch->hw;
3871 u_char a_st_wr_state, r_e1_wr_sta;
3874 if (debug & DEBUG_HFCMULTI_INIT)
3875 printk(KERN_DEBUG "%s: entered\n", __func__);
3878 pt = hc->chan[i].port;
3879 if (hc->ctype == HFC_TYPE_E1) {
3881 hc->chan[hc->dnum[pt]].slot_tx = -1;
3882 hc->chan[hc->dnum[pt]].slot_rx = -1;
3883 hc->chan[hc->dnum[pt]].conf = -1;
3885 mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
3887 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3889 for (i = 1; i <= 31; i++) {
3890 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3892 hc->chan[i].slot_tx = -1;
3893 hc->chan[i].slot_rx = -1;
3894 hc->chan[i].conf = -1;
3895 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3898 if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3900 dch = hc->chan[hc->dnum[0]].dch;
3901 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3902 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3903 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3905 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3906 HFC_outb(hc, R_RX0, 0);
3907 hc->hw.r_tx0 = 0 | V_OUT_EN;
3909 HFC_outb(hc, R_RX0, 1);
3910 hc->hw.r_tx0 = 1 | V_OUT_EN;
3912 hc->hw.r_tx1 = V_ATX | V_NTRI;
3913 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3914 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3915 HFC_outb(hc, R_TX_FR0, 0x00);
3916 HFC_outb(hc, R_TX_FR1, 0xf8);
3918 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3919 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3921 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3923 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3924 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3926 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3927 if (debug & DEBUG_HFCMULTI_INIT)
3928 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3930 r_e1_wr_sta = 0; /* G0 */
3931 hc->e1_getclock = 0;
3933 if (debug & DEBUG_HFCMULTI_INIT)
3934 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3936 r_e1_wr_sta = 0; /* F0 */
3937 hc->e1_getclock = 1;
3939 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3940 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3942 HFC_outb(hc, R_SYNC_OUT, 0);
3943 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3944 hc->e1_getclock = 1;
3945 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3946 hc->e1_getclock = 0;
3947 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3948 /* SLAVE (clock master) */
3949 if (debug & DEBUG_HFCMULTI_INIT)
3951 "%s: E1 port is clock master "
3952 "(clock from PCM)\n", __func__);
3953 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3955 if (hc->e1_getclock) {
3956 /* MASTER (clock slave) */
3957 if (debug & DEBUG_HFCMULTI_INIT)
3959 "%s: E1 port is clock slave "
3960 "(clock to PCM)\n", __func__);
3961 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3963 /* MASTER (clock master) */
3964 if (debug & DEBUG_HFCMULTI_INIT)
3965 printk(KERN_DEBUG "%s: E1 port is "
3967 "(clock from QUARTZ)\n",
3969 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3970 V_PCM_SYNC | V_JATT_OFF);
3971 HFC_outb(hc, R_SYNC_OUT, 0);
3974 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3975 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3976 HFC_outb(hc, R_PWM0, 0x50);
3977 HFC_outb(hc, R_PWM1, 0xff);
3978 /* state machine setup */
3979 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3980 udelay(6); /* wait at least 5,21us */
3981 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3982 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3983 hc->syncronized = 0;
3984 plxsd_checksync(hc, 0);
3987 if (hc->ctype != HFC_TYPE_E1) {
3989 hc->chan[i].slot_tx = -1;
3990 hc->chan[i].slot_rx = -1;
3991 hc->chan[i].conf = -1;
3992 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3993 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3994 hc->chan[i - 2].slot_tx = -1;
3995 hc->chan[i - 2].slot_rx = -1;
3996 hc->chan[i - 2].conf = -1;
3997 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3998 hc->chan[i - 1].slot_tx = -1;
3999 hc->chan[i - 1].slot_rx = -1;
4000 hc->chan[i - 1].conf = -1;
4001 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
4002 /* select interface */
4003 HFC_outb(hc, R_ST_SEL, pt);
4004 /* undocumented: delay after R_ST_SEL */
4006 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
4007 if (debug & DEBUG_HFCMULTI_INIT)
4009 "%s: ST port %d is NT-mode\n",
4012 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
4013 a_st_wr_state = 1; /* G1 */
4014 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
4016 if (debug & DEBUG_HFCMULTI_INIT)
4018 "%s: ST port %d is TE-mode\n",
4021 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
4022 a_st_wr_state = 2; /* F2 */
4023 hc->hw.a_st_ctrl0[pt] = 0;
4025 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4026 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
4027 if (hc->ctype == HFC_TYPE_XHFC) {
4028 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4029 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4030 0x7c << 1 /* V_ST_PULSE */);
4033 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
4034 /* disable E-channel */
4035 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4036 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4037 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4039 HFC_outb(hc, A_ST_CTRL1, 0);
4040 /* enable B-channel receive */
4041 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
4042 /* state machine setup */
4043 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4044 udelay(6); /* wait at least 5,21us */
4045 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4046 hc->hw.r_sci_msk |= 1 << pt;
4047 /* state machine interrupts */
4048 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4049 /* unset sync on port */
4050 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4052 ~(1 << hc->chan[dch->slot].port);
4053 plxsd_checksync(hc, 0);
4056 if (debug & DEBUG_HFCMULTI_INIT)
4057 printk("%s: done\n", __func__);
4062 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4063 struct channel_req *rq)
4068 if (debug & DEBUG_HW_OPEN)
4069 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4070 dch->dev.id, __builtin_return_address(0));
4071 if (rq->protocol == ISDN_P_NONE)
4073 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4074 (dch->dev.D.protocol != rq->protocol)) {
4075 if (debug & DEBUG_HFCMULTI_MODE)
4076 printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4077 __func__, dch->dev.D.protocol, rq->protocol);
4079 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4080 (rq->protocol != ISDN_P_TE_S0))
4081 l1_event(dch->l1, CLOSE_CHANNEL);
4082 if (dch->dev.D.protocol != rq->protocol) {
4083 if (rq->protocol == ISDN_P_TE_S0) {
4084 err = create_l1(dch, hfcm_l1callback);
4088 dch->dev.D.protocol = rq->protocol;
4089 spin_lock_irqsave(&hc->lock, flags);
4090 hfcmulti_initmode(dch);
4091 spin_unlock_irqrestore(&hc->lock, flags);
4093 if (test_bit(FLG_ACTIVE, &dch->Flags))
4094 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4095 0, NULL, GFP_KERNEL);
4096 rq->ch = &dch->dev.D;
4097 if (!try_module_get(THIS_MODULE))
4098 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4103 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4104 struct channel_req *rq)
4106 struct bchannel *bch;
4109 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4111 if (rq->protocol == ISDN_P_NONE)
4113 if (hc->ctype == HFC_TYPE_E1)
4114 ch = rq->adr.channel;
4116 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4117 bch = hc->chan[ch].bch;
4119 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4123 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4124 return -EBUSY; /* b-channel can be only open once */
4125 bch->ch.protocol = rq->protocol;
4126 hc->chan[ch].rx_off = 0;
4128 if (!try_module_get(THIS_MODULE))
4129 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4134 * device control function
4137 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4139 struct hfc_multi *hc = dch->hw;
4141 int wd_mode, wd_cnt;
4144 case MISDN_CTRL_GETOP:
4145 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4147 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4148 wd_cnt = cq->p1 & 0xf;
4149 wd_mode = !!(cq->p1 >> 4);
4150 if (debug & DEBUG_HFCMULTI_MSG)
4151 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4152 ", counter 0x%x\n", __func__,
4153 wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4154 /* set the watchdog timer */
4155 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4156 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4157 if (hc->ctype == HFC_TYPE_XHFC)
4158 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4159 /* init the watchdog register and reset the counter */
4160 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4161 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4162 /* enable the watchdog output for Speech-Design */
4163 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4164 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4165 HFC_outb(hc, R_GPIO_OUT1, 0);
4166 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4169 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4170 if (debug & DEBUG_HFCMULTI_MSG)
4171 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4173 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4175 case MISDN_CTRL_L1_TIMER3:
4176 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4179 printk(KERN_WARNING "%s: unknown Op %x\n",
4188 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4190 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4191 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4192 struct hfc_multi *hc = dch->hw;
4193 struct channel_req *rq;
4197 if (dch->debug & DEBUG_HW)
4198 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4199 __func__, cmd, arg);
4203 switch (rq->protocol) {
4206 if (hc->ctype == HFC_TYPE_E1) {
4210 err = open_dchannel(hc, dch, rq); /* locked there */
4214 if (hc->ctype != HFC_TYPE_E1) {
4218 err = open_dchannel(hc, dch, rq); /* locked there */
4221 spin_lock_irqsave(&hc->lock, flags);
4222 err = open_bchannel(hc, dch, rq);
4223 spin_unlock_irqrestore(&hc->lock, flags);
4227 if (debug & DEBUG_HW_OPEN)
4228 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4229 __func__, dch->dev.id,
4230 __builtin_return_address(0));
4231 module_put(THIS_MODULE);
4233 case CONTROL_CHANNEL:
4234 spin_lock_irqsave(&hc->lock, flags);
4235 err = channel_dctrl(dch, arg);
4236 spin_unlock_irqrestore(&hc->lock, flags);
4239 if (dch->debug & DEBUG_HW)
4240 printk(KERN_DEBUG "%s: unknown command %x\n",
4248 clockctl(void *priv, int enable)
4250 struct hfc_multi *hc = priv;
4252 hc->iclock_on = enable;
4257 * initialize the card
4261 * start timer irq, wait some time and check if we have interrupts.
4262 * if not, reset chip and try again.
4265 init_card(struct hfc_multi *hc)
4269 void __iomem *plx_acc;
4272 if (debug & DEBUG_HFCMULTI_INIT)
4273 printk(KERN_DEBUG "%s: entered\n", __func__);
4275 spin_lock_irqsave(&hc->lock, flags);
4276 /* set interrupts but leave global interrupt disabled */
4277 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4279 spin_unlock_irqrestore(&hc->lock, flags);
4281 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4283 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4289 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4290 spin_lock_irqsave(&plx_lock, plx_flags);
4291 plx_acc = hc->plx_membase + PLX_INTCSR;
4292 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4293 plx_acc); /* enable PCI & LINT1 irq */
4294 spin_unlock_irqrestore(&plx_lock, plx_flags);
4297 if (debug & DEBUG_HFCMULTI_INIT)
4298 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4299 __func__, hc->irq, hc->irqcnt);
4300 err = init_chip(hc);
4304 * Finally enable IRQ output
4305 * this is only allowed, if an IRQ routine is already
4306 * established for this HFC, so don't do that earlier
4308 spin_lock_irqsave(&hc->lock, flags);
4310 spin_unlock_irqrestore(&hc->lock, flags);
4311 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4312 set_current_state(TASK_UNINTERRUPTIBLE);
4313 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4314 /* turn IRQ off until chip is completely initialized */
4315 spin_lock_irqsave(&hc->lock, flags);
4317 spin_unlock_irqrestore(&hc->lock, flags);
4318 if (debug & DEBUG_HFCMULTI_INIT)
4319 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4320 __func__, hc->irq, hc->irqcnt);
4322 if (debug & DEBUG_HFCMULTI_INIT)
4323 printk(KERN_DEBUG "%s: done\n", __func__);
4327 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4328 printk(KERN_INFO "ignoring missing interrupts\n");
4332 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4338 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4339 spin_lock_irqsave(&plx_lock, plx_flags);
4340 plx_acc = hc->plx_membase + PLX_INTCSR;
4341 writew(0x00, plx_acc); /*disable IRQs*/
4342 spin_unlock_irqrestore(&plx_lock, plx_flags);
4345 if (debug & DEBUG_HFCMULTI_INIT)
4346 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4348 free_irq(hc->irq, hc);
4352 if (debug & DEBUG_HFCMULTI_INIT)
4353 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4358 * find pci device and set it up
4362 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4363 const struct pci_device_id *ent)
4365 struct hm_map *m = (struct hm_map *)ent->driver_data;
4368 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4369 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4373 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4375 if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4376 ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
4377 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4378 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4379 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4383 if (hc->pci_dev->irq <= 0) {
4384 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4387 if (pci_enable_device(hc->pci_dev)) {
4388 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4392 hc->ledstate = 0xAFFEAFFE;
4393 hc->opticalsupport = m->opticalsupport;
4396 hc->pci_membase = NULL;
4397 hc->plx_membase = NULL;
4399 /* set memory access methods */
4400 if (m->io_mode) /* use mode from card config */
4401 hc->io_mode = m->io_mode;
4402 switch (hc->io_mode) {
4403 case HFC_IO_MODE_PLXSD:
4404 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4405 hc->slots = 128; /* required */
4406 hc->HFC_outb = HFC_outb_pcimem;
4407 hc->HFC_inb = HFC_inb_pcimem;
4408 hc->HFC_inw = HFC_inw_pcimem;
4409 hc->HFC_wait = HFC_wait_pcimem;
4410 hc->read_fifo = read_fifo_pcimem;
4411 hc->write_fifo = write_fifo_pcimem;
4412 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4413 /* MEMBASE 1 is PLX PCI Bridge */
4415 if (!hc->plx_origmembase) {
4417 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4418 pci_disable_device(hc->pci_dev);
4422 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4423 if (!hc->plx_membase) {
4425 "HFC-multi: failed to remap plx address space. "
4426 "(internal error)\n");
4427 pci_disable_device(hc->pci_dev);
4431 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4432 (u_long)hc->plx_membase, hc->plx_origmembase);
4434 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4435 /* MEMBASE 1 is PLX PCI Bridge */
4436 if (!hc->pci_origmembase) {
4438 "HFC-multi: No IO-Memory for PCI card found\n");
4439 pci_disable_device(hc->pci_dev);
4443 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4444 if (!hc->pci_membase) {
4445 printk(KERN_WARNING "HFC-multi: failed to remap io "
4446 "address space. (internal error)\n");
4447 pci_disable_device(hc->pci_dev);
4452 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4454 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4455 hc->pci_dev->irq, HZ, hc->leds);
4456 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4458 case HFC_IO_MODE_PCIMEM:
4459 hc->HFC_outb = HFC_outb_pcimem;
4460 hc->HFC_inb = HFC_inb_pcimem;
4461 hc->HFC_inw = HFC_inw_pcimem;
4462 hc->HFC_wait = HFC_wait_pcimem;
4463 hc->read_fifo = read_fifo_pcimem;
4464 hc->write_fifo = write_fifo_pcimem;
4465 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4466 if (!hc->pci_origmembase) {
4468 "HFC-multi: No IO-Memory for PCI card found\n");
4469 pci_disable_device(hc->pci_dev);
4473 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4474 if (!hc->pci_membase) {
4476 "HFC-multi: failed to remap io address space. "
4477 "(internal error)\n");
4478 pci_disable_device(hc->pci_dev);
4481 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4482 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4483 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4484 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4486 case HFC_IO_MODE_REGIO:
4487 hc->HFC_outb = HFC_outb_regio;
4488 hc->HFC_inb = HFC_inb_regio;
4489 hc->HFC_inw = HFC_inw_regio;
4490 hc->HFC_wait = HFC_wait_regio;
4491 hc->read_fifo = read_fifo_regio;
4492 hc->write_fifo = write_fifo_regio;
4493 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4494 if (!hc->pci_iobase) {
4496 "HFC-multi: No IO for PCI card found\n");
4497 pci_disable_device(hc->pci_dev);
4501 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4502 printk(KERN_WARNING "HFC-multi: failed to request "
4503 "address space at 0x%08lx (internal error)\n",
4505 pci_disable_device(hc->pci_dev);
4510 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4511 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4512 hc->pci_dev->irq, HZ, hc->leds);
4513 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4516 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4517 pci_disable_device(hc->pci_dev);
4521 pci_set_drvdata(hc->pci_dev, hc);
4523 /* At this point the needed PCI config is done */
4524 /* fifos are still not enabled */
4534 release_port(struct hfc_multi *hc, struct dchannel *dch)
4538 struct bchannel *pb;
4541 pt = hc->chan[ci].port;
4543 if (debug & DEBUG_HFCMULTI_INIT)
4544 printk(KERN_DEBUG "%s: entered for port %d\n",
4547 if (pt >= hc->ports) {
4548 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4553 if (debug & DEBUG_HFCMULTI_INIT)
4554 printk(KERN_DEBUG "%s: releasing port=%d\n",
4557 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4558 l1_event(dch->l1, CLOSE_CHANNEL);
4560 hc->chan[ci].dch = NULL;
4562 if (hc->created[pt]) {
4563 hc->created[pt] = 0;
4564 mISDN_unregister_device(&dch->dev);
4567 spin_lock_irqsave(&hc->lock, flags);
4569 if (dch->timer.function) {
4570 del_timer(&dch->timer);
4571 dch->timer.function = NULL;
4574 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4576 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4577 hc->syncronized = 0;
4578 plxsd_checksync(hc, 1);
4581 for (i = 0; i <= 31; i++) {
4582 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4584 if (hc->chan[i].bch) {
4585 if (debug & DEBUG_HFCMULTI_INIT)
4587 "%s: free port %d channel %d\n",
4588 __func__, hc->chan[i].port + 1, i);
4589 pb = hc->chan[i].bch;
4590 hc->chan[i].bch = NULL;
4591 spin_unlock_irqrestore(&hc->lock, flags);
4592 mISDN_freebchannel(pb);
4594 kfree(hc->chan[i].coeff);
4595 spin_lock_irqsave(&hc->lock, flags);
4600 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4602 ~(1 << hc->chan[ci].port);
4603 plxsd_checksync(hc, 1);
4606 if (hc->chan[ci - 2].bch) {
4607 if (debug & DEBUG_HFCMULTI_INIT)
4609 "%s: free port %d channel %d\n",
4610 __func__, hc->chan[ci - 2].port + 1,
4612 pb = hc->chan[ci - 2].bch;
4613 hc->chan[ci - 2].bch = NULL;
4614 spin_unlock_irqrestore(&hc->lock, flags);
4615 mISDN_freebchannel(pb);
4617 kfree(hc->chan[ci - 2].coeff);
4618 spin_lock_irqsave(&hc->lock, flags);
4620 if (hc->chan[ci - 1].bch) {
4621 if (debug & DEBUG_HFCMULTI_INIT)
4623 "%s: free port %d channel %d\n",
4624 __func__, hc->chan[ci - 1].port + 1,
4626 pb = hc->chan[ci - 1].bch;
4627 hc->chan[ci - 1].bch = NULL;
4628 spin_unlock_irqrestore(&hc->lock, flags);
4629 mISDN_freebchannel(pb);
4631 kfree(hc->chan[ci - 1].coeff);
4632 spin_lock_irqsave(&hc->lock, flags);
4636 spin_unlock_irqrestore(&hc->lock, flags);
4638 if (debug & DEBUG_HFCMULTI_INIT)
4639 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4641 mISDN_freedchannel(dch);
4644 if (debug & DEBUG_HFCMULTI_INIT)
4645 printk(KERN_DEBUG "%s: done!\n", __func__);
4649 release_card(struct hfc_multi *hc)
4654 if (debug & DEBUG_HFCMULTI_INIT)
4655 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4658 /* unregister clock source */
4660 mISDN_unregister_clock(hc->iclock);
4662 /* disable and free irq */
4663 spin_lock_irqsave(&hc->lock, flags);
4665 spin_unlock_irqrestore(&hc->lock, flags);
4668 if (debug & DEBUG_HFCMULTI_INIT)
4669 printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4670 __func__, hc->irq, hc);
4671 free_irq(hc->irq, hc);
4676 /* disable D-channels & B-channels */
4677 if (debug & DEBUG_HFCMULTI_INIT)
4678 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4680 for (ch = 0; ch <= 31; ch++) {
4681 if (hc->chan[ch].dch)
4682 release_port(hc, hc->chan[ch].dch);
4689 /* release hardware */
4690 release_io_hfcmulti(hc);
4692 if (debug & DEBUG_HFCMULTI_INIT)
4693 printk(KERN_DEBUG "%s: remove instance from list\n",
4695 list_del(&hc->list);
4697 if (debug & DEBUG_HFCMULTI_INIT)
4698 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4699 if (hc == syncmaster)
4702 if (debug & DEBUG_HFCMULTI_INIT)
4703 printk(KERN_DEBUG "%s: card successfully removed\n",
4708 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
4710 /* set optical line type */
4711 if (port[Port_cnt] & 0x001) {
4712 if (!m->opticalsupport) {
4714 "This board has no optical "
4717 if (debug & DEBUG_HFCMULTI_INIT)
4719 "%s: PORT set optical "
4720 "interfacs: card(%d) "
4724 test_and_set_bit(HFC_CFG_OPTICAL,
4725 &hc->chan[hc->dnum[0]].cfg);
4728 /* set LOS report */
4729 if (port[Port_cnt] & 0x004) {
4730 if (debug & DEBUG_HFCMULTI_INIT)
4731 printk(KERN_DEBUG "%s: PORT set "
4732 "LOS report: card(%d) port(%d)\n",
4733 __func__, HFC_cnt + 1, 1);
4734 test_and_set_bit(HFC_CFG_REPORT_LOS,
4735 &hc->chan[hc->dnum[0]].cfg);
4737 /* set AIS report */
4738 if (port[Port_cnt] & 0x008) {
4739 if (debug & DEBUG_HFCMULTI_INIT)
4740 printk(KERN_DEBUG "%s: PORT set "
4741 "AIS report: card(%d) port(%d)\n",
4742 __func__, HFC_cnt + 1, 1);
4743 test_and_set_bit(HFC_CFG_REPORT_AIS,
4744 &hc->chan[hc->dnum[0]].cfg);
4746 /* set SLIP report */
4747 if (port[Port_cnt] & 0x010) {
4748 if (debug & DEBUG_HFCMULTI_INIT)
4750 "%s: PORT set SLIP report: "
4751 "card(%d) port(%d)\n",
4752 __func__, HFC_cnt + 1, 1);
4753 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4754 &hc->chan[hc->dnum[0]].cfg);
4756 /* set RDI report */
4757 if (port[Port_cnt] & 0x020) {
4758 if (debug & DEBUG_HFCMULTI_INIT)
4760 "%s: PORT set RDI report: "
4761 "card(%d) port(%d)\n",
4762 __func__, HFC_cnt + 1, 1);
4763 test_and_set_bit(HFC_CFG_REPORT_RDI,
4764 &hc->chan[hc->dnum[0]].cfg);
4766 /* set CRC-4 Mode */
4767 if (!(port[Port_cnt] & 0x100)) {
4768 if (debug & DEBUG_HFCMULTI_INIT)
4769 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4770 " card(%d) port(%d)\n",
4771 __func__, HFC_cnt + 1, 1);
4772 test_and_set_bit(HFC_CFG_CRC4,
4773 &hc->chan[hc->dnum[0]].cfg);
4775 if (debug & DEBUG_HFCMULTI_INIT)
4776 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4777 " report: card(%d) port(%d)\n",
4778 __func__, HFC_cnt + 1, 1);
4780 /* set forced clock */
4781 if (port[Port_cnt] & 0x0200) {
4782 if (debug & DEBUG_HFCMULTI_INIT)
4783 printk(KERN_DEBUG "%s: PORT force getting clock from "
4784 "E1: card(%d) port(%d)\n",
4785 __func__, HFC_cnt + 1, 1);
4786 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4788 if (port[Port_cnt] & 0x0400) {
4789 if (debug & DEBUG_HFCMULTI_INIT)
4790 printk(KERN_DEBUG "%s: PORT force putting clock to "
4791 "E1: card(%d) port(%d)\n",
4792 __func__, HFC_cnt + 1, 1);
4793 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4796 if (port[Port_cnt] & 0x0800) {
4797 if (debug & DEBUG_HFCMULTI_INIT)
4798 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4799 "E1: card(%d) port(%d)\n",
4800 __func__, HFC_cnt + 1, 1);
4801 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4803 /* set elastic jitter buffer */
4804 if (port[Port_cnt] & 0x3000) {
4805 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4806 if (debug & DEBUG_HFCMULTI_INIT)
4808 "%s: PORT set elastic "
4809 "buffer to %d: card(%d) port(%d)\n",
4810 __func__, hc->chan[hc->dnum[0]].jitter,
4813 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4817 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4819 struct dchannel *dch;
4820 struct bchannel *bch;
4822 char name[MISDN_MAX_IDLEN];
4825 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4829 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4831 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4832 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4833 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4834 dch->dev.D.send = handle_dmsg;
4835 dch->dev.D.ctrl = hfcm_dctrl;
4836 dch->slot = hc->dnum[pt];
4837 hc->chan[hc->dnum[pt]].dch = dch;
4838 hc->chan[hc->dnum[pt]].port = pt;
4839 hc->chan[hc->dnum[pt]].nt_timer = -1;
4840 for (ch = 1; ch <= 31; ch++) {
4841 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4843 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4845 printk(KERN_ERR "%s: no memory for bchannel\n",
4850 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4851 if (!hc->chan[ch].coeff) {
4852 printk(KERN_ERR "%s: no memory for coeffs\n",
4861 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4863 bch->ch.send = handle_bmsg;
4864 bch->ch.ctrl = hfcm_bctrl;
4866 list_add(&bch->ch.list, &dch->dev.bchannels);
4867 hc->chan[ch].bch = bch;
4868 hc->chan[ch].port = pt;
4869 set_channelmap(bch->nr, dch->dev.channelmap);
4872 dch->dev.nrbchan = bcount;
4874 init_e1_port_hw(hc, m);
4876 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4879 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4880 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4883 hc->created[pt] = 1;
4886 release_port(hc, dch);
4891 init_multi_port(struct hfc_multi *hc, int pt)
4893 struct dchannel *dch;
4894 struct bchannel *bch;
4896 char name[MISDN_MAX_IDLEN];
4898 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4902 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4904 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4905 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4906 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4907 dch->dev.D.send = handle_dmsg;
4908 dch->dev.D.ctrl = hfcm_dctrl;
4909 dch->dev.nrbchan = 2;
4912 hc->chan[i + 2].dch = dch;
4913 hc->chan[i + 2].port = pt;
4914 hc->chan[i + 2].nt_timer = -1;
4915 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4916 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4918 printk(KERN_ERR "%s: no memory for bchannel\n",
4923 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4924 if (!hc->chan[i + ch].coeff) {
4925 printk(KERN_ERR "%s: no memory for coeffs\n",
4934 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4936 bch->ch.send = handle_bmsg;
4937 bch->ch.ctrl = hfcm_bctrl;
4938 bch->ch.nr = ch + 1;
4939 list_add(&bch->ch.list, &dch->dev.bchannels);
4940 hc->chan[i + ch].bch = bch;
4941 hc->chan[i + ch].port = pt;
4942 set_channelmap(bch->nr, dch->dev.channelmap);
4944 /* set master clock */
4945 if (port[Port_cnt] & 0x001) {
4946 if (debug & DEBUG_HFCMULTI_INIT)
4948 "%s: PROTOCOL set master clock: "
4949 "card(%d) port(%d)\n",
4950 __func__, HFC_cnt + 1, pt + 1);
4951 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4952 printk(KERN_ERR "Error: Master clock "
4953 "for port(%d) of card(%d) is only"
4954 " possible with TE-mode\n",
4955 pt + 1, HFC_cnt + 1);
4959 if (hc->masterclk >= 0) {
4960 printk(KERN_ERR "Error: Master clock "
4961 "for port(%d) of card(%d) already "
4962 "defined for port(%d)\n",
4963 pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4969 /* set transmitter line to non capacitive */
4970 if (port[Port_cnt] & 0x002) {
4971 if (debug & DEBUG_HFCMULTI_INIT)
4973 "%s: PROTOCOL set non capacitive "
4974 "transmitter: card(%d) port(%d)\n",
4975 __func__, HFC_cnt + 1, pt + 1);
4976 test_and_set_bit(HFC_CFG_NONCAP_TX,
4977 &hc->chan[i + 2].cfg);
4979 /* disable E-channel */
4980 if (port[Port_cnt] & 0x004) {
4981 if (debug & DEBUG_HFCMULTI_INIT)
4983 "%s: PROTOCOL disable E-channel: "
4984 "card(%d) port(%d)\n",
4985 __func__, HFC_cnt + 1, pt + 1);
4986 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4987 &hc->chan[i + 2].cfg);
4989 if (hc->ctype == HFC_TYPE_XHFC) {
4990 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4991 HFC_cnt + 1, pt + 1);
4992 ret = mISDN_register_device(&dch->dev, NULL, name);
4994 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4995 hc->ctype, HFC_cnt + 1, pt + 1);
4996 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
5000 hc->created[pt] = 1;
5003 release_port(hc, dch);
5008 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
5009 const struct pci_device_id *ent)
5013 struct hfc_multi *hc;
5015 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
5019 if (HFC_cnt >= MAX_CARDS) {
5020 printk(KERN_ERR "too many cards (max=%d).\n",
5024 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
5025 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
5026 "type[%d] %d was supplied as module parameter\n",
5027 m->vendor_name, m->card_name, m->type, HFC_cnt,
5028 type[HFC_cnt] & 0xff);
5029 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
5030 "first, to see cards and their types.");
5033 if (debug & DEBUG_HFCMULTI_INIT)
5034 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
5035 __func__, m->vendor_name, m->card_name, m->type,
5038 /* allocate card+fifo structure */
5039 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5041 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5044 spin_lock_init(&hc->lock);
5046 hc->ctype = m->type;
5047 hc->ports = m->ports;
5049 hc->pcm = pcm[HFC_cnt];
5050 hc->io_mode = iomode[HFC_cnt];
5051 if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5055 for (ch = 0; ch <= 31; ch++) {
5056 if (!((1 << ch) & dmask[E1_cnt]))
5059 hc->bmask[pt] = bmask[bmask_cnt++];
5060 if ((maskcheck & hc->bmask[pt])
5061 || (dmask[E1_cnt] & hc->bmask[pt])) {
5063 "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5068 maskcheck |= hc->bmask[pt];
5070 "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5071 E1_cnt + 1, ch, hc->bmask[pt]);
5076 if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5077 /* default card layout */
5079 hc->bmask[0] = 0xfffefffe;
5083 /* set chip specific features */
5085 if (type[HFC_cnt] & 0x100) {
5086 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5087 hc->silence = 0xff; /* ulaw silence */
5089 hc->silence = 0x2a; /* alaw silence */
5090 if ((poll >> 1) > sizeof(hc->silence_data)) {
5091 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5096 for (i = 0; i < (poll >> 1); i++)
5097 hc->silence_data[i] = hc->silence;
5099 if (hc->ctype != HFC_TYPE_XHFC) {
5100 if (!(type[HFC_cnt] & 0x200))
5101 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5102 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5105 if (type[HFC_cnt] & 0x800)
5106 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5107 if (type[HFC_cnt] & 0x1000) {
5108 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5109 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5111 if (type[HFC_cnt] & 0x4000)
5112 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5113 if (type[HFC_cnt] & 0x8000)
5114 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5116 if (type[HFC_cnt] & 0x10000)
5118 if (type[HFC_cnt] & 0x20000)
5120 if (type[HFC_cnt] & 0x80000) {
5121 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5123 hc->wdbyte = V_GPIO_OUT2;
5124 printk(KERN_NOTICE "Watchdog enabled\n");
5128 /* setup pci, hc->slots may change due to PLXSD */
5129 ret_err = setup_pci(hc, pdev, ent);
5131 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5132 ret_err = setup_embedded(hc, m);
5135 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5140 if (hc == syncmaster)
5146 hc->HFC_outb_nodebug = hc->HFC_outb;
5147 hc->HFC_inb_nodebug = hc->HFC_inb;
5148 hc->HFC_inw_nodebug = hc->HFC_inw;
5149 hc->HFC_wait_nodebug = hc->HFC_wait;
5150 #ifdef HFC_REGISTER_DEBUG
5151 hc->HFC_outb = HFC_outb_debug;
5152 hc->HFC_inb = HFC_inb_debug;
5153 hc->HFC_inw = HFC_inw_debug;
5154 hc->HFC_wait = HFC_wait_debug;
5156 /* create channels */
5157 for (pt = 0; pt < hc->ports; pt++) {
5158 if (Port_cnt >= MAX_PORTS) {
5159 printk(KERN_ERR "too many ports (max=%d).\n",
5164 if (hc->ctype == HFC_TYPE_E1)
5165 ret_err = init_e1_port(hc, m, pt);
5167 ret_err = init_multi_port(hc, pt);
5168 if (debug & DEBUG_HFCMULTI_INIT)
5170 "%s: Registering D-channel, card(%d) port(%d) "
5172 __func__, HFC_cnt + 1, pt + 1, ret_err);
5175 while (pt) { /* release already registered ports */
5177 if (hc->ctype == HFC_TYPE_E1)
5179 hc->chan[hc->dnum[pt]].dch);
5182 hc->chan[(pt << 2) + 2].dch);
5186 if (hc->ctype != HFC_TYPE_E1)
5187 Port_cnt++; /* for each S0 port */
5189 if (hc->ctype == HFC_TYPE_E1) {
5190 Port_cnt++; /* for each E1 port */
5195 switch (m->dip_type) {
5198 * Get DIP setting for beroNet 1S/2S/4S cards
5199 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5200 * GPI 19/23 (R_GPI_IN2))
5202 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5203 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5204 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5206 /* Port mode (TE/NT) jumpers */
5207 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5209 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5212 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5213 m->vendor_name, m->card_name, dips, pmj);
5217 * Get DIP Setting for beroNet 8S0+ cards
5218 * Enable PCI auxbridge function
5220 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5221 /* prepare access to auxport */
5222 outw(0x4000, hc->pci_iobase + 4);
5224 * some dummy reads are required to
5225 * read valid DIP switch data
5227 dips = inb(hc->pci_iobase);
5228 dips = inb(hc->pci_iobase);
5229 dips = inb(hc->pci_iobase);
5230 dips = ~inb(hc->pci_iobase) & 0x3F;
5231 outw(0x0, hc->pci_iobase + 4);
5232 /* disable PCI auxbridge function */
5233 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5234 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5235 m->vendor_name, m->card_name, dips);
5239 * get DIP Setting for beroNet E1 cards
5240 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5242 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5243 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5244 m->vendor_name, m->card_name, dips);
5249 spin_lock_irqsave(&HFClock, flags);
5250 list_add_tail(&hc->list, &HFClist);
5251 spin_unlock_irqrestore(&HFClock, flags);
5253 /* use as clock source */
5254 if (clock == HFC_cnt + 1)
5255 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5257 /* initialize hardware */
5258 hc->irq = (m->irq) ? : hc->pci_dev->irq;
5259 ret_err = init_card(hc);
5261 printk(KERN_ERR "init card returns %d\n", ret_err);
5266 /* start IRQ and return */
5267 spin_lock_irqsave(&hc->lock, flags);
5269 spin_unlock_irqrestore(&hc->lock, flags);
5273 release_io_hfcmulti(hc);
5274 if (hc == syncmaster)
5280 static void hfc_remove_pci(struct pci_dev *pdev)
5282 struct hfc_multi *card = pci_get_drvdata(pdev);
5286 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5287 "device:%x subvendor:%x subdevice:%x\n",
5288 pdev->vendor, pdev->device,
5289 pdev->subsystem_vendor, pdev->subsystem_device);
5292 spin_lock_irqsave(&HFClock, flags);
5294 spin_unlock_irqrestore(&HFClock, flags);
5297 printk(KERN_DEBUG "%s: drvdata already removed\n",
5302 #define VENDOR_CCD "Cologne Chip AG"
5303 #define VENDOR_BN "beroNet GmbH"
5304 #define VENDOR_DIG "Digium Inc."
5305 #define VENDOR_JH "Junghanns.NET GmbH"
5306 #define VENDOR_PRIM "PrimuX"
5308 static const struct hm_map hfcm_map[] = {
5309 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5310 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5311 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5312 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5313 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5314 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5315 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5316 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5317 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5318 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5319 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5320 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5322 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5323 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5324 HFC_IO_MODE_REGIO, 0},
5325 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5326 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5328 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5329 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5330 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5332 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5333 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5334 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5335 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5337 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5338 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5339 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5341 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5342 HFC_IO_MODE_PLXSD, 0},
5343 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5344 HFC_IO_MODE_PLXSD, 0},
5345 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5346 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5347 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5348 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5349 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5350 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5351 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5352 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5356 #define H(x) ((unsigned long)&hfcm_map[x])
5357 static const struct pci_device_id hfmultipci_ids[] = {
5359 /* Cards with HFC-4S Chip */
5360 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5361 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5362 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5363 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5364 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5365 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5366 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5367 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5368 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5369 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5370 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5371 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5372 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5373 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5374 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5375 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5376 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5377 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5378 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5379 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5380 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5381 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5382 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5383 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5384 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5385 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5386 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5387 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5388 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5389 0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5390 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5391 0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5393 /* Cards with HFC-8S Chip */
5394 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5395 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5396 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5397 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5398 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5399 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5400 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5401 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5402 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5403 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5404 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5405 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5406 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5407 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5408 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5409 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5410 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5411 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
5414 /* Cards with HFC-E1 Chip */
5415 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5416 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5417 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5418 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5419 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5420 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5421 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5422 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5424 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5425 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5426 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5427 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5428 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5429 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5431 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5432 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5433 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5434 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5436 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5437 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5439 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5440 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5441 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5446 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5449 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5451 struct hm_map *m = (struct hm_map *)ent->driver_data;
5454 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5455 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5456 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5457 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5459 "Unknown HFC multiport controller (vendor:%04x device:%04x "
5460 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5461 pdev->device, pdev->subsystem_vendor,
5462 pdev->subsystem_device);
5464 "Please contact the driver maintainer for support.\n");
5467 ret = hfcmulti_init(m, pdev, ent);
5471 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5475 static struct pci_driver hfcmultipci_driver = {
5476 .name = "hfc_multi",
5477 .probe = hfcmulti_probe,
5478 .remove = hfc_remove_pci,
5479 .id_table = hfmultipci_ids,
5483 HFCmulti_cleanup(void)
5485 struct hfc_multi *card, *next;
5487 /* get rid of all devices of this driver */
5488 list_for_each_entry_safe(card, next, &HFClist, list)
5490 pci_unregister_driver(&hfcmultipci_driver);
5500 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5503 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5506 spin_lock_init(&HFClock);
5507 spin_lock_init(&plx_lock);
5509 if (debug & DEBUG_HFCMULTI_INIT)
5510 printk(KERN_DEBUG "%s: init entered\n", __func__);
5537 "%s: Wrong poll value (%d).\n", __func__, poll);
5546 /* Register the embedded devices.
5547 * This should be done before the PCI cards registration */
5565 for (i = 0; i < xhfc; ++i) {
5566 err = hfcmulti_init(&m, NULL, NULL);
5568 printk(KERN_ERR "error registering embedded driver: "
5573 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5576 /* Register the PCI cards */
5577 err = pci_register_driver(&hfcmultipci_driver);
5579 printk(KERN_ERR "error registering pci driver: %x\n", err);
5587 module_init(HFCmulti_init);
5588 module_exit(HFCmulti_cleanup);