drivers/isdn/hardware/mISDN/hfcmulti.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   4  *
   5  * Author       Andreas Eversberg (jolly@eversberg.eu)
   6  * ported to mqueue mechanism:
   7  *              Peter Sprenger (sprengermoving-bytes.de)
   8  *
   9  * inspired by existing hfc-pci driver:
  10  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  11  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  12  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  13  *
  14  * Thanks to Cologne Chip AG for this great controller!
  15  */
  16
  17 /*
  18  * module parameters:
  19  * type:
  20  *      By default (0), the card is automatically detected.
  21  *      Or use the following combinations:
  22  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  23  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  24  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  25  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  26  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  27  *      Bit 10    = spare
  28  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  29  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  30  *      Bit 13    = spare
  31  *      Bit 14    = 0x04000 = Use external ram (128K)
  32  *      Bit 15    = 0x08000 = Use external ram (512K)
  33  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  34  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  35  *      Bit 18    = spare
  36  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  37  * (all other bits are reserved and shall be 0)
  38  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  39  *               bus (PCM master)
  40  *
  41  * port: (optional or required for all ports on all installed cards)
  42  *      HFC-4S/HFC-8S only bits:
  43  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  44  *                          (ony once per chip).
  45  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  46  *                          Don't use this unless you know what you are doing!
  47  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  48  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  49  *               received from port 1
  50  *
  51  *      HFC-E1 only bits:
  52  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  53  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  54  *      Bit 2     = 0x0004 = Report LOS
  55  *      Bit 3     = 0x0008 = Report AIS
  56  *      Bit 4     = 0x0010 = Report SLIP
  57  *      Bit 5     = 0x0020 = Report RDI
  58  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  59  *                           mode instead.
  60  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  61  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  62  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  63  *                           (E1 only)
  64  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  65  *                           for default.
  66  * (all other bits are reserved and shall be 0)
  67  *
  68  * debug:
  69  *      NOTE: only one debug value must be given for all cards
  70  *      enable debugging (see hfc_multi.h for debug options)
  71  *
  72  * poll:
  73  *      NOTE: only one poll value must be given for all cards
  74  *      Give the number of samples for each fifo process.
  75  *      By default 128 is used. Decrease to reduce delay, increase to
  76  *      reduce cpu load. If unsure, don't mess with it!
  77  *      Valid is 8, 16, 32, 64, 128, 256.
  78  *
  79  * pcm:
  80  *      NOTE: only one pcm value must be given for every card.
  81  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  82  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  83  *      If multiple cards are PCM master (because they are not interconnected),
  84  *      each card with PCM master will have increasing PCM id.
  85  *      All PCM busses with the same ID are expected to be connected and have
  86  *      common time slots slots.
  87  *      Only one chip of the PCM bus must be master, the others slave.
  88  *      -1 means no support of PCM bus not even.
  89  *      Omit this value, if all cards are interconnected or none is connected.
  90  *      If unsure, don't give this parameter.
  91  *
  92  * dmask and bmask:
  93  *      NOTE: One dmask value must be given for every HFC-E1 card.
  94  *      If omitted, the E1 card has D-channel on time slot 16, which is default.
  95  *      dmask is a 32 bit mask. The bit must be set for an alternate time slot.
  96  *      If multiple bits are set, multiple virtual card fragments are created.
  97  *      For each bit set, a bmask value must be given. Each bit on the bmask
  98  *      value stands for a B-channel. The bmask may not overlap with dmask or
  99  *      with other bmask values for that card.
 100  *      Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
 101  *              This will create one fragment with D-channel on slot 1 with
 102  *              B-channels on slots 2..15, and a second fragment with D-channel
 103  *              on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
 104  *      If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
 105  *      not function.
 106  *      Example: dmask=0x00000001 bmask=0xfffffffe
 107  *              This will create a port with all 31 usable timeslots as
 108  *              B-channels.
 109  *      If no bits are set on bmask, no B-channel is created for that fragment.
 110  *      Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
 111  *              This will create 31 ports with one D-channel only.
 112  *      If you don't know how to use it, you don't need it!
 113  *
 114  * iomode:
 115  *      NOTE: only one mode value must be given for every card.
 116  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 117  *      By default, the IO mode is pci memory IO (MEMIO).
 118  *      Some cards require specific IO mode, so it cannot be changed.
 119  *      It may be useful to set IO mode to register io (REGIO) to solve
 120  *      PCI bridge problems.
 121  *      If unsure, don't give this parameter.
 122  *
 123  * clockdelay_nt:
 124  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 125  *      Give the value of the clock control register (A_ST_CLK_DLY)
 126  *      of the S/T interfaces in NT mode.
 127  *      This register is needed for the TBR3 certification, so don't change it.
 128  *
 129  * clockdelay_te:
 130  *      NOTE: only one clockdelay_te value must be given once
 131  *      Give the value of the clock control register (A_ST_CLK_DLY)
 132  *      of the S/T interfaces in TE mode.
 133  *      This register is needed for the TBR3 certification, so don't change it.
 134  *
 135  * clock:
 136  *      NOTE: only one clock value must be given once
 137  *      Selects interface with clock source for mISDN and applications.
 138  *      Set to card number starting with 1. Set to -1 to disable.
 139  *      By default, the first card is used as clock source.
 140  *
 141  * hwid:
 142  *      NOTE: only one hwid value must be given once
 143  *      Enable special embedded devices with XHFC controllers.
 144  */
 145
 146 /*
 147  * debug register access (never use this, it will flood your system log)
 148  * #define HFC_REGISTER_DEBUG
 149  */
 150
 151 #define HFC_MULTI_VERSION       "2.03"
 152
 153 #include <linux/interrupt.h>
 154 #include <linux/module.h>
 155 #include <linux/slab.h>
 156 #include <linux/pci.h>
 157 #include <linux/delay.h>
 158 #include <linux/mISDNhw.h>
 159 #include <linux/mISDNdsp.h>
 160
 161 /*
 162   #define IRQCOUNT_DEBUG
 163   #define IRQ_DEBUG
 164 */
 165
 166 #include "hfc_multi.h"
 167 #ifdef ECHOPREP
 168 #include "gaintab.h"
 169 #endif
 170
 171 #define MAX_CARDS       8
 172 #define MAX_PORTS       (8 * MAX_CARDS)
 173 #define MAX_FRAGS       (32 * MAX_CARDS)
 174
 175 static LIST_HEAD(HFClist);
 176 static DEFINE_SPINLOCK(HFClock); /* global hfc list lock */
 177
 178 static void ph_state_change(struct dchannel *);
 179
 180 static struct hfc_multi *syncmaster;
 181 static int plxsd_master; /* if we have a master card (yet) */
 182 static DEFINE_SPINLOCK(plx_lock); /* may not acquire other lock inside */
 183
 184 #define TYP_E1          1
 185 #define TYP_4S          4
 186 #define TYP_8S          8
 187
 188 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 189 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 190 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 191 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 192 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 193                                    (0x60 MUST be included!) */
 194
 195 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 196 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 197 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 198
 199 /*
 200  * module stuff
 201  */
 202
 203 static uint     type[MAX_CARDS];
 204 static int      pcm[MAX_CARDS];
 205 static uint     dmask[MAX_CARDS];
 206 static uint     bmask[MAX_FRAGS];
 207 static uint     iomode[MAX_CARDS];
 208 static uint     port[MAX_PORTS];
 209 static uint     debug;
 210 static uint     poll;
 211 static int      clock;
 212 static uint     timer;
 213 static uint     clockdelay_te = CLKDEL_TE;
 214 static uint     clockdelay_nt = CLKDEL_NT;
 215 #define HWID_NONE       0
 216 #define HWID_MINIP4     1
 217 #define HWID_MINIP8     2
 218 #define HWID_MINIP16    3
 219 static uint     hwid = HWID_NONE;
 220
 221 static int      HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
 222
 223 MODULE_AUTHOR("Andreas Eversberg");
 224 MODULE_LICENSE("GPL");
 225 MODULE_VERSION(HFC_MULTI_VERSION);
 226 module_param(debug, uint, S_IRUGO | S_IWUSR);
 227 module_param(poll, uint, S_IRUGO | S_IWUSR);
 228 module_param(clock, int, S_IRUGO | S_IWUSR);
 229 module_param(timer, uint, S_IRUGO | S_IWUSR);
 230 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 231 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 232 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 233 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
 234 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
 235 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
 236 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 237 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 238 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
 239
 240 #ifdef HFC_REGISTER_DEBUG
 241 #define HFC_outb(hc, reg, val)                                  \
 242         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 243 #define HFC_outb_nodebug(hc, reg, val)                                  \
 244         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 245 #define HFC_inb(hc, reg)                                \
 246         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 247 #define HFC_inb_nodebug(hc, reg)                                \
 248         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 249 #define HFC_inw(hc, reg)                                \
 250         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 251 #define HFC_inw_nodebug(hc, reg)                                \
 252         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 253 #define HFC_wait(hc)                            \
 254         (hc->HFC_wait(hc, __func__, __LINE__))
 255 #define HFC_wait_nodebug(hc)                            \
 256         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 257 #else
 258 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 259 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 260 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 261 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 262 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 263 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 264 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 265 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 266 #endif
 267
 268 #ifdef CONFIG_MISDN_HFCMULTI_8xx
 269 #include "hfc_multi_8xx.h"
 270 #endif
 271
 272 /* HFC_IO_MODE_PCIMEM */
 273 static void
 274 #ifdef HFC_REGISTER_DEBUG
 275 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 276                 const char *function, int line)
 277 #else
 278         HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 279 #endif
 280 {
 281         writeb(val, hc->pci_membase + reg);
 282 }
 283 static u_char
 284 #ifdef HFC_REGISTER_DEBUG
 285 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 286 #else
 287         HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 288 #endif
 289 {
 290         return readb(hc->pci_membase + reg);
 291 }
 292 static u_short
 293 #ifdef HFC_REGISTER_DEBUG
 294 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 295 #else
 296         HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 297 #endif
 298 {
 299         return readw(hc->pci_membase + reg);
 300 }
 301 static void
 302 #ifdef HFC_REGISTER_DEBUG
 303 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 304 #else
 305         HFC_wait_pcimem(struct hfc_multi *hc)
 306 #endif
 307 {
 308         while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
 309                 cpu_relax();
 310 }
 311
 312 /* HFC_IO_MODE_REGIO */
 313 static void
 314 #ifdef HFC_REGISTER_DEBUG
 315 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 316                const char *function, int line)
 317 #else
 318         HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 319 #endif
 320 {
 321         outb(reg, hc->pci_iobase + 4);
 322         outb(val, hc->pci_iobase);
 323 }
 324 static u_char
 325 #ifdef HFC_REGISTER_DEBUG
 326 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 327 #else
 328         HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 329 #endif
 330 {
 331         outb(reg, hc->pci_iobase + 4);
 332         return inb(hc->pci_iobase);
 333 }
 334 static u_short
 335 #ifdef HFC_REGISTER_DEBUG
 336 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 337 #else
 338         HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 339 #endif
 340 {
 341         outb(reg, hc->pci_iobase + 4);
 342         return inw(hc->pci_iobase);
 343 }
 344 static void
 345 #ifdef HFC_REGISTER_DEBUG
 346 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 347 #else
 348         HFC_wait_regio(struct hfc_multi *hc)
 349 #endif
 350 {
 351         outb(R_STATUS, hc->pci_iobase + 4);
 352         while (inb(hc->pci_iobase) & V_BUSY)
 353                 cpu_relax();
 354 }
 355
 356 #ifdef HFC_REGISTER_DEBUG
 357 static void
 358 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 359                const char *function, int line)
 360 {
 361         char regname[256] = "", bits[9] = "xxxxxxxx";
 362         int i;
 363
 364         i = -1;
 365         while (hfc_register_names[++i].name) {
 366                 if (hfc_register_names[i].reg == reg)
 367                         strcat(regname, hfc_register_names[i].name);
 368         }
 369         if (regname[0] == '\0')
 370                 strcpy(regname, "register");
 371
 372         bits[7] = '0' + (!!(val & 1));
 373         bits[6] = '0' + (!!(val & 2));
 374         bits[5] = '0' + (!!(val & 4));
 375         bits[4] = '0' + (!!(val & 8));
 376         bits[3] = '0' + (!!(val & 16));
 377         bits[2] = '0' + (!!(val & 32));
 378         bits[1] = '0' + (!!(val & 64));
 379         bits[0] = '0' + (!!(val & 128));
 380         printk(KERN_DEBUG
 381                "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 382                hc->id, reg, regname, val, bits, function, line);
 383         HFC_outb_nodebug(hc, reg, val);
 384 }
 385 static u_char
 386 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 387 {
 388         char regname[256] = "", bits[9] = "xxxxxxxx";
 389         u_char val = HFC_inb_nodebug(hc, reg);
 390         int i;
 391
 392         i = 0;
 393         while (hfc_register_names[i++].name)
 394                 ;
 395         while (hfc_register_names[++i].name) {
 396                 if (hfc_register_names[i].reg == reg)
 397                         strcat(regname, hfc_register_names[i].name);
 398         }
 399         if (regname[0] == '\0')
 400                 strcpy(regname, "register");
 401
 402         bits[7] = '0' + (!!(val & 1));
 403         bits[6] = '0' + (!!(val & 2));
 404         bits[5] = '0' + (!!(val & 4));
 405         bits[4] = '0' + (!!(val & 8));
 406         bits[3] = '0' + (!!(val & 16));
 407         bits[2] = '0' + (!!(val & 32));
 408         bits[1] = '0' + (!!(val & 64));
 409         bits[0] = '0' + (!!(val & 128));
 410         printk(KERN_DEBUG
 411                "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 412                hc->id, reg, regname, val, bits, function, line);
 413         return val;
 414 }
 415 static u_short
 416 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 417 {
 418         char regname[256] = "";
 419         u_short val = HFC_inw_nodebug(hc, reg);
 420         int i;
 421
 422         i = 0;
 423         while (hfc_register_names[i++].name)
 424                 ;
 425         while (hfc_register_names[++i].name) {
 426                 if (hfc_register_names[i].reg == reg)
 427                         strcat(regname, hfc_register_names[i].name);
 428         }
 429         if (regname[0] == '\0')
 430                 strcpy(regname, "register");
 431
 432         printk(KERN_DEBUG
 433                "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 434                hc->id, reg, regname, val, function, line);
 435         return val;
 436 }
 437 static void
 438 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 439 {
 440         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 441                hc->id, function, line);
 442         HFC_wait_nodebug(hc);
 443 }
 444 #endif
 445
 446 /* write fifo data (REGIO) */
 447 static void
 448 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 449 {
 450         outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
 451         while (len >> 2) {
 452                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 453                 data += 4;
 454                 len -= 4;
 455         }
 456         while (len >> 1) {
 457                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 458                 data += 2;
 459                 len -= 2;
 460         }
 461         while (len) {
 462                 outb(*data, hc->pci_iobase);
 463                 data++;
 464                 len--;
 465         }
 466 }
 467 /* write fifo data (PCIMEM) */
 468 static void
 469 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 470 {
 471         while (len >> 2) {
 472                 writel(cpu_to_le32(*(u32 *)data),
 473                        hc->pci_membase + A_FIFO_DATA0);
 474                 data += 4;
 475                 len -= 4;
 476         }
 477         while (len >> 1) {
 478                 writew(cpu_to_le16(*(u16 *)data),
 479                        hc->pci_membase + A_FIFO_DATA0);
 480                 data += 2;
 481                 len -= 2;
 482         }
 483         while (len) {
 484                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 485                 data++;
 486                 len--;
 487         }
 488 }
 489
 490 /* read fifo data (REGIO) */
 491 static void
 492 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 493 {
 494         outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
 495         while (len >> 2) {
 496                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 497                 data += 4;
 498                 len -= 4;
 499         }
 500         while (len >> 1) {
 501                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 502                 data += 2;
 503                 len -= 2;
 504         }
 505         while (len) {
 506                 *data = inb(hc->pci_iobase);
 507                 data++;
 508                 len--;
 509         }
 510 }
 511
 512 /* read fifo data (PCIMEM) */
 513 static void
 514 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 515 {
 516         while (len >> 2) {
 517                 *(u32 *)data =
 518                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 519                 data += 4;
 520                 len -= 4;
 521         }
 522         while (len >> 1) {
 523                 *(u16 *)data =
 524                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 525                 data += 2;
 526                 len -= 2;
 527         }
 528         while (len) {
 529                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 530                 data++;
 531                 len--;
 532         }
 533 }
 534
 535 static void
 536 enable_hwirq(struct hfc_multi *hc)
 537 {
 538         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 539         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 540 }
 541
 542 static void
 543 disable_hwirq(struct hfc_multi *hc)
 544 {
 545         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 546         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 547 }
 548
 549 #define NUM_EC 2
 550 #define MAX_TDM_CHAN 32
 551
 552
 553 static inline void
 554 enablepcibridge(struct hfc_multi *c)
 555 {
 556         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 557 }
 558
 559 static inline void
 560 disablepcibridge(struct hfc_multi *c)
 561 {
 562         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 563 }
 564
 565 static inline unsigned char
 566 readpcibridge(struct hfc_multi *hc, unsigned char address)
 567 {
 568         unsigned short cipv;
 569         unsigned char data;
 570
 571         if (!hc->pci_iobase)
 572                 return 0;
 573
 574         /* slow down a PCI read access by 1 PCI clock cycle */
 575         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 576
 577         if (address == 0)
 578                 cipv = 0x4000;
 579         else
 580                 cipv = 0x5800;
 581
 582         /* select local bridge port address by writing to CIP port */
 583         /* data = HFC_inb(c, cipv); * was _io before */
 584         outw(cipv, hc->pci_iobase + 4);
 585         data = inb(hc->pci_iobase);
 586
 587         /* restore R_CTRL for normal PCI read cycle speed */
 588         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 589
 590         return data;
 591 }
 592
 593 static inline void
 594 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 595 {
 596         unsigned short cipv;
 597         unsigned int datav;
 598
 599         if (!hc->pci_iobase)
 600                 return;
 601
 602         if (address == 0)
 603                 cipv = 0x4000;
 604         else
 605                 cipv = 0x5800;
 606
 607         /* select local bridge port address by writing to CIP port */
 608         outw(cipv, hc->pci_iobase + 4);
 609         /* define a 32 bit dword with 4 identical bytes for write sequence */
 610         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 611                 ((__u32) data << 24);
 612
 613         /*
 614          * write this 32 bit dword to the bridge data port
 615          * this will initiate a write sequence of up to 4 writes to the same
 616          * address on the local bus interface the number of write accesses
 617          * is undefined but >=1 and depends on the next PCI transaction
 618          * during write sequence on the local bus
 619          */
 620         outl(datav, hc->pci_iobase);
 621 }
 622
 623 static inline void
 624 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 625 {
 626         /* Do data pin read low byte */
 627         HFC_outb(hc, R_GPIO_OUT1, reg);
 628 }
 629
 630 static inline void
 631 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 632 {
 633         cpld_set_reg(hc, reg);
 634
 635         enablepcibridge(hc);
 636         writepcibridge(hc, 1, val);
 637         disablepcibridge(hc);
 638
 639         return;
 640 }
 641
 642 static inline void
 643 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 644 {
 645         cpld_write_reg(hc, 0, 0xff & addr);
 646         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 647 }
 648
 649 static inline unsigned char
 650 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 651 {
 652         unsigned char res;
 653
 654         vpm_write_address(c, addr);
 655
 656         if (!which)
 657                 cpld_set_reg(c, 2);
 658         else
 659                 cpld_set_reg(c, 3);
 660
 661         enablepcibridge(c);
 662         res = readpcibridge(c, 1);
 663         disablepcibridge(c);
 664
 665         cpld_set_reg(c, 0);
 666
 667         return res;
 668 }
 669
 670 static inline void
 671 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 672         unsigned char data)
 673 {
 674         vpm_write_address(c, addr);
 675
 676         enablepcibridge(c);
 677
 678         if (!which)
 679                 cpld_set_reg(c, 2);
 680         else
 681                 cpld_set_reg(c, 3);
 682
 683         writepcibridge(c, 1, data);
 684
 685         cpld_set_reg(c, 0);
 686
 687         disablepcibridge(c);
 688
 689         {
 690                 unsigned char regin;
 691                 regin = vpm_in(c, which, addr);
 692                 if (regin != data)
 693                         printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 694                                "0x%x\n", data, addr, regin);
 695         }
 696
 697 }
 698
 699
 700 static void
 701 vpm_init(struct hfc_multi *wc)
 702 {
 703         unsigned char reg;
 704         unsigned int mask;
 705         unsigned int i, x, y;
 706         unsigned int ver;
 707
 708         for (x = 0; x < NUM_EC; x++) {
 709                 /* Setup GPIO's */
 710                 if (!x) {
 711                         ver = vpm_in(wc, x, 0x1a0);
 712                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 713                 }
 714
 715                 for (y = 0; y < 4; y++) {
 716                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 717                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 718                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 719                 }
 720
 721                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 722                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 723                 vpm_out(wc, x, 0x1a3, reg & ~2);
 724
 725                 /* Setup Echo length (256 taps) */
 726                 vpm_out(wc, x, 0x022, 1);
 727                 vpm_out(wc, x, 0x023, 0xff);
 728
 729                 /* Setup timeslots */
 730                 vpm_out(wc, x, 0x02f, 0x00);
 731                 mask = 0x02020202 << (x * 4);
 732
 733                 /* Setup the tdm channel masks for all chips */
 734                 for (i = 0; i < 4; i++)
 735                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 736
 737                 /* Setup convergence rate */
 738                 printk(KERN_DEBUG "VPM: A-law mode\n");
 739                 reg = 0x00 | 0x10 | 0x01;
 740                 vpm_out(wc, x, 0x20, reg);
 741                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 742                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 743
 744                 vpm_out(wc, x, 0x24, 0x02);
 745                 reg = vpm_in(wc, x, 0x24);
 746                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 747
 748                 /* Initialize echo cans */
 749                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 750                         if (mask & (0x00000001 << i))
 751                                 vpm_out(wc, x, i, 0x00);
 752                 }
 753
 754                 /*
 755                  * ARM arch at least disallows a udelay of
 756                  * more than 2ms... it gives a fake "__bad_udelay"
 757                  * reference at link-time.
 758                  * long delays in kernel code are pretty sucky anyway
 759                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 760                  */
 761
 762                 udelay(2000);
 763                 udelay(2000);
 764                 udelay(2000);
 765                 udelay(2000);
 766                 udelay(2000);
 767
 768                 /* Put in bypass mode */
 769                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 770                         if (mask & (0x00000001 << i))
 771                                 vpm_out(wc, x, i, 0x01);
 772                 }
 773
 774                 /* Enable bypass */
 775                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 776                         if (mask & (0x00000001 << i))
 777                                 vpm_out(wc, x, 0x78 + i, 0x01);
 778                 }
 779
 780         }
 781 }
 782
 783 #ifdef UNUSED
 784 static void
 785 vpm_check(struct hfc_multi *hctmp)
 786 {
 787         unsigned char gpi2;
 788
 789         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 790
 791         if ((gpi2 & 0x3) != 0x3)
 792                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 793 }
 794 #endif /* UNUSED */
 795
 796
 797 /*
 798  * Interface to enable/disable the HW Echocan
 799  *
 800  * these functions are called within a spin_lock_irqsave on
 801  * the channel instance lock, so we are not disturbed by irqs
 802  *
 803  * we can later easily change the interface to make  other
 804  * things configurable, for now we configure the taps
 805  *
 806  */
 807
 808 static void
 809 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 810 {
 811         unsigned int timeslot;
 812         unsigned int unit;
 813         struct bchannel *bch = hc->chan[ch].bch;
 814 #ifdef TXADJ
 815         int txadj = -4;
 816         struct sk_buff *skb;
 817 #endif
 818         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 819                 return;
 820
 821         if (!bch)
 822                 return;
 823
 824 #ifdef TXADJ
 825         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 826                                sizeof(int), &txadj, GFP_ATOMIC);
 827         if (skb)
 828                 recv_Bchannel_skb(bch, skb);
 829 #endif
 830
 831         timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
 832         unit = ch % 4;
 833
 834         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 835                taps, timeslot);
 836
 837         vpm_out(hc, unit, timeslot, 0x7e);
 838 }
 839
 840 static void
 841 vpm_echocan_off(struct hfc_multi *hc, int ch)
 842 {
 843         unsigned int timeslot;
 844         unsigned int unit;
 845         struct bchannel *bch = hc->chan[ch].bch;
 846 #ifdef TXADJ
 847         int txadj = 0;
 848         struct sk_buff *skb;
 849 #endif
 850
 851         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 852                 return;
 853
 854         if (!bch)
 855                 return;
 856
 857 #ifdef TXADJ
 858         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 859                                sizeof(int), &txadj, GFP_ATOMIC);
 860         if (skb)
 861                 recv_Bchannel_skb(bch, skb);
 862 #endif
 863
 864         timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
 865         unit = ch % 4;
 866
 867         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 868                timeslot);
 869         /* FILLME */
 870         vpm_out(hc, unit, timeslot, 0x01);
 871 }
 872
 873
 874 /*
 875  * Speech Design resync feature
 876  * NOTE: This is called sometimes outside interrupt handler.
 877  * We must lock irqsave, so no other interrupt (other card) will occur!
 878  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 879  */
 880 static inline void
 881 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 882 {
 883         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 884         void __iomem *plx_acc_32;
 885         u_int pv;
 886         u_long flags;
 887
 888         spin_lock_irqsave(&HFClock, flags);
 889         spin_lock(&plx_lock); /* must be locked inside other locks */
 890
 891         if (debug & DEBUG_HFCMULTI_PLXSD)
 892                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 893                        __func__, syncmaster);
 894
 895         /* select new master */
 896         if (newmaster) {
 897                 if (debug & DEBUG_HFCMULTI_PLXSD)
 898                         printk(KERN_DEBUG "using provided controller\n");
 899         } else {
 900                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 901                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 902                                 if (hc->syncronized) {
 903                                         newmaster = hc;
 904                                         break;
 905                                 }
 906                         }
 907                 }
 908         }
 909
 910         /* Disable sync of all cards */
 911         list_for_each_entry_safe(hc, next, &HFClist, list) {
 912                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 913                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 914                         pv = readl(plx_acc_32);
 915                         pv &= ~PLX_SYNC_O_EN;
 916                         writel(pv, plx_acc_32);
 917                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 918                                 pcmmaster = hc;
 919                                 if (hc->ctype == HFC_TYPE_E1) {
 920                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 921                                                 printk(KERN_DEBUG
 922                                                        "Schedule SYNC_I\n");
 923                                         hc->e1_resync |= 1; /* get SYNC_I */
 924                                 }
 925                         }
 926                 }
 927         }
 928
 929         if (newmaster) {
 930                 hc = newmaster;
 931                 if (debug & DEBUG_HFCMULTI_PLXSD)
 932                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 933                                "interface.\n", hc->id, hc);
 934                 /* Enable new sync master */
 935                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 936                 pv = readl(plx_acc_32);
 937                 pv |= PLX_SYNC_O_EN;
 938                 writel(pv, plx_acc_32);
 939                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 940                 if (hc->ctype == HFC_TYPE_E1
 941                     && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 942                         if (debug & DEBUG_HFCMULTI_PLXSD)
 943                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 944                         hc->e1_resync |= 2; /* switch to jatt */
 945                 }
 946         } else {
 947                 if (pcmmaster) {
 948                         hc = pcmmaster;
 949                         if (debug & DEBUG_HFCMULTI_PLXSD)
 950                                 printk(KERN_DEBUG
 951                                        "id=%d (0x%p) = PCM master syncronized "
 952                                        "with QUARTZ\n", hc->id, hc);
 953                         if (hc->ctype == HFC_TYPE_E1) {
 954                                 /* Use the crystal clock for the PCM
 955                                    master card */
 956                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 957                                         printk(KERN_DEBUG
 958                                                "Schedule QUARTZ for HFC-E1\n");
 959                                 hc->e1_resync |= 4; /* switch quartz */
 960                         } else {
 961                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 962                                         printk(KERN_DEBUG
 963                                                "QUARTZ is automatically "
 964                                                "enabled by HFC-%dS\n", hc->ctype);
 965                         }
 966                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 967                         pv = readl(plx_acc_32);
 968                         pv |= PLX_SYNC_O_EN;
 969                         writel(pv, plx_acc_32);
 970                 } else
 971                         if (!rm)
 972                                 printk(KERN_ERR "%s no pcm master, this MUST "
 973                                        "not happen!\n", __func__);
 974         }
 975         syncmaster = newmaster;
 976
 977         spin_unlock(&plx_lock);
 978         spin_unlock_irqrestore(&HFClock, flags);
 979 }
 980
 981 /* This must be called AND hc must be locked irqsave!!! */
 982 static inline void
 983 plxsd_checksync(struct hfc_multi *hc, int rm)
 984 {
 985         if (hc->syncronized) {
 986                 if (syncmaster == NULL) {
 987                         if (debug & DEBUG_HFCMULTI_PLXSD)
 988                                 printk(KERN_DEBUG "%s: GOT sync on card %d"
 989                                        " (id=%d)\n", __func__, hc->id + 1,
 990                                        hc->id);
 991                         hfcmulti_resync(hc, hc, rm);
 992                 }
 993         } else {
 994                 if (syncmaster == hc) {
 995                         if (debug & DEBUG_HFCMULTI_PLXSD)
 996                                 printk(KERN_DEBUG "%s: LOST sync on card %d"
 997                                        " (id=%d)\n", __func__, hc->id + 1,
 998                                        hc->id);
 999                         hfcmulti_resync(hc, NULL, rm);
1000                 }
1001         }
1002 }
1003
1004
1005 /*
1006  * free hardware resources used by driver
1007  */
1008 static void
1009 release_io_hfcmulti(struct hfc_multi *hc)
1010 {
1011         void __iomem *plx_acc_32;
1012         u_int   pv;
1013         u_long  plx_flags;
1014
1015         if (debug & DEBUG_HFCMULTI_INIT)
1016                 printk(KERN_DEBUG "%s: entered\n", __func__);
1017
1018         /* soft reset also masks all interrupts */
1019         hc->hw.r_cirm |= V_SRES;
1020         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1021         udelay(1000);
1022         hc->hw.r_cirm &= ~V_SRES;
1023         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1024         udelay(1000); /* instead of 'wait' that may cause locking */
1025
1026         /* release Speech Design card, if PLX was initialized */
1027         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1028                 if (debug & DEBUG_HFCMULTI_PLXSD)
1029                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1030                                __func__, hc->id + 1);
1031                 spin_lock_irqsave(&plx_lock, plx_flags);
1032                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1033                 writel(PLX_GPIOC_INIT, plx_acc_32);
1034                 pv = readl(plx_acc_32);
1035                 /* Termination off */
1036                 pv &= ~PLX_TERM_ON;
1037                 /* Disconnect the PCM */
1038                 pv |= PLX_SLAVE_EN_N;
1039                 pv &= ~PLX_MASTER_EN;
1040                 pv &= ~PLX_SYNC_O_EN;
1041                 /* Put the DSP in Reset */
1042                 pv &= ~PLX_DSP_RES_N;
1043                 writel(pv, plx_acc_32);
1044                 if (debug & DEBUG_HFCMULTI_INIT)
1045                         printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1046                                __func__, pv);
1047                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1048         }
1049
1050         /* disable memory mapped ports / io ports */
1051         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1052         if (hc->pci_dev)
1053                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1054         if (hc->pci_membase)
1055                 iounmap(hc->pci_membase);
1056         if (hc->plx_membase)
1057                 iounmap(hc->plx_membase);
1058         if (hc->pci_iobase)
1059                 release_region(hc->pci_iobase, 8);
1060         if (hc->xhfc_membase)
1061                 iounmap((void *)hc->xhfc_membase);
1062
1063         if (hc->pci_dev) {
1064                 pci_disable_device(hc->pci_dev);
1065                 pci_set_drvdata(hc->pci_dev, NULL);
1066         }
1067         if (debug & DEBUG_HFCMULTI_INIT)
1068                 printk(KERN_DEBUG "%s: done\n", __func__);
1069 }
1070
1071 /*
1072  * function called to reset the HFC chip. A complete software reset of chip
1073  * and fifos is done. All configuration of the chip is done.
1074  */
1075
1076 static int
1077 init_chip(struct hfc_multi *hc)
1078 {
1079         u_long                  flags, val, val2 = 0, rev;
1080         int                     i, err = 0;
1081         u_char                  r_conf_en, rval;
1082         void __iomem            *plx_acc_32;
1083         u_int                   pv;
1084         u_long                  plx_flags, hfc_flags;
1085         int                     plx_count;
1086         struct hfc_multi        *pos, *next, *plx_last_hc;
1087
1088         spin_lock_irqsave(&hc->lock, flags);
1089         /* reset all registers */
1090         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1091
1092         /* revision check */
1093         if (debug & DEBUG_HFCMULTI_INIT)
1094                 printk(KERN_DEBUG "%s: entered\n", __func__);
1095         val = HFC_inb(hc, R_CHIP_ID);
1096         if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1097             (val >> 1) != 0x31) {
1098                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1099                 err = -EIO;
1100                 goto out;
1101         }
1102         rev = HFC_inb(hc, R_CHIP_RV);
1103         printk(KERN_INFO
1104                "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1105                val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1106                " (old FIFO handling)" : "");
1107         if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1108                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1109                 printk(KERN_WARNING
1110                        "HFC_multi: NOTE: Your chip is revision 0, "
1111                        "ask Cologne Chip for update. Newer chips "
1112                        "have a better FIFO handling. Old chips "
1113                        "still work but may have slightly lower "
1114                        "HDLC transmit performance.\n");
1115         }
1116         if (rev > 1) {
1117                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1118                        "consider chip revision = %ld. The chip / "
1119                        "bridge may not work.\n", rev);
1120         }
1121
1122         /* set s-ram size */
1123         hc->Flen = 0x10;
1124         hc->Zmin = 0x80;
1125         hc->Zlen = 384;
1126         hc->DTMFbase = 0x1000;
1127         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1128                 if (debug & DEBUG_HFCMULTI_INIT)
1129                         printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
1130                                __func__);
1131                 hc->hw.r_ctrl |= V_EXT_RAM;
1132                 hc->hw.r_ram_sz = 1;
1133                 hc->Flen = 0x20;
1134                 hc->Zmin = 0xc0;
1135                 hc->Zlen = 1856;
1136                 hc->DTMFbase = 0x2000;
1137         }
1138         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1139                 if (debug & DEBUG_HFCMULTI_INIT)
1140                         printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
1141                                __func__);
1142                 hc->hw.r_ctrl |= V_EXT_RAM;
1143                 hc->hw.r_ram_sz = 2;
1144                 hc->Flen = 0x20;
1145                 hc->Zmin = 0xc0;
1146                 hc->Zlen = 8000;
1147                 hc->DTMFbase = 0x2000;
1148         }
1149         if (hc->ctype == HFC_TYPE_XHFC) {
1150                 hc->Flen = 0x8;
1151                 hc->Zmin = 0x0;
1152                 hc->Zlen = 64;
1153                 hc->DTMFbase = 0x0;
1154         }
1155         hc->max_trans = poll << 1;
1156         if (hc->max_trans > hc->Zlen)
1157                 hc->max_trans = hc->Zlen;
1158
1159         /* Speech Design PLX bridge */
1160         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1161                 if (debug & DEBUG_HFCMULTI_PLXSD)
1162                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1163                                __func__, hc->id + 1);
1164                 spin_lock_irqsave(&plx_lock, plx_flags);
1165                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1166                 writel(PLX_GPIOC_INIT, plx_acc_32);
1167                 pv = readl(plx_acc_32);
1168                 /* The first and the last cards are terminating the PCM bus */
1169                 pv |= PLX_TERM_ON; /* hc is currently the last */
1170                 /* Disconnect the PCM */
1171                 pv |= PLX_SLAVE_EN_N;
1172                 pv &= ~PLX_MASTER_EN;
1173                 pv &= ~PLX_SYNC_O_EN;
1174                 /* Put the DSP in Reset */
1175                 pv &= ~PLX_DSP_RES_N;
1176                 writel(pv, plx_acc_32);
1177                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1178                 if (debug & DEBUG_HFCMULTI_INIT)
1179                         printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1180                                __func__, pv);
1181                 /*
1182                  * If we are the 3rd PLXSD card or higher, we must turn
1183                  * termination of last PLXSD card off.
1184                  */
1185                 spin_lock_irqsave(&HFClock, hfc_flags);
1186                 plx_count = 0;
1187                 plx_last_hc = NULL;
1188                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1189                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1190                                 plx_count++;
1191                                 if (pos != hc)
1192                                         plx_last_hc = pos;
1193                         }
1194                 }
1195                 if (plx_count >= 3) {
1196                         if (debug & DEBUG_HFCMULTI_PLXSD)
1197                                 printk(KERN_DEBUG "%s: card %d is between, so "
1198                                        "we disable termination\n",
1199                                        __func__, plx_last_hc->id + 1);
1200                         spin_lock_irqsave(&plx_lock, plx_flags);
1201                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1202                         pv = readl(plx_acc_32);
1203                         pv &= ~PLX_TERM_ON;
1204                         writel(pv, plx_acc_32);
1205                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1206                         if (debug & DEBUG_HFCMULTI_INIT)
1207                                 printk(KERN_DEBUG
1208                                        "%s: term off: PLX_GPIO=%x\n",
1209                                        __func__, pv);
1210                 }
1211                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1212                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1213         }
1214
1215         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1216                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1217
1218         /* we only want the real Z2 read-pointer for revision > 0 */
1219         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1220                 hc->hw.r_ram_sz |= V_FZ_MD;
1221
1222         /* select pcm mode */
1223         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1224                 if (debug & DEBUG_HFCMULTI_INIT)
1225                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1226                                __func__);
1227         } else
1228                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1229                         if (debug & DEBUG_HFCMULTI_INIT)
1230                                 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1231                                        __func__);
1232                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1233                 } else {
1234                         if (debug & DEBUG_HFCMULTI_INIT)
1235                                 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1236                                        __func__);
1237                 }
1238
1239         /* soft reset */
1240         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1241         if (hc->ctype == HFC_TYPE_XHFC)
1242                 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1243                          0x11 /* 16 Bytes TX/RX */);
1244         else
1245                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1246         HFC_outb(hc, R_FIFO_MD, 0);
1247         if (hc->ctype == HFC_TYPE_XHFC)
1248                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1249         else
1250                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1251                         | V_RLD_EPR;
1252         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1253         udelay(100);
1254         hc->hw.r_cirm = 0;
1255         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1256         udelay(100);
1257         if (hc->ctype != HFC_TYPE_XHFC)
1258                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1259
1260         /* Speech Design PLX bridge pcm and sync mode */
1261         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1262                 spin_lock_irqsave(&plx_lock, plx_flags);
1263                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1264                 pv = readl(plx_acc_32);
1265                 /* Connect PCM */
1266                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1267                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1268                         pv |= PLX_SYNC_O_EN;
1269                         if (debug & DEBUG_HFCMULTI_INIT)
1270                                 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1271                                        __func__, pv);
1272                 } else {
1273                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1274                         pv &= ~PLX_SYNC_O_EN;
1275                         if (debug & DEBUG_HFCMULTI_INIT)
1276                                 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1277                                        __func__, pv);
1278                 }
1279                 writel(pv, plx_acc_32);
1280                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1281         }
1282
1283         /* PCM setup */
1284         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1285         if (hc->slots == 32)
1286                 HFC_outb(hc, R_PCM_MD1, 0x00);
1287         if (hc->slots == 64)
1288                 HFC_outb(hc, R_PCM_MD1, 0x10);
1289         if (hc->slots == 128)
1290                 HFC_outb(hc, R_PCM_MD1, 0x20);
1291         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1292         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1293                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1294         else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1295                 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1296         else
1297                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1298         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1299         for (i = 0; i < 256; i++) {
1300                 HFC_outb_nodebug(hc, R_SLOT, i);
1301                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1302                 if (hc->ctype != HFC_TYPE_XHFC)
1303                         HFC_outb_nodebug(hc, A_CONF, 0);
1304                 hc->slot_owner[i] = -1;
1305         }
1306
1307         /* set clock speed */
1308         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1309                 if (debug & DEBUG_HFCMULTI_INIT)
1310                         printk(KERN_DEBUG
1311                                "%s: setting double clock\n", __func__);
1312                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1313         }
1314
1315         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1316                 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1317
1318         /* B410P GPIO */
1319         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1320                 printk(KERN_NOTICE "Setting GPIOs\n");
1321                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1322                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1323                 udelay(1000);
1324                 printk(KERN_NOTICE "calling vpm_init\n");
1325                 vpm_init(hc);
1326         }
1327
1328         /* check if R_F0_CNT counts (8 kHz frame count) */
1329         val = HFC_inb(hc, R_F0_CNTL);
1330         val += HFC_inb(hc, R_F0_CNTH) << 8;
1331         if (debug & DEBUG_HFCMULTI_INIT)
1332                 printk(KERN_DEBUG
1333                        "HFC_multi F0_CNT %ld after reset\n", val);
1334         spin_unlock_irqrestore(&hc->lock, flags);
1335         set_current_state(TASK_UNINTERRUPTIBLE);
1336         schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1337         spin_lock_irqsave(&hc->lock, flags);
1338         val2 = HFC_inb(hc, R_F0_CNTL);
1339         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1340         if (debug & DEBUG_HFCMULTI_INIT)
1341                 printk(KERN_DEBUG
1342                        "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1343                        val2);
1344         if (val2 >= val + 8) { /* 1 ms */
1345                 /* it counts, so we keep the pcm mode */
1346                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1347                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1348                 else
1349                         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1350                                 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1351                         else {
1352                                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1353                                 printk(KERN_INFO "controller is PCM bus SLAVE "
1354                                        "(auto detected)\n");
1355                         }
1356         } else {
1357                 /* does not count */
1358                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1359                 controller_fail:
1360                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1361                                "pulse. Seems that controller fails.\n");
1362                         err = -EIO;
1363                         goto out;
1364                 }
1365                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1366                         printk(KERN_INFO "controller is PCM bus SLAVE "
1367                                "(ignoring missing PCM clock)\n");
1368                 } else {
1369                         /* only one pcm master */
1370                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1371                             && plxsd_master) {
1372                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1373                                        "on another Speech Design card found. "
1374                                        "Please be sure to connect PCM cable.\n");
1375                                 err = -EIO;
1376                                 goto out;
1377                         }
1378                         /* retry with master clock */
1379                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1380                                 spin_lock_irqsave(&plx_lock, plx_flags);
1381                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1382                                 pv = readl(plx_acc_32);
1383                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1384                                 pv |= PLX_SYNC_O_EN;
1385                                 writel(pv, plx_acc_32);
1386                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1387                                 if (debug & DEBUG_HFCMULTI_INIT)
1388                                         printk(KERN_DEBUG "%s: master: "
1389                                                "PLX_GPIO=%x\n", __func__, pv);
1390                         }
1391                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1392                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1393                         spin_unlock_irqrestore(&hc->lock, flags);
1394                         set_current_state(TASK_UNINTERRUPTIBLE);
1395                         schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1396                         spin_lock_irqsave(&hc->lock, flags);
1397                         val2 = HFC_inb(hc, R_F0_CNTL);
1398                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1399                         if (debug & DEBUG_HFCMULTI_INIT)
1400                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1401                                        "10 ms (2nd try)\n", val2);
1402                         if (val2 >= val + 8) { /* 1 ms */
1403                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1404                                                  &hc->chip);
1405                                 printk(KERN_INFO "controller is PCM bus MASTER "
1406                                        "(auto detected)\n");
1407                         } else
1408                                 goto controller_fail;
1409                 }
1410         }
1411
1412         /* Release the DSP Reset */
1413         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1414                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1415                         plxsd_master = 1;
1416                 spin_lock_irqsave(&plx_lock, plx_flags);
1417                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1418                 pv = readl(plx_acc_32);
1419                 pv |=  PLX_DSP_RES_N;
1420                 writel(pv, plx_acc_32);
1421                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1422                 if (debug & DEBUG_HFCMULTI_INIT)
1423                         printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1424                                __func__, pv);
1425         }
1426
1427         /* pcm id */
1428         if (hc->pcm)
1429                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1430                        hc->pcm);
1431         else {
1432                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1433                     || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1434                         PCM_cnt++; /* SD has proprietary bridging */
1435                 }
1436                 hc->pcm = PCM_cnt;
1437                 printk(KERN_INFO "controller has PCM BUS ID %d "
1438                        "(auto selected)\n", hc->pcm);
1439         }
1440
1441         /* set up timer */
1442         HFC_outb(hc, R_TI_WD, poll_timer);
1443         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1444
1445         /* set E1 state machine IRQ */
1446         if (hc->ctype == HFC_TYPE_E1)
1447                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1448
1449         /* set DTMF detection */
1450         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1451                 if (debug & DEBUG_HFCMULTI_INIT)
1452                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1453                                "for all B-channel\n", __func__);
1454                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1455                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1456                         hc->hw.r_dtmf |= V_ULAW_SEL;
1457                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1458                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1459         }
1460
1461         /* conference engine */
1462         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1463                 r_conf_en = V_CONF_EN | V_ULAW;
1464         else
1465                 r_conf_en = V_CONF_EN;
1466         if (hc->ctype != HFC_TYPE_XHFC)
1467                 HFC_outb(hc, R_CONF_EN, r_conf_en);
1468
1469         /* setting leds */
1470         switch (hc->leds) {
1471         case 1: /* HFC-E1 OEM */
1472                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1473                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1474                 else
1475                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1476
1477                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1478                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1479
1480                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1481                 break;
1482
1483         case 2: /* HFC-4S OEM */
1484         case 3:
1485                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1486                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1487                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1488                 break;
1489         }
1490
1491         if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1492                 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1493                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1494         }
1495
1496         /* set master clock */
1497         if (hc->masterclk >= 0) {
1498                 if (debug & DEBUG_HFCMULTI_INIT)
1499                         printk(KERN_DEBUG "%s: setting ST master clock "
1500                                "to port %d (0..%d)\n",
1501                                __func__, hc->masterclk, hc->ports - 1);
1502                 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1503                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1504         }
1505
1506
1507
1508         /* setting misc irq */
1509         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1510         if (debug & DEBUG_HFCMULTI_INIT)
1511                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1512                        hc->hw.r_irqmsk_misc);
1513
1514         /* RAM access test */
1515         HFC_outb(hc, R_RAM_ADDR0, 0);
1516         HFC_outb(hc, R_RAM_ADDR1, 0);
1517         HFC_outb(hc, R_RAM_ADDR2, 0);
1518         for (i = 0; i < 256; i++) {
1519                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1520                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1521         }
1522         for (i = 0; i < 256; i++) {
1523                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1524                 HFC_inb_nodebug(hc, R_RAM_DATA);
1525                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1526                 if (rval != ((i * 3) & 0xff)) {
1527                         printk(KERN_DEBUG
1528                                "addr:%x val:%x should:%x\n", i, rval,
1529                                (i * 3) & 0xff);
1530                         err++;
1531                 }
1532         }
1533         if (err) {
1534                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1535                 err = -EIO;
1536                 goto out;
1537         }
1538
1539         if (debug & DEBUG_HFCMULTI_INIT)
1540                 printk(KERN_DEBUG "%s: done\n", __func__);
1541 out:
1542         spin_unlock_irqrestore(&hc->lock, flags);
1543         return err;
1544 }
1545
1546
1547 /*
1548  * control the watchdog
1549  */
1550 static void
1551 hfcmulti_watchdog(struct hfc_multi *hc)
1552 {
1553         hc->wdcount++;
1554
1555         if (hc->wdcount > 10) {
1556                 hc->wdcount = 0;
1557                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1558                         V_GPIO_OUT3 : V_GPIO_OUT2;
1559
1560                 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1561                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1562                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1563         }
1564 }
1565
1566
1567
1568 /*
1569  * output leds
1570  */
1571 static void
1572 hfcmulti_leds(struct hfc_multi *hc)
1573 {
1574         unsigned long lled;
1575         unsigned long leddw;
1576         int i, state, active, leds;
1577         struct dchannel *dch;
1578         int led[4];
1579
1580         switch (hc->leds) {
1581         case 1: /* HFC-E1 OEM */
1582                 /* 2 red steady:       LOS
1583                  * 1 red steady:       L1 not active
1584                  * 2 green steady:     L1 active
1585                  * 1st green flashing: activity on TX
1586                  * 2nd green flashing: activity on RX
1587                  */
1588                 led[0] = 0;
1589                 led[1] = 0;
1590                 led[2] = 0;
1591                 led[3] = 0;
1592                 dch = hc->chan[hc->dnum[0]].dch;
1593                 if (dch) {
1594                         if (hc->chan[hc->dnum[0]].los)
1595                                 led[1] = 1;
1596                         if (hc->e1_state != 1) {
1597                                 led[0] = 1;
1598                                 hc->flash[2] = 0;
1599                                 hc->flash[3] = 0;
1600                         } else {
1601                                 led[2] = 1;
1602                                 led[3] = 1;
1603                                 if (!hc->flash[2] && hc->activity_tx)
1604                                         hc->flash[2] = poll;
1605                                 if (!hc->flash[3] && hc->activity_rx)
1606                                         hc->flash[3] = poll;
1607                                 if (hc->flash[2] && hc->flash[2] < 1024)
1608                                         led[2] = 0;
1609                                 if (hc->flash[3] && hc->flash[3] < 1024)
1610                                         led[3] = 0;
1611                                 if (hc->flash[2] >= 2048)
1612                                         hc->flash[2] = 0;
1613                                 if (hc->flash[3] >= 2048)
1614                                         hc->flash[3] = 0;
1615                                 if (hc->flash[2])
1616                                         hc->flash[2] += poll;
1617                                 if (hc->flash[3])
1618                                         hc->flash[3] += poll;
1619                         }
1620                 }
1621                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1622                 /* leds are inverted */
1623                 if (leds != (int)hc->ledstate) {
1624                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1625                         hc->ledstate = leds;
1626                 }
1627                 break;
1628
1629         case 2: /* HFC-4S OEM */
1630                 /* red steady:     PH_DEACTIVATE
1631                  * green steady:   PH_ACTIVATE
1632                  * green flashing: activity on TX
1633                  */
1634                 for (i = 0; i < 4; i++) {
1635                         state = 0;
1636                         active = -1;
1637                         dch = hc->chan[(i << 2) | 2].dch;
1638                         if (dch) {
1639                                 state = dch->state;
1640                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1641                                         active = 3;
1642                                 else
1643                                         active = 7;
1644                         }
1645                         if (state) {
1646                                 if (state == active) {
1647                                         led[i] = 1; /* led green */
1648                                         hc->activity_tx |= hc->activity_rx;
1649                                         if (!hc->flash[i] &&
1650                                                 (hc->activity_tx & (1 << i)))
1651                                                         hc->flash[i] = poll;
1652                                         if (hc->flash[i] && hc->flash[i] < 1024)
1653                                                 led[i] = 0; /* led off */
1654                                         if (hc->flash[i] >= 2048)
1655                                                 hc->flash[i] = 0;
1656                                         if (hc->flash[i])
1657                                                 hc->flash[i] += poll;
1658                                 } else {
1659                                         led[i] = 2; /* led red */
1660                                         hc->flash[i] = 0;
1661                                 }
1662                         } else
1663                                 led[i] = 0; /* led off */
1664                 }
1665                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1666                         leds = 0;
1667                         for (i = 0; i < 4; i++) {
1668                                 if (led[i] == 1) {
1669                                         /*green*/
1670                                         leds |= (0x2 << (i * 2));
1671                                 } else if (led[i] == 2) {
1672                                         /*red*/
1673                                         leds |= (0x1 << (i * 2));
1674                                 }
1675                         }
1676                         if (leds != (int)hc->ledstate) {
1677                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1678                                 hc->ledstate = leds;
1679                         }
1680                 } else {
1681                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1682                                 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1683                                 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1684                                 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1685                         if (leds != (int)hc->ledstate) {
1686                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1687                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1688                                 hc->ledstate = leds;
1689                         }
1690                 }
1691                 break;
1692
1693         case 3: /* HFC 1S/2S Beronet */
1694                 /* red steady:     PH_DEACTIVATE
1695                  * green steady:   PH_ACTIVATE
1696                  * green flashing: activity on TX
1697                  */
1698                 for (i = 0; i < 2; i++) {
1699                         state = 0;
1700                         active = -1;
1701                         dch = hc->chan[(i << 2) | 2].dch;
1702                         if (dch) {
1703                                 state = dch->state;
1704                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1705                                         active = 3;
1706                                 else
1707                                         active = 7;
1708                         }
1709                         if (state) {
1710                                 if (state == active) {
1711                                         led[i] = 1; /* led green */
1712                                         hc->activity_tx |= hc->activity_rx;
1713                                         if (!hc->flash[i] &&
1714                                                 (hc->activity_tx & (1 << i)))
1715                                                         hc->flash[i] = poll;
1716                                         if (hc->flash[i] < 1024)
1717                                                 led[i] = 0; /* led off */
1718                                         if (hc->flash[i] >= 2048)
1719                                                 hc->flash[i] = 0;
1720                                         if (hc->flash[i])
1721                                                 hc->flash[i] += poll;
1722                                 } else {
1723                                         led[i] = 2; /* led red */
1724                                         hc->flash[i] = 0;
1725                                 }
1726                         } else
1727                                 led[i] = 0; /* led off */
1728                 }
1729                 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1730                         | ((led[1]&1) << 3);
1731                 if (leds != (int)hc->ledstate) {
1732                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1733                                          ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1734                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1735                                          ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1736                         hc->ledstate = leds;
1737                 }
1738                 break;
1739         case 8: /* HFC 8S+ Beronet */
1740                 /* off:      PH_DEACTIVATE
1741                  * steady:   PH_ACTIVATE
1742                  * flashing: activity on TX
1743                  */
1744                 lled = 0xff; /* leds off */
1745                 for (i = 0; i < 8; i++) {
1746                         state = 0;
1747                         active = -1;
1748                         dch = hc->chan[(i << 2) | 2].dch;
1749                         if (dch) {
1750                                 state = dch->state;
1751                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1752                                         active = 3;
1753                                 else
1754                                         active = 7;
1755                         }
1756                         if (state) {
1757                                 if (state == active) {
1758                                         lled &= ~(1 << i); /* led on */
1759                                         hc->activity_tx |= hc->activity_rx;
1760                                         if (!hc->flash[i] &&
1761                                                 (hc->activity_tx & (1 << i)))
1762                                                         hc->flash[i] = poll;
1763                                         if (hc->flash[i] < 1024)
1764                                                 lled |= 1 << i; /* led off */
1765                                         if (hc->flash[i] >= 2048)
1766                                                 hc->flash[i] = 0;
1767                                         if (hc->flash[i])
1768                                                 hc->flash[i] += poll;
1769                                 } else
1770                                         hc->flash[i] = 0;
1771                         }
1772                 }
1773                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1774                 if (leddw != hc->ledstate) {
1775                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1776                            HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1777                         /* was _io before */
1778                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1779                         outw(0x4000, hc->pci_iobase + 4);
1780                         outl(leddw, hc->pci_iobase);
1781                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1782                         hc->ledstate = leddw;
1783                 }
1784                 break;
1785         }
1786         hc->activity_tx = 0;
1787         hc->activity_rx = 0;
1788 }
1789 /*
1790  * read dtmf coefficients
1791  */
1792
1793 static void
1794 hfcmulti_dtmf(struct hfc_multi *hc)
1795 {
1796         s32             *coeff;
1797         u_int           mantissa;
1798         int             co, ch;
1799         struct bchannel *bch = NULL;
1800         u8              exponent;
1801         int             dtmf = 0;
1802         int             addr;
1803         u16             w_float;
1804         struct sk_buff  *skb;
1805         struct mISDNhead *hh;
1806
1807         if (debug & DEBUG_HFCMULTI_DTMF)
1808                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1809         for (ch = 0; ch <= 31; ch++) {
1810                 /* only process enabled B-channels */
1811                 bch = hc->chan[ch].bch;
1812                 if (!bch)
1813                         continue;
1814                 if (!hc->created[hc->chan[ch].port])
1815                         continue;
1816                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1817                         continue;
1818                 if (debug & DEBUG_HFCMULTI_DTMF)
1819                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1820                                __func__, ch);
1821                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1822                 dtmf = 1;
1823                 for (co = 0; co < 8; co++) {
1824                         /* read W(n-1) coefficient */
1825                         addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1826                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1827                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1828                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1829                                          | V_ADDR_INC);
1830                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1831                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1832                         if (debug & DEBUG_HFCMULTI_DTMF)
1833                                 printk(" %04x", w_float);
1834
1835                         /* decode float (see chip doc) */
1836                         mantissa = w_float & 0x0fff;
1837                         if (w_float & 0x8000)
1838                                 mantissa |= 0xfffff000;
1839                         exponent = (w_float >> 12) & 0x7;
1840                         if (exponent) {
1841                                 mantissa ^= 0x1000;
1842                                 mantissa <<= (exponent - 1);
1843                         }
1844
1845                         /* store coefficient */
1846                         coeff[co << 1] = mantissa;
1847
1848                         /* read W(n) coefficient */
1849                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1850                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1851                         if (debug & DEBUG_HFCMULTI_DTMF)
1852                                 printk(" %04x", w_float);
1853
1854                         /* decode float (see chip doc) */
1855                         mantissa = w_float & 0x0fff;
1856                         if (w_float & 0x8000)
1857                                 mantissa |= 0xfffff000;
1858                         exponent = (w_float >> 12) & 0x7;
1859                         if (exponent) {
1860                                 mantissa ^= 0x1000;
1861                                 mantissa <<= (exponent - 1);
1862                         }
1863
1864                         /* store coefficient */
1865                         coeff[(co << 1) | 1] = mantissa;
1866                 }
1867                 if (debug & DEBUG_HFCMULTI_DTMF)
1868                         printk(" DTMF ready %08x %08x %08x %08x "
1869                                "%08x %08x %08x %08x\n",
1870                                coeff[0], coeff[1], coeff[2], coeff[3],
1871                                coeff[4], coeff[5], coeff[6], coeff[7]);
1872                 hc->chan[ch].coeff_count++;
1873                 if (hc->chan[ch].coeff_count == 8) {
1874                         hc->chan[ch].coeff_count = 0;
1875                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1876                         if (!skb) {
1877                                 printk(KERN_DEBUG "%s: No memory for skb\n",
1878                                        __func__);
1879                                 continue;
1880                         }
1881                         hh = mISDN_HEAD_P(skb);
1882                         hh->prim = PH_CONTROL_IND;
1883                         hh->id = DTMF_HFC_COEF;
1884                         skb_put_data(skb, hc->chan[ch].coeff, 512);
1885                         recv_Bchannel_skb(bch, skb);
1886                 }
1887         }
1888
1889         /* restart DTMF processing */
1890         hc->dtmf = dtmf;
1891         if (dtmf)
1892                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1893 }
1894
1895
1896 /*
1897  * fill fifo as much as possible
1898  */
1899
1900 static void
1901 hfcmulti_tx(struct hfc_multi *hc, int ch)
1902 {
1903         int i, ii, temp, len = 0;
1904         int Zspace, z1, z2; /* must be int for calculation */
1905         int Fspace, f1, f2;
1906         u_char *d;
1907         int *txpending, slot_tx;
1908         struct  bchannel *bch;
1909         struct  dchannel *dch;
1910         struct  sk_buff **sp = NULL;
1911         int *idxp;
1912
1913         bch = hc->chan[ch].bch;
1914         dch = hc->chan[ch].dch;
1915         if ((!dch) && (!bch))
1916                 return;
1917
1918         txpending = &hc->chan[ch].txpending;
1919         slot_tx = hc->chan[ch].slot_tx;
1920         if (dch) {
1921                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1922                         return;
1923                 sp = &dch->tx_skb;
1924                 idxp = &dch->tx_idx;
1925         } else {
1926                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1927                         return;
1928                 sp = &bch->tx_skb;
1929                 idxp = &bch->tx_idx;
1930         }
1931         if (*sp)
1932                 len = (*sp)->len;
1933
1934         if ((!len) && *txpending != 1)
1935                 return; /* no data */
1936
1937         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1938             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1939             (hc->chan[ch].slot_rx < 0) &&
1940             (hc->chan[ch].slot_tx < 0))
1941                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1942         else
1943                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1944         HFC_wait_nodebug(hc);
1945
1946         if (*txpending == 2) {
1947                 /* reset fifo */
1948                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1949                 HFC_wait_nodebug(hc);
1950                 HFC_outb(hc, A_SUBCH_CFG, 0);
1951                 *txpending = 1;
1952         }
1953 next_frame:
1954         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1955                 f1 = HFC_inb_nodebug(hc, A_F1);
1956                 f2 = HFC_inb_nodebug(hc, A_F2);
1957                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1958                         if (debug & DEBUG_HFCMULTI_FIFO)
1959                                 printk(KERN_DEBUG
1960                                        "%s(card %d): reread f2 because %d!=%d\n",
1961                                        __func__, hc->id + 1, temp, f2);
1962                         f2 = temp; /* repeat until F2 is equal */
1963                 }
1964                 Fspace = f2 - f1 - 1;
1965                 if (Fspace < 0)
1966                         Fspace += hc->Flen;
1967                 /*
1968                  * Old FIFO handling doesn't give us the current Z2 read
1969                  * pointer, so we cannot send the next frame before the fifo
1970                  * is empty. It makes no difference except for a slightly
1971                  * lower performance.
1972                  */
1973                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1974                         if (f1 != f2)
1975                                 Fspace = 0;
1976                         else
1977                                 Fspace = 1;
1978                 }
1979                 /* one frame only for ST D-channels, to allow resending */
1980                 if (hc->ctype != HFC_TYPE_E1 && dch) {
1981                         if (f1 != f2)
1982                                 Fspace = 0;
1983                 }
1984                 /* F-counter full condition */
1985                 if (Fspace == 0)
1986                         return;
1987         }
1988         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1989         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1990         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1991                 if (debug & DEBUG_HFCMULTI_FIFO)
1992                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1993                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1994                 z2 = temp; /* repeat unti Z2 is equal */
1995         }
1996         hc->chan[ch].Zfill = z1 - z2;
1997         if (hc->chan[ch].Zfill < 0)
1998                 hc->chan[ch].Zfill += hc->Zlen;
1999         Zspace = z2 - z1;
2000         if (Zspace <= 0)
2001                 Zspace += hc->Zlen;
2002         Zspace -= 4; /* keep not too full, so pointers will not overrun */
2003         /* fill transparent data only to maxinum transparent load (minus 4) */
2004         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2005                 Zspace = Zspace - hc->Zlen + hc->max_trans;
2006         if (Zspace <= 0) /* no space of 4 bytes */
2007                 return;
2008
2009         /* if no data */
2010         if (!len) {
2011                 if (z1 == z2) { /* empty */
2012                         /* if done with FIFO audio data during PCM connection */
2013                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2014                             *txpending && slot_tx >= 0) {
2015                                 if (debug & DEBUG_HFCMULTI_MODE)
2016                                         printk(KERN_DEBUG
2017                                                "%s: reconnecting PCM due to no "
2018                                                "more FIFO data: channel %d "
2019                                                "slot_tx %d\n",
2020                                                __func__, ch, slot_tx);
2021                                 /* connect slot */
2022                                 if (hc->ctype == HFC_TYPE_XHFC)
2023                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2024                                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2025                                 /* Enable FIFO, no interrupt */
2026                                 else
2027                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2028                                                  V_HDLC_TRP | V_IFF);
2029                                 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2030                                 HFC_wait_nodebug(hc);
2031                                 if (hc->ctype == HFC_TYPE_XHFC)
2032                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2033                                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2034                                 /* Enable FIFO, no interrupt */
2035                                 else
2036                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2037                                                  V_HDLC_TRP | V_IFF);
2038                                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2039                                 HFC_wait_nodebug(hc);
2040                         }
2041                         *txpending = 0;
2042                 }
2043                 return; /* no data */
2044         }
2045
2046         /* "fill fifo if empty" feature */
2047         if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2048             && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2049                 if (debug & DEBUG_HFCMULTI_FILL)
2050                         printk(KERN_DEBUG "%s: buffer empty, so we have "
2051                                "underrun\n", __func__);
2052                 /* fill buffer, to prevent future underrun */
2053                 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2054                 Zspace -= (poll >> 1);
2055         }
2056
2057         /* if audio data and connected slot */
2058         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2059             && slot_tx >= 0) {
2060                 if (debug & DEBUG_HFCMULTI_MODE)
2061                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
2062                                "FIFO data: channel %d slot_tx %d\n",
2063                                __func__, ch, slot_tx);
2064                 /* disconnect slot */
2065                 if (hc->ctype == HFC_TYPE_XHFC)
2066                         HFC_outb(hc, A_CON_HDLC, 0x80
2067                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2068                 /* Enable FIFO, no interrupt */
2069                 else
2070                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2071                                  V_HDLC_TRP | V_IFF);
2072                 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2073                 HFC_wait_nodebug(hc);
2074                 if (hc->ctype == HFC_TYPE_XHFC)
2075                         HFC_outb(hc, A_CON_HDLC, 0x80
2076                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2077                 /* Enable FIFO, no interrupt */
2078                 else
2079                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2080                                  V_HDLC_TRP | V_IFF);
2081                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2082                 HFC_wait_nodebug(hc);
2083         }
2084         *txpending = 1;
2085
2086         /* show activity */
2087         if (dch)
2088                 hc->activity_tx |= 1 << hc->chan[ch].port;
2089
2090         /* fill fifo to what we have left */
2091         ii = len;
2092         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2093                 temp = 1;
2094         else
2095                 temp = 0;
2096         i = *idxp;
2097         d = (*sp)->data + i;
2098         if (ii - i > Zspace)
2099                 ii = Zspace + i;
2100         if (debug & DEBUG_HFCMULTI_FIFO)
2101                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2102                        "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2103                        __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2104                        temp ? "HDLC" : "TRANS");
2105
2106         /* Have to prep the audio data */
2107         hc->write_fifo(hc, d, ii - i);
2108         hc->chan[ch].Zfill += ii - i;
2109         *idxp = ii;
2110
2111         /* if not all data has been written */
2112         if (ii != len) {
2113                 /* NOTE: fifo is started by the calling function */
2114                 return;
2115         }
2116
2117         /* if all data has been written, terminate frame */
2118         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2119                 /* increment f-counter */
2120                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2121                 HFC_wait_nodebug(hc);
2122         }
2123
2124         dev_kfree_skb(*sp);
2125         /* check for next frame */
2126         if (bch && get_next_bframe(bch)) {
2127                 len = (*sp)->len;
2128                 goto next_frame;
2129         }
2130         if (dch && get_next_dframe(dch)) {
2131                 len = (*sp)->len;
2132                 goto next_frame;
2133         }
2134
2135         /*
2136          * now we have no more data, so in case of transparent,
2137          * we set the last byte in fifo to 'silence' in case we will get
2138          * no more data at all. this prevents sending an undefined value.
2139          */
2140         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2141                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2142 }
2143
2144
2145 /* NOTE: only called if E1 card is in active state */
2146 static void
2147 hfcmulti_rx(struct hfc_multi *hc, int ch)
2148 {
2149         int temp;
2150         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2151         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2152         int again = 0;
2153         struct  bchannel *bch;
2154         struct  dchannel *dch = NULL;
2155         struct sk_buff  *skb, **sp = NULL;
2156         int     maxlen;
2157
2158         bch = hc->chan[ch].bch;
2159         if (bch) {
2160                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2161                         return;
2162         } else if (hc->chan[ch].dch) {
2163                 dch = hc->chan[ch].dch;
2164                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2165                         return;
2166         } else {
2167                 return;
2168         }
2169 next_frame:
2170         /* on first AND before getting next valid frame, R_FIFO must be written
2171            to. */
2172         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2173             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2174             (hc->chan[ch].slot_rx < 0) &&
2175             (hc->chan[ch].slot_tx < 0))
2176                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2177         else
2178                 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2179         HFC_wait_nodebug(hc);
2180
2181         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2182         if (hc->chan[ch].rx_off) {
2183                 if (bch)
2184                         bch->dropcnt += poll; /* not exact but fair enough */
2185                 return;
2186         }
2187
2188         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2189                 f1 = HFC_inb_nodebug(hc, A_F1);
2190                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2191                         if (debug & DEBUG_HFCMULTI_FIFO)
2192                                 printk(KERN_DEBUG
2193                                        "%s(card %d): reread f1 because %d!=%d\n",
2194                                        __func__, hc->id + 1, temp, f1);
2195                         f1 = temp; /* repeat until F1 is equal */
2196                 }
2197                 f2 = HFC_inb_nodebug(hc, A_F2);
2198         }
2199         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2200         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2201                 if (debug & DEBUG_HFCMULTI_FIFO)
2202                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2203                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2204                 z1 = temp; /* repeat until Z1 is equal */
2205         }
2206         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2207         Zsize = z1 - z2;
2208         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2209                 /* complete hdlc frame */
2210                 Zsize++;
2211         if (Zsize < 0)
2212                 Zsize += hc->Zlen;
2213         /* if buffer is empty */
2214         if (Zsize <= 0)
2215                 return;
2216
2217         if (bch) {
2218                 maxlen = bchannel_get_rxbuf(bch, Zsize);
2219                 if (maxlen < 0) {
2220                         pr_warn("card%d.B%d: No bufferspace for %d bytes\n",
2221                                 hc->id + 1, bch->nr, Zsize);
2222                         return;
2223                 }
2224                 sp = &bch->rx_skb;
2225                 maxlen = bch->maxlen;
2226         } else { /* Dchannel */
2227                 sp = &dch->rx_skb;
2228                 maxlen = dch->maxlen + 3;
2229                 if (*sp == NULL) {
2230                         *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2231                         if (*sp == NULL) {
2232                                 pr_warn("card%d: No mem for dch rx_skb\n",
2233                                         hc->id + 1);
2234                                 return;
2235                         }
2236                 }
2237         }
2238         /* show activity */
2239         if (dch)
2240                 hc->activity_rx |= 1 << hc->chan[ch].port;
2241
2242         /* empty fifo with what we have */
2243         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2244                 if (debug & DEBUG_HFCMULTI_FIFO)
2245                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2246                                "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2247                                "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2248                                Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2249                                f1, f2, Zsize + (*sp)->len, again);
2250                 /* HDLC */
2251                 if ((Zsize + (*sp)->len) > maxlen) {
2252                         if (debug & DEBUG_HFCMULTI_FIFO)
2253                                 printk(KERN_DEBUG
2254                                        "%s(card %d): hdlc-frame too large.\n",
2255                                        __func__, hc->id + 1);
2256                         skb_trim(*sp, 0);
2257                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2258                         HFC_wait_nodebug(hc);
2259                         return;
2260                 }
2261
2262                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2263
2264                 if (f1 != f2) {
2265                         /* increment Z2,F2-counter */
2266                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2267                         HFC_wait_nodebug(hc);
2268                         /* check size */
2269                         if ((*sp)->len < 4) {
2270                                 if (debug & DEBUG_HFCMULTI_FIFO)
2271                                         printk(KERN_DEBUG
2272                                                "%s(card %d): Frame below minimum "
2273                                                "size\n", __func__, hc->id + 1);
2274                                 skb_trim(*sp, 0);
2275                                 goto next_frame;
2276                         }
2277                         /* there is at least one complete frame, check crc */
2278                         if ((*sp)->data[(*sp)->len - 1]) {
2279                                 if (debug & DEBUG_HFCMULTI_CRC)
2280                                         printk(KERN_DEBUG
2281                                                "%s: CRC-error\n", __func__);
2282                                 skb_trim(*sp, 0);
2283                                 goto next_frame;
2284                         }
2285                         skb_trim(*sp, (*sp)->len - 3);
2286                         if ((*sp)->len < MISDN_COPY_SIZE) {
2287                                 skb = *sp;
2288                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2289                                 if (*sp) {
2290                                         skb_put_data(*sp, skb->data, skb->len);
2291                                         skb_trim(skb, 0);
2292                                 } else {
2293                                         printk(KERN_DEBUG "%s: No mem\n",
2294                                                __func__);
2295                                         *sp = skb;
2296                                         skb = NULL;
2297                                 }
2298                         } else {
2299                                 skb = NULL;
2300                         }
2301                         if (debug & DEBUG_HFCMULTI_FIFO) {
2302                                 printk(KERN_DEBUG "%s(card %d):",
2303                                        __func__, hc->id + 1);
2304                                 temp = 0;
2305                                 while (temp < (*sp)->len)
2306                                         printk(" %02x", (*sp)->data[temp++]);
2307                                 printk("\n");
2308                         }
2309                         if (dch)
2310                                 recv_Dchannel(dch);
2311                         else
2312                                 recv_Bchannel(bch, MISDN_ID_ANY, false);
2313                         *sp = skb;
2314                         again++;
2315                         goto next_frame;
2316                 }
2317                 /* there is an incomplete frame */
2318         } else {
2319                 /* transparent */
2320                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2321                 if (debug & DEBUG_HFCMULTI_FIFO)
2322                         printk(KERN_DEBUG
2323                                "%s(card %d): fifo(%d) reading %d bytes "
2324                                "(z1=%04x, z2=%04x) TRANS\n",
2325                                __func__, hc->id + 1, ch, Zsize, z1, z2);
2326                 /* only bch is transparent */
2327                 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2328         }
2329 }
2330
2331
2332 /*
2333  * Interrupt handler
2334  */
2335 static void
2336 signal_state_up(struct dchannel *dch, int info, char *msg)
2337 {
2338         struct sk_buff  *skb;
2339         int             id, data = info;
2340
2341         if (debug & DEBUG_HFCMULTI_STATE)
2342                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2343
2344         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2345
2346         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2347                                GFP_ATOMIC);
2348         if (!skb)
2349                 return;
2350         recv_Dchannel_skb(dch, skb);
2351 }
2352
2353 static inline void
2354 handle_timer_irq(struct hfc_multi *hc)
2355 {
2356         int             ch, temp;
2357         struct dchannel *dch;
2358         u_long          flags;
2359
2360         /* process queued resync jobs */
2361         if (hc->e1_resync) {
2362                 /* lock, so e1_resync gets not changed */
2363                 spin_lock_irqsave(&HFClock, flags);
2364                 if (hc->e1_resync & 1) {
2365                         if (debug & DEBUG_HFCMULTI_PLXSD)
2366                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2367                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2368                         /* disable JATT, if RX_SYNC is set */
2369                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2370                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2371                 }
2372                 if (hc->e1_resync & 2) {
2373                         if (debug & DEBUG_HFCMULTI_PLXSD)
2374                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2375                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2376                 }
2377                 if (hc->e1_resync & 4) {
2378                         if (debug & DEBUG_HFCMULTI_PLXSD)
2379                                 printk(KERN_DEBUG
2380                                        "Enable QUARTZ for HFC-E1\n");
2381                         /* set jatt to quartz */
2382                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2383                                  | V_JATT_OFF);
2384                         /* switch to JATT, in case it is not already */
2385                         HFC_outb(hc, R_SYNC_OUT, 0);
2386                 }
2387                 hc->e1_resync = 0;
2388                 spin_unlock_irqrestore(&HFClock, flags);
2389         }
2390
2391         if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2392                 for (ch = 0; ch <= 31; ch++) {
2393                         if (hc->created[hc->chan[ch].port]) {
2394                                 hfcmulti_tx(hc, ch);
2395                                 /* fifo is started when switching to rx-fifo */
2396                                 hfcmulti_rx(hc, ch);
2397                                 if (hc->chan[ch].dch &&
2398                                     hc->chan[ch].nt_timer > -1) {
2399                                         dch = hc->chan[ch].dch;
2400                                         if (!(--hc->chan[ch].nt_timer)) {
2401                                                 schedule_event(dch,
2402                                                                FLG_PHCHANGE);
2403                                                 if (debug &
2404                                                     DEBUG_HFCMULTI_STATE)
2405                                                         printk(KERN_DEBUG
2406                                                                "%s: nt_timer at "
2407                                                                "state %x\n",
2408                                                                __func__,
2409                                                                dch->state);
2410                                         }
2411                                 }
2412                         }
2413                 }
2414         if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2415                 dch = hc->chan[hc->dnum[0]].dch;
2416                 /* LOS */
2417                 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2418                 hc->chan[hc->dnum[0]].los = temp;
2419                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2420                         if (!temp && hc->chan[hc->dnum[0]].los)
2421                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2422                                                 "LOS detected");
2423                         if (temp && !hc->chan[hc->dnum[0]].los)
2424                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2425                                                 "LOS gone");
2426                 }
2427                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2428                         /* AIS */
2429                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2430                         if (!temp && hc->chan[hc->dnum[0]].ais)
2431                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2432                                                 "AIS detected");
2433                         if (temp && !hc->chan[hc->dnum[0]].ais)
2434                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2435                                                 "AIS gone");
2436                         hc->chan[hc->dnum[0]].ais = temp;
2437                 }
2438                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2439                         /* SLIP */
2440                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2441                         if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2442                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2443                                                 " bit SLIP detected RX");
2444                         hc->chan[hc->dnum[0]].slip_rx = temp;
2445                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2446                         if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2447                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2448                                                 " bit SLIP detected TX");
2449                         hc->chan[hc->dnum[0]].slip_tx = temp;
2450                 }
2451                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2452                         /* RDI */
2453                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2454                         if (!temp && hc->chan[hc->dnum[0]].rdi)
2455                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2456                                                 "RDI detected");
2457                         if (temp && !hc->chan[hc->dnum[0]].rdi)
2458                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2459                                                 "RDI gone");
2460                         hc->chan[hc->dnum[0]].rdi = temp;
2461                 }
2462                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2463                 switch (hc->chan[hc->dnum[0]].sync) {
2464                 case 0:
2465                         if ((temp & 0x60) == 0x60) {
2466                                 if (debug & DEBUG_HFCMULTI_SYNC)
2467                                         printk(KERN_DEBUG
2468                                                "%s: (id=%d) E1 now "
2469                                                "in clock sync\n",
2470                                                __func__, hc->id);
2471                                 HFC_outb(hc, R_RX_OFF,
2472                                     hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2473                                 HFC_outb(hc, R_TX_OFF,
2474                                     hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2475                                 hc->chan[hc->dnum[0]].sync = 1;
2476                                 goto check_framesync;
2477                         }
2478                         break;
2479                 case 1:
2480                         if ((temp & 0x60) != 0x60) {
2481                                 if (debug & DEBUG_HFCMULTI_SYNC)
2482                                         printk(KERN_DEBUG
2483                                                "%s: (id=%d) E1 "
2484                                                "lost clock sync\n",
2485                                                __func__, hc->id);
2486                                 hc->chan[hc->dnum[0]].sync = 0;
2487                                 break;
2488                         }
2489                 check_framesync:
2490                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2491                         if (temp == 0x27) {
2492                                 if (debug & DEBUG_HFCMULTI_SYNC)
2493                                         printk(KERN_DEBUG
2494                                                "%s: (id=%d) E1 "
2495                                                "now in frame sync\n",
2496                                                __func__, hc->id);
2497                                 hc->chan[hc->dnum[0]].sync = 2;
2498                         }
2499                         break;
2500                 case 2:
2501                         if ((temp & 0x60) != 0x60) {
2502                                 if (debug & DEBUG_HFCMULTI_SYNC)
2503                                         printk(KERN_DEBUG
2504                                                "%s: (id=%d) E1 lost "
2505                                                "clock & frame sync\n",
2506                                                __func__, hc->id);
2507                                 hc->chan[hc->dnum[0]].sync = 0;
2508                                 break;
2509                         }
2510                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2511                         if (temp != 0x27) {
2512                                 if (debug & DEBUG_HFCMULTI_SYNC)
2513                                         printk(KERN_DEBUG
2514                                                "%s: (id=%d) E1 "
2515                                                "lost frame sync\n",
2516                                                __func__, hc->id);
2517                                 hc->chan[hc->dnum[0]].sync = 1;
2518                         }
2519                         break;
2520                 }
2521         }
2522
2523         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2524                 hfcmulti_watchdog(hc);
2525
2526         if (hc->leds)
2527                 hfcmulti_leds(hc);
2528 }
2529
2530 static void
2531 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2532 {
2533         struct dchannel *dch;
2534         int             ch;
2535         int             active;
2536         u_char          st_status, temp;
2537
2538         /* state machine */
2539         for (ch = 0; ch <= 31; ch++) {
2540                 if (hc->chan[ch].dch) {
2541                         dch = hc->chan[ch].dch;
2542                         if (r_irq_statech & 1) {
2543                                 HFC_outb_nodebug(hc, R_ST_SEL,
2544                                                  hc->chan[ch].port);
2545                                 /* undocumented: delay after R_ST_SEL */
2546                                 udelay(1);
2547                                 /* undocumented: status changes during read */
2548                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2549                                 while (st_status != (temp =
2550                                                      HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2551                                         if (debug & DEBUG_HFCMULTI_STATE)
2552                                                 printk(KERN_DEBUG "%s: reread "
2553                                                        "STATE because %d!=%d\n",
2554                                                        __func__, temp,
2555                                                        st_status);
2556                                         st_status = temp; /* repeat */
2557                                 }
2558
2559                                 /* Speech Design TE-sync indication */
2560                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2561                                     dch->dev.D.protocol == ISDN_P_TE_S0) {
2562                                         if (st_status & V_FR_SYNC_ST)
2563                                                 hc->syncronized |=
2564                                                         (1 << hc->chan[ch].port);
2565                                         else
2566                                                 hc->syncronized &=
2567                                                         ~(1 << hc->chan[ch].port);
2568                                 }
2569                                 dch->state = st_status & 0x0f;
2570                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2571                                         active = 3;
2572                                 else
2573                                         active = 7;
2574                                 if (dch->state == active) {
2575                                         HFC_outb_nodebug(hc, R_FIFO,
2576                                                          (ch << 1) | 1);
2577                                         HFC_wait_nodebug(hc);
2578                                         HFC_outb_nodebug(hc,
2579                                                          R_INC_RES_FIFO, V_RES_F);
2580                                         HFC_wait_nodebug(hc);
2581                                         dch->tx_idx = 0;
2582                                 }
2583                                 schedule_event(dch, FLG_PHCHANGE);
2584                                 if (debug & DEBUG_HFCMULTI_STATE)
2585                                         printk(KERN_DEBUG
2586                                                "%s: S/T newstate %x port %d\n",
2587                                                __func__, dch->state,
2588                                                hc->chan[ch].port);
2589                         }
2590                         r_irq_statech >>= 1;
2591                 }
2592         }
2593         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2594                 plxsd_checksync(hc, 0);
2595 }
2596
2597 static void
2598 fifo_irq(struct hfc_multi *hc, int block)
2599 {
2600         int     ch, j;
2601         struct dchannel *dch;
2602         struct bchannel *bch;
2603         u_char r_irq_fifo_bl;
2604
2605         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2606         j = 0;
2607         while (j < 8) {
2608                 ch = (block << 2) + (j >> 1);
2609                 dch = hc->chan[ch].dch;
2610                 bch = hc->chan[ch].bch;
2611                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2612                         j += 2;
2613                         continue;
2614                 }
2615                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2616                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2617                         hfcmulti_tx(hc, ch);
2618                         /* start fifo */
2619                         HFC_outb_nodebug(hc, R_FIFO, 0);
2620                         HFC_wait_nodebug(hc);
2621                 }
2622                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2623                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2624                         hfcmulti_tx(hc, ch);
2625                         /* start fifo */
2626                         HFC_outb_nodebug(hc, R_FIFO, 0);
2627                         HFC_wait_nodebug(hc);
2628                 }
2629                 j++;
2630                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2631                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2632                         hfcmulti_rx(hc, ch);
2633                 }
2634                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2635                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2636                         hfcmulti_rx(hc, ch);
2637                 }
2638                 j++;
2639         }
2640 }
2641
2642 #ifdef IRQ_DEBUG
2643 int irqsem;
2644 #endif
2645 static irqreturn_t
2646 hfcmulti_interrupt(int intno, void *dev_id)
2647 {
2648 #ifdef IRQCOUNT_DEBUG
2649         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2650                 iq5 = 0, iq6 = 0, iqcnt = 0;
2651 #endif
2652         struct hfc_multi        *hc = dev_id;
2653         struct dchannel         *dch;
2654         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2655         int                     i;
2656         void __iomem            *plx_acc;
2657         u_short                 wval;
2658         u_char                  e1_syncsta, temp, temp2;
2659         u_long                  flags;
2660
2661         if (!hc) {
2662                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2663                 return IRQ_NONE;
2664         }
2665
2666         spin_lock(&hc->lock);
2667
2668 #ifdef IRQ_DEBUG
2669         if (irqsem)
2670                 printk(KERN_ERR "irq for card %d during irq from "
2671                        "card %d, this is no bug.\n", hc->id + 1, irqsem);
2672         irqsem = hc->id + 1;
2673 #endif
2674 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2675         if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2676                 goto irq_notforus;
2677 #endif
2678         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2679                 spin_lock_irqsave(&plx_lock, flags);
2680                 plx_acc = hc->plx_membase + PLX_INTCSR;
2681                 wval = readw(plx_acc);
2682                 spin_unlock_irqrestore(&plx_lock, flags);
2683                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2684                         goto irq_notforus;
2685         }
2686
2687         status = HFC_inb_nodebug(hc, R_STATUS);
2688         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2689 #ifdef IRQCOUNT_DEBUG
2690         if (r_irq_statech)
2691                 iq1++;
2692         if (status & V_DTMF_STA)
2693                 iq2++;
2694         if (status & V_LOST_STA)
2695                 iq3++;
2696         if (status & V_EXT_IRQSTA)
2697                 iq4++;
2698         if (status & V_MISC_IRQSTA)
2699                 iq5++;
2700         if (status & V_FR_IRQSTA)
2701                 iq6++;
2702         if (iqcnt++ > 5000) {
2703                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2704                        iq1, iq2, iq3, iq4, iq5, iq6);
2705                 iqcnt = 0;
2706         }
2707 #endif
2708
2709         if (!r_irq_statech &&
2710             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2711                         V_MISC_IRQSTA | V_FR_IRQSTA))) {
2712                 /* irq is not for us */
2713                 goto irq_notforus;
2714         }
2715         hc->irqcnt++;
2716         if (r_irq_statech) {
2717                 if (hc->ctype != HFC_TYPE_E1)
2718                         ph_state_irq(hc, r_irq_statech);
2719         }
2720         if (status & V_LOST_STA) {
2721                 /* LOST IRQ */
2722                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2723         }
2724         if (status & V_MISC_IRQSTA) {
2725                 /* misc IRQ */
2726                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2727                 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2728                 if (r_irq_misc & V_STA_IRQ) {
2729                         if (hc->ctype == HFC_TYPE_E1) {
2730                                 /* state machine */
2731                                 dch = hc->chan[hc->dnum[0]].dch;
2732                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2733                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2734                                     && hc->e1_getclock) {
2735                                         if (e1_syncsta & V_FR_SYNC_E1)
2736                                                 hc->syncronized = 1;
2737                                         else
2738                                                 hc->syncronized = 0;
2739                                 }
2740                                 /* undocumented: status changes during read */
2741                                 temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2742                                 while (temp != (temp2 =
2743                                                       HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2744                                         if (debug & DEBUG_HFCMULTI_STATE)
2745                                                 printk(KERN_DEBUG "%s: reread "
2746                                                        "STATE because %d!=%d\n",
2747                                                     __func__, temp, temp2);
2748                                         temp = temp2; /* repeat */
2749                                 }
2750                                 /* broadcast state change to all fragments */
2751                                 if (debug & DEBUG_HFCMULTI_STATE)
2752                                         printk(KERN_DEBUG
2753                                                "%s: E1 (id=%d) newstate %x\n",
2754                                             __func__, hc->id, temp & 0x7);
2755                                 for (i = 0; i < hc->ports; i++) {
2756                                         dch = hc->chan[hc->dnum[i]].dch;
2757                                         dch->state = temp & 0x7;
2758                                         schedule_event(dch, FLG_PHCHANGE);
2759                                 }
2760
2761                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2762                                         plxsd_checksync(hc, 0);
2763                         }
2764                 }
2765                 if (r_irq_misc & V_TI_IRQ) {
2766                         if (hc->iclock_on)
2767                                 mISDN_clock_update(hc->iclock, poll, NULL);
2768                         handle_timer_irq(hc);
2769                 }
2770
2771                 if (r_irq_misc & V_DTMF_IRQ)
2772                         hfcmulti_dtmf(hc);
2773
2774                 if (r_irq_misc & V_IRQ_PROC) {
2775                         static int irq_proc_cnt;
2776                         if (!irq_proc_cnt++)
2777                                 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2778                                        " this should not happen\n", __func__);
2779                 }
2780
2781         }
2782         if (status & V_FR_IRQSTA) {
2783                 /* FIFO IRQ */
2784                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2785                 for (i = 0; i < 8; i++) {
2786                         if (r_irq_oview & (1 << i))
2787                                 fifo_irq(hc, i);
2788                 }
2789         }
2790
2791 #ifdef IRQ_DEBUG
2792         irqsem = 0;
2793 #endif
2794         spin_unlock(&hc->lock);
2795         return IRQ_HANDLED;
2796
2797 irq_notforus:
2798 #ifdef IRQ_DEBUG
2799         irqsem = 0;
2800 #endif
2801         spin_unlock(&hc->lock);
2802         return IRQ_NONE;
2803 }
2804
2805
2806 /*
2807  * timer callback for D-chan busy resolution. Currently no function
2808  */
2809
2810 static void
2811 hfcmulti_dbusy_timer(struct timer_list *t)
2812 {
2813 }
2814
2815
2816 /*
2817  * activate/deactivate hardware for selected channels and mode
2818  *
2819  * configure B-channel with the given protocol
2820  * ch eqals to the HFC-channel (0-31)
2821  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2822  * for S/T, 1-31 for E1)
2823  * the hdlc interrupts will be set/unset
2824  */
2825 static int
2826 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2827               int bank_tx, int slot_rx, int bank_rx)
2828 {
2829         int flow_tx = 0, flow_rx = 0, routing = 0;
2830         int oslot_tx, oslot_rx;
2831         int conf;
2832
2833         if (ch < 0 || ch > 31)
2834                 return -EINVAL;
2835         oslot_tx = hc->chan[ch].slot_tx;
2836         oslot_rx = hc->chan[ch].slot_rx;
2837         conf = hc->chan[ch].conf;
2838
2839         if (debug & DEBUG_HFCMULTI_MODE)
2840                 printk(KERN_DEBUG
2841                        "%s: card %d channel %d protocol %x slot old=%d new=%d "
2842                        "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2843                        __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2844                        bank_tx, oslot_rx, slot_rx, bank_rx);
2845
2846         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2847                 /* remove from slot */
2848                 if (debug & DEBUG_HFCMULTI_MODE)
2849                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2850                                __func__, oslot_tx);
2851                 if (hc->slot_owner[oslot_tx << 1] == ch) {
2852                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2853                         HFC_outb(hc, A_SL_CFG, 0);
2854                         if (hc->ctype != HFC_TYPE_XHFC)
2855                                 HFC_outb(hc, A_CONF, 0);
2856                         hc->slot_owner[oslot_tx << 1] = -1;
2857                 } else {
2858                         if (debug & DEBUG_HFCMULTI_MODE)
2859                                 printk(KERN_DEBUG
2860                                        "%s: we are not owner of this tx slot "
2861                                        "anymore, channel %d is.\n",
2862                                        __func__, hc->slot_owner[oslot_tx << 1]);
2863                 }
2864         }
2865
2866         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2867                 /* remove from slot */
2868                 if (debug & DEBUG_HFCMULTI_MODE)
2869                         printk(KERN_DEBUG
2870                                "%s: remove from slot %d (RX)\n",
2871                                __func__, oslot_rx);
2872                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2873                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2874                         HFC_outb(hc, A_SL_CFG, 0);
2875                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2876                 } else {
2877                         if (debug & DEBUG_HFCMULTI_MODE)
2878                                 printk(KERN_DEBUG
2879                                        "%s: we are not owner of this rx slot "
2880                                        "anymore, channel %d is.\n",
2881                                        __func__,
2882                                        hc->slot_owner[(oslot_rx << 1) | 1]);
2883                 }
2884         }
2885
2886         if (slot_tx < 0) {
2887                 flow_tx = 0x80; /* FIFO->ST */
2888                 /* disable pcm slot */
2889                 hc->chan[ch].slot_tx = -1;
2890                 hc->chan[ch].bank_tx = 0;
2891         } else {
2892                 /* set pcm slot */
2893                 if (hc->chan[ch].txpending)
2894                         flow_tx = 0x80; /* FIFO->ST */
2895                 else
2896                         flow_tx = 0xc0; /* PCM->ST */
2897                 /* put on slot */
2898                 routing = bank_tx ? 0xc0 : 0x80;
2899                 if (conf >= 0 || bank_tx > 1)
2900                         routing = 0x40; /* loop */
2901                 if (debug & DEBUG_HFCMULTI_MODE)
2902                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2903                                " %d flow %02x routing %02x conf %d (TX)\n",
2904                                __func__, ch, slot_tx, bank_tx,
2905                                flow_tx, routing, conf);
2906                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2907                 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2908                 if (hc->ctype != HFC_TYPE_XHFC)
2909                         HFC_outb(hc, A_CONF,
2910                                  (conf < 0) ? 0 : (conf | V_CONF_SL));
2911                 hc->slot_owner[slot_tx << 1] = ch;
2912                 hc->chan[ch].slot_tx = slot_tx;
2913                 hc->chan[ch].bank_tx = bank_tx;
2914         }
2915         if (slot_rx < 0) {
2916                 /* disable pcm slot */
2917                 flow_rx = 0x80; /* ST->FIFO */
2918                 hc->chan[ch].slot_rx = -1;
2919                 hc->chan[ch].bank_rx = 0;
2920         } else {
2921                 /* set pcm slot */
2922                 if (hc->chan[ch].txpending)
2923                         flow_rx = 0x80; /* ST->FIFO */
2924                 else
2925                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2926                 /* put on slot */
2927                 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2928                 if (conf >= 0 || bank_rx > 1)
2929                         routing = 0x40; /* loop */
2930                 if (debug & DEBUG_HFCMULTI_MODE)
2931                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2932                                " %d flow %02x routing %02x conf %d (RX)\n",
2933                                __func__, ch, slot_rx, bank_rx,
2934                                flow_rx, routing, conf);
2935                 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2936                 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2937                 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2938                 hc->chan[ch].slot_rx = slot_rx;
2939                 hc->chan[ch].bank_rx = bank_rx;
2940         }
2941
2942         switch (protocol) {
2943         case (ISDN_P_NONE):
2944                 /* disable TX fifo */
2945                 HFC_outb(hc, R_FIFO, ch << 1);
2946                 HFC_wait(hc);
2947                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2948                 HFC_outb(hc, A_SUBCH_CFG, 0);
2949                 HFC_outb(hc, A_IRQ_MSK, 0);
2950                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2951                 HFC_wait(hc);
2952                 /* disable RX fifo */
2953                 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2954                 HFC_wait(hc);
2955                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2956                 HFC_outb(hc, A_SUBCH_CFG, 0);
2957                 HFC_outb(hc, A_IRQ_MSK, 0);
2958                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2959                 HFC_wait(hc);
2960                 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2961                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2962                                 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
2963                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2964                         /* undocumented: delay after R_ST_SEL */
2965                         udelay(1);
2966                         HFC_outb(hc, A_ST_CTRL0,
2967                                  hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2968                 }
2969                 if (hc->chan[ch].bch) {
2970                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2971                         test_and_clear_bit(FLG_TRANSPARENT,
2972                                            &hc->chan[ch].bch->Flags);
2973                 }
2974                 break;
2975         case (ISDN_P_B_RAW): /* B-channel */
2976
2977                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2978                     (hc->chan[ch].slot_rx < 0) &&
2979                     (hc->chan[ch].slot_tx < 0)) {
2980
2981                         printk(KERN_DEBUG
2982                                "Setting B-channel %d to echo cancelable "
2983                                "state on PCM slot %d\n", ch,
2984                                ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2985                         printk(KERN_DEBUG
2986                                "Enabling pass through for channel\n");
2987                         vpm_out(hc, ch, ((ch / 4) * 8) +
2988                                 ((ch % 4) * 4) + 1, 0x01);
2989                         /* rx path */
2990                         /* S/T -> PCM */
2991                         HFC_outb(hc, R_FIFO, (ch << 1));
2992                         HFC_wait(hc);
2993                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2994                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2995                                               ((ch % 4) * 4) + 1) << 1);
2996                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2997
2998                         /* PCM -> FIFO */
2999                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3000                         HFC_wait(hc);
3001                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3002                         HFC_outb(hc, A_SUBCH_CFG, 0);
3003                         HFC_outb(hc, A_IRQ_MSK, 0);
3004                         if (hc->chan[ch].protocol != protocol) {
3005                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3006                                 HFC_wait(hc);
3007                         }
3008                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3009                                                ((ch % 4) * 4) + 1) << 1) | 1);
3010                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3011
3012                         /* tx path */
3013                         /* PCM -> S/T */
3014                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3015                         HFC_wait(hc);
3016                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3017                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3018                                                ((ch % 4) * 4)) << 1) | 1);
3019                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3020
3021                         /* FIFO -> PCM */
3022                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3023                         HFC_wait(hc);
3024                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3025                         HFC_outb(hc, A_SUBCH_CFG, 0);
3026                         HFC_outb(hc, A_IRQ_MSK, 0);
3027                         if (hc->chan[ch].protocol != protocol) {
3028                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3029                                 HFC_wait(hc);
3030                         }
3031                         /* tx silence */
3032                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3033                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3034                                               ((ch % 4) * 4)) << 1);
3035                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3036                 } else {
3037                         /* enable TX fifo */
3038                         HFC_outb(hc, R_FIFO, ch << 1);
3039                         HFC_wait(hc);
3040                         if (hc->ctype == HFC_TYPE_XHFC)
3041                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3042                                          V_HDLC_TRP | V_IFF);
3043                         /* Enable FIFO, no interrupt */
3044                         else
3045                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3046                                          V_HDLC_TRP | V_IFF);
3047                         HFC_outb(hc, A_SUBCH_CFG, 0);
3048                         HFC_outb(hc, A_IRQ_MSK, 0);
3049                         if (hc->chan[ch].protocol != protocol) {
3050                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3051                                 HFC_wait(hc);
3052                         }
3053                         /* tx silence */
3054                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3055                         /* enable RX fifo */
3056                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3057                         HFC_wait(hc);
3058                         if (hc->ctype == HFC_TYPE_XHFC)
3059                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3060                                          V_HDLC_TRP);
3061                         /* Enable FIFO, no interrupt*/
3062                         else
3063                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3064                                          V_HDLC_TRP);
3065                         HFC_outb(hc, A_SUBCH_CFG, 0);
3066                         HFC_outb(hc, A_IRQ_MSK, 0);
3067                         if (hc->chan[ch].protocol != protocol) {
3068                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3069                                 HFC_wait(hc);
3070                         }
3071                 }
3072                 if (hc->ctype != HFC_TYPE_E1) {
3073                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3074                                 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3075                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3076                         /* undocumented: delay after R_ST_SEL */
3077                         udelay(1);
3078                         HFC_outb(hc, A_ST_CTRL0,
3079                                  hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3080                 }
3081                 if (hc->chan[ch].bch)
3082                         test_and_set_bit(FLG_TRANSPARENT,
3083                                          &hc->chan[ch].bch->Flags);
3084                 break;
3085         case (ISDN_P_B_HDLC): /* B-channel */
3086         case (ISDN_P_TE_S0): /* D-channel */
3087         case (ISDN_P_NT_S0):
3088         case (ISDN_P_TE_E1):
3089         case (ISDN_P_NT_E1):
3090                 /* enable TX fifo */
3091                 HFC_outb(hc, R_FIFO, ch << 1);
3092                 HFC_wait(hc);
3093                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3094                         /* E1 or B-channel */
3095                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3096                         HFC_outb(hc, A_SUBCH_CFG, 0);
3097                 } else {
3098                         /* D-Channel without HDLC fill flags */
3099                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3100                         HFC_outb(hc, A_SUBCH_CFG, 2);
3101                 }
3102                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3103                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3104                 HFC_wait(hc);
3105                 /* enable RX fifo */
3106                 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3107                 HFC_wait(hc);
3108                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3109                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3110                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3111                 else
3112                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3113                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3114                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3115                 HFC_wait(hc);
3116                 if (hc->chan[ch].bch) {
3117                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3118                         if (hc->ctype != HFC_TYPE_E1) {
3119                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3120                                         ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3121                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3122                                 /* undocumented: delay after R_ST_SEL */
3123                                 udelay(1);
3124                                 HFC_outb(hc, A_ST_CTRL0,
3125                                          hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3126                         }
3127                 }
3128                 break;
3129         default:
3130                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3131                        __func__, protocol);
3132                 hc->chan[ch].protocol = ISDN_P_NONE;
3133                 return -ENOPROTOOPT;
3134         }
3135         hc->chan[ch].protocol = protocol;
3136         return 0;
3137 }
3138
3139
3140 /*
3141  * connect/disconnect PCM
3142  */
3143
3144 static void
3145 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3146              int slot_rx, int bank_rx)
3147 {
3148         if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3149                 /* disable PCM */
3150                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3151                 return;
3152         }
3153
3154         /* enable pcm */
3155         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3156                       slot_rx, bank_rx);
3157 }
3158
3159 /*
3160  * set/disable conference
3161  */
3162
3163 static void
3164 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3165 {
3166         if (num >= 0 && num <= 7)
3167                 hc->chan[ch].conf = num;
3168         else
3169                 hc->chan[ch].conf = -1;
3170         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3171                       hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3172                       hc->chan[ch].bank_rx);
3173 }
3174
3175
3176 /*
3177  * set/disable sample loop
3178  */
3179
3180 /* NOTE: this function is experimental and therefore disabled */
3181
3182 /*
3183  * Layer 1 callback function
3184  */
3185 static int
3186 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3187 {
3188         struct hfc_multi        *hc = dch->hw;
3189         struct sk_buff_head     free_queue;
3190         u_long  flags;
3191
3192         switch (cmd) {
3193         case INFO3_P8:
3194         case INFO3_P10:
3195                 break;
3196         case HW_RESET_REQ:
3197                 /* start activation */
3198                 spin_lock_irqsave(&hc->lock, flags);
3199                 if (hc->ctype == HFC_TYPE_E1) {
3200                         if (debug & DEBUG_HFCMULTI_MSG)
3201                                 printk(KERN_DEBUG
3202                                        "%s: HW_RESET_REQ no BRI\n",
3203                                        __func__);
3204                 } else {
3205                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3206                         /* undocumented: delay after R_ST_SEL */
3207                         udelay(1);
3208                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3209                         udelay(6); /* wait at least 5,21us */
3210                         HFC_outb(hc, A_ST_WR_STATE, 3);
3211                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3212                         /* activate */
3213                 }
3214                 spin_unlock_irqrestore(&hc->lock, flags);
3215                 l1_event(dch->l1, HW_POWERUP_IND);
3216                 break;
3217         case HW_DEACT_REQ:
3218                 __skb_queue_head_init(&free_queue);
3219                 /* start deactivation */
3220                 spin_lock_irqsave(&hc->lock, flags);
3221                 if (hc->ctype == HFC_TYPE_E1) {
3222                         if (debug & DEBUG_HFCMULTI_MSG)
3223                                 printk(KERN_DEBUG
3224                                        "%s: HW_DEACT_REQ no BRI\n",
3225                                        __func__);
3226                 } else {
3227                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3228                         /* undocumented: delay after R_ST_SEL */
3229                         udelay(1);
3230                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3231                         /* deactivate */
3232                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3233                                 hc->syncronized &=
3234                                         ~(1 << hc->chan[dch->slot].port);
3235                                 plxsd_checksync(hc, 0);
3236                         }
3237                 }
3238                 skb_queue_splice_init(&dch->squeue, &free_queue);
3239                 if (dch->tx_skb) {
3240                         __skb_queue_tail(&free_queue, dch->tx_skb);
3241                         dch->tx_skb = NULL;
3242                 }
3243                 dch->tx_idx = 0;
3244                 if (dch->rx_skb) {
3245                         __skb_queue_tail(&free_queue, dch->rx_skb);
3246                         dch->rx_skb = NULL;
3247                 }
3248                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3249                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3250                         del_timer(&dch->timer);
3251                 spin_unlock_irqrestore(&hc->lock, flags);
3252                 __skb_queue_purge(&free_queue);
3253                 break;
3254         case HW_POWERUP_REQ:
3255                 spin_lock_irqsave(&hc->lock, flags);
3256                 if (hc->ctype == HFC_TYPE_E1) {
3257                         if (debug & DEBUG_HFCMULTI_MSG)
3258                                 printk(KERN_DEBUG
3259                                        "%s: HW_POWERUP_REQ no BRI\n",
3260                                        __func__);
3261                 } else {
3262                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3263                         /* undocumented: delay after R_ST_SEL */
3264                         udelay(1);
3265                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3266                         udelay(6); /* wait at least 5,21us */
3267                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3268                 }
3269                 spin_unlock_irqrestore(&hc->lock, flags);
3270                 break;
3271         case PH_ACTIVATE_IND:
3272                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3273                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3274                             GFP_ATOMIC);
3275                 break;
3276         case PH_DEACTIVATE_IND:
3277                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3278                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3279                             GFP_ATOMIC);
3280                 break;
3281         default:
3282                 if (dch->debug & DEBUG_HW)
3283                         printk(KERN_DEBUG "%s: unknown command %x\n",
3284                                __func__, cmd);
3285                 return -1;
3286         }
3287         return 0;
3288 }
3289
3290 /*
3291  * Layer2 -> Layer 1 Transfer
3292  */
3293
3294 static int
3295 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3296 {
3297         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3298         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3299         struct hfc_multi        *hc = dch->hw;
3300         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3301         int                     ret = -EINVAL;
3302         unsigned int            id;
3303         u_long                  flags;
3304
3305         switch (hh->prim) {
3306         case PH_DATA_REQ:
3307                 if (skb->len < 1)
3308                         break;
3309                 spin_lock_irqsave(&hc->lock, flags);
3310                 ret = dchannel_senddata(dch, skb);
3311                 if (ret > 0) { /* direct TX */
3312                         id = hh->id; /* skb can be freed */
3313                         hfcmulti_tx(hc, dch->slot);
3314                         ret = 0;
3315                         /* start fifo */
3316                         HFC_outb(hc, R_FIFO, 0);
3317                         HFC_wait(hc);
3318                         spin_unlock_irqrestore(&hc->lock, flags);
3319                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3320                 } else
3321                         spin_unlock_irqrestore(&hc->lock, flags);
3322                 return ret;
3323         case PH_ACTIVATE_REQ:
3324                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3325                         spin_lock_irqsave(&hc->lock, flags);
3326                         ret = 0;
3327                         if (debug & DEBUG_HFCMULTI_MSG)
3328                                 printk(KERN_DEBUG
3329                                        "%s: PH_ACTIVATE port %d (0..%d)\n",
3330                                        __func__, hc->chan[dch->slot].port,
3331                                        hc->ports - 1);
3332                         /* start activation */
3333                         if (hc->ctype == HFC_TYPE_E1) {
3334                                 ph_state_change(dch);
3335                                 if (debug & DEBUG_HFCMULTI_STATE)
3336                                         printk(KERN_DEBUG
3337                                                "%s: E1 report state %x \n",
3338                                                __func__, dch->state);
3339                         } else {
3340                                 HFC_outb(hc, R_ST_SEL,
3341                                          hc->chan[dch->slot].port);
3342                                 /* undocumented: delay after R_ST_SEL */
3343                                 udelay(1);
3344                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3345                                 /* G1 */
3346                                 udelay(6); /* wait at least 5,21us */
3347                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3348                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3349                                          (V_ST_ACT * 3)); /* activate */
3350                                 dch->state = 1;
3351                         }
3352                         spin_unlock_irqrestore(&hc->lock, flags);
3353                 } else
3354                         ret = l1_event(dch->l1, hh->prim);
3355                 break;
3356         case PH_DEACTIVATE_REQ:
3357                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3358                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3359                         struct sk_buff_head free_queue;
3360
3361                         __skb_queue_head_init(&free_queue);
3362                         spin_lock_irqsave(&hc->lock, flags);
3363                         if (debug & DEBUG_HFCMULTI_MSG)
3364                                 printk(KERN_DEBUG
3365                                        "%s: PH_DEACTIVATE port %d (0..%d)\n",
3366                                        __func__, hc->chan[dch->slot].port,
3367                                        hc->ports - 1);
3368                         /* start deactivation */
3369                         if (hc->ctype == HFC_TYPE_E1) {
3370                                 if (debug & DEBUG_HFCMULTI_MSG)
3371                                         printk(KERN_DEBUG
3372                                                "%s: PH_DEACTIVATE no BRI\n",
3373                                                __func__);
3374                         } else {
3375                                 HFC_outb(hc, R_ST_SEL,
3376                                          hc->chan[dch->slot].port);
3377                                 /* undocumented: delay after R_ST_SEL */
3378                                 udelay(1);
3379                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3380                                 /* deactivate */
3381                                 dch->state = 1;
3382                         }
3383                         skb_queue_splice_init(&dch->squeue, &free_queue);
3384                         if (dch->tx_skb) {
3385                                 __skb_queue_tail(&free_queue, dch->tx_skb);
3386                                 dch->tx_skb = NULL;
3387                         }
3388                         dch->tx_idx = 0;
3389                         if (dch->rx_skb) {
3390                                 __skb_queue_tail(&free_queue, dch->rx_skb);
3391                                 dch->rx_skb = NULL;
3392                         }
3393                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3394                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3395                                 del_timer(&dch->timer);
3396 #ifdef FIXME
3397                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3398                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3399 #endif
3400                         ret = 0;
3401                         spin_unlock_irqrestore(&hc->lock, flags);
3402                         __skb_queue_purge(&free_queue);
3403                 } else
3404                         ret = l1_event(dch->l1, hh->prim);
3405                 break;
3406         }
3407         if (!ret)
3408                 dev_kfree_skb(skb);
3409         return ret;
3410 }
3411
3412 static void
3413 deactivate_bchannel(struct bchannel *bch)
3414 {
3415         struct hfc_multi        *hc = bch->hw;
3416         u_long                  flags;
3417
3418         spin_lock_irqsave(&hc->lock, flags);
3419         mISDN_clear_bchannel(bch);
3420         hc->chan[bch->slot].coeff_count = 0;
3421         hc->chan[bch->slot].rx_off = 0;
3422         hc->chan[bch->slot].conf = -1;
3423         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3424         spin_unlock_irqrestore(&hc->lock, flags);
3425 }
3426
3427 static int
3428 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3429 {
3430         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3431         struct hfc_multi        *hc = bch->hw;
3432         int                     ret = -EINVAL;
3433         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3434         unsigned long           flags;
3435
3436         switch (hh->prim) {
3437         case PH_DATA_REQ:
3438                 if (!skb->len)
3439                         break;
3440                 spin_lock_irqsave(&hc->lock, flags);
3441                 ret = bchannel_senddata(bch, skb);
3442                 if (ret > 0) { /* direct TX */
3443                         hfcmulti_tx(hc, bch->slot);
3444                         ret = 0;
3445                         /* start fifo */
3446                         HFC_outb_nodebug(hc, R_FIFO, 0);
3447                         HFC_wait_nodebug(hc);
3448                 }
3449                 spin_unlock_irqrestore(&hc->lock, flags);
3450                 return ret;
3451         case PH_ACTIVATE_REQ:
3452                 if (debug & DEBUG_HFCMULTI_MSG)
3453                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3454                                __func__, bch->slot);
3455                 spin_lock_irqsave(&hc->lock, flags);
3456                 /* activate B-channel if not already activated */
3457                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3458                         hc->chan[bch->slot].txpending = 0;
3459                         ret = mode_hfcmulti(hc, bch->slot,
3460                                             ch->protocol,
3461                                             hc->chan[bch->slot].slot_tx,
3462                                             hc->chan[bch->slot].bank_tx,
3463                                             hc->chan[bch->slot].slot_rx,
3464                                             hc->chan[bch->slot].bank_rx);
3465                         if (!ret) {
3466                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3467                                     && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3468                                         /* start decoder */
3469                                         hc->dtmf = 1;
3470                                         if (debug & DEBUG_HFCMULTI_DTMF)
3471                                                 printk(KERN_DEBUG
3472                                                        "%s: start dtmf decoder\n",
3473                                                        __func__);
3474                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3475                                                  V_RST_DTMF);
3476                                 }
3477                         }
3478                 } else
3479                         ret = 0;
3480                 spin_unlock_irqrestore(&hc->lock, flags);
3481                 if (!ret)
3482                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3483                                     GFP_KERNEL);
3484                 break;
3485         case PH_CONTROL_REQ:
3486                 spin_lock_irqsave(&hc->lock, flags);
3487                 switch (hh->id) {
3488                 case HFC_SPL_LOOP_ON: /* set sample loop */
3489                         if (debug & DEBUG_HFCMULTI_MSG)
3490                                 printk(KERN_DEBUG
3491                                        "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3492                                        __func__, skb->len);
3493                         ret = 0;
3494                         break;
3495                 case HFC_SPL_LOOP_OFF: /* set silence */
3496                         if (debug & DEBUG_HFCMULTI_MSG)
3497                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3498                                        __func__);
3499                         ret = 0;
3500                         break;
3501                 default:
3502                         printk(KERN_ERR
3503                                "%s: unknown PH_CONTROL_REQ info %x\n",
3504                                __func__, hh->id);
3505                         ret = -EINVAL;
3506                 }
3507                 spin_unlock_irqrestore(&hc->lock, flags);
3508                 break;
3509         case PH_DEACTIVATE_REQ:
3510                 deactivate_bchannel(bch); /* locked there */
3511                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3512                             GFP_KERNEL);
3513                 ret = 0;
3514                 break;
3515         }
3516         if (!ret)
3517                 dev_kfree_skb(skb);
3518         return ret;
3519 }
3520
3521 /*
3522  * bchannel control function
3523  */
3524 static int
3525 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3526 {
3527         int                     ret = 0;
3528         struct dsp_features     *features =
3529                 (struct dsp_features *)(*((u_long *)&cq->p1));
3530         struct hfc_multi        *hc = bch->hw;
3531         int                     slot_tx;
3532         int                     bank_tx;
3533         int                     slot_rx;
3534         int                     bank_rx;
3535         int                     num;
3536
3537         switch (cq->op) {
3538         case MISDN_CTRL_GETOP:
3539                 ret = mISDN_ctrl_bchannel(bch, cq);
3540                 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3541                 break;
3542         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3543                 ret = mISDN_ctrl_bchannel(bch, cq);
3544                 hc->chan[bch->slot].rx_off = !!cq->p1;
3545                 if (!hc->chan[bch->slot].rx_off) {
3546                         /* reset fifo on rx on */
3547                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3548                         HFC_wait_nodebug(hc);
3549                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3550                         HFC_wait_nodebug(hc);
3551                 }
3552                 if (debug & DEBUG_HFCMULTI_MSG)
3553                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3554                                __func__, bch->nr, hc->chan[bch->slot].rx_off);
3555                 break;
3556         case MISDN_CTRL_FILL_EMPTY:
3557                 ret = mISDN_ctrl_bchannel(bch, cq);
3558                 hc->silence = bch->fill[0];
3559                 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3560                 break;
3561         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3562                 if (debug & DEBUG_HFCMULTI_MSG)
3563                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3564                                __func__);
3565                 /* create confirm */
3566                 features->hfc_id = hc->id;
3567                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3568                         features->hfc_dtmf = 1;
3569                 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3570                         features->hfc_conf = 1;
3571                 features->hfc_loops = 0;
3572                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3573                         features->hfc_echocanhw = 1;
3574                 } else {
3575                         features->pcm_id = hc->pcm;
3576                         features->pcm_slots = hc->slots;
3577                         features->pcm_banks = 2;
3578                 }
3579                 break;
3580         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3581                 slot_tx = cq->p1 & 0xff;
3582                 bank_tx = cq->p1 >> 8;
3583                 slot_rx = cq->p2 & 0xff;
3584                 bank_rx = cq->p2 >> 8;
3585                 if (debug & DEBUG_HFCMULTI_MSG)
3586                         printk(KERN_DEBUG
3587                                "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3588                                "slot %d bank %d (RX)\n",
3589                                __func__, slot_tx, bank_tx,
3590                                slot_rx, bank_rx);
3591                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3592                     slot_rx < hc->slots && bank_rx <= 2)
3593                         hfcmulti_pcm(hc, bch->slot,
3594                                      slot_tx, bank_tx, slot_rx, bank_rx);
3595                 else {
3596                         printk(KERN_WARNING
3597                                "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3598                                "slot %d bank %d (RX) out of range\n",
3599                                __func__, slot_tx, bank_tx,
3600                                slot_rx, bank_rx);
3601                         ret = -EINVAL;
3602                 }
3603                 break;
3604         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3605                 if (debug & DEBUG_HFCMULTI_MSG)
3606                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3607                                __func__);
3608                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3609                 break;
3610         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3611                 num = cq->p1 & 0xff;
3612                 if (debug & DEBUG_HFCMULTI_MSG)
3613                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3614                                __func__, num);
3615                 if (num <= 7)
3616                         hfcmulti_conf(hc, bch->slot, num);
3617                 else {
3618                         printk(KERN_WARNING
3619                                "%s: HW_CONF_JOIN conf %d out of range\n",
3620                                __func__, num);
3621                         ret = -EINVAL;
3622                 }
3623                 break;
3624         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3625                 if (debug & DEBUG_HFCMULTI_MSG)
3626                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3627                 hfcmulti_conf(hc, bch->slot, -1);
3628                 break;
3629         case MISDN_CTRL_HFC_ECHOCAN_ON:
3630                 if (debug & DEBUG_HFCMULTI_MSG)
3631                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3632                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3633                         vpm_echocan_on(hc, bch->slot, cq->p1);
3634                 else
3635                         ret = -EINVAL;
3636                 break;
3637
3638         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3639                 if (debug & DEBUG_HFCMULTI_MSG)
3640                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3641                                __func__);
3642                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3643                         vpm_echocan_off(hc, bch->slot);
3644                 else
3645                         ret = -EINVAL;
3646                 break;
3647         default:
3648                 ret = mISDN_ctrl_bchannel(bch, cq);
3649                 break;
3650         }
3651         return ret;
3652 }
3653
3654 static int
3655 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3656 {
3657         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3658         struct hfc_multi        *hc = bch->hw;
3659         int                     err = -EINVAL;
3660         u_long  flags;
3661
3662         if (bch->debug & DEBUG_HW)
3663                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3664                        __func__, cmd, arg);
3665         switch (cmd) {
3666         case CLOSE_CHANNEL:
3667                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3668                 deactivate_bchannel(bch); /* locked there */
3669                 ch->protocol = ISDN_P_NONE;
3670                 ch->peer = NULL;
3671                 module_put(THIS_MODULE);
3672                 err = 0;
3673                 break;
3674         case CONTROL_CHANNEL:
3675                 spin_lock_irqsave(&hc->lock, flags);
3676                 err = channel_bctrl(bch, arg);
3677                 spin_unlock_irqrestore(&hc->lock, flags);
3678                 break;
3679         default:
3680                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3681                        __func__, cmd);
3682         }
3683         return err;
3684 }
3685
3686 /*
3687  * handle D-channel events
3688  *
3689  * handle state change event
3690  */
3691 static void
3692 ph_state_change(struct dchannel *dch)
3693 {
3694         struct hfc_multi *hc;
3695         int ch, i;
3696
3697         if (!dch) {
3698                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3699                 return;
3700         }
3701         hc = dch->hw;
3702         ch = dch->slot;
3703
3704         if (hc->ctype == HFC_TYPE_E1) {
3705                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3706                         if (debug & DEBUG_HFCMULTI_STATE)
3707                                 printk(KERN_DEBUG
3708                                        "%s: E1 TE (id=%d) newstate %x\n",
3709                                        __func__, hc->id, dch->state);
3710                 } else {
3711                         if (debug & DEBUG_HFCMULTI_STATE)
3712                                 printk(KERN_DEBUG
3713                                        "%s: E1 NT (id=%d) newstate %x\n",
3714                                        __func__, hc->id, dch->state);
3715                 }
3716                 switch (dch->state) {
3717                 case (1):
3718                         if (hc->e1_state != 1) {
3719                                 for (i = 1; i <= 31; i++) {
3720                                         /* reset fifos on e1 activation */
3721                                         HFC_outb_nodebug(hc, R_FIFO,
3722                                                          (i << 1) | 1);
3723                                         HFC_wait_nodebug(hc);
3724                                         HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3725                                                          V_RES_F);
3726                                         HFC_wait_nodebug(hc);
3727                                 }
3728                         }
3729                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3730                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3731                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3732                         break;
3733
3734                 default:
3735                         if (hc->e1_state != 1)
3736                                 return;
3737                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3738                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3739                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3740                 }
3741                 hc->e1_state = dch->state;
3742         } else {
3743                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3744                         if (debug & DEBUG_HFCMULTI_STATE)
3745                                 printk(KERN_DEBUG
3746                                        "%s: S/T TE newstate %x\n",
3747                                        __func__, dch->state);
3748                         switch (dch->state) {
3749                         case (0):
3750                                 l1_event(dch->l1, HW_RESET_IND);
3751                                 break;
3752                         case (3):
3753                                 l1_event(dch->l1, HW_DEACT_IND);
3754                                 break;
3755                         case (5):
3756                         case (8):
3757                                 l1_event(dch->l1, ANYSIGNAL);
3758                                 break;
3759                         case (6):
3760                                 l1_event(dch->l1, INFO2);
3761                                 break;
3762                         case (7):
3763                                 l1_event(dch->l1, INFO4_P8);
3764                                 break;
3765                         }
3766                 } else {
3767                         if (debug & DEBUG_HFCMULTI_STATE)
3768                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3769                                        __func__, dch->state);
3770                         switch (dch->state) {
3771                         case (2):
3772                                 if (hc->chan[ch].nt_timer == 0) {
3773                                         hc->chan[ch].nt_timer = -1;
3774                                         HFC_outb(hc, R_ST_SEL,
3775                                                  hc->chan[ch].port);
3776                                         /* undocumented: delay after R_ST_SEL */
3777                                         udelay(1);
3778                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3779                                                  V_ST_LD_STA); /* G4 */
3780                                         udelay(6); /* wait at least 5,21us */
3781                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3782                                         dch->state = 4;
3783                                 } else {
3784                                         /* one extra count for the next event */
3785                                         hc->chan[ch].nt_timer =
3786                                                 nt_t1_count[poll_timer] + 1;
3787                                         HFC_outb(hc, R_ST_SEL,
3788                                                  hc->chan[ch].port);
3789                                         /* undocumented: delay after R_ST_SEL */
3790                                         udelay(1);
3791                                         /* allow G2 -> G3 transition */
3792                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3793                                                  V_SET_G2_G3);
3794                                 }
3795                                 break;
3796                         case (1):
3797                                 hc->chan[ch].nt_timer = -1;
3798                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3799                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3800                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3801                                 break;
3802                         case (4):
3803                                 hc->chan[ch].nt_timer = -1;
3804                                 break;
3805                         case (3):
3806                                 hc->chan[ch].nt_timer = -1;
3807                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3808                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3809                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3810                                 break;
3811                         }
3812                 }
3813         }
3814 }
3815
3816 /*
3817  * called for card mode init message
3818  */
3819
3820 static void
3821 hfcmulti_initmode(struct dchannel *dch)
3822 {
3823         struct hfc_multi *hc = dch->hw;
3824         u_char          a_st_wr_state, r_e1_wr_sta;
3825         int             i, pt;
3826
3827         if (debug & DEBUG_HFCMULTI_INIT)
3828                 printk(KERN_DEBUG "%s: entered\n", __func__);
3829
3830         i = dch->slot;
3831         pt = hc->chan[i].port;
3832         if (hc->ctype == HFC_TYPE_E1) {
3833                 /* E1 */
3834                 hc->chan[hc->dnum[pt]].slot_tx = -1;
3835                 hc->chan[hc->dnum[pt]].slot_rx = -1;
3836                 hc->chan[hc->dnum[pt]].conf = -1;
3837                 if (hc->dnum[pt]) {
3838                         mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
3839                                       -1, 0, -1, 0);
3840                         timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3841                 }
3842                 for (i = 1; i <= 31; i++) {
3843                         if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3844                                 continue;
3845                         hc->chan[i].slot_tx = -1;
3846                         hc->chan[i].slot_rx = -1;
3847                         hc->chan[i].conf = -1;
3848                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3849                 }
3850         }
3851         if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3852                 /* E1, port 0 */
3853                 dch = hc->chan[hc->dnum[0]].dch;
3854                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3855                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3856                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3857                 }
3858                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3859                         HFC_outb(hc, R_RX0, 0);
3860                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3861                 } else {
3862                         HFC_outb(hc, R_RX0, 1);
3863                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3864                 }
3865                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3866                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3867                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3868                 HFC_outb(hc, R_TX_FR0, 0x00);
3869                 HFC_outb(hc, R_TX_FR1, 0xf8);
3870
3871                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3872                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3873
3874                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3875
3876                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3877                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3878
3879                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3880                         if (debug & DEBUG_HFCMULTI_INIT)
3881                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3882                                        __func__);
3883                         r_e1_wr_sta = 0; /* G0 */
3884                         hc->e1_getclock = 0;
3885                 } else {
3886                         if (debug & DEBUG_HFCMULTI_INIT)
3887                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3888                                        __func__);
3889                         r_e1_wr_sta = 0; /* F0 */
3890                         hc->e1_getclock = 1;
3891                 }
3892                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3893                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3894                 else
3895                         HFC_outb(hc, R_SYNC_OUT, 0);
3896                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3897                         hc->e1_getclock = 1;
3898                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3899                         hc->e1_getclock = 0;
3900                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3901                         /* SLAVE (clock master) */
3902                         if (debug & DEBUG_HFCMULTI_INIT)
3903                                 printk(KERN_DEBUG
3904                                        "%s: E1 port is clock master "
3905                                        "(clock from PCM)\n", __func__);
3906                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3907                 } else {
3908                         if (hc->e1_getclock) {
3909                                 /* MASTER (clock slave) */
3910                                 if (debug & DEBUG_HFCMULTI_INIT)
3911                                         printk(KERN_DEBUG
3912                                                "%s: E1 port is clock slave "
3913                                                "(clock to PCM)\n", __func__);
3914                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3915                         } else {
3916                                 /* MASTER (clock master) */
3917                                 if (debug & DEBUG_HFCMULTI_INIT)
3918                                         printk(KERN_DEBUG "%s: E1 port is "
3919                                                "clock master "
3920                                                "(clock from QUARTZ)\n",
3921                                                __func__);
3922                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3923                                          V_PCM_SYNC | V_JATT_OFF);
3924                                 HFC_outb(hc, R_SYNC_OUT, 0);
3925                         }
3926                 }
3927                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3928                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3929                 HFC_outb(hc, R_PWM0, 0x50);
3930                 HFC_outb(hc, R_PWM1, 0xff);
3931                 /* state machine setup */
3932                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3933                 udelay(6); /* wait at least 5,21us */
3934                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3935                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3936                         hc->syncronized = 0;
3937                         plxsd_checksync(hc, 0);
3938                 }
3939         }
3940         if (hc->ctype != HFC_TYPE_E1) {
3941                 /* ST */
3942                 hc->chan[i].slot_tx = -1;
3943                 hc->chan[i].slot_rx = -1;
3944                 hc->chan[i].conf = -1;
3945                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3946                 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3947                 hc->chan[i - 2].slot_tx = -1;
3948                 hc->chan[i - 2].slot_rx = -1;
3949                 hc->chan[i - 2].conf = -1;
3950                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3951                 hc->chan[i - 1].slot_tx = -1;
3952                 hc->chan[i - 1].slot_rx = -1;
3953                 hc->chan[i - 1].conf = -1;
3954                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3955                 /* select interface */
3956                 HFC_outb(hc, R_ST_SEL, pt);
3957                 /* undocumented: delay after R_ST_SEL */
3958                 udelay(1);
3959                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3960                         if (debug & DEBUG_HFCMULTI_INIT)
3961                                 printk(KERN_DEBUG
3962                                        "%s: ST port %d is NT-mode\n",
3963                                        __func__, pt);
3964                         /* clock delay */
3965                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3966                         a_st_wr_state = 1; /* G1 */
3967                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3968                 } else {
3969                         if (debug & DEBUG_HFCMULTI_INIT)
3970                                 printk(KERN_DEBUG
3971                                        "%s: ST port %d is TE-mode\n",
3972                                        __func__, pt);
3973                         /* clock delay */
3974                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3975                         a_st_wr_state = 2; /* F2 */
3976                         hc->hw.a_st_ctrl0[pt] = 0;
3977                 }
3978                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3979                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3980                 if (hc->ctype == HFC_TYPE_XHFC) {
3981                         hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
3982                         HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
3983                                  0x7c << 1 /* V_ST_PULSE */);
3984                 }
3985                 /* line setup */
3986                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3987                 /* disable E-channel */
3988                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3989                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3990                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3991                 else
3992                         HFC_outb(hc, A_ST_CTRL1, 0);
3993                 /* enable B-channel receive */
3994                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3995                 /* state machine setup */
3996                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3997                 udelay(6); /* wait at least 5,21us */
3998                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3999                 hc->hw.r_sci_msk |= 1 << pt;
4000                 /* state machine interrupts */
4001                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4002                 /* unset sync on port */
4003                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4004                         hc->syncronized &=
4005                                 ~(1 << hc->chan[dch->slot].port);
4006                         plxsd_checksync(hc, 0);
4007                 }
4008         }
4009         if (debug & DEBUG_HFCMULTI_INIT)
4010                 printk("%s: done\n", __func__);
4011 }
4012
4013
4014 static int
4015 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4016               struct channel_req *rq)
4017 {
4018         int     err = 0;
4019         u_long  flags;
4020
4021         if (debug & DEBUG_HW_OPEN)
4022                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4023                        dch->dev.id, __builtin_return_address(0));
4024         if (rq->protocol == ISDN_P_NONE)
4025                 return -EINVAL;
4026         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4027             (dch->dev.D.protocol != rq->protocol)) {
4028                 if (debug & DEBUG_HFCMULTI_MODE)
4029                         printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4030                                __func__, dch->dev.D.protocol, rq->protocol);
4031         }
4032         if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4033             (rq->protocol != ISDN_P_TE_S0))
4034                 l1_event(dch->l1, CLOSE_CHANNEL);
4035         if (dch->dev.D.protocol != rq->protocol) {
4036                 if (rq->protocol == ISDN_P_TE_S0) {
4037                         err = create_l1(dch, hfcm_l1callback);
4038                         if (err)
4039                                 return err;
4040                 }
4041                 dch->dev.D.protocol = rq->protocol;
4042                 spin_lock_irqsave(&hc->lock, flags);
4043                 hfcmulti_initmode(dch);
4044                 spin_unlock_irqrestore(&hc->lock, flags);
4045         }
4046         if (test_bit(FLG_ACTIVE, &dch->Flags))
4047                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4048                             0, NULL, GFP_KERNEL);
4049         rq->ch = &dch->dev.D;
4050         if (!try_module_get(THIS_MODULE))
4051                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4052         return 0;
4053 }
4054
4055 static int
4056 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4057               struct channel_req *rq)
4058 {
4059         struct bchannel *bch;
4060         int             ch;
4061
4062         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4063                 return -EINVAL;
4064         if (rq->protocol == ISDN_P_NONE)
4065                 return -EINVAL;
4066         if (hc->ctype == HFC_TYPE_E1)
4067                 ch = rq->adr.channel;
4068         else
4069                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4070         bch = hc->chan[ch].bch;
4071         if (!bch) {
4072                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4073                        __func__, ch);
4074                 return -EINVAL;
4075         }
4076         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4077                 return -EBUSY; /* b-channel can be only open once */
4078         bch->ch.protocol = rq->protocol;
4079         hc->chan[ch].rx_off = 0;
4080         rq->ch = &bch->ch;
4081         if (!try_module_get(THIS_MODULE))
4082                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4083         return 0;
4084 }
4085
4086 /*
4087  * device control function
4088  */
4089 static int
4090 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4091 {
4092         struct hfc_multi        *hc = dch->hw;
4093         int     ret = 0;
4094         int     wd_mode, wd_cnt;
4095
4096         switch (cq->op) {
4097         case MISDN_CTRL_GETOP:
4098                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4099                 break;
4100         case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4101                 wd_cnt = cq->p1 & 0xf;
4102                 wd_mode = !!(cq->p1 >> 4);
4103                 if (debug & DEBUG_HFCMULTI_MSG)
4104                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4105                                ", counter 0x%x\n", __func__,
4106                                wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4107                 /* set the watchdog timer */
4108                 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4109                 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4110                 if (hc->ctype == HFC_TYPE_XHFC)
4111                         hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4112                 /* init the watchdog register and reset the counter */
4113                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4114                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4115                         /* enable the watchdog output for Speech-Design */
4116                         HFC_outb(hc, R_GPIO_SEL,  V_GPIO_SEL7);
4117                         HFC_outb(hc, R_GPIO_EN1,  V_GPIO_EN15);
4118                         HFC_outb(hc, R_GPIO_OUT1, 0);
4119                         HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4120                 }
4121                 break;
4122         case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4123                 if (debug & DEBUG_HFCMULTI_MSG)
4124                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4125                                __func__);
4126                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4127                 break;
4128         case MISDN_CTRL_L1_TIMER3:
4129                 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4130                 break;
4131         default:
4132                 printk(KERN_WARNING "%s: unknown Op %x\n",
4133                        __func__, cq->op);
4134                 ret = -EINVAL;
4135                 break;
4136         }
4137         return ret;
4138 }
4139
4140 static int
4141 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4142 {
4143         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4144         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4145         struct hfc_multi        *hc = dch->hw;
4146         struct channel_req      *rq;
4147         int                     err = 0;
4148         u_long                  flags;
4149
4150         if (dch->debug & DEBUG_HW)
4151                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4152                        __func__, cmd, arg);
4153         switch (cmd) {
4154         case OPEN_CHANNEL:
4155                 rq = arg;
4156                 switch (rq->protocol) {
4157                 case ISDN_P_TE_S0:
4158                 case ISDN_P_NT_S0:
4159                         if (hc->ctype == HFC_TYPE_E1) {
4160                                 err = -EINVAL;
4161                                 break;
4162                         }
4163                         err = open_dchannel(hc, dch, rq); /* locked there */
4164                         break;
4165                 case ISDN_P_TE_E1:
4166                 case ISDN_P_NT_E1:
4167                         if (hc->ctype != HFC_TYPE_E1) {
4168                                 err = -EINVAL;
4169                                 break;
4170                         }
4171                         err = open_dchannel(hc, dch, rq); /* locked there */
4172                         break;
4173                 default:
4174                         spin_lock_irqsave(&hc->lock, flags);
4175                         err = open_bchannel(hc, dch, rq);
4176                         spin_unlock_irqrestore(&hc->lock, flags);
4177                 }
4178                 break;
4179         case CLOSE_CHANNEL:
4180                 if (debug & DEBUG_HW_OPEN)
4181                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4182                                __func__, dch->dev.id,
4183                                __builtin_return_address(0));
4184                 module_put(THIS_MODULE);
4185                 break;
4186         case CONTROL_CHANNEL:
4187                 spin_lock_irqsave(&hc->lock, flags);
4188                 err = channel_dctrl(dch, arg);
4189                 spin_unlock_irqrestore(&hc->lock, flags);
4190                 break;
4191         default:
4192                 if (dch->debug & DEBUG_HW)
4193                         printk(KERN_DEBUG "%s: unknown command %x\n",
4194                                __func__, cmd);
4195                 err = -EINVAL;
4196         }
4197         return err;
4198 }
4199
4200 static int
4201 clockctl(void *priv, int enable)
4202 {
4203         struct hfc_multi *hc = priv;
4204
4205         hc->iclock_on = enable;
4206         return 0;
4207 }
4208
4209 /*
4210  * initialize the card
4211  */
4212
4213 /*
4214  * start timer irq, wait some time and check if we have interrupts.
4215  * if not, reset chip and try again.
4216  */
4217 static int
4218 init_card(struct hfc_multi *hc)
4219 {
4220         int     err = -EIO;
4221         u_long  flags;
4222         void    __iomem *plx_acc;
4223         u_long  plx_flags;
4224
4225         if (debug & DEBUG_HFCMULTI_INIT)
4226                 printk(KERN_DEBUG "%s: entered\n", __func__);
4227
4228         spin_lock_irqsave(&hc->lock, flags);
4229         /* set interrupts but leave global interrupt disabled */
4230         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4231         disable_hwirq(hc);
4232         spin_unlock_irqrestore(&hc->lock, flags);
4233
4234         if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4235                         "HFC-multi", hc)) {
4236                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4237                        hc->irq);
4238                 hc->irq = 0;
4239                 return -EIO;
4240         }
4241
4242         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4243                 spin_lock_irqsave(&plx_lock, plx_flags);
4244                 plx_acc = hc->plx_membase + PLX_INTCSR;
4245                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4246                        plx_acc); /* enable PCI & LINT1 irq */
4247                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4248         }
4249
4250         if (debug & DEBUG_HFCMULTI_INIT)
4251                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4252                        __func__, hc->irq, hc->irqcnt);
4253         err = init_chip(hc);
4254         if (err)
4255                 goto error;
4256         /*
4257          * Finally enable IRQ output
4258          * this is only allowed, if an IRQ routine is already
4259          * established for this HFC, so don't do that earlier
4260          */
4261         spin_lock_irqsave(&hc->lock, flags);
4262         enable_hwirq(hc);
4263         spin_unlock_irqrestore(&hc->lock, flags);
4264         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4265         set_current_state(TASK_UNINTERRUPTIBLE);
4266         schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4267         /* turn IRQ off until chip is completely initialized */
4268         spin_lock_irqsave(&hc->lock, flags);
4269         disable_hwirq(hc);
4270         spin_unlock_irqrestore(&hc->lock, flags);
4271         if (debug & DEBUG_HFCMULTI_INIT)
4272                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4273                        __func__, hc->irq, hc->irqcnt);
4274         if (hc->irqcnt) {
4275                 if (debug & DEBUG_HFCMULTI_INIT)
4276                         printk(KERN_DEBUG "%s: done\n", __func__);
4277
4278                 return 0;
4279         }
4280         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4281                 printk(KERN_INFO "ignoring missing interrupts\n");
4282                 return 0;
4283         }
4284
4285         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4286                hc->irq);
4287
4288         err = -EIO;
4289
4290 error:
4291         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4292                 spin_lock_irqsave(&plx_lock, plx_flags);
4293                 plx_acc = hc->plx_membase + PLX_INTCSR;
4294                 writew(0x00, plx_acc); /*disable IRQs*/
4295                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4296         }
4297
4298         if (debug & DEBUG_HFCMULTI_INIT)
4299                 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4300         if (hc->irq) {
4301                 free_irq(hc->irq, hc);
4302                 hc->irq = 0;
4303         }
4304
4305         if (debug & DEBUG_HFCMULTI_INIT)
4306                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4307         return err;
4308 }
4309
4310 /*
4311  * find pci device and set it up
4312  */
4313
4314 static int
4315 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4316           const struct pci_device_id *ent)
4317 {
4318         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4319
4320         printk(KERN_INFO
4321                "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4322                m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4323
4324         hc->pci_dev = pdev;
4325         if (m->clock2)
4326                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4327
4328         if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4329             ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
4330                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4331                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4332                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4333                 hc->slots = 32;
4334         }
4335
4336         if (hc->pci_dev->irq <= 0) {
4337                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4338                 return -EIO;
4339         }
4340         if (pci_enable_device(hc->pci_dev)) {
4341                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4342                 return -EIO;
4343         }
4344         hc->leds = m->leds;
4345         hc->ledstate = 0xAFFEAFFE;
4346         hc->opticalsupport = m->opticalsupport;
4347
4348         hc->pci_iobase = 0;
4349         hc->pci_membase = NULL;
4350         hc->plx_membase = NULL;
4351
4352         /* set memory access methods */
4353         if (m->io_mode) /* use mode from card config */
4354                 hc->io_mode = m->io_mode;
4355         switch (hc->io_mode) {
4356         case HFC_IO_MODE_PLXSD:
4357                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4358                 hc->slots = 128; /* required */
4359                 hc->HFC_outb = HFC_outb_pcimem;
4360                 hc->HFC_inb = HFC_inb_pcimem;
4361                 hc->HFC_inw = HFC_inw_pcimem;
4362                 hc->HFC_wait = HFC_wait_pcimem;
4363                 hc->read_fifo = read_fifo_pcimem;
4364                 hc->write_fifo = write_fifo_pcimem;
4365                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4366                 /* MEMBASE 1 is PLX PCI Bridge */
4367
4368                 if (!hc->plx_origmembase) {
4369                         printk(KERN_WARNING
4370                                "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4371                         pci_disable_device(hc->pci_dev);
4372                         return -EIO;
4373                 }
4374
4375                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4376                 if (!hc->plx_membase) {
4377                         printk(KERN_WARNING
4378                                "HFC-multi: failed to remap plx address space. "
4379                                "(internal error)\n");
4380                         pci_disable_device(hc->pci_dev);
4381                         return -EIO;
4382                 }
4383                 printk(KERN_INFO
4384                        "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4385                        (u_long)hc->plx_membase, hc->plx_origmembase);
4386
4387                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4388                 /* MEMBASE 1 is PLX PCI Bridge */
4389                 if (!hc->pci_origmembase) {
4390                         printk(KERN_WARNING
4391                                "HFC-multi: No IO-Memory for PCI card found\n");
4392                         pci_disable_device(hc->pci_dev);
4393                         return -EIO;
4394                 }
4395
4396                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4397                 if (!hc->pci_membase) {
4398                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4399                                "address space. (internal error)\n");
4400                         pci_disable_device(hc->pci_dev);
4401                         return -EIO;
4402                 }
4403
4404                 printk(KERN_INFO
4405                        "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4406                        "leds-type %d\n",
4407                        hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4408                        hc->pci_dev->irq, HZ, hc->leds);
4409                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4410                 break;
4411         case HFC_IO_MODE_PCIMEM:
4412                 hc->HFC_outb = HFC_outb_pcimem;
4413                 hc->HFC_inb = HFC_inb_pcimem;
4414                 hc->HFC_inw = HFC_inw_pcimem;
4415                 hc->HFC_wait = HFC_wait_pcimem;
4416                 hc->read_fifo = read_fifo_pcimem;
4417                 hc->write_fifo = write_fifo_pcimem;
4418                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4419                 if (!hc->pci_origmembase) {
4420                         printk(KERN_WARNING
4421                                "HFC-multi: No IO-Memory for PCI card found\n");
4422                         pci_disable_device(hc->pci_dev);
4423                         return -EIO;
4424                 }
4425
4426                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4427                 if (!hc->pci_membase) {
4428                         printk(KERN_WARNING
4429                                "HFC-multi: failed to remap io address space. "
4430                                "(internal error)\n");
4431                         pci_disable_device(hc->pci_dev);
4432                         return -EIO;
4433                 }
4434                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4435                        "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4436                        hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4437                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4438                 break;
4439         case HFC_IO_MODE_REGIO:
4440                 hc->HFC_outb = HFC_outb_regio;
4441                 hc->HFC_inb = HFC_inb_regio;
4442                 hc->HFC_inw = HFC_inw_regio;
4443                 hc->HFC_wait = HFC_wait_regio;
4444                 hc->read_fifo = read_fifo_regio;
4445                 hc->write_fifo = write_fifo_regio;
4446                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4447                 if (!hc->pci_iobase) {
4448                         printk(KERN_WARNING
4449                                "HFC-multi: No IO for PCI card found\n");
4450                         pci_disable_device(hc->pci_dev);
4451                         return -EIO;
4452                 }
4453
4454                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4455                         printk(KERN_WARNING "HFC-multi: failed to request "
4456                                "address space at 0x%08lx (internal error)\n",
4457                                hc->pci_iobase);
4458                         pci_disable_device(hc->pci_dev);
4459                         return -EIO;
4460                 }
4461
4462                 printk(KERN_INFO
4463                        "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4464                        m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4465                        hc->pci_dev->irq, HZ, hc->leds);
4466                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4467                 break;
4468         default:
4469                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4470                 pci_disable_device(hc->pci_dev);
4471                 return -EIO;
4472         }
4473
4474         pci_set_drvdata(hc->pci_dev, hc);
4475
4476         /* At this point the needed PCI config is done */
4477         /* fifos are still not enabled */
4478         return 0;
4479 }
4480
4481
4482 /*
4483  * remove port
4484  */
4485
4486 static void
4487 release_port(struct hfc_multi *hc, struct dchannel *dch)
4488 {
4489         int     pt, ci, i = 0;
4490         u_long  flags;
4491         struct bchannel *pb;
4492
4493         ci = dch->slot;
4494         pt = hc->chan[ci].port;
4495
4496         if (debug & DEBUG_HFCMULTI_INIT)
4497                 printk(KERN_DEBUG "%s: entered for port %d\n",
4498                        __func__, pt + 1);
4499
4500         if (pt >= hc->ports) {
4501                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4502                        __func__, pt + 1);
4503                 return;
4504         }
4505
4506         if (debug & DEBUG_HFCMULTI_INIT)
4507                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4508                        __func__, pt + 1);
4509
4510         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4511                 l1_event(dch->l1, CLOSE_CHANNEL);
4512
4513         hc->chan[ci].dch = NULL;
4514
4515         if (hc->created[pt]) {
4516                 hc->created[pt] = 0;
4517                 mISDN_unregister_device(&dch->dev);
4518         }
4519
4520         spin_lock_irqsave(&hc->lock, flags);
4521
4522         if (dch->timer.function) {
4523                 del_timer(&dch->timer);
4524                 dch->timer.function = NULL;
4525         }
4526
4527         if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4528                 /* remove sync */
4529                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4530                         hc->syncronized = 0;
4531                         plxsd_checksync(hc, 1);
4532                 }
4533                 /* free channels */
4534                 for (i = 0; i <= 31; i++) {
4535                         if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4536                                 continue;
4537                         if (hc->chan[i].bch) {
4538                                 if (debug & DEBUG_HFCMULTI_INIT)
4539                                         printk(KERN_DEBUG
4540                                                "%s: free port %d channel %d\n",
4541                                                __func__, hc->chan[i].port + 1, i);
4542                                 pb = hc->chan[i].bch;
4543                                 hc->chan[i].bch = NULL;
4544                                 spin_unlock_irqrestore(&hc->lock, flags);
4545                                 mISDN_freebchannel(pb);
4546                                 kfree(pb);
4547                                 kfree(hc->chan[i].coeff);
4548                                 spin_lock_irqsave(&hc->lock, flags);
4549                         }
4550                 }
4551         } else {
4552                 /* remove sync */
4553                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4554                         hc->syncronized &=
4555                                 ~(1 << hc->chan[ci].port);
4556                         plxsd_checksync(hc, 1);
4557                 }
4558                 /* free channels */
4559                 if (hc->chan[ci - 2].bch) {
4560                         if (debug & DEBUG_HFCMULTI_INIT)
4561                                 printk(KERN_DEBUG
4562                                        "%s: free port %d channel %d\n",
4563                                        __func__, hc->chan[ci - 2].port + 1,
4564                                        ci - 2);
4565                         pb = hc->chan[ci - 2].bch;
4566                         hc->chan[ci - 2].bch = NULL;
4567                         spin_unlock_irqrestore(&hc->lock, flags);
4568                         mISDN_freebchannel(pb);
4569                         kfree(pb);
4570                         kfree(hc->chan[ci - 2].coeff);
4571                         spin_lock_irqsave(&hc->lock, flags);
4572                 }
4573                 if (hc->chan[ci - 1].bch) {
4574                         if (debug & DEBUG_HFCMULTI_INIT)
4575                                 printk(KERN_DEBUG
4576                                        "%s: free port %d channel %d\n",
4577                                        __func__, hc->chan[ci - 1].port + 1,
4578                                        ci - 1);
4579                         pb = hc->chan[ci - 1].bch;
4580                         hc->chan[ci - 1].bch = NULL;
4581                         spin_unlock_irqrestore(&hc->lock, flags);
4582                         mISDN_freebchannel(pb);
4583                         kfree(pb);
4584                         kfree(hc->chan[ci - 1].coeff);
4585                         spin_lock_irqsave(&hc->lock, flags);
4586                 }
4587         }
4588
4589         spin_unlock_irqrestore(&hc->lock, flags);
4590
4591         if (debug & DEBUG_HFCMULTI_INIT)
4592                 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4593                         pt+1, ci);
4594         mISDN_freedchannel(dch);
4595         kfree(dch);
4596
4597         if (debug & DEBUG_HFCMULTI_INIT)
4598                 printk(KERN_DEBUG "%s: done!\n", __func__);
4599 }
4600
4601 static void
4602 release_card(struct hfc_multi *hc)
4603 {
4604         u_long  flags;
4605         int     ch;
4606
4607         if (debug & DEBUG_HFCMULTI_INIT)
4608                 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4609                        __func__, hc->id);
4610
4611         /* unregister clock source */
4612         if (hc->iclock)
4613                 mISDN_unregister_clock(hc->iclock);
4614
4615         /* disable and free irq */
4616         spin_lock_irqsave(&hc->lock, flags);
4617         disable_hwirq(hc);
4618         spin_unlock_irqrestore(&hc->lock, flags);
4619         udelay(1000);
4620         if (hc->irq) {
4621                 if (debug & DEBUG_HFCMULTI_INIT)
4622                         printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4623                             __func__, hc->irq, hc);
4624                 free_irq(hc->irq, hc);
4625                 hc->irq = 0;
4626
4627         }
4628
4629         /* disable D-channels & B-channels */
4630         if (debug & DEBUG_HFCMULTI_INIT)
4631                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4632                        __func__);
4633         for (ch = 0; ch <= 31; ch++) {
4634                 if (hc->chan[ch].dch)
4635                         release_port(hc, hc->chan[ch].dch);
4636         }
4637
4638         /* dimm leds */
4639         if (hc->leds)
4640                 hfcmulti_leds(hc);
4641
4642         /* release hardware */
4643         release_io_hfcmulti(hc);
4644
4645         if (debug & DEBUG_HFCMULTI_INIT)
4646                 printk(KERN_DEBUG "%s: remove instance from list\n",
4647                        __func__);
4648         list_del(&hc->list);
4649
4650         if (debug & DEBUG_HFCMULTI_INIT)
4651                 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4652         if (hc == syncmaster)
4653                 syncmaster = NULL;
4654         kfree(hc);
4655         if (debug & DEBUG_HFCMULTI_INIT)
4656                 printk(KERN_DEBUG "%s: card successfully removed\n",
4657                        __func__);
4658 }
4659
4660 static void
4661 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
4662 {
4663         /* set optical line type */
4664         if (port[Port_cnt] & 0x001) {
4665                 if (!m->opticalsupport)  {
4666                         printk(KERN_INFO
4667                                "This board has no optical "
4668                                "support\n");
4669                 } else {
4670                         if (debug & DEBUG_HFCMULTI_INIT)
4671                                 printk(KERN_DEBUG
4672                                        "%s: PORT set optical "
4673                                        "interfacs: card(%d) "
4674                                        "port(%d)\n",
4675                                        __func__,
4676                                        HFC_cnt + 1, 1);
4677                         test_and_set_bit(HFC_CFG_OPTICAL,
4678                             &hc->chan[hc->dnum[0]].cfg);
4679                 }
4680         }
4681         /* set LOS report */
4682         if (port[Port_cnt] & 0x004) {
4683                 if (debug & DEBUG_HFCMULTI_INIT)
4684                         printk(KERN_DEBUG "%s: PORT set "
4685                                "LOS report: card(%d) port(%d)\n",
4686                                __func__, HFC_cnt + 1, 1);
4687                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4688                     &hc->chan[hc->dnum[0]].cfg);
4689         }
4690         /* set AIS report */
4691         if (port[Port_cnt] & 0x008) {
4692                 if (debug & DEBUG_HFCMULTI_INIT)
4693                         printk(KERN_DEBUG "%s: PORT set "
4694                                "AIS report: card(%d) port(%d)\n",
4695                                __func__, HFC_cnt + 1, 1);
4696                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4697                     &hc->chan[hc->dnum[0]].cfg);
4698         }
4699         /* set SLIP report */
4700         if (port[Port_cnt] & 0x010) {
4701                 if (debug & DEBUG_HFCMULTI_INIT)
4702                         printk(KERN_DEBUG
4703                                "%s: PORT set SLIP report: "
4704                                "card(%d) port(%d)\n",
4705                                __func__, HFC_cnt + 1, 1);
4706                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4707                     &hc->chan[hc->dnum[0]].cfg);
4708         }
4709         /* set RDI report */
4710         if (port[Port_cnt] & 0x020) {
4711                 if (debug & DEBUG_HFCMULTI_INIT)
4712                         printk(KERN_DEBUG
4713                                "%s: PORT set RDI report: "
4714                                "card(%d) port(%d)\n",
4715                                __func__, HFC_cnt + 1, 1);
4716                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4717                     &hc->chan[hc->dnum[0]].cfg);
4718         }
4719         /* set CRC-4 Mode */
4720         if (!(port[Port_cnt] & 0x100)) {
4721                 if (debug & DEBUG_HFCMULTI_INIT)
4722                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4723                                " card(%d) port(%d)\n",
4724                                __func__, HFC_cnt + 1, 1);
4725                 test_and_set_bit(HFC_CFG_CRC4,
4726                     &hc->chan[hc->dnum[0]].cfg);
4727         } else {
4728                 if (debug & DEBUG_HFCMULTI_INIT)
4729                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4730                                " report: card(%d) port(%d)\n",
4731                                __func__, HFC_cnt + 1, 1);
4732         }
4733         /* set forced clock */
4734         if (port[Port_cnt] & 0x0200) {
4735                 if (debug & DEBUG_HFCMULTI_INIT)
4736                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4737                                "E1: card(%d) port(%d)\n",
4738                                __func__, HFC_cnt + 1, 1);
4739                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4740         } else
4741                 if (port[Port_cnt] & 0x0400) {
4742                         if (debug & DEBUG_HFCMULTI_INIT)
4743                                 printk(KERN_DEBUG "%s: PORT force putting clock to "
4744                                        "E1: card(%d) port(%d)\n",
4745                                        __func__, HFC_cnt + 1, 1);
4746                         test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4747                 }
4748         /* set JATT PLL */
4749         if (port[Port_cnt] & 0x0800) {
4750                 if (debug & DEBUG_HFCMULTI_INIT)
4751                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4752                                "E1: card(%d) port(%d)\n",
4753                                __func__, HFC_cnt + 1, 1);
4754                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4755         }
4756         /* set elastic jitter buffer */
4757         if (port[Port_cnt] & 0x3000) {
4758                 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4759                 if (debug & DEBUG_HFCMULTI_INIT)
4760                         printk(KERN_DEBUG
4761                                "%s: PORT set elastic "
4762                                "buffer to %d: card(%d) port(%d)\n",
4763                             __func__, hc->chan[hc->dnum[0]].jitter,
4764                                HFC_cnt + 1, 1);
4765         } else
4766                 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4767 }
4768
4769 static int
4770 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4771 {
4772         struct dchannel *dch;
4773         struct bchannel *bch;
4774         int             ch, ret = 0;
4775         char            name[MISDN_MAX_IDLEN];
4776         int             bcount = 0;
4777
4778         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4779         if (!dch)
4780                 return -ENOMEM;
4781         dch->debug = debug;
4782         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4783         dch->hw = hc;
4784         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4785         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4786             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4787         dch->dev.D.send = handle_dmsg;
4788         dch->dev.D.ctrl = hfcm_dctrl;
4789         dch->slot = hc->dnum[pt];
4790         hc->chan[hc->dnum[pt]].dch = dch;
4791         hc->chan[hc->dnum[pt]].port = pt;
4792         hc->chan[hc->dnum[pt]].nt_timer = -1;
4793         for (ch = 1; ch <= 31; ch++) {
4794                 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4795                         continue;
4796                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4797                 if (!bch) {
4798                         printk(KERN_ERR "%s: no memory for bchannel\n",
4799                             __func__);
4800                         ret = -ENOMEM;
4801                         goto free_chan;
4802                 }
4803                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4804                 if (!hc->chan[ch].coeff) {
4805                         printk(KERN_ERR "%s: no memory for coeffs\n",
4806                             __func__);
4807                         ret = -ENOMEM;
4808                         kfree(bch);
4809                         goto free_chan;
4810                 }
4811                 bch->nr = ch;
4812                 bch->slot = ch;
4813                 bch->debug = debug;
4814                 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4815                 bch->hw = hc;
4816                 bch->ch.send = handle_bmsg;
4817                 bch->ch.ctrl = hfcm_bctrl;
4818                 bch->ch.nr = ch;
4819                 list_add(&bch->ch.list, &dch->dev.bchannels);
4820                 hc->chan[ch].bch = bch;
4821                 hc->chan[ch].port = pt;
4822                 set_channelmap(bch->nr, dch->dev.channelmap);
4823                 bcount++;
4824         }
4825         dch->dev.nrbchan = bcount;
4826         if (pt == 0)
4827                 init_e1_port_hw(hc, m);
4828         if (hc->ports > 1)
4829                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4830                                 HFC_cnt + 1, pt+1);
4831         else
4832                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4833         ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4834         if (ret)
4835                 goto free_chan;
4836         hc->created[pt] = 1;
4837         return ret;
4838 free_chan:
4839         release_port(hc, dch);
4840         return ret;
4841 }
4842
4843 static int
4844 init_multi_port(struct hfc_multi *hc, int pt)
4845 {
4846         struct dchannel *dch;
4847         struct bchannel *bch;
4848         int             ch, i, ret = 0;
4849         char            name[MISDN_MAX_IDLEN];
4850
4851         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4852         if (!dch)
4853                 return -ENOMEM;
4854         dch->debug = debug;
4855         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4856         dch->hw = hc;
4857         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4858         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4859                 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4860         dch->dev.D.send = handle_dmsg;
4861         dch->dev.D.ctrl = hfcm_dctrl;
4862         dch->dev.nrbchan = 2;
4863         i = pt << 2;
4864         dch->slot = i + 2;
4865         hc->chan[i + 2].dch = dch;
4866         hc->chan[i + 2].port = pt;
4867         hc->chan[i + 2].nt_timer = -1;
4868         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4869                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4870                 if (!bch) {
4871                         printk(KERN_ERR "%s: no memory for bchannel\n",
4872                                __func__);
4873                         ret = -ENOMEM;
4874                         goto free_chan;
4875                 }
4876                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4877                 if (!hc->chan[i + ch].coeff) {
4878                         printk(KERN_ERR "%s: no memory for coeffs\n",
4879                                __func__);
4880                         ret = -ENOMEM;
4881                         kfree(bch);
4882                         goto free_chan;
4883                 }
4884                 bch->nr = ch + 1;
4885                 bch->slot = i + ch;
4886                 bch->debug = debug;
4887                 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4888                 bch->hw = hc;
4889                 bch->ch.send = handle_bmsg;
4890                 bch->ch.ctrl = hfcm_bctrl;
4891                 bch->ch.nr = ch + 1;
4892                 list_add(&bch->ch.list, &dch->dev.bchannels);
4893                 hc->chan[i + ch].bch = bch;
4894                 hc->chan[i + ch].port = pt;
4895                 set_channelmap(bch->nr, dch->dev.channelmap);
4896         }
4897         /* set master clock */
4898         if (port[Port_cnt] & 0x001) {
4899                 if (debug & DEBUG_HFCMULTI_INIT)
4900                         printk(KERN_DEBUG
4901                                "%s: PROTOCOL set master clock: "
4902                                "card(%d) port(%d)\n",
4903                                __func__, HFC_cnt + 1, pt + 1);
4904                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4905                         printk(KERN_ERR "Error: Master clock "
4906                                "for port(%d) of card(%d) is only"
4907                                " possible with TE-mode\n",
4908                                pt + 1, HFC_cnt + 1);
4909                         ret = -EINVAL;
4910                         goto free_chan;
4911                 }
4912                 if (hc->masterclk >= 0) {
4913                         printk(KERN_ERR "Error: Master clock "
4914                                "for port(%d) of card(%d) already "
4915                                "defined for port(%d)\n",
4916                                pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4917                         ret = -EINVAL;
4918                         goto free_chan;
4919                 }
4920                 hc->masterclk = pt;
4921         }
4922         /* set transmitter line to non capacitive */
4923         if (port[Port_cnt] & 0x002) {
4924                 if (debug & DEBUG_HFCMULTI_INIT)
4925                         printk(KERN_DEBUG
4926                                "%s: PROTOCOL set non capacitive "
4927                                "transmitter: card(%d) port(%d)\n",
4928                                __func__, HFC_cnt + 1, pt + 1);
4929                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4930                                  &hc->chan[i + 2].cfg);
4931         }
4932         /* disable E-channel */
4933         if (port[Port_cnt] & 0x004) {
4934                 if (debug & DEBUG_HFCMULTI_INIT)
4935                         printk(KERN_DEBUG
4936                                "%s: PROTOCOL disable E-channel: "
4937                                "card(%d) port(%d)\n",
4938                                __func__, HFC_cnt + 1, pt + 1);
4939                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4940                                  &hc->chan[i + 2].cfg);
4941         }
4942         if (hc->ctype == HFC_TYPE_XHFC) {
4943                 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4944                          HFC_cnt + 1, pt + 1);
4945                 ret = mISDN_register_device(&dch->dev, NULL, name);
4946         } else {
4947                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4948                          hc->ctype, HFC_cnt + 1, pt + 1);
4949                 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4950         }
4951         if (ret)
4952                 goto free_chan;
4953         hc->created[pt] = 1;
4954         return ret;
4955 free_chan:
4956         release_port(hc, dch);
4957         return ret;
4958 }
4959
4960 static int
4961 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4962               const struct pci_device_id *ent)
4963 {
4964         int             ret_err = 0;
4965         int             pt;
4966         struct hfc_multi        *hc;
4967         u_long          flags;
4968         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4969         int             i, ch;
4970         u_int           maskcheck;
4971
4972         if (HFC_cnt >= MAX_CARDS) {
4973                 printk(KERN_ERR "too many cards (max=%d).\n",
4974                        MAX_CARDS);
4975                 return -EINVAL;
4976         }
4977         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4978                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4979                        "type[%d] %d was supplied as module parameter\n",
4980                        m->vendor_name, m->card_name, m->type, HFC_cnt,
4981                        type[HFC_cnt] & 0xff);
4982                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4983                        "first, to see cards and their types.");
4984                 return -EINVAL;
4985         }
4986         if (debug & DEBUG_HFCMULTI_INIT)
4987                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4988                        __func__, m->vendor_name, m->card_name, m->type,
4989                        type[HFC_cnt]);
4990
4991         /* allocate card+fifo structure */
4992         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4993         if (!hc) {
4994                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4995                 return -ENOMEM;
4996         }
4997         spin_lock_init(&hc->lock);
4998         hc->mtyp = m;
4999         hc->ctype =  m->type;
5000         hc->ports = m->ports;
5001         hc->id = HFC_cnt;
5002         hc->pcm = pcm[HFC_cnt];
5003         hc->io_mode = iomode[HFC_cnt];
5004         if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5005                 /* fragment card */
5006                 pt = 0;
5007                 maskcheck = 0;
5008                 for (ch = 0; ch <= 31; ch++) {
5009                         if (!((1 << ch) & dmask[E1_cnt]))
5010                                 continue;
5011                         hc->dnum[pt] = ch;
5012                         hc->bmask[pt] = bmask[bmask_cnt++];
5013                         if ((maskcheck & hc->bmask[pt])
5014                          || (dmask[E1_cnt] & hc->bmask[pt])) {
5015                                 printk(KERN_INFO
5016                                        "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5017                                        E1_cnt + 1, pt);
5018                                 kfree(hc);
5019                                 return -EINVAL;
5020                         }
5021                         maskcheck |= hc->bmask[pt];
5022                         printk(KERN_INFO
5023                                "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5024                                 E1_cnt + 1, ch, hc->bmask[pt]);
5025                         pt++;
5026                 }
5027                 hc->ports = pt;
5028         }
5029         if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5030                 /* default card layout */
5031                 hc->dnum[0] = 16;
5032                 hc->bmask[0] = 0xfffefffe;
5033                 hc->ports = 1;
5034         }
5035
5036         /* set chip specific features */
5037         hc->masterclk = -1;
5038         if (type[HFC_cnt] & 0x100) {
5039                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5040                 hc->silence = 0xff; /* ulaw silence */
5041         } else
5042                 hc->silence = 0x2a; /* alaw silence */
5043         if ((poll >> 1) > sizeof(hc->silence_data)) {
5044                 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5045                        "please fix\n");
5046                 kfree(hc);
5047                 return -EINVAL;
5048         }
5049         for (i = 0; i < (poll >> 1); i++)
5050                 hc->silence_data[i] = hc->silence;
5051
5052         if (hc->ctype != HFC_TYPE_XHFC) {
5053                 if (!(type[HFC_cnt] & 0x200))
5054                         test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5055                 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5056         }
5057
5058         if (type[HFC_cnt] & 0x800)
5059                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5060         if (type[HFC_cnt] & 0x1000) {
5061                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5062                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5063         }
5064         if (type[HFC_cnt] & 0x4000)
5065                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5066         if (type[HFC_cnt] & 0x8000)
5067                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5068         hc->slots = 32;
5069         if (type[HFC_cnt] & 0x10000)
5070                 hc->slots = 64;
5071         if (type[HFC_cnt] & 0x20000)
5072                 hc->slots = 128;
5073         if (type[HFC_cnt] & 0x80000) {
5074                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5075                 hc->wdcount = 0;
5076                 hc->wdbyte = V_GPIO_OUT2;
5077                 printk(KERN_NOTICE "Watchdog enabled\n");
5078         }
5079
5080         if (pdev && ent)
5081                 /* setup pci, hc->slots may change due to PLXSD */
5082                 ret_err = setup_pci(hc, pdev, ent);
5083         else
5084 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5085                 ret_err = setup_embedded(hc, m);
5086 #else
5087         {
5088                 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5089                 ret_err = -EIO;
5090         }
5091 #endif
5092         if (ret_err) {
5093                 if (hc == syncmaster)
5094                         syncmaster = NULL;
5095                 kfree(hc);
5096                 return ret_err;
5097         }
5098
5099         hc->HFC_outb_nodebug = hc->HFC_outb;
5100         hc->HFC_inb_nodebug = hc->HFC_inb;
5101         hc->HFC_inw_nodebug = hc->HFC_inw;
5102         hc->HFC_wait_nodebug = hc->HFC_wait;
5103 #ifdef HFC_REGISTER_DEBUG
5104         hc->HFC_outb = HFC_outb_debug;
5105         hc->HFC_inb = HFC_inb_debug;
5106         hc->HFC_inw = HFC_inw_debug;
5107         hc->HFC_wait = HFC_wait_debug;
5108 #endif
5109         /* create channels */
5110         for (pt = 0; pt < hc->ports; pt++) {
5111                 if (Port_cnt >= MAX_PORTS) {
5112                         printk(KERN_ERR "too many ports (max=%d).\n",
5113                                MAX_PORTS);
5114                         ret_err = -EINVAL;
5115                         goto free_card;
5116                 }
5117                 if (hc->ctype == HFC_TYPE_E1)
5118                         ret_err = init_e1_port(hc, m, pt);
5119                 else
5120                         ret_err = init_multi_port(hc, pt);
5121                 if (debug & DEBUG_HFCMULTI_INIT)
5122                         printk(KERN_DEBUG
5123                             "%s: Registering D-channel, card(%d) port(%d) "
5124                                "result %d\n",
5125                             __func__, HFC_cnt + 1, pt + 1, ret_err);
5126
5127                 if (ret_err) {
5128                         while (pt) { /* release already registered ports */
5129                                 pt--;
5130                                 if (hc->ctype == HFC_TYPE_E1)
5131                                         release_port(hc,
5132                                                 hc->chan[hc->dnum[pt]].dch);
5133                                 else
5134                                         release_port(hc,
5135                                                 hc->chan[(pt << 2) + 2].dch);
5136                         }
5137                         goto free_card;
5138                 }
5139                 if (hc->ctype != HFC_TYPE_E1)
5140                         Port_cnt++; /* for each S0 port */
5141         }
5142         if (hc->ctype == HFC_TYPE_E1) {
5143                 Port_cnt++; /* for each E1 port */
5144                 E1_cnt++;
5145         }
5146
5147         /* disp switches */
5148         switch (m->dip_type) {
5149         case DIP_4S:
5150                 /*
5151                  * Get DIP setting for beroNet 1S/2S/4S cards
5152                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5153                  * GPI 19/23 (R_GPI_IN2))
5154                  */
5155                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5156                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5157                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5158
5159                 /* Port mode (TE/NT) jumpers */
5160                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
5161
5162                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5163                         pmj = ~pmj & 0xf;
5164
5165                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5166                        m->vendor_name, m->card_name, dips, pmj);
5167                 break;
5168         case DIP_8S:
5169                 /*
5170                  * Get DIP Setting for beroNet 8S0+ cards
5171                  * Enable PCI auxbridge function
5172                  */
5173                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5174                 /* prepare access to auxport */
5175                 outw(0x4000, hc->pci_iobase + 4);
5176                 /*
5177                  * some dummy reads are required to
5178                  * read valid DIP switch data
5179                  */
5180                 dips = inb(hc->pci_iobase);
5181                 dips = inb(hc->pci_iobase);
5182                 dips = inb(hc->pci_iobase);
5183                 dips = ~inb(hc->pci_iobase) & 0x3F;
5184                 outw(0x0, hc->pci_iobase + 4);
5185                 /* disable PCI auxbridge function */
5186                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5187                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5188                        m->vendor_name, m->card_name, dips);
5189                 break;
5190         case DIP_E1:
5191                 /*
5192                  * get DIP Setting for beroNet E1 cards
5193                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5194                  */
5195                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5196                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5197                        m->vendor_name, m->card_name, dips);
5198                 break;
5199         }
5200
5201         /* add to list */
5202         spin_lock_irqsave(&HFClock, flags);
5203         list_add_tail(&hc->list, &HFClist);
5204         spin_unlock_irqrestore(&HFClock, flags);
5205
5206         /* use as clock source */
5207         if (clock == HFC_cnt + 1)
5208                 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5209
5210         /* initialize hardware */
5211         hc->irq = (m->irq) ? : hc->pci_dev->irq;
5212         ret_err = init_card(hc);
5213         if (ret_err) {
5214                 printk(KERN_ERR "init card returns %d\n", ret_err);
5215                 release_card(hc);
5216                 return ret_err;
5217         }
5218
5219         /* start IRQ and return */
5220         spin_lock_irqsave(&hc->lock, flags);
5221         enable_hwirq(hc);
5222         spin_unlock_irqrestore(&hc->lock, flags);
5223         return 0;
5224
5225 free_card:
5226         release_io_hfcmulti(hc);
5227         if (hc == syncmaster)
5228                 syncmaster = NULL;
5229         kfree(hc);
5230         return ret_err;
5231 }
5232
5233 static void hfc_remove_pci(struct pci_dev *pdev)
5234 {
5235         struct hfc_multi        *card = pci_get_drvdata(pdev);
5236         u_long                  flags;
5237
5238         if (debug)
5239                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5240                        "device:%x subvendor:%x subdevice:%x\n",
5241                        pdev->vendor, pdev->device,
5242                        pdev->subsystem_vendor, pdev->subsystem_device);
5243
5244         if (card) {
5245                 spin_lock_irqsave(&HFClock, flags);
5246                 release_card(card);
5247                 spin_unlock_irqrestore(&HFClock, flags);
5248         }  else {
5249                 if (debug)
5250                         printk(KERN_DEBUG "%s: drvdata already removed\n",
5251                                __func__);
5252         }
5253 }
5254
5255 #define VENDOR_CCD      "Cologne Chip AG"
5256 #define VENDOR_BN       "beroNet GmbH"
5257 #define VENDOR_DIG      "Digium Inc."
5258 #define VENDOR_JH       "Junghanns.NET GmbH"
5259 #define VENDOR_PRIM     "PrimuX"
5260
5261 static const struct hm_map hfcm_map[] = {
5262         /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5263         /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5264         /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5265         /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5266         /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5267         /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5268         /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5269         /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5270         /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5271         /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5272         /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5273         /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5274
5275         /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5276         /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5277                  HFC_IO_MODE_REGIO, 0},
5278         /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5279         /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5280
5281         /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5282         /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5283         /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5284
5285         /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5286         /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5287         /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5288         /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5289
5290         /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5291         /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5292         /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5293
5294         /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5295                  HFC_IO_MODE_PLXSD, 0},
5296         /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5297                  HFC_IO_MODE_PLXSD, 0},
5298         /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5299         /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5300         /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5301         /*31*/  {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5302                  HFC_IO_MODE_EMBSD, XHFC_IRQ},
5303         /*32*/  {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5304         /*33*/  {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5305         /*34*/  {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5306 };
5307
5308 #undef H
5309 #define H(x)    ((unsigned long)&hfcm_map[x])
5310 static const struct pci_device_id hfmultipci_ids[] = {
5311
5312         /* Cards with HFC-4S Chip */
5313         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5314           PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5315         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5316           PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5317         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5318           PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5319         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5320           PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5321         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5322           PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5323         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5324           PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5325         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5326           PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5327         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5328           PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5329         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5330           PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5331         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5332           PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5333         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5334           PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5335         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5336           PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5337         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5338           PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5339         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5340           PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5341         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5342           0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5343         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5344           0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5345
5346         /* Cards with HFC-8S Chip */
5347         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5348           PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5349         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5350           PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5351         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5352           PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5353         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5354           PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5355         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5356           PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5357         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5358           PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5359         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5360           PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5361         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5362           PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5363         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5364           PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S  */
5365
5366
5367         /* Cards with HFC-E1 Chip */
5368         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5369           PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5370         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5371           PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5372         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5373           PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5374         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5375           PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5376
5377         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5378           PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5379         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5380           PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5381         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5382           PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5383
5384         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5385           PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5386         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5387           PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5388
5389         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5390           PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5391
5392         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5393         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5394         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5395         {0, }
5396 };
5397 #undef H
5398
5399 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5400
5401 static int
5402 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5403 {
5404         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5405         int             ret;
5406
5407         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5408                     ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5409                     ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5410                     ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5411                 printk(KERN_ERR
5412                        "Unknown HFC multiport controller (vendor:%04x device:%04x "
5413                        "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5414                        pdev->device, pdev->subsystem_vendor,
5415                        pdev->subsystem_device);
5416                 printk(KERN_ERR
5417                        "Please contact the driver maintainer for support.\n");
5418                 return -ENODEV;
5419         }
5420         ret = hfcmulti_init(m, pdev, ent);
5421         if (ret)
5422                 return ret;
5423         HFC_cnt++;
5424         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5425         return 0;
5426 }
5427
5428 static struct pci_driver hfcmultipci_driver = {
5429         .name           = "hfc_multi",
5430         .probe          = hfcmulti_probe,
5431         .remove         = hfc_remove_pci,
5432         .id_table       = hfmultipci_ids,
5433 };
5434
5435 static void __exit
5436 HFCmulti_cleanup(void)
5437 {
5438         struct hfc_multi *card, *next;
5439
5440         /* get rid of all devices of this driver */
5441         list_for_each_entry_safe(card, next, &HFClist, list)
5442                 release_card(card);
5443         pci_unregister_driver(&hfcmultipci_driver);
5444 }
5445
5446 static int __init
5447 HFCmulti_init(void)
5448 {
5449         int err;
5450         int i, xhfc = 0;
5451         struct hm_map m;
5452
5453         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5454
5455 #ifdef IRQ_DEBUG
5456         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5457 #endif
5458
5459         if (debug & DEBUG_HFCMULTI_INIT)
5460                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5461
5462         switch (poll) {
5463         case 0:
5464                 poll_timer = 6;
5465                 poll = 128;
5466                 break;
5467         case 8:
5468                 poll_timer = 2;
5469                 break;
5470         case 16:
5471                 poll_timer = 3;
5472                 break;
5473         case 32:
5474                 poll_timer = 4;
5475                 break;
5476         case 64:
5477                 poll_timer = 5;
5478                 break;
5479         case 128:
5480                 poll_timer = 6;
5481                 break;
5482         case 256:
5483                 poll_timer = 7;
5484                 break;
5485         default:
5486                 printk(KERN_ERR
5487                        "%s: Wrong poll value (%d).\n", __func__, poll);
5488                 err = -EINVAL;
5489                 return err;
5490
5491         }
5492
5493         if (!clock)
5494                 clock = 1;
5495
5496         /* Register the embedded devices.
5497          * This should be done before the PCI cards registration */
5498         switch (hwid) {
5499         case HWID_MINIP4:
5500                 xhfc = 1;
5501                 m = hfcm_map[31];
5502                 break;
5503         case HWID_MINIP8:
5504                 xhfc = 2;
5505                 m = hfcm_map[31];
5506                 break;
5507         case HWID_MINIP16:
5508                 xhfc = 4;
5509                 m = hfcm_map[31];
5510                 break;
5511         default:
5512                 xhfc = 0;
5513         }
5514
5515         for (i = 0; i < xhfc; ++i) {
5516                 err = hfcmulti_init(&m, NULL, NULL);
5517                 if (err) {
5518                         printk(KERN_ERR "error registering embedded driver: "
5519                                "%x\n", err);
5520                         return err;
5521                 }
5522                 HFC_cnt++;
5523                 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5524         }
5525
5526         /* Register the PCI cards */
5527         err = pci_register_driver(&hfcmultipci_driver);
5528         if (err < 0) {
5529                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5530                 return err;
5531         }
5532
5533         return 0;
5534 }
5535
5536
5537 module_init(HFCmulti_init);
5538 module_exit(HFCmulti_cleanup);