1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 #include <linux/bitops.h>
9 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/irqchip.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/syscore_ops.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #define IRQS_PER_BANK 32
23 struct stm32_exti_bank {
35 struct stm32_desc_irq {
40 struct stm32_exti_drv_data {
41 const struct stm32_exti_bank **exti_banks;
42 const struct stm32_desc_irq *desc_irqs;
47 struct stm32_exti_chip_data {
48 struct stm32_exti_host_data *host_data;
49 const struct stm32_exti_bank *reg_bank;
50 struct raw_spinlock rlock;
57 struct stm32_exti_host_data {
59 struct stm32_exti_chip_data *chips_data;
60 const struct stm32_exti_drv_data *drv_data;
63 static struct stm32_exti_host_data *stm32_host_data;
65 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
72 .fpr_ofst = UNDEF_REG,
75 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
79 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
80 .exti_banks = stm32f4xx_exti_banks,
81 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
84 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
91 .fpr_ofst = UNDEF_REG,
94 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
101 .fpr_ofst = UNDEF_REG,
104 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
111 .fpr_ofst = UNDEF_REG,
114 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
120 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
121 .exti_banks = stm32h7xx_exti_banks,
122 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
125 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
135 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
145 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
155 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
161 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
162 { .exti = 0, .irq_parent = 6 },
163 { .exti = 1, .irq_parent = 7 },
164 { .exti = 2, .irq_parent = 8 },
165 { .exti = 3, .irq_parent = 9 },
166 { .exti = 4, .irq_parent = 10 },
167 { .exti = 5, .irq_parent = 23 },
168 { .exti = 6, .irq_parent = 64 },
169 { .exti = 7, .irq_parent = 65 },
170 { .exti = 8, .irq_parent = 66 },
171 { .exti = 9, .irq_parent = 67 },
172 { .exti = 10, .irq_parent = 40 },
173 { .exti = 11, .irq_parent = 42 },
174 { .exti = 12, .irq_parent = 76 },
175 { .exti = 13, .irq_parent = 77 },
176 { .exti = 14, .irq_parent = 121 },
177 { .exti = 15, .irq_parent = 127 },
178 { .exti = 16, .irq_parent = 1 },
179 { .exti = 65, .irq_parent = 144 },
180 { .exti = 68, .irq_parent = 143 },
181 { .exti = 73, .irq_parent = 129 },
184 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
185 .exti_banks = stm32mp1_exti_banks,
186 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
187 .desc_irqs = stm32mp1_desc_irq,
188 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
191 static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
192 irq_hw_number_t hwirq)
194 const struct stm32_desc_irq *desc_irq;
197 if (!drv_data->desc_irqs)
200 for (i = 0; i < drv_data->irq_nr; i++) {
201 desc_irq = &drv_data->desc_irqs[i];
202 if (desc_irq->exti == hwirq)
203 return desc_irq->irq_parent;
209 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
211 struct stm32_exti_chip_data *chip_data = gc->private;
212 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
213 unsigned long pending;
215 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
216 if (stm32_bank->fpr_ofst != UNDEF_REG)
217 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
222 static void stm32_irq_handler(struct irq_desc *desc)
224 struct irq_domain *domain = irq_desc_get_handler_data(desc);
225 struct irq_chip *chip = irq_desc_get_chip(desc);
226 unsigned int virq, nbanks = domain->gc->num_chips;
227 struct irq_chip_generic *gc;
228 unsigned long pending;
229 int n, i, irq_base = 0;
231 chained_irq_enter(chip, desc);
233 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
234 gc = irq_get_domain_generic_chip(domain, irq_base);
236 while ((pending = stm32_exti_pending(gc))) {
237 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
238 virq = irq_find_mapping(domain, irq_base + n);
239 generic_handle_irq(virq);
244 chained_irq_exit(chip, desc);
247 static int stm32_exti_set_type(struct irq_data *d,
248 unsigned int type, u32 *rtsr, u32 *ftsr)
250 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
253 case IRQ_TYPE_EDGE_RISING:
257 case IRQ_TYPE_EDGE_FALLING:
261 case IRQ_TYPE_EDGE_BOTH:
272 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
274 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
275 struct stm32_exti_chip_data *chip_data = gc->private;
276 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
282 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
283 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
285 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
291 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
292 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
299 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
302 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
303 void __iomem *base = chip_data->host_data->base;
305 /* save rtsr, ftsr registers */
306 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
307 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
309 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
312 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
315 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
316 void __iomem *base = chip_data->host_data->base;
318 /* restore rtsr, ftsr, registers */
319 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
320 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
322 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
325 static void stm32_irq_suspend(struct irq_chip_generic *gc)
327 struct stm32_exti_chip_data *chip_data = gc->private;
330 stm32_chip_suspend(chip_data, gc->wake_active);
334 static void stm32_irq_resume(struct irq_chip_generic *gc)
336 struct stm32_exti_chip_data *chip_data = gc->private;
339 stm32_chip_resume(chip_data, gc->mask_cache);
343 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
344 unsigned int nr_irqs, void *data)
346 struct irq_fwspec *fwspec = data;
347 irq_hw_number_t hwirq;
349 hwirq = fwspec->param[0];
351 irq_map_generic_chip(d, virq, hwirq);
356 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
357 unsigned int nr_irqs)
359 struct irq_data *data = irq_domain_get_irq_data(d, virq);
361 irq_domain_reset_irq_data(data);
364 static const struct irq_domain_ops irq_exti_domain_ops = {
365 .map = irq_map_generic_chip,
366 .alloc = stm32_exti_alloc,
367 .free = stm32_exti_free,
368 .xlate = irq_domain_xlate_twocell,
371 static void stm32_irq_ack(struct irq_data *d)
373 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
374 struct stm32_exti_chip_data *chip_data = gc->private;
375 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
379 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
380 if (stm32_bank->fpr_ofst != UNDEF_REG)
381 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
386 /* directly set the target bit without reading first. */
387 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
389 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
390 void __iomem *base = chip_data->host_data->base;
391 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
393 writel_relaxed(val, base + reg);
396 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
398 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
399 void __iomem *base = chip_data->host_data->base;
402 val = readl_relaxed(base + reg);
403 val |= BIT(d->hwirq % IRQS_PER_BANK);
404 writel_relaxed(val, base + reg);
409 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
411 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
412 void __iomem *base = chip_data->host_data->base;
415 val = readl_relaxed(base + reg);
416 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
417 writel_relaxed(val, base + reg);
422 static void stm32_exti_h_eoi(struct irq_data *d)
424 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
425 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
427 raw_spin_lock(&chip_data->rlock);
429 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
430 if (stm32_bank->fpr_ofst != UNDEF_REG)
431 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
433 raw_spin_unlock(&chip_data->rlock);
435 if (d->parent_data->chip)
436 irq_chip_eoi_parent(d);
439 static void stm32_exti_h_mask(struct irq_data *d)
441 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
442 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
444 raw_spin_lock(&chip_data->rlock);
445 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
446 raw_spin_unlock(&chip_data->rlock);
448 if (d->parent_data->chip)
449 irq_chip_mask_parent(d);
452 static void stm32_exti_h_unmask(struct irq_data *d)
454 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
455 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
457 raw_spin_lock(&chip_data->rlock);
458 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
459 raw_spin_unlock(&chip_data->rlock);
461 if (d->parent_data->chip)
462 irq_chip_unmask_parent(d);
465 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
467 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
468 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
469 void __iomem *base = chip_data->host_data->base;
473 raw_spin_lock(&chip_data->rlock);
474 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
475 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
477 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
479 raw_spin_unlock(&chip_data->rlock);
483 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
484 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
485 raw_spin_unlock(&chip_data->rlock);
490 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
492 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
493 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
495 raw_spin_lock(&chip_data->rlock);
498 chip_data->wake_active |= mask;
500 chip_data->wake_active &= ~mask;
502 raw_spin_unlock(&chip_data->rlock);
507 static int stm32_exti_h_set_affinity(struct irq_data *d,
508 const struct cpumask *dest, bool force)
510 if (d->parent_data->chip)
511 return irq_chip_set_affinity_parent(d, dest, force);
517 static int stm32_exti_h_suspend(void)
519 struct stm32_exti_chip_data *chip_data;
522 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
523 chip_data = &stm32_host_data->chips_data[i];
524 raw_spin_lock(&chip_data->rlock);
525 stm32_chip_suspend(chip_data, chip_data->wake_active);
526 raw_spin_unlock(&chip_data->rlock);
532 static void stm32_exti_h_resume(void)
534 struct stm32_exti_chip_data *chip_data;
537 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
538 chip_data = &stm32_host_data->chips_data[i];
539 raw_spin_lock(&chip_data->rlock);
540 stm32_chip_resume(chip_data, chip_data->mask_cache);
541 raw_spin_unlock(&chip_data->rlock);
545 static struct syscore_ops stm32_exti_h_syscore_ops = {
546 .suspend = stm32_exti_h_suspend,
547 .resume = stm32_exti_h_resume,
550 static void stm32_exti_h_syscore_init(void)
552 register_syscore_ops(&stm32_exti_h_syscore_ops);
555 static inline void stm32_exti_h_syscore_init(void) {}
558 static struct irq_chip stm32_exti_h_chip = {
559 .name = "stm32-exti-h",
560 .irq_eoi = stm32_exti_h_eoi,
561 .irq_mask = stm32_exti_h_mask,
562 .irq_unmask = stm32_exti_h_unmask,
563 .irq_retrigger = irq_chip_retrigger_hierarchy,
564 .irq_set_type = stm32_exti_h_set_type,
565 .irq_set_wake = stm32_exti_h_set_wake,
566 .flags = IRQCHIP_MASK_ON_SUSPEND,
567 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
570 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
572 unsigned int nr_irqs, void *data)
574 struct stm32_exti_host_data *host_data = dm->host_data;
575 struct stm32_exti_chip_data *chip_data;
576 struct irq_fwspec *fwspec = data;
577 struct irq_fwspec p_fwspec;
578 irq_hw_number_t hwirq;
581 hwirq = fwspec->param[0];
582 bank = hwirq / IRQS_PER_BANK;
583 chip_data = &host_data->chips_data[bank];
585 irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
586 &stm32_exti_h_chip, chip_data);
588 p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
590 p_fwspec.fwnode = dm->parent->fwnode;
591 p_fwspec.param_count = 3;
592 p_fwspec.param[0] = GIC_SPI;
593 p_fwspec.param[1] = p_irq;
594 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
596 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
603 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
604 struct device_node *node)
606 struct stm32_exti_host_data *host_data;
608 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
612 host_data->drv_data = dd;
613 host_data->chips_data = kcalloc(dd->bank_nr,
614 sizeof(struct stm32_exti_chip_data),
616 if (!host_data->chips_data)
619 host_data->base = of_iomap(node, 0);
620 if (!host_data->base) {
621 pr_err("%pOF: Unable to map registers\n", node);
622 goto free_chips_data;
625 stm32_host_data = host_data;
630 kfree(host_data->chips_data);
638 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
640 struct device_node *node)
642 const struct stm32_exti_bank *stm32_bank;
643 struct stm32_exti_chip_data *chip_data;
644 void __iomem *base = h_data->base;
647 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
648 chip_data = &h_data->chips_data[bank_idx];
649 chip_data->host_data = h_data;
650 chip_data->reg_bank = stm32_bank;
652 raw_spin_lock_init(&chip_data->rlock);
654 /* Determine number of irqs supported */
655 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
656 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
659 * This IP has no reset, so after hot reboot we should
660 * clear registers to avoid residue
662 writel_relaxed(0, base + stm32_bank->imr_ofst);
663 writel_relaxed(0, base + stm32_bank->emr_ofst);
665 pr_info("%s: bank%d, External IRQs available:%#x\n",
666 node->full_name, bank_idx, irqs_mask);
671 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
672 struct device_node *node)
674 struct stm32_exti_host_data *host_data;
675 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
677 struct irq_chip_generic *gc;
678 struct irq_domain *domain;
680 host_data = stm32_exti_host_init(drv_data, node);
684 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
685 &irq_exti_domain_ops, NULL);
687 pr_err("%s: Could not register interrupt domain.\n",
693 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
694 handle_edge_irq, clr, 0, 0);
696 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
698 goto out_free_domain;
701 for (i = 0; i < drv_data->bank_nr; i++) {
702 const struct stm32_exti_bank *stm32_bank;
703 struct stm32_exti_chip_data *chip_data;
705 stm32_bank = drv_data->exti_banks[i];
706 chip_data = stm32_exti_chip_init(host_data, i, node);
708 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
710 gc->reg_base = host_data->base;
711 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
712 gc->chip_types->chip.irq_ack = stm32_irq_ack;
713 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
714 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
715 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
716 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
717 gc->suspend = stm32_irq_suspend;
718 gc->resume = stm32_irq_resume;
719 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
721 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
722 gc->private = (void *)chip_data;
725 nr_irqs = of_irq_count(node);
726 for (i = 0; i < nr_irqs; i++) {
727 unsigned int irq = irq_of_parse_and_map(node, i);
729 irq_set_handler_data(irq, domain);
730 irq_set_chained_handler(irq, stm32_irq_handler);
736 irq_domain_remove(domain);
738 iounmap(host_data->base);
739 kfree(host_data->chips_data);
744 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
745 .alloc = stm32_exti_h_domain_alloc,
746 .free = irq_domain_free_irqs_common,
750 __init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
751 struct device_node *node,
752 struct device_node *parent)
754 struct irq_domain *parent_domain, *domain;
755 struct stm32_exti_host_data *host_data;
758 parent_domain = irq_find_host(parent);
759 if (!parent_domain) {
760 pr_err("interrupt-parent not found\n");
764 host_data = stm32_exti_host_init(drv_data, node);
768 for (i = 0; i < drv_data->bank_nr; i++)
769 stm32_exti_chip_init(host_data, i, node);
771 domain = irq_domain_add_hierarchy(parent_domain, 0,
772 drv_data->bank_nr * IRQS_PER_BANK,
773 node, &stm32_exti_h_domain_ops,
777 pr_err("%s: Could not register exti domain.\n", node->name);
782 stm32_exti_h_syscore_init();
787 iounmap(host_data->base);
788 kfree(host_data->chips_data);
793 static int __init stm32f4_exti_of_init(struct device_node *np,
794 struct device_node *parent)
796 return stm32_exti_init(&stm32f4xx_drv_data, np);
799 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
801 static int __init stm32h7_exti_of_init(struct device_node *np,
802 struct device_node *parent)
804 return stm32_exti_init(&stm32h7xx_drv_data, np);
807 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
809 static int __init stm32mp1_exti_of_init(struct device_node *np,
810 struct device_node *parent)
812 return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
815 IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);