1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/hwspinlock.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/syscore_ops.h>
23 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 #define IRQS_PER_BANK 32
27 #define HWSPNLCK_TIMEOUT 1000 /* usec */
29 struct stm32_exti_bank {
41 struct stm32_desc_irq {
44 struct irq_chip *chip;
47 struct stm32_exti_drv_data {
48 const struct stm32_exti_bank **exti_banks;
49 const struct stm32_desc_irq *desc_irqs;
54 struct stm32_exti_chip_data {
55 struct stm32_exti_host_data *host_data;
56 const struct stm32_exti_bank *reg_bank;
57 struct raw_spinlock rlock;
64 struct stm32_exti_host_data {
66 struct stm32_exti_chip_data *chips_data;
67 const struct stm32_exti_drv_data *drv_data;
68 struct hwspinlock *hwlock;
71 static struct stm32_exti_host_data *stm32_host_data;
73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
80 .fpr_ofst = UNDEF_REG,
83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
88 .exti_banks = stm32f4xx_exti_banks,
89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
99 .fpr_ofst = UNDEF_REG,
102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
109 .fpr_ofst = UNDEF_REG,
112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
119 .fpr_ofst = UNDEF_REG,
122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
129 .exti_banks = stm32h7xx_exti_banks,
130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
133 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
143 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
153 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
169 static struct irq_chip stm32_exti_h_chip;
170 static struct irq_chip stm32_exti_h_chip_direct;
172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
196 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
197 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
198 { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
199 { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
200 { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
201 { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
202 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
203 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
204 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
205 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
206 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
207 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
210 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
211 .exti_banks = stm32mp1_exti_banks,
212 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
213 .desc_irqs = stm32mp1_desc_irq,
214 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
218 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
219 irq_hw_number_t hwirq)
221 const struct stm32_desc_irq *desc = NULL;
224 if (!drv_data->desc_irqs)
227 for (i = 0; i < drv_data->irq_nr; i++) {
228 desc = &drv_data->desc_irqs[i];
229 if (desc->exti == hwirq)
236 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
238 struct stm32_exti_chip_data *chip_data = gc->private;
239 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
240 unsigned long pending;
242 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
243 if (stm32_bank->fpr_ofst != UNDEF_REG)
244 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
249 static void stm32_irq_handler(struct irq_desc *desc)
251 struct irq_domain *domain = irq_desc_get_handler_data(desc);
252 struct irq_chip *chip = irq_desc_get_chip(desc);
253 unsigned int virq, nbanks = domain->gc->num_chips;
254 struct irq_chip_generic *gc;
255 unsigned long pending;
256 int n, i, irq_base = 0;
258 chained_irq_enter(chip, desc);
260 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
261 gc = irq_get_domain_generic_chip(domain, irq_base);
263 while ((pending = stm32_exti_pending(gc))) {
264 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
265 virq = irq_find_mapping(domain, irq_base + n);
266 generic_handle_irq(virq);
271 chained_irq_exit(chip, desc);
274 static int stm32_exti_set_type(struct irq_data *d,
275 unsigned int type, u32 *rtsr, u32 *ftsr)
277 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
280 case IRQ_TYPE_EDGE_RISING:
284 case IRQ_TYPE_EDGE_FALLING:
288 case IRQ_TYPE_EDGE_BOTH:
299 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
301 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
302 struct stm32_exti_chip_data *chip_data = gc->private;
303 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
304 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
311 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
313 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
318 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
319 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
321 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
325 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
326 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
330 hwspin_unlock_in_atomic(hwlock);
337 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
340 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
341 void __iomem *base = chip_data->host_data->base;
343 /* save rtsr, ftsr registers */
344 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
345 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
347 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
350 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
353 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
354 void __iomem *base = chip_data->host_data->base;
356 /* restore rtsr, ftsr, registers */
357 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
358 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
360 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
363 static void stm32_irq_suspend(struct irq_chip_generic *gc)
365 struct stm32_exti_chip_data *chip_data = gc->private;
368 stm32_chip_suspend(chip_data, gc->wake_active);
372 static void stm32_irq_resume(struct irq_chip_generic *gc)
374 struct stm32_exti_chip_data *chip_data = gc->private;
377 stm32_chip_resume(chip_data, gc->mask_cache);
381 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
382 unsigned int nr_irqs, void *data)
384 struct irq_fwspec *fwspec = data;
385 irq_hw_number_t hwirq;
387 hwirq = fwspec->param[0];
389 irq_map_generic_chip(d, virq, hwirq);
394 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
395 unsigned int nr_irqs)
397 struct irq_data *data = irq_domain_get_irq_data(d, virq);
399 irq_domain_reset_irq_data(data);
402 static const struct irq_domain_ops irq_exti_domain_ops = {
403 .map = irq_map_generic_chip,
404 .alloc = stm32_exti_alloc,
405 .free = stm32_exti_free,
406 .xlate = irq_domain_xlate_twocell,
409 static void stm32_irq_ack(struct irq_data *d)
411 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
412 struct stm32_exti_chip_data *chip_data = gc->private;
413 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
417 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
418 if (stm32_bank->fpr_ofst != UNDEF_REG)
419 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
424 /* directly set the target bit without reading first. */
425 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
427 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
428 void __iomem *base = chip_data->host_data->base;
429 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
431 writel_relaxed(val, base + reg);
434 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
436 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
437 void __iomem *base = chip_data->host_data->base;
440 val = readl_relaxed(base + reg);
441 val |= BIT(d->hwirq % IRQS_PER_BANK);
442 writel_relaxed(val, base + reg);
447 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
449 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
450 void __iomem *base = chip_data->host_data->base;
453 val = readl_relaxed(base + reg);
454 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
455 writel_relaxed(val, base + reg);
460 static void stm32_exti_h_eoi(struct irq_data *d)
462 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
463 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
465 raw_spin_lock(&chip_data->rlock);
467 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
468 if (stm32_bank->fpr_ofst != UNDEF_REG)
469 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
471 raw_spin_unlock(&chip_data->rlock);
473 if (d->parent_data->chip)
474 irq_chip_eoi_parent(d);
477 static void stm32_exti_h_mask(struct irq_data *d)
479 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
480 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
482 raw_spin_lock(&chip_data->rlock);
483 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
484 raw_spin_unlock(&chip_data->rlock);
486 if (d->parent_data->chip)
487 irq_chip_mask_parent(d);
490 static void stm32_exti_h_unmask(struct irq_data *d)
492 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
493 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
495 raw_spin_lock(&chip_data->rlock);
496 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
497 raw_spin_unlock(&chip_data->rlock);
499 if (d->parent_data->chip)
500 irq_chip_unmask_parent(d);
503 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
505 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
506 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
507 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
508 void __iomem *base = chip_data->host_data->base;
512 raw_spin_lock(&chip_data->rlock);
515 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
517 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
522 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
523 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
525 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
529 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
530 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
534 hwspin_unlock_in_atomic(hwlock);
536 raw_spin_unlock(&chip_data->rlock);
541 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
543 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
544 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
546 raw_spin_lock(&chip_data->rlock);
549 chip_data->wake_active |= mask;
551 chip_data->wake_active &= ~mask;
553 raw_spin_unlock(&chip_data->rlock);
558 static int stm32_exti_h_set_affinity(struct irq_data *d,
559 const struct cpumask *dest, bool force)
561 if (d->parent_data->chip)
562 return irq_chip_set_affinity_parent(d, dest, force);
567 static int __maybe_unused stm32_exti_h_suspend(void)
569 struct stm32_exti_chip_data *chip_data;
572 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
573 chip_data = &stm32_host_data->chips_data[i];
574 raw_spin_lock(&chip_data->rlock);
575 stm32_chip_suspend(chip_data, chip_data->wake_active);
576 raw_spin_unlock(&chip_data->rlock);
582 static void __maybe_unused stm32_exti_h_resume(void)
584 struct stm32_exti_chip_data *chip_data;
587 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
588 chip_data = &stm32_host_data->chips_data[i];
589 raw_spin_lock(&chip_data->rlock);
590 stm32_chip_resume(chip_data, chip_data->mask_cache);
591 raw_spin_unlock(&chip_data->rlock);
595 static struct syscore_ops stm32_exti_h_syscore_ops = {
596 #ifdef CONFIG_PM_SLEEP
597 .suspend = stm32_exti_h_suspend,
598 .resume = stm32_exti_h_resume,
602 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
604 stm32_host_data = host_data;
605 register_syscore_ops(&stm32_exti_h_syscore_ops);
608 static void stm32_exti_h_syscore_deinit(void)
610 unregister_syscore_ops(&stm32_exti_h_syscore_ops);
613 static int stm32_exti_h_retrigger(struct irq_data *d)
615 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
616 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
617 void __iomem *base = chip_data->host_data->base;
618 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
620 writel_relaxed(mask, base + stm32_bank->swier_ofst);
625 static struct irq_chip stm32_exti_h_chip = {
626 .name = "stm32-exti-h",
627 .irq_eoi = stm32_exti_h_eoi,
628 .irq_mask = stm32_exti_h_mask,
629 .irq_unmask = stm32_exti_h_unmask,
630 .irq_retrigger = stm32_exti_h_retrigger,
631 .irq_set_type = stm32_exti_h_set_type,
632 .irq_set_wake = stm32_exti_h_set_wake,
633 .flags = IRQCHIP_MASK_ON_SUSPEND,
634 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
637 static struct irq_chip stm32_exti_h_chip_direct = {
638 .name = "stm32-exti-h-direct",
639 .irq_eoi = irq_chip_eoi_parent,
640 .irq_ack = irq_chip_ack_parent,
641 .irq_mask = irq_chip_mask_parent,
642 .irq_unmask = irq_chip_unmask_parent,
643 .irq_retrigger = irq_chip_retrigger_hierarchy,
644 .irq_set_type = irq_chip_set_type_parent,
645 .irq_set_wake = stm32_exti_h_set_wake,
646 .flags = IRQCHIP_MASK_ON_SUSPEND,
647 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
650 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
652 unsigned int nr_irqs, void *data)
654 struct stm32_exti_host_data *host_data = dm->host_data;
655 struct stm32_exti_chip_data *chip_data;
656 const struct stm32_desc_irq *desc;
657 struct irq_fwspec *fwspec = data;
658 struct irq_fwspec p_fwspec;
659 irq_hw_number_t hwirq;
662 hwirq = fwspec->param[0];
663 bank = hwirq / IRQS_PER_BANK;
664 chip_data = &host_data->chips_data[bank];
667 desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
671 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
673 if (desc->irq_parent) {
674 p_fwspec.fwnode = dm->parent->fwnode;
675 p_fwspec.param_count = 3;
676 p_fwspec.param[0] = GIC_SPI;
677 p_fwspec.param[1] = desc->irq_parent;
678 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
680 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
687 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
688 struct device_node *node)
690 struct stm32_exti_host_data *host_data;
692 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
696 host_data->drv_data = dd;
697 host_data->chips_data = kcalloc(dd->bank_nr,
698 sizeof(struct stm32_exti_chip_data),
700 if (!host_data->chips_data)
703 host_data->base = of_iomap(node, 0);
704 if (!host_data->base) {
705 pr_err("%pOF: Unable to map registers\n", node);
706 goto free_chips_data;
709 stm32_host_data = host_data;
714 kfree(host_data->chips_data);
722 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
724 struct device_node *node)
726 const struct stm32_exti_bank *stm32_bank;
727 struct stm32_exti_chip_data *chip_data;
728 void __iomem *base = h_data->base;
730 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
731 chip_data = &h_data->chips_data[bank_idx];
732 chip_data->host_data = h_data;
733 chip_data->reg_bank = stm32_bank;
735 raw_spin_lock_init(&chip_data->rlock);
738 * This IP has no reset, so after hot reboot we should
739 * clear registers to avoid residue
741 writel_relaxed(0, base + stm32_bank->imr_ofst);
742 writel_relaxed(0, base + stm32_bank->emr_ofst);
744 pr_info("%pOF: bank%d\n", node, bank_idx);
749 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
750 struct device_node *node)
752 struct stm32_exti_host_data *host_data;
753 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
755 struct irq_chip_generic *gc;
756 struct irq_domain *domain;
758 host_data = stm32_exti_host_init(drv_data, node);
762 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
763 &irq_exti_domain_ops, NULL);
765 pr_err("%pOFn: Could not register interrupt domain.\n",
771 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
772 handle_edge_irq, clr, 0, 0);
774 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
776 goto out_free_domain;
779 for (i = 0; i < drv_data->bank_nr; i++) {
780 const struct stm32_exti_bank *stm32_bank;
781 struct stm32_exti_chip_data *chip_data;
783 stm32_bank = drv_data->exti_banks[i];
784 chip_data = stm32_exti_chip_init(host_data, i, node);
786 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
788 gc->reg_base = host_data->base;
789 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
790 gc->chip_types->chip.irq_ack = stm32_irq_ack;
791 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
792 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
793 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
794 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
795 gc->suspend = stm32_irq_suspend;
796 gc->resume = stm32_irq_resume;
797 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
799 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
800 gc->private = (void *)chip_data;
803 nr_irqs = of_irq_count(node);
804 for (i = 0; i < nr_irqs; i++) {
805 unsigned int irq = irq_of_parse_and_map(node, i);
807 irq_set_handler_data(irq, domain);
808 irq_set_chained_handler(irq, stm32_irq_handler);
814 irq_domain_remove(domain);
816 iounmap(host_data->base);
817 kfree(host_data->chips_data);
822 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
823 .alloc = stm32_exti_h_domain_alloc,
824 .free = irq_domain_free_irqs_common,
825 .xlate = irq_domain_xlate_twocell,
828 static void stm32_exti_remove_irq(void *data)
830 struct irq_domain *domain = data;
832 irq_domain_remove(domain);
835 static int stm32_exti_remove(struct platform_device *pdev)
837 stm32_exti_h_syscore_deinit();
841 static int stm32_exti_probe(struct platform_device *pdev)
844 struct device *dev = &pdev->dev;
845 struct device_node *np = dev->of_node;
846 struct irq_domain *parent_domain, *domain;
847 struct stm32_exti_host_data *host_data;
848 const struct stm32_exti_drv_data *drv_data;
849 struct resource *res;
851 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
855 /* check for optional hwspinlock which may be not available yet */
856 ret = of_hwspin_lock_get_id(np, 0);
857 if (ret == -EPROBE_DEFER)
858 /* hwspinlock framework not yet ready */
862 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
863 if (!host_data->hwlock) {
864 dev_err(dev, "Failed to request hwspinlock\n");
867 } else if (ret != -ENOENT) {
868 /* note: ENOENT is a valid case (means 'no hwspinlock') */
869 dev_err(dev, "Failed to get hwspinlock\n");
873 /* initialize host_data */
874 drv_data = of_device_get_match_data(dev);
876 dev_err(dev, "no of match data\n");
879 host_data->drv_data = drv_data;
881 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
882 sizeof(*host_data->chips_data),
884 if (!host_data->chips_data)
887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
888 host_data->base = devm_ioremap_resource(dev, res);
889 if (IS_ERR(host_data->base)) {
890 dev_err(dev, "Unable to map registers\n");
891 return PTR_ERR(host_data->base);
894 for (i = 0; i < drv_data->bank_nr; i++)
895 stm32_exti_chip_init(host_data, i, np);
897 parent_domain = irq_find_host(of_irq_find_parent(np));
898 if (!parent_domain) {
899 dev_err(dev, "GIC interrupt-parent not found\n");
903 domain = irq_domain_add_hierarchy(parent_domain, 0,
904 drv_data->bank_nr * IRQS_PER_BANK,
905 np, &stm32_exti_h_domain_ops,
909 dev_err(dev, "Could not register exti domain\n");
913 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
917 stm32_exti_h_syscore_init(host_data);
922 /* platform driver only for MP1 */
923 static const struct of_device_id stm32_exti_ids[] = {
924 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
927 MODULE_DEVICE_TABLE(of, stm32_exti_ids);
929 static struct platform_driver stm32_exti_driver = {
930 .probe = stm32_exti_probe,
931 .remove = stm32_exti_remove,
933 .name = "stm32_exti",
934 .of_match_table = stm32_exti_ids,
938 static int __init stm32_exti_arch_init(void)
940 return platform_driver_register(&stm32_exti_driver);
943 static void __exit stm32_exti_arch_exit(void)
945 return platform_driver_unregister(&stm32_exti_driver);
948 arch_initcall(stm32_exti_arch_init);
949 module_exit(stm32_exti_arch_exit);
951 /* no platform driver for F4 and H7 */
952 static int __init stm32f4_exti_of_init(struct device_node *np,
953 struct device_node *parent)
955 return stm32_exti_init(&stm32f4xx_drv_data, np);
958 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
960 static int __init stm32h7_exti_of_init(struct device_node *np,
961 struct device_node *parent)
963 return stm32_exti_init(&stm32h7xx_drv_data, np);
966 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);