1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2003-2004 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/device.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irqchip.h>
20 #include <linux/irqchip/chained_irq.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
25 #include <asm/exception.h>
26 #include <asm/mach/irq.h>
28 #include <mach/regs-irq.h>
29 #include <mach/regs-gpio.h>
32 #include <plat/regs-irqtype.h>
35 #define S3C_IRQTYPE_NONE 0
36 #define S3C_IRQTYPE_EINT 1
37 #define S3C_IRQTYPE_EDGE 2
38 #define S3C_IRQTYPE_LEVEL 3
43 unsigned long parent_irq;
45 /* data gets filled during init */
46 struct s3c_irq_intc *intc;
47 unsigned long sub_bits;
48 struct s3c_irq_intc *sub_intc;
52 * Structure holding the controller data
53 * @reg_pending register holding pending irqs
54 * @reg_intpnd special register intpnd in main intc
55 * @reg_mask mask register
56 * @domain irq_domain of the controller
57 * @parent parent controller for ext and sub irqs
58 * @irqs irq-data, always s3c_irq_data[32]
61 void __iomem *reg_pending;
62 void __iomem *reg_intpnd;
63 void __iomem *reg_mask;
64 struct irq_domain *domain;
65 struct s3c_irq_intc *parent;
66 struct s3c_irq_data *irqs;
70 * Array holding pointers to the global controller structs
73 * [2] ... main_intc2 on s3c2416
75 static struct s3c_irq_intc *s3c_intc[3];
77 static void s3c_irq_mask(struct irq_data *data)
79 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
80 struct s3c_irq_intc *intc = irq_data->intc;
81 struct s3c_irq_intc *parent_intc = intc->parent;
82 struct s3c_irq_data *parent_data;
86 mask = readl_relaxed(intc->reg_mask);
87 mask |= (1UL << irq_data->offset);
88 writel_relaxed(mask, intc->reg_mask);
91 parent_data = &parent_intc->irqs[irq_data->parent_irq];
93 /* check to see if we need to mask the parent IRQ
94 * The parent_irq is always in main_intc, so the hwirq
95 * for find_mapping does not need an offset in any case.
97 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
98 irqno = irq_find_mapping(parent_intc->domain,
99 irq_data->parent_irq);
100 s3c_irq_mask(irq_get_irq_data(irqno));
105 static void s3c_irq_unmask(struct irq_data *data)
107 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
108 struct s3c_irq_intc *intc = irq_data->intc;
109 struct s3c_irq_intc *parent_intc = intc->parent;
113 mask = readl_relaxed(intc->reg_mask);
114 mask &= ~(1UL << irq_data->offset);
115 writel_relaxed(mask, intc->reg_mask);
118 irqno = irq_find_mapping(parent_intc->domain,
119 irq_data->parent_irq);
120 s3c_irq_unmask(irq_get_irq_data(irqno));
124 static inline void s3c_irq_ack(struct irq_data *data)
126 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
127 struct s3c_irq_intc *intc = irq_data->intc;
128 unsigned long bitval = 1UL << irq_data->offset;
130 writel_relaxed(bitval, intc->reg_pending);
131 if (intc->reg_intpnd)
132 writel_relaxed(bitval, intc->reg_intpnd);
135 static int s3c_irq_type(struct irq_data *data, unsigned int type)
140 case IRQ_TYPE_EDGE_RISING:
141 case IRQ_TYPE_EDGE_FALLING:
142 case IRQ_TYPE_EDGE_BOTH:
143 irq_set_handler(data->irq, handle_edge_irq);
145 case IRQ_TYPE_LEVEL_LOW:
146 case IRQ_TYPE_LEVEL_HIGH:
147 irq_set_handler(data->irq, handle_level_irq);
150 pr_err("No such irq type %d\n", type);
157 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
158 void __iomem *extint_reg,
159 unsigned long gpcon_offset,
160 unsigned long extint_offset,
163 unsigned long newvalue = 0, value;
165 /* Set the GPIO to external interrupt mode */
166 value = readl_relaxed(gpcon_reg);
167 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
168 writel_relaxed(value, gpcon_reg);
170 /* Set the external interrupt to pointed trigger type */
174 pr_warn("No edge setting!\n");
177 case IRQ_TYPE_EDGE_RISING:
178 newvalue = S3C2410_EXTINT_RISEEDGE;
181 case IRQ_TYPE_EDGE_FALLING:
182 newvalue = S3C2410_EXTINT_FALLEDGE;
185 case IRQ_TYPE_EDGE_BOTH:
186 newvalue = S3C2410_EXTINT_BOTHEDGE;
189 case IRQ_TYPE_LEVEL_LOW:
190 newvalue = S3C2410_EXTINT_LOWLEV;
193 case IRQ_TYPE_LEVEL_HIGH:
194 newvalue = S3C2410_EXTINT_HILEV;
198 pr_err("No such irq type %d\n", type);
202 value = readl_relaxed(extint_reg);
203 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
204 writel_relaxed(value, extint_reg);
209 static int s3c_irqext_type(struct irq_data *data, unsigned int type)
211 void __iomem *extint_reg;
212 void __iomem *gpcon_reg;
213 unsigned long gpcon_offset, extint_offset;
215 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
216 gpcon_reg = S3C2410_GPFCON;
217 extint_reg = S3C24XX_EXTINT0;
218 gpcon_offset = (data->hwirq) * 2;
219 extint_offset = (data->hwirq) * 4;
220 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
221 gpcon_reg = S3C2410_GPGCON;
222 extint_reg = S3C24XX_EXTINT1;
223 gpcon_offset = (data->hwirq - 8) * 2;
224 extint_offset = (data->hwirq - 8) * 4;
225 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
226 gpcon_reg = S3C2410_GPGCON;
227 extint_reg = S3C24XX_EXTINT2;
228 gpcon_offset = (data->hwirq - 8) * 2;
229 extint_offset = (data->hwirq - 16) * 4;
234 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
235 extint_offset, type);
238 static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
240 void __iomem *extint_reg;
241 void __iomem *gpcon_reg;
242 unsigned long gpcon_offset, extint_offset;
244 if (data->hwirq <= 3) {
245 gpcon_reg = S3C2410_GPFCON;
246 extint_reg = S3C24XX_EXTINT0;
247 gpcon_offset = (data->hwirq) * 2;
248 extint_offset = (data->hwirq) * 4;
253 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
254 extint_offset, type);
257 static struct irq_chip s3c_irq_chip = {
259 .irq_ack = s3c_irq_ack,
260 .irq_mask = s3c_irq_mask,
261 .irq_unmask = s3c_irq_unmask,
262 .irq_set_type = s3c_irq_type,
263 .irq_set_wake = s3c_irq_wake
266 static struct irq_chip s3c_irq_level_chip = {
268 .irq_mask = s3c_irq_mask,
269 .irq_unmask = s3c_irq_unmask,
270 .irq_ack = s3c_irq_ack,
271 .irq_set_type = s3c_irq_type,
274 static struct irq_chip s3c_irqext_chip = {
276 .irq_mask = s3c_irq_mask,
277 .irq_unmask = s3c_irq_unmask,
278 .irq_ack = s3c_irq_ack,
279 .irq_set_type = s3c_irqext_type,
280 .irq_set_wake = s3c_irqext_wake
283 static struct irq_chip s3c_irq_eint0t4 = {
285 .irq_ack = s3c_irq_ack,
286 .irq_mask = s3c_irq_mask,
287 .irq_unmask = s3c_irq_unmask,
288 .irq_set_wake = s3c_irq_wake,
289 .irq_set_type = s3c_irqext0_type,
292 static void s3c_irq_demux(struct irq_desc *desc)
294 struct irq_chip *chip = irq_desc_get_chip(desc);
295 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
296 struct s3c_irq_intc *intc = irq_data->intc;
297 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
298 unsigned int n, offset, irq;
299 unsigned long src, msk;
301 /* we're using individual domains for the non-dt case
302 * and one big domain for the dt case where the subintc
303 * starts at hwirq number 32.
305 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
307 chained_irq_enter(chip, desc);
309 src = readl_relaxed(sub_intc->reg_pending);
310 msk = readl_relaxed(sub_intc->reg_mask);
313 src &= irq_data->sub_bits;
318 irq = irq_find_mapping(sub_intc->domain, offset + n);
319 generic_handle_irq(irq);
322 chained_irq_exit(chip, desc);
325 static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
326 struct pt_regs *regs, int intc_offset)
331 pnd = readl_relaxed(intc->reg_intpnd);
335 /* non-dt machines use individual domains */
336 if (!irq_domain_get_of_node(intc->domain))
339 /* We have a problem that the INTOFFSET register does not always
340 * show one interrupt. Occasionally we get two interrupts through
341 * the prioritiser, and this causes the INTOFFSET register to show
342 * what looks like the logical-or of the two interrupt numbers.
344 * Thanks to Klaus, Shannon, et al for helping to debug this problem
346 offset = readl_relaxed(intc->reg_intpnd + 4);
348 /* Find the bit manually, when the offset is wrong.
349 * The pending register only ever contains the one bit of the next
350 * interrupt to handle.
352 if (!(pnd & (1 << offset)))
355 handle_domain_irq(intc->domain, intc_offset + offset, regs);
359 asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
363 * For platform based machines, neither ERR nor NULL can happen here.
364 * The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds:
366 * s3c_intc[0] = s3c24xx_init_intc()
368 * If this fails, the next calls to s3c24xx_init_intc() won't be executed.
370 * For DT machine, s3c_init_intc_of() could set the IRQ handler without
371 * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no
372 * such code path, so again the s3c_intc[0] will have a valid pointer if
373 * set_handle_irq() is called.
375 * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something.
377 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
380 if (!IS_ERR_OR_NULL(s3c_intc[2]))
381 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
390 * s3c24xx_set_fiq - set the FIQ routing
391 * @irq: IRQ number to route to FIQ on processor.
392 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
394 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
395 * @on is true, the @irq is checked to see if it can be routed and the
396 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
397 * routing is cleared, regardless of which @irq is specified.
399 int s3c24xx_set_fiq(unsigned int irq, bool on)
405 offs = irq - FIQ_START;
414 writel_relaxed(intmod, S3C2410_INTMOD);
418 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
421 static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
424 struct s3c_irq_intc *intc = h->host_data;
425 struct s3c_irq_data *irq_data = &intc->irqs[hw];
426 struct s3c_irq_intc *parent_intc;
427 struct s3c_irq_data *parent_irq_data;
430 /* attach controller pointer to irq_data */
431 irq_data->intc = intc;
432 irq_data->offset = hw;
434 parent_intc = intc->parent;
436 /* set handler and flags */
437 switch (irq_data->type) {
438 case S3C_IRQTYPE_NONE:
440 case S3C_IRQTYPE_EINT:
441 /* On the S3C2412, the EINT0to3 have a parent irq
442 * but need the s3c_irq_eint0t4 chip
444 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
445 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
448 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
451 case S3C_IRQTYPE_EDGE:
452 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
453 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
456 irq_set_chip_and_handler(virq, &s3c_irq_chip,
459 case S3C_IRQTYPE_LEVEL:
461 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
464 irq_set_chip_and_handler(virq, &s3c_irq_chip,
468 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
472 irq_set_chip_data(virq, irq_data);
474 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
475 if (irq_data->parent_irq > 31) {
476 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
477 irq_data->parent_irq);
481 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
482 parent_irq_data->sub_intc = intc;
483 parent_irq_data->sub_bits |= (1UL << hw);
485 /* attach the demuxer to the parent irq */
486 irqno = irq_find_mapping(parent_intc->domain,
487 irq_data->parent_irq);
489 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
490 irq_data->parent_irq);
493 irq_set_chained_handler(irqno, s3c_irq_demux);
499 static const struct irq_domain_ops s3c24xx_irq_ops = {
500 .map = s3c24xx_irq_map,
501 .xlate = irq_domain_xlate_twocell,
504 static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
506 void __iomem *reg_source;
511 /* if intpnd is set, read the next pending irq from there */
512 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
515 for (i = 0; i < 4; i++) {
516 pend = readl_relaxed(reg_source);
518 if (pend == 0 || pend == last)
521 writel_relaxed(pend, intc->reg_pending);
522 if (intc->reg_intpnd)
523 writel_relaxed(pend, intc->reg_intpnd);
525 pr_info("irq: clearing pending status %08x\n", (int)pend);
530 static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
531 struct s3c_irq_data *irq_data,
532 struct s3c_irq_intc *parent,
533 unsigned long address)
535 struct s3c_irq_intc *intc;
536 void __iomem *base = (void *)0xf6000000; /* static mapping */
541 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
543 return ERR_PTR(-ENOMEM);
545 intc->irqs = irq_data;
548 intc->parent = parent;
550 /* select the correct data for the controller.
551 * Need to hard code the irq num start and offset
552 * to preserve the static mapping for now
556 pr_debug("irq: found main intc\n");
557 intc->reg_pending = base;
558 intc->reg_mask = base + 0x08;
559 intc->reg_intpnd = base + 0x10;
561 irq_start = S3C2410_IRQ(0);
564 pr_debug("irq: found subintc\n");
565 intc->reg_pending = base + 0x18;
566 intc->reg_mask = base + 0x1c;
568 irq_start = S3C2410_IRQSUB(0);
571 pr_debug("irq: found intc2\n");
572 intc->reg_pending = base + 0x40;
573 intc->reg_mask = base + 0x48;
574 intc->reg_intpnd = base + 0x50;
576 irq_start = S3C2416_IRQ(0);
579 pr_debug("irq: found eintc\n");
580 base = (void *)0xfd000000;
582 intc->reg_mask = base + 0xa4;
583 intc->reg_pending = base + 0xa8;
585 irq_start = S3C2410_IRQ(32);
588 pr_err("irq: unsupported controller address\n");
593 /* now that all the data is complete, init the irq-domain */
594 s3c24xx_clear_intc(intc);
595 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
599 pr_err("irq: could not create irq-domain\n");
604 set_handle_irq(s3c24xx_handle_irq);
613 static struct s3c_irq_data __maybe_unused init_eint[32] = {
614 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
615 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
616 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
617 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
633 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
634 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
635 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
636 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
637 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
640 #ifdef CONFIG_CPU_S3C2410
641 static struct s3c_irq_data init_s3c2410base[32] = {
642 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
643 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
644 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
645 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
646 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
647 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
648 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
649 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
650 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
651 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
652 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
654 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
657 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
658 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
659 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
660 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
661 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
662 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
663 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
664 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
665 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
666 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
667 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
668 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
669 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
670 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
671 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
672 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
673 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
676 static struct s3c_irq_data init_s3c2410subint[32] = {
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
680 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
681 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
682 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
686 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
687 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
690 void __init s3c2410_init_irq(void)
696 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
698 if (IS_ERR(s3c_intc[0])) {
699 pr_err("irq: could not create main interrupt controller\n");
703 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
704 s3c_intc[0], 0x4a000018);
705 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
709 #ifdef CONFIG_CPU_S3C2412
710 static struct s3c_irq_data init_s3c2412base[32] = {
711 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
712 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
713 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
714 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
715 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
716 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
717 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
718 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
719 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
720 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
721 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
722 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
723 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
724 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
725 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
726 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
727 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
728 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
729 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
730 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
731 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
732 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
733 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
734 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
735 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
736 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
737 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
738 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
739 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
740 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
741 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
742 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
745 static struct s3c_irq_data init_s3c2412eint[32] = {
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
765 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
766 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
767 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
768 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
769 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
772 static struct s3c_irq_data init_s3c2412subint[32] = {
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
782 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
783 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
784 { .type = S3C_IRQTYPE_NONE, },
785 { .type = S3C_IRQTYPE_NONE, },
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
790 void __init s3c2412_init_irq(void)
792 pr_info("S3C2412: IRQ Support\n");
798 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
800 if (IS_ERR(s3c_intc[0])) {
801 pr_err("irq: could not create main interrupt controller\n");
805 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
806 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
807 s3c_intc[0], 0x4a000018);
811 #ifdef CONFIG_CPU_S3C2416
812 static struct s3c_irq_data init_s3c2416base[32] = {
813 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
814 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
815 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
816 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
817 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
818 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
819 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
820 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
821 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
823 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
824 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
825 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
826 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
827 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
828 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
829 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
830 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
831 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
832 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
833 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
834 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
835 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
836 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
837 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
838 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
839 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
840 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
841 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
842 { .type = S3C_IRQTYPE_NONE, },
843 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
844 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
847 static struct s3c_irq_data init_s3c2416subint[32] = {
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
852 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
853 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
857 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
858 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
859 { .type = S3C_IRQTYPE_NONE }, /* reserved */
860 { .type = S3C_IRQTYPE_NONE }, /* reserved */
861 { .type = S3C_IRQTYPE_NONE }, /* reserved */
862 { .type = S3C_IRQTYPE_NONE }, /* reserved */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
872 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
873 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
874 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
875 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
876 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
879 static struct s3c_irq_data init_s3c2416_second[32] = {
880 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
881 { .type = S3C_IRQTYPE_NONE }, /* reserved */
882 { .type = S3C_IRQTYPE_NONE }, /* reserved */
883 { .type = S3C_IRQTYPE_NONE }, /* reserved */
884 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
885 { .type = S3C_IRQTYPE_NONE }, /* reserved */
886 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
889 void __init s3c2416_init_irq(void)
891 pr_info("S3C2416: IRQ Support\n");
897 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
899 if (IS_ERR(s3c_intc[0])) {
900 pr_err("irq: could not create main interrupt controller\n");
904 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
905 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
906 s3c_intc[0], 0x4a000018);
908 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
914 #ifdef CONFIG_CPU_S3C2440
915 static struct s3c_irq_data init_s3c2440base[32] = {
916 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
917 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
918 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
919 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
920 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
921 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
922 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
923 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
924 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
925 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
926 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
927 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
928 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
929 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
930 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
931 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
932 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
933 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
934 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
935 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
936 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
937 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
938 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
939 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
940 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
941 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
942 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
943 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
944 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
945 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
946 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
947 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
950 static struct s3c_irq_data init_s3c2440subint[32] = {
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
953 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
954 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
955 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
956 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
960 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
961 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
962 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
963 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
964 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
965 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
968 void __init s3c2440_init_irq(void)
970 pr_info("S3C2440: IRQ Support\n");
976 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
978 if (IS_ERR(s3c_intc[0])) {
979 pr_err("irq: could not create main interrupt controller\n");
983 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
984 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
985 s3c_intc[0], 0x4a000018);
989 #ifdef CONFIG_CPU_S3C2442
990 static struct s3c_irq_data init_s3c2442base[32] = {
991 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
992 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
993 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
994 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
995 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
996 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
997 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
998 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
999 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1000 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
1001 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1005 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1006 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1009 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1014 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1015 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1017 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1018 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1019 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1020 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1021 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1022 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1025 static struct s3c_irq_data init_s3c2442subint[32] = {
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1029 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1030 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1031 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1033 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1034 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1035 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1036 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1037 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1038 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1041 void __init s3c2442_init_irq(void)
1043 pr_info("S3C2442: IRQ Support\n");
1046 init_FIQ(FIQ_START);
1049 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1051 if (IS_ERR(s3c_intc[0])) {
1052 pr_err("irq: could not create main interrupt controller\n");
1056 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1057 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1058 s3c_intc[0], 0x4a000018);
1062 #ifdef CONFIG_CPU_S3C2443
1063 static struct s3c_irq_data init_s3c2443base[32] = {
1064 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1065 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1066 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1067 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1068 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1069 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1070 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1072 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1073 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1074 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1075 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1076 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1077 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1078 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1079 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1080 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1081 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1082 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1087 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1088 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1089 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1090 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1091 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1092 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1093 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1094 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1095 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1099 static struct s3c_irq_data init_s3c2443subint[32] = {
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1104 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1109 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1110 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1113 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1124 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1125 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1126 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1127 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1128 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1131 void __init s3c2443_init_irq(void)
1133 pr_info("S3C2443: IRQ Support\n");
1136 init_FIQ(FIQ_START);
1139 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1141 if (IS_ERR(s3c_intc[0])) {
1142 pr_err("irq: could not create main interrupt controller\n");
1146 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1147 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1148 s3c_intc[0], 0x4a000018);
1153 static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1156 unsigned int ctrl_num = hw / 32;
1157 unsigned int intc_hw = hw % 32;
1158 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1159 struct s3c_irq_intc *parent_intc = intc->parent;
1160 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1162 /* attach controller pointer to irq_data */
1163 irq_data->intc = intc;
1164 irq_data->offset = intc_hw;
1167 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1169 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1172 irq_set_chip_data(virq, irq_data);
1177 /* Translate our of irq notation
1178 * format: <ctrl_num ctrl_irq parent_irq type>
1180 static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1181 const u32 *intspec, unsigned int intsize,
1182 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1184 struct s3c_irq_intc *intc;
1185 struct s3c_irq_intc *parent_intc;
1186 struct s3c_irq_data *irq_data;
1187 struct s3c_irq_data *parent_irq_data;
1190 if (WARN_ON(intsize < 4))
1193 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1194 pr_err("controller number %d invalid\n", intspec[0]);
1197 intc = s3c_intc[intspec[0]];
1199 *out_hwirq = intspec[0] * 32 + intspec[2];
1200 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1202 parent_intc = intc->parent;
1204 irq_data = &intc->irqs[intspec[2]];
1205 irq_data->parent_irq = intspec[1];
1206 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1207 parent_irq_data->sub_intc = intc;
1208 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1210 /* parent_intc is always s3c_intc[0], so no offset */
1211 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1213 pr_err("irq: could not map parent interrupt\n");
1217 irq_set_chained_handler(irqno, s3c_irq_demux);
1223 static const struct irq_domain_ops s3c24xx_irq_ops_of = {
1224 .map = s3c24xx_irq_map_of,
1225 .xlate = s3c24xx_irq_xlate_of,
1228 struct s3c24xx_irq_of_ctrl {
1230 unsigned long offset;
1231 struct s3c_irq_intc **handle;
1232 struct s3c_irq_intc **parent;
1233 struct irq_domain_ops *ops;
1236 static int __init s3c_init_intc_of(struct device_node *np,
1237 struct device_node *interrupt_parent,
1238 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1240 struct s3c_irq_intc *intc;
1241 struct s3c24xx_irq_of_ctrl *ctrl;
1242 struct irq_domain *domain;
1243 void __iomem *reg_base;
1246 reg_base = of_iomap(np, 0);
1248 pr_err("irq-s3c24xx: could not map irq registers\n");
1252 domain = irq_domain_add_linear(np, num_ctrl * 32,
1253 &s3c24xx_irq_ops_of, NULL);
1255 pr_err("irq: could not create irq-domain\n");
1259 for (i = 0; i < num_ctrl; i++) {
1260 ctrl = &s3c_ctrl[i];
1262 pr_debug("irq: found controller %s\n", ctrl->name);
1264 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1268 intc->domain = domain;
1269 intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data),
1277 intc->reg_pending = reg_base + ctrl->offset;
1278 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1280 if (*(ctrl->parent)) {
1281 intc->parent = *(ctrl->parent);
1283 pr_warn("irq: parent of %s missing\n",
1290 intc->reg_pending = reg_base + ctrl->offset;
1291 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1292 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1295 s3c24xx_clear_intc(intc);
1299 set_handle_irq(s3c24xx_handle_irq);
1304 static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1311 .parent = &s3c_intc[0],
1315 int __init s3c2410_init_intc_of(struct device_node *np,
1316 struct device_node *interrupt_parent)
1318 return s3c_init_intc_of(np, interrupt_parent,
1319 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1321 IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1323 static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1330 .parent = &s3c_intc[0],
1337 int __init s3c2416_init_intc_of(struct device_node *np,
1338 struct device_node *interrupt_parent)
1340 return s3c_init_intc_of(np, interrupt_parent,
1341 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
1343 IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);