1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L IRQC Driver
5 * Copyright (C) 2022 Renesas Electronics Corporation.
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/spinlock.h>
22 #define IRQC_IRQ_START 1
23 #define IRQC_IRQ_COUNT 8
24 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
25 #define IRQC_TINT_COUNT 32
26 #define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
33 #define TITSR0_MAX_INT 16
34 #define TITSEL_WIDTH 0x2
35 #define TSSR(n) (0x30 + ((n) * 4))
37 #define TSSEL_SHIFT(n) (8 * (n))
38 #define TSSEL_MASK GENMASK(7, 0)
41 #define TSSR_OFFSET(n) ((n) % 4)
42 #define TSSR_INDEX(n) ((n) / 4)
44 #define TITSR_TITSEL_EDGE_RISING 0
45 #define TITSR_TITSEL_EDGE_FALLING 1
46 #define TITSR_TITSEL_LEVEL_HIGH 2
47 #define TITSR_TITSEL_LEVEL_LOW 3
49 #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2))
50 #define IITSR_IITSEL_LEVEL_LOW 0
51 #define IITSR_IITSEL_EDGE_FALLING 1
52 #define IITSR_IITSEL_EDGE_RISING 2
53 #define IITSR_IITSEL_EDGE_BOTH 3
54 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
56 #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
57 #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
59 struct rzg2l_irqc_priv {
61 struct irq_fwspec fwspec[IRQC_NUM_IRQ];
65 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
67 return data->domain->host_data;
70 static void rzg2l_irq_eoi(struct irq_data *d)
72 unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
73 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
74 u32 bit = BIT(hw_irq);
77 reg = readl_relaxed(priv->base + ISCR);
79 writel_relaxed(reg & ~bit, priv->base + ISCR);
82 static void rzg2l_tint_eoi(struct irq_data *d)
84 unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START;
85 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
86 u32 bit = BIT(hw_irq);
89 reg = readl_relaxed(priv->base + TSCR);
91 writel_relaxed(reg & ~bit, priv->base + TSCR);
94 static void rzg2l_irqc_eoi(struct irq_data *d)
96 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
97 unsigned int hw_irq = irqd_to_hwirq(d);
99 raw_spin_lock(&priv->lock);
100 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
102 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
104 raw_spin_unlock(&priv->lock);
105 irq_chip_eoi_parent(d);
108 static void rzg2l_irqc_irq_disable(struct irq_data *d)
110 unsigned int hw_irq = irqd_to_hwirq(d);
112 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
113 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
114 u32 offset = hw_irq - IRQC_TINT_START;
115 u32 tssr_offset = TSSR_OFFSET(offset);
116 u8 tssr_index = TSSR_INDEX(offset);
119 raw_spin_lock(&priv->lock);
120 reg = readl_relaxed(priv->base + TSSR(tssr_index));
121 reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
122 writel_relaxed(reg, priv->base + TSSR(tssr_index));
123 raw_spin_unlock(&priv->lock);
125 irq_chip_disable_parent(d);
128 static void rzg2l_irqc_irq_enable(struct irq_data *d)
130 unsigned int hw_irq = irqd_to_hwirq(d);
132 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
133 unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d);
134 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
135 u32 offset = hw_irq - IRQC_TINT_START;
136 u32 tssr_offset = TSSR_OFFSET(offset);
137 u8 tssr_index = TSSR_INDEX(offset);
140 raw_spin_lock(&priv->lock);
141 reg = readl_relaxed(priv->base + TSSR(tssr_index));
142 reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
143 writel_relaxed(reg, priv->base + TSSR(tssr_index));
144 raw_spin_unlock(&priv->lock);
146 irq_chip_enable_parent(d);
149 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
151 unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
152 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
155 switch (type & IRQ_TYPE_SENSE_MASK) {
156 case IRQ_TYPE_LEVEL_LOW:
157 sense = IITSR_IITSEL_LEVEL_LOW;
160 case IRQ_TYPE_EDGE_FALLING:
161 sense = IITSR_IITSEL_EDGE_FALLING;
164 case IRQ_TYPE_EDGE_RISING:
165 sense = IITSR_IITSEL_EDGE_RISING;
168 case IRQ_TYPE_EDGE_BOTH:
169 sense = IITSR_IITSEL_EDGE_BOTH;
176 raw_spin_lock(&priv->lock);
177 tmp = readl_relaxed(priv->base + IITSR);
178 tmp &= ~IITSR_IITSEL_MASK(hw_irq);
179 tmp |= IITSR_IITSEL(hw_irq, sense);
180 writel_relaxed(tmp, priv->base + IITSR);
181 raw_spin_unlock(&priv->lock);
186 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
188 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
189 unsigned int hwirq = irqd_to_hwirq(d);
190 u32 titseln = hwirq - IRQC_TINT_START;
195 switch (type & IRQ_TYPE_SENSE_MASK) {
196 case IRQ_TYPE_EDGE_RISING:
197 sense = TITSR_TITSEL_EDGE_RISING;
200 case IRQ_TYPE_EDGE_FALLING:
201 sense = TITSR_TITSEL_EDGE_FALLING;
209 if (titseln >= TITSR0_MAX_INT) {
210 titseln -= TITSR0_MAX_INT;
214 raw_spin_lock(&priv->lock);
215 reg = readl_relaxed(priv->base + offset);
216 reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
217 reg |= sense << (titseln * TITSEL_WIDTH);
218 writel_relaxed(reg, priv->base + offset);
219 raw_spin_unlock(&priv->lock);
224 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
226 unsigned int hw_irq = irqd_to_hwirq(d);
229 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
230 ret = rzg2l_irq_set_type(d, type);
231 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
232 ret = rzg2l_tint_set_edge(d, type);
236 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
239 static const struct irq_chip irqc_chip = {
240 .name = "rzg2l-irqc",
241 .irq_eoi = rzg2l_irqc_eoi,
242 .irq_mask = irq_chip_mask_parent,
243 .irq_unmask = irq_chip_unmask_parent,
244 .irq_disable = rzg2l_irqc_irq_disable,
245 .irq_enable = rzg2l_irqc_irq_enable,
246 .irq_get_irqchip_state = irq_chip_get_parent_state,
247 .irq_set_irqchip_state = irq_chip_set_parent_state,
248 .irq_retrigger = irq_chip_retrigger_hierarchy,
249 .irq_set_type = rzg2l_irqc_set_type,
250 .irq_set_affinity = irq_chip_set_affinity_parent,
251 .flags = IRQCHIP_MASK_ON_SUSPEND |
252 IRQCHIP_SET_TYPE_MASKED |
253 IRQCHIP_SKIP_SET_WAKE,
256 static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
257 unsigned int nr_irqs, void *arg)
259 struct rzg2l_irqc_priv *priv = domain->host_data;
260 unsigned long tint = 0;
261 irq_hw_number_t hwirq;
265 ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
270 * For TINT interrupts ie where pinctrl driver is child of irqc domain
271 * the hwirq and TINT are encoded in fwspec->param[0].
272 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
273 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
274 * in IRQC registers to enable a given gpio pin as interrupt.
276 if (hwirq > IRQC_IRQ_COUNT) {
277 tint = TINT_EXTRACT_GPIOINT(hwirq);
278 hwirq = TINT_EXTRACT_HWIRQ(hwirq);
280 if (hwirq < IRQC_TINT_START)
284 if (hwirq > (IRQC_NUM_IRQ - 1))
287 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
288 (void *)(uintptr_t)tint);
292 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
295 static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
296 .alloc = rzg2l_irqc_alloc,
297 .free = irq_domain_free_irqs_common,
298 .translate = irq_domain_translate_twocell,
301 static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
302 struct device_node *np)
304 struct of_phandle_args map;
308 for (i = 0; i < IRQC_NUM_IRQ; i++) {
309 ret = of_irq_parse_one(np, i, &map);
312 of_phandle_args_to_fwspec(np, map.args, map.args_count,
319 static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
321 struct irq_domain *irq_domain, *parent_domain;
322 struct platform_device *pdev;
323 struct reset_control *resetn;
324 struct rzg2l_irqc_priv *priv;
327 pdev = of_find_device_by_node(node);
331 parent_domain = irq_find_host(parent);
332 if (!parent_domain) {
333 dev_err(&pdev->dev, "cannot find parent domain\n");
337 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
341 priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
342 if (IS_ERR(priv->base))
343 return PTR_ERR(priv->base);
345 ret = rzg2l_irqc_parse_interrupts(priv, node);
347 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
351 resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
353 return PTR_ERR(resetn);
355 ret = reset_control_deassert(resetn);
357 dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
361 pm_runtime_enable(&pdev->dev);
362 ret = pm_runtime_resume_and_get(&pdev->dev);
364 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
368 raw_spin_lock_init(&priv->lock);
370 irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
371 node, &rzg2l_irqc_domain_ops,
374 dev_err(&pdev->dev, "failed to add irq domain\n");
382 pm_runtime_put(&pdev->dev);
384 pm_runtime_disable(&pdev->dev);
385 reset_control_assert(resetn);
389 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
390 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
391 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
392 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
393 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");