drivers/irqchip/irq-mips-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9
  10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
  11
  12 #include <linux/bitmap.h>
  13 #include <linux/clocksource.h>
  14 #include <linux/cpuhotplug.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqchip.h>
  19 #include <linux/of_address.h>
  20 #include <linux/percpu.h>
  21 #include <linux/sched.h>
  22 #include <linux/smp.h>
  23
  24 #include <asm/mips-cps.h>
  25 #include <asm/setup.h>
  26 #include <asm/traps.h>
  27
  28 #include <dt-bindings/interrupt-controller/mips-gic.h>
  29
  30 #define GIC_MAX_INTRS           256
  31 #define GIC_MAX_LONGS           BITS_TO_LONGS(GIC_MAX_INTRS)
  32
  33 /* Add 2 to convert GIC CPU pin to core interrupt */
  34 #define GIC_CPU_PIN_OFFSET      2
  35
  36 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
  37 #define GIC_PIN_TO_VEC_OFFSET   1
  38
  39 /* Convert between local/shared IRQ number and GIC HW IRQ number. */
  40 #define GIC_LOCAL_HWIRQ_BASE    0
  41 #define GIC_LOCAL_TO_HWIRQ(x)   (GIC_LOCAL_HWIRQ_BASE + (x))
  42 #define GIC_HWIRQ_TO_LOCAL(x)   ((x) - GIC_LOCAL_HWIRQ_BASE)
  43 #define GIC_SHARED_HWIRQ_BASE   GIC_NUM_LOCAL_INTRS
  44 #define GIC_SHARED_TO_HWIRQ(x)  (GIC_SHARED_HWIRQ_BASE + (x))
  45 #define GIC_HWIRQ_TO_SHARED(x)  ((x) - GIC_SHARED_HWIRQ_BASE)
  46
  47 void __iomem *mips_gic_base;
  48
  49 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
  50
  51 static DEFINE_SPINLOCK(gic_lock);
  52 static struct irq_domain *gic_irq_domain;
  53 static int gic_shared_intrs;
  54 static unsigned int gic_cpu_pin;
  55 static unsigned int timer_cpu_pin;
  56 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
  57
  58 #ifdef CONFIG_GENERIC_IRQ_IPI
  59 static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
  60 static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
  61 #endif /* CONFIG_GENERIC_IRQ_IPI */
  62
  63 static struct gic_all_vpes_chip_data {
  64         u32     map;
  65         bool    mask;
  66 } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
  67
  68 static void gic_clear_pcpu_masks(unsigned int intr)
  69 {
  70         unsigned int i;
  71
  72         /* Clear the interrupt's bit in all pcpu_masks */
  73         for_each_possible_cpu(i)
  74                 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
  75 }
  76
  77 static bool gic_local_irq_is_routable(int intr)
  78 {
  79         u32 vpe_ctl;
  80
  81         /* All local interrupts are routable in EIC mode. */
  82         if (cpu_has_veic)
  83                 return true;
  84
  85         vpe_ctl = read_gic_vl_ctl();
  86         switch (intr) {
  87         case GIC_LOCAL_INT_TIMER:
  88                 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
  89         case GIC_LOCAL_INT_PERFCTR:
  90                 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
  91         case GIC_LOCAL_INT_FDC:
  92                 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
  93         case GIC_LOCAL_INT_SWINT0:
  94         case GIC_LOCAL_INT_SWINT1:
  95                 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
  96         default:
  97                 return true;
  98         }
  99 }
 100
 101 static void gic_bind_eic_interrupt(int irq, int set)
 102 {
 103         /* Convert irq vector # to hw int # */
 104         irq -= GIC_PIN_TO_VEC_OFFSET;
 105
 106         /* Set irq to use shadow set */
 107         write_gic_vl_eic_shadow_set(irq, set);
 108 }
 109
 110 static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
 111 {
 112         irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
 113
 114         write_gic_wedge(GIC_WEDGE_RW | hwirq);
 115 }
 116
 117 int gic_get_c0_compare_int(void)
 118 {
 119         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
 120                 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 121         return irq_create_mapping(gic_irq_domain,
 122                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
 123 }
 124
 125 int gic_get_c0_perfcount_int(void)
 126 {
 127         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
 128                 /* Is the performance counter shared with the timer? */
 129                 if (cp0_perfcount_irq < 0)
 130                         return -1;
 131                 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 132         }
 133         return irq_create_mapping(gic_irq_domain,
 134                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
 135 }
 136
 137 int gic_get_c0_fdc_int(void)
 138 {
 139         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
 140                 /* Is the FDC IRQ even present? */
 141                 if (cp0_fdc_irq < 0)
 142                         return -1;
 143                 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
 144         }
 145
 146         return irq_create_mapping(gic_irq_domain,
 147                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 148 }
 149
 150 static void gic_handle_shared_int(bool chained)
 151 {
 152         unsigned int intr, virq;
 153         unsigned long *pcpu_mask;
 154         DECLARE_BITMAP(pending, GIC_MAX_INTRS);
 155
 156         /* Get per-cpu bitmaps */
 157         pcpu_mask = this_cpu_ptr(pcpu_masks);
 158
 159         if (mips_cm_is64)
 160                 __ioread64_copy(pending, addr_gic_pend(),
 161                                 DIV_ROUND_UP(gic_shared_intrs, 64));
 162         else
 163                 __ioread32_copy(pending, addr_gic_pend(),
 164                                 DIV_ROUND_UP(gic_shared_intrs, 32));
 165
 166         bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
 167
 168         for_each_set_bit(intr, pending, gic_shared_intrs) {
 169                 virq = irq_linear_revmap(gic_irq_domain,
 170                                          GIC_SHARED_TO_HWIRQ(intr));
 171                 if (chained)
 172                         generic_handle_irq(virq);
 173                 else
 174                         do_IRQ(virq);
 175         }
 176 }
 177
 178 static void gic_mask_irq(struct irq_data *d)
 179 {
 180         unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
 181
 182         write_gic_rmask(intr);
 183         gic_clear_pcpu_masks(intr);
 184 }
 185
 186 static void gic_unmask_irq(struct irq_data *d)
 187 {
 188         unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
 189         unsigned int cpu;
 190
 191         write_gic_smask(intr);
 192
 193         gic_clear_pcpu_masks(intr);
 194         cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
 195         set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
 196 }
 197
 198 static void gic_ack_irq(struct irq_data *d)
 199 {
 200         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 201
 202         write_gic_wedge(irq);
 203 }
 204
 205 static int gic_set_type(struct irq_data *d, unsigned int type)
 206 {
 207         unsigned int irq, pol, trig, dual;
 208         unsigned long flags;
 209
 210         irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 211
 212         spin_lock_irqsave(&gic_lock, flags);
 213         switch (type & IRQ_TYPE_SENSE_MASK) {
 214         case IRQ_TYPE_EDGE_FALLING:
 215                 pol = GIC_POL_FALLING_EDGE;
 216                 trig = GIC_TRIG_EDGE;
 217                 dual = GIC_DUAL_SINGLE;
 218                 break;
 219         case IRQ_TYPE_EDGE_RISING:
 220                 pol = GIC_POL_RISING_EDGE;
 221                 trig = GIC_TRIG_EDGE;
 222                 dual = GIC_DUAL_SINGLE;
 223                 break;
 224         case IRQ_TYPE_EDGE_BOTH:
 225                 pol = 0; /* Doesn't matter */
 226                 trig = GIC_TRIG_EDGE;
 227                 dual = GIC_DUAL_DUAL;
 228                 break;
 229         case IRQ_TYPE_LEVEL_LOW:
 230                 pol = GIC_POL_ACTIVE_LOW;
 231                 trig = GIC_TRIG_LEVEL;
 232                 dual = GIC_DUAL_SINGLE;
 233                 break;
 234         case IRQ_TYPE_LEVEL_HIGH:
 235         default:
 236                 pol = GIC_POL_ACTIVE_HIGH;
 237                 trig = GIC_TRIG_LEVEL;
 238                 dual = GIC_DUAL_SINGLE;
 239                 break;
 240         }
 241
 242         change_gic_pol(irq, pol);
 243         change_gic_trig(irq, trig);
 244         change_gic_dual(irq, dual);
 245
 246         if (trig == GIC_TRIG_EDGE)
 247                 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
 248                                                  handle_edge_irq, NULL);
 249         else
 250                 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
 251                                                  handle_level_irq, NULL);
 252         spin_unlock_irqrestore(&gic_lock, flags);
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_SMP
 258 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 259                             bool force)
 260 {
 261         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 262         unsigned long flags;
 263         unsigned int cpu;
 264
 265         cpu = cpumask_first_and(cpumask, cpu_online_mask);
 266         if (cpu >= NR_CPUS)
 267                 return -EINVAL;
 268
 269         /* Assumption : cpumask refers to a single CPU */
 270         spin_lock_irqsave(&gic_lock, flags);
 271
 272         /* Re-route this IRQ */
 273         write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
 274
 275         /* Update the pcpu_masks */
 276         gic_clear_pcpu_masks(irq);
 277         if (read_gic_mask(irq))
 278                 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
 279
 280         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 281         spin_unlock_irqrestore(&gic_lock, flags);
 282
 283         return IRQ_SET_MASK_OK;
 284 }
 285 #endif
 286
 287 static struct irq_chip gic_level_irq_controller = {
 288         .name                   =       "MIPS GIC",
 289         .irq_mask               =       gic_mask_irq,
 290         .irq_unmask             =       gic_unmask_irq,
 291         .irq_set_type           =       gic_set_type,
 292 #ifdef CONFIG_SMP
 293         .irq_set_affinity       =       gic_set_affinity,
 294 #endif
 295 };
 296
 297 static struct irq_chip gic_edge_irq_controller = {
 298         .name                   =       "MIPS GIC",
 299         .irq_ack                =       gic_ack_irq,
 300         .irq_mask               =       gic_mask_irq,
 301         .irq_unmask             =       gic_unmask_irq,
 302         .irq_set_type           =       gic_set_type,
 303 #ifdef CONFIG_SMP
 304         .irq_set_affinity       =       gic_set_affinity,
 305 #endif
 306         .ipi_send_single        =       gic_send_ipi,
 307 };
 308
 309 static void gic_handle_local_int(bool chained)
 310 {
 311         unsigned long pending, masked;
 312         unsigned int intr, virq;
 313
 314         pending = read_gic_vl_pend();
 315         masked = read_gic_vl_mask();
 316
 317         bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
 318
 319         for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
 320                 virq = irq_linear_revmap(gic_irq_domain,
 321                                          GIC_LOCAL_TO_HWIRQ(intr));
 322                 if (chained)
 323                         generic_handle_irq(virq);
 324                 else
 325                         do_IRQ(virq);
 326         }
 327 }
 328
 329 static void gic_mask_local_irq(struct irq_data *d)
 330 {
 331         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 332
 333         write_gic_vl_rmask(BIT(intr));
 334 }
 335
 336 static void gic_unmask_local_irq(struct irq_data *d)
 337 {
 338         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 339
 340         write_gic_vl_smask(BIT(intr));
 341 }
 342
 343 static struct irq_chip gic_local_irq_controller = {
 344         .name                   =       "MIPS GIC Local",
 345         .irq_mask               =       gic_mask_local_irq,
 346         .irq_unmask             =       gic_unmask_local_irq,
 347 };
 348
 349 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 350 {
 351         struct gic_all_vpes_chip_data *cd;
 352         unsigned long flags;
 353         int intr, cpu;
 354
 355         intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 356         cd = irq_data_get_irq_chip_data(d);
 357         cd->mask = false;
 358
 359         spin_lock_irqsave(&gic_lock, flags);
 360         for_each_online_cpu(cpu) {
 361                 write_gic_vl_other(mips_cm_vp_id(cpu));
 362                 write_gic_vo_rmask(BIT(intr));
 363         }
 364         spin_unlock_irqrestore(&gic_lock, flags);
 365 }
 366
 367 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 368 {
 369         struct gic_all_vpes_chip_data *cd;
 370         unsigned long flags;
 371         int intr, cpu;
 372
 373         intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 374         cd = irq_data_get_irq_chip_data(d);
 375         cd->mask = true;
 376
 377         spin_lock_irqsave(&gic_lock, flags);
 378         for_each_online_cpu(cpu) {
 379                 write_gic_vl_other(mips_cm_vp_id(cpu));
 380                 write_gic_vo_smask(BIT(intr));
 381         }
 382         spin_unlock_irqrestore(&gic_lock, flags);
 383 }
 384
 385 static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
 386 {
 387         struct gic_all_vpes_chip_data *cd;
 388         unsigned int intr;
 389
 390         intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 391         cd = irq_data_get_irq_chip_data(d);
 392
 393         write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
 394         if (cd->mask)
 395                 write_gic_vl_smask(BIT(intr));
 396 }
 397
 398 static struct irq_chip gic_all_vpes_local_irq_controller = {
 399         .name                   = "MIPS GIC Local",
 400         .irq_mask               = gic_mask_local_irq_all_vpes,
 401         .irq_unmask             = gic_unmask_local_irq_all_vpes,
 402         .irq_cpu_online         = gic_all_vpes_irq_cpu_online,
 403 };
 404
 405 static void __gic_irq_dispatch(void)
 406 {
 407         gic_handle_local_int(false);
 408         gic_handle_shared_int(false);
 409 }
 410
 411 static void gic_irq_dispatch(struct irq_desc *desc)
 412 {
 413         gic_handle_local_int(true);
 414         gic_handle_shared_int(true);
 415 }
 416
 417 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
 418                                      irq_hw_number_t hw, unsigned int cpu)
 419 {
 420         int intr = GIC_HWIRQ_TO_SHARED(hw);
 421         struct irq_data *data;
 422         unsigned long flags;
 423
 424         data = irq_get_irq_data(virq);
 425
 426         spin_lock_irqsave(&gic_lock, flags);
 427         write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
 428         write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
 429         irq_data_update_effective_affinity(data, cpumask_of(cpu));
 430         spin_unlock_irqrestore(&gic_lock, flags);
 431
 432         return 0;
 433 }
 434
 435 static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
 436                                 const u32 *intspec, unsigned int intsize,
 437                                 irq_hw_number_t *out_hwirq,
 438                                 unsigned int *out_type)
 439 {
 440         if (intsize != 3)
 441                 return -EINVAL;
 442
 443         if (intspec[0] == GIC_SHARED)
 444                 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
 445         else if (intspec[0] == GIC_LOCAL)
 446                 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
 447         else
 448                 return -EINVAL;
 449         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 450
 451         return 0;
 452 }
 453
 454 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 455                               irq_hw_number_t hwirq)
 456 {
 457         struct gic_all_vpes_chip_data *cd;
 458         unsigned long flags;
 459         unsigned int intr;
 460         int err, cpu;
 461         u32 map;
 462
 463         if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
 464 #ifdef CONFIG_GENERIC_IRQ_IPI
 465                 /* verify that shared irqs don't conflict with an IPI irq */
 466                 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
 467                         return -EBUSY;
 468 #endif /* CONFIG_GENERIC_IRQ_IPI */
 469
 470                 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
 471                                                     &gic_level_irq_controller,
 472                                                     NULL);
 473                 if (err)
 474                         return err;
 475
 476                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 477                 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
 478         }
 479
 480         intr = GIC_HWIRQ_TO_LOCAL(hwirq);
 481         map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
 482
 483         switch (intr) {
 484         case GIC_LOCAL_INT_TIMER:
 485                 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
 486                 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
 487                 fallthrough;
 488         case GIC_LOCAL_INT_PERFCTR:
 489         case GIC_LOCAL_INT_FDC:
 490                 /*
 491                  * HACK: These are all really percpu interrupts, but
 492                  * the rest of the MIPS kernel code does not use the
 493                  * percpu IRQ API for them.
 494                  */
 495                 cd = &gic_all_vpes_chip_data[intr];
 496                 cd->map = map;
 497                 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
 498                                                     &gic_all_vpes_local_irq_controller,
 499                                                     cd);
 500                 if (err)
 501                         return err;
 502
 503                 irq_set_handler(virq, handle_percpu_irq);
 504                 break;
 505
 506         default:
 507                 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
 508                                                     &gic_local_irq_controller,
 509                                                     NULL);
 510                 if (err)
 511                         return err;
 512
 513                 irq_set_handler(virq, handle_percpu_devid_irq);
 514                 irq_set_percpu_devid(virq);
 515                 break;
 516         }
 517
 518         if (!gic_local_irq_is_routable(intr))
 519                 return -EPERM;
 520
 521         spin_lock_irqsave(&gic_lock, flags);
 522         for_each_online_cpu(cpu) {
 523                 write_gic_vl_other(mips_cm_vp_id(cpu));
 524                 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
 525         }
 526         spin_unlock_irqrestore(&gic_lock, flags);
 527
 528         return 0;
 529 }
 530
 531 static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
 532                                 unsigned int nr_irqs, void *arg)
 533 {
 534         struct irq_fwspec *fwspec = arg;
 535         irq_hw_number_t hwirq;
 536
 537         if (fwspec->param[0] == GIC_SHARED)
 538                 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
 539         else
 540                 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
 541
 542         return gic_irq_domain_map(d, virq, hwirq);
 543 }
 544
 545 void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
 546                          unsigned int nr_irqs)
 547 {
 548 }
 549
 550 static const struct irq_domain_ops gic_irq_domain_ops = {
 551         .xlate = gic_irq_domain_xlate,
 552         .alloc = gic_irq_domain_alloc,
 553         .free = gic_irq_domain_free,
 554         .map = gic_irq_domain_map,
 555 };
 556
 557 #ifdef CONFIG_GENERIC_IRQ_IPI
 558
 559 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
 560                                 const u32 *intspec, unsigned int intsize,
 561                                 irq_hw_number_t *out_hwirq,
 562                                 unsigned int *out_type)
 563 {
 564         /*
 565          * There's nothing to translate here. hwirq is dynamically allocated and
 566          * the irq type is always edge triggered.
 567          * */
 568         *out_hwirq = 0;
 569         *out_type = IRQ_TYPE_EDGE_RISING;
 570
 571         return 0;
 572 }
 573
 574 static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
 575                                 unsigned int nr_irqs, void *arg)
 576 {
 577         struct cpumask *ipimask = arg;
 578         irq_hw_number_t hwirq, base_hwirq;
 579         int cpu, ret, i;
 580
 581         base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
 582         if (base_hwirq == gic_shared_intrs)
 583                 return -ENOMEM;
 584
 585         /* check that we have enough space */
 586         for (i = base_hwirq; i < nr_irqs; i++) {
 587                 if (!test_bit(i, ipi_available))
 588                         return -EBUSY;
 589         }
 590         bitmap_clear(ipi_available, base_hwirq, nr_irqs);
 591
 592         /* map the hwirq for each cpu consecutively */
 593         i = 0;
 594         for_each_cpu(cpu, ipimask) {
 595                 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
 596
 597                 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
 598                                                     &gic_edge_irq_controller,
 599                                                     NULL);
 600                 if (ret)
 601                         goto error;
 602
 603                 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
 604                                                     &gic_edge_irq_controller,
 605                                                     NULL);
 606                 if (ret)
 607                         goto error;
 608
 609                 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
 610                 if (ret)
 611                         goto error;
 612
 613                 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
 614                 if (ret)
 615                         goto error;
 616
 617                 i++;
 618         }
 619
 620         return 0;
 621 error:
 622         bitmap_set(ipi_available, base_hwirq, nr_irqs);
 623         return ret;
 624 }
 625
 626 static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
 627                                 unsigned int nr_irqs)
 628 {
 629         irq_hw_number_t base_hwirq;
 630         struct irq_data *data;
 631
 632         data = irq_get_irq_data(virq);
 633         if (!data)
 634                 return;
 635
 636         base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
 637         bitmap_set(ipi_available, base_hwirq, nr_irqs);
 638 }
 639
 640 static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
 641                                 enum irq_domain_bus_token bus_token)
 642 {
 643         bool is_ipi;
 644
 645         switch (bus_token) {
 646         case DOMAIN_BUS_IPI:
 647                 is_ipi = d->bus_token == bus_token;
 648                 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
 649                 break;
 650         default:
 651                 return 0;
 652         }
 653 }
 654
 655 static const struct irq_domain_ops gic_ipi_domain_ops = {
 656         .xlate = gic_ipi_domain_xlate,
 657         .alloc = gic_ipi_domain_alloc,
 658         .free = gic_ipi_domain_free,
 659         .match = gic_ipi_domain_match,
 660 };
 661
 662 static int gic_register_ipi_domain(struct device_node *node)
 663 {
 664         struct irq_domain *gic_ipi_domain;
 665         unsigned int v[2], num_ipis;
 666
 667         gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
 668                                                   IRQ_DOMAIN_FLAG_IPI_PER_CPU,
 669                                                   GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
 670                                                   node, &gic_ipi_domain_ops, NULL);
 671         if (!gic_ipi_domain) {
 672                 pr_err("Failed to add IPI domain");
 673                 return -ENXIO;
 674         }
 675
 676         irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
 677
 678         if (node &&
 679             !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
 680                 bitmap_set(ipi_resrv, v[0], v[1]);
 681         } else {
 682                 /*
 683                  * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
 684                  * meeting the requirements of arch/mips SMP.
 685                  */
 686                 num_ipis = 2 * num_possible_cpus();
 687                 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
 688         }
 689
 690         bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
 691
 692         return 0;
 693 }
 694
 695 #else /* !CONFIG_GENERIC_IRQ_IPI */
 696
 697 static inline int gic_register_ipi_domain(struct device_node *node)
 698 {
 699         return 0;
 700 }
 701
 702 #endif /* !CONFIG_GENERIC_IRQ_IPI */
 703
 704 static int gic_cpu_startup(unsigned int cpu)
 705 {
 706         /* Enable or disable EIC */
 707         change_gic_vl_ctl(GIC_VX_CTL_EIC,
 708                           cpu_has_veic ? GIC_VX_CTL_EIC : 0);
 709
 710         /* Clear all local IRQ masks (ie. disable all local interrupts) */
 711         write_gic_vl_rmask(~0);
 712
 713         /* Invoke irq_cpu_online callbacks to enable desired interrupts */
 714         irq_cpu_online();
 715
 716         return 0;
 717 }
 718
 719 static int __init gic_of_init(struct device_node *node,
 720                               struct device_node *parent)
 721 {
 722         unsigned int cpu_vec, i, gicconfig;
 723         unsigned long reserved;
 724         phys_addr_t gic_base;
 725         struct resource res;
 726         size_t gic_len;
 727         int ret;
 728
 729         /* Find the first available CPU vector. */
 730         i = 0;
 731         reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
 732         while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
 733                                            i++, &cpu_vec))
 734                 reserved |= BIT(cpu_vec);
 735
 736         cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
 737         if (cpu_vec == hweight_long(ST0_IM)) {
 738                 pr_err("No CPU vectors available\n");
 739                 return -ENODEV;
 740         }
 741
 742         if (of_address_to_resource(node, 0, &res)) {
 743                 /*
 744                  * Probe the CM for the GIC base address if not specified
 745                  * in the device-tree.
 746                  */
 747                 if (mips_cm_present()) {
 748                         gic_base = read_gcr_gic_base() &
 749                                 ~CM_GCR_GIC_BASE_GICEN;
 750                         gic_len = 0x20000;
 751                         pr_warn("Using inherited base address %pa\n",
 752                                 &gic_base);
 753                 } else {
 754                         pr_err("Failed to get memory range\n");
 755                         return -ENODEV;
 756                 }
 757         } else {
 758                 gic_base = res.start;
 759                 gic_len = resource_size(&res);
 760         }
 761
 762         if (mips_cm_present()) {
 763                 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
 764                 /* Ensure GIC region is enabled before trying to access it */
 765                 __sync();
 766         }
 767
 768         mips_gic_base = ioremap(gic_base, gic_len);
 769         if (!mips_gic_base) {
 770                 pr_err("Failed to ioremap gic_base\n");
 771                 return -ENOMEM;
 772         }
 773
 774         gicconfig = read_gic_config();
 775         gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
 776         gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
 777         gic_shared_intrs = (gic_shared_intrs + 1) * 8;
 778
 779         if (cpu_has_veic) {
 780                 /* Always use vector 1 in EIC mode */
 781                 gic_cpu_pin = 0;
 782                 timer_cpu_pin = gic_cpu_pin;
 783                 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
 784                                __gic_irq_dispatch);
 785         } else {
 786                 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
 787                 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
 788                                         gic_irq_dispatch);
 789                 /*
 790                  * With the CMP implementation of SMP (deprecated), other CPUs
 791                  * are started by the bootloader and put into a timer based
 792                  * waiting poll loop. We must not re-route those CPU's local
 793                  * timer interrupts as the wait instruction will never finish,
 794                  * so just handle whatever CPU interrupt it is routed to by
 795                  * default.
 796                  *
 797                  * This workaround should be removed when CMP support is
 798                  * dropped.
 799                  */
 800                 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
 801                     gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
 802                         timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
 803                         irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
 804                                                 GIC_CPU_PIN_OFFSET +
 805                                                 timer_cpu_pin,
 806                                                 gic_irq_dispatch);
 807                 } else {
 808                         timer_cpu_pin = gic_cpu_pin;
 809                 }
 810         }
 811
 812         gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
 813                                                gic_shared_intrs, 0,
 814                                                &gic_irq_domain_ops, NULL);
 815         if (!gic_irq_domain) {
 816                 pr_err("Failed to add IRQ domain");
 817                 return -ENXIO;
 818         }
 819
 820         ret = gic_register_ipi_domain(node);
 821         if (ret)
 822                 return ret;
 823
 824         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 825
 826         /* Setup defaults */
 827         for (i = 0; i < gic_shared_intrs; i++) {
 828                 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
 829                 change_gic_trig(i, GIC_TRIG_LEVEL);
 830                 write_gic_rmask(i);
 831         }
 832
 833         return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
 834                                  "irqchip/mips/gic:starting",
 835                                  gic_cpu_startup, NULL);
 836 }
 837 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);