2 * Freescale SCFG MSI(-X) support
4 * Copyright (C) 2016 Freescale Semiconductor.
6 * Author: Minghuan Lian <Minghuan.Lian@nxp.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/msi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23 #include <linux/spinlock.h>
24 #include <linux/dma-iommu.h>
26 #define MSI_IRQS_PER_MSIR 32
27 #define MSI_MSIR_OFFSET 4
29 #define MSI_LS1043V1_1_IRQS_PER_MSIR 8
30 #define MSI_LS1043V1_1_MSIR_OFFSET 0x10
32 struct ls_scfg_msi_cfg {
33 u32 ibs_shift; /* Shift of interrupt bit select */
34 u32 msir_irqs; /* The irq number per MSIR */
35 u32 msir_base; /* The base address of MSIR */
39 struct ls_scfg_msi *msi_data;
42 unsigned int bit_start;
44 unsigned int srs; /* Shared interrupt register select */
50 struct platform_device *pdev;
51 struct irq_domain *parent;
52 struct irq_domain *msi_domain;
54 phys_addr_t msiir_addr;
55 struct ls_scfg_msi_cfg *cfg;
57 struct ls_scfg_msir *msir;
62 static struct irq_chip ls_scfg_msi_irq_chip = {
64 .irq_mask = pci_msi_mask_irq,
65 .irq_unmask = pci_msi_unmask_irq,
68 static struct msi_domain_info ls_scfg_msi_domain_info = {
69 .flags = (MSI_FLAG_USE_DEF_DOM_OPS |
70 MSI_FLAG_USE_DEF_CHIP_OPS |
72 .chip = &ls_scfg_msi_irq_chip,
75 static int msi_affinity_flag = 1;
77 static int __init early_parse_ls_scfg_msi(char *p)
79 if (p && strncmp(p, "no-affinity", 11) == 0)
80 msi_affinity_flag = 0;
82 msi_affinity_flag = 1;
86 early_param("lsmsi", early_parse_ls_scfg_msi);
88 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
90 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
92 msg->address_hi = upper_32_bits(msi_data->msiir_addr);
93 msg->address_lo = lower_32_bits(msi_data->msiir_addr);
94 msg->data = data->hwirq;
96 if (msi_affinity_flag)
97 msg->data |= cpumask_first(data->common->affinity);
99 iommu_dma_map_msi_msg(data->irq, msg);
102 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
103 const struct cpumask *mask, bool force)
105 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
108 if (!msi_affinity_flag)
112 cpu = cpumask_any_and(mask, cpu_online_mask);
114 cpu = cpumask_first(mask);
116 if (cpu >= msi_data->msir_num)
119 if (msi_data->msir[cpu].gic_irq <= 0) {
120 pr_warn("cannot bind the irq to cpu%d\n", cpu);
124 cpumask_copy(irq_data->common->affinity, mask);
126 return IRQ_SET_MASK_OK;
129 static struct irq_chip ls_scfg_msi_parent_chip = {
131 .irq_compose_msi_msg = ls_scfg_msi_compose_msg,
132 .irq_set_affinity = ls_scfg_msi_set_affinity,
135 static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
137 unsigned int nr_irqs,
140 struct ls_scfg_msi *msi_data = domain->host_data;
143 WARN_ON(nr_irqs != 1);
145 spin_lock(&msi_data->lock);
146 pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
147 if (pos < msi_data->irqs_num)
148 __set_bit(pos, msi_data->used);
151 spin_unlock(&msi_data->lock);
156 irq_domain_set_info(domain, virq, pos,
157 &ls_scfg_msi_parent_chip, msi_data,
158 handle_simple_irq, NULL, NULL);
163 static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
164 unsigned int virq, unsigned int nr_irqs)
166 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
167 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
171 if (pos < 0 || pos >= msi_data->irqs_num) {
172 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
176 spin_lock(&msi_data->lock);
177 __clear_bit(pos, msi_data->used);
178 spin_unlock(&msi_data->lock);
181 static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
182 .alloc = ls_scfg_msi_domain_irq_alloc,
183 .free = ls_scfg_msi_domain_irq_free,
186 static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
188 struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
189 struct ls_scfg_msi *msi_data = msir->msi_data;
191 int pos, size, virq, hwirq;
193 chained_irq_enter(irq_desc_get_chip(desc), desc);
195 val = ioread32be(msir->reg);
197 pos = msir->bit_start;
198 size = msir->bit_end + 1;
200 for_each_set_bit_from(pos, &val, size) {
201 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
203 virq = irq_find_mapping(msi_data->parent, hwirq);
205 generic_handle_irq(virq);
208 chained_irq_exit(irq_desc_get_chip(desc), desc);
211 static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
213 /* Initialize MSI domain parent */
214 msi_data->parent = irq_domain_add_linear(NULL,
216 &ls_scfg_msi_domain_ops,
218 if (!msi_data->parent) {
219 dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n");
223 msi_data->msi_domain = pci_msi_create_irq_domain(
224 of_node_to_fwnode(msi_data->pdev->dev.of_node),
225 &ls_scfg_msi_domain_info,
227 if (!msi_data->msi_domain) {
228 dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n");
229 irq_domain_remove(msi_data->parent);
236 static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
238 struct ls_scfg_msir *msir;
241 virq = platform_get_irq(msi_data->pdev, index);
245 msir = &msi_data->msir[index];
247 msir->msi_data = msi_data;
248 msir->gic_irq = virq;
249 msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
251 if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
252 msir->bit_start = 32 - ((msir->index + 1) *
253 MSI_LS1043V1_1_IRQS_PER_MSIR);
254 msir->bit_end = msir->bit_start +
255 MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
258 msir->bit_end = msi_data->cfg->msir_irqs - 1;
261 irq_set_chained_handler_and_data(msir->gic_irq,
262 ls_scfg_msi_irq_handler,
265 if (msi_affinity_flag) {
266 /* Associate MSIR interrupt to the cpu */
267 irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
268 msir->srs = 0; /* This value is determined by the CPU */
272 /* Release the hwirqs corresponding to this MSIR */
273 if (!msi_affinity_flag || msir->index == 0) {
274 for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
275 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
276 bitmap_clear(msi_data->used, hwirq, 1);
283 static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
285 struct ls_scfg_msi *msi_data = msir->msi_data;
288 if (msir->gic_irq > 0)
289 irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
291 for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
292 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
293 bitmap_set(msi_data->used, hwirq, 1);
299 static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
301 .msir_irqs = MSI_IRQS_PER_MSIR,
302 .msir_base = MSI_MSIR_OFFSET,
305 static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
307 .msir_irqs = MSI_IRQS_PER_MSIR,
308 .msir_base = MSI_MSIR_OFFSET,
311 static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
313 .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
314 .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
317 static const struct of_device_id ls_scfg_msi_id[] = {
318 /* The following two misspelled compatibles are obsolete */
319 { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
320 { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
322 { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
323 { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
324 { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
325 { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
328 MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
330 static int ls_scfg_msi_probe(struct platform_device *pdev)
332 const struct of_device_id *match;
333 struct ls_scfg_msi *msi_data;
334 struct resource *res;
337 match = of_match_device(ls_scfg_msi_id, &pdev->dev);
341 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
345 msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
349 if (IS_ERR(msi_data->regs)) {
350 dev_err(&pdev->dev, "failed to initialize 'regs'\n");
351 return PTR_ERR(msi_data->regs);
353 msi_data->msiir_addr = res->start;
355 msi_data->pdev = pdev;
356 spin_lock_init(&msi_data->lock);
358 msi_data->irqs_num = MSI_IRQS_PER_MSIR *
359 (1 << msi_data->cfg->ibs_shift);
360 msi_data->used = devm_kcalloc(&pdev->dev,
361 BITS_TO_LONGS(msi_data->irqs_num),
362 sizeof(*msi_data->used),
367 * Reserve all the hwirqs
368 * The available hwirqs will be released in ls1_msi_setup_hwirq()
370 bitmap_set(msi_data->used, 0, msi_data->irqs_num);
372 msi_data->msir_num = of_irq_count(pdev->dev.of_node);
374 if (msi_affinity_flag) {
377 cpu_num = num_possible_cpus();
378 if (msi_data->msir_num >= cpu_num)
379 msi_data->msir_num = cpu_num;
381 msi_affinity_flag = 0;
384 msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
385 sizeof(*msi_data->msir),
390 for (i = 0; i < msi_data->msir_num; i++)
391 ls_scfg_msi_setup_hwirq(msi_data, i);
393 ret = ls_scfg_msi_domains_init(msi_data);
397 platform_set_drvdata(pdev, msi_data);
402 static int ls_scfg_msi_remove(struct platform_device *pdev)
404 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
407 for (i = 0; i < msi_data->msir_num; i++)
408 ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
410 irq_domain_remove(msi_data->msi_domain);
411 irq_domain_remove(msi_data->parent);
413 platform_set_drvdata(pdev, NULL);
418 static struct platform_driver ls_scfg_msi_driver = {
420 .name = "ls-scfg-msi",
421 .of_match_table = ls_scfg_msi_id,
423 .probe = ls_scfg_msi_probe,
424 .remove = ls_scfg_msi_remove,
427 module_platform_driver(ls_scfg_msi_driver);
429 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@nxp.com>");
430 MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver");
431 MODULE_LICENSE("GPL v2");