drivers/irqchip/irq-gic.c

   1 /*
   2  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Interrupt architecture for the GIC:
   9  *
  10  * o There is one Interrupt Distributor, which receives interrupts
  11  *   from system devices and sends them to the Interrupt Controllers.
  12  *
  13  * o There is one CPU Interface per CPU, which sends interrupts sent
  14  *   by the Distributor, and interrupts generated locally, to the
  15  *   associated CPU. The base address of the CPU interface is usually
  16  *   aliased so that the same address points to different chips depending
  17  *   on the CPU it is accessed from.
  18  *
  19  * Note that IRQs 0-31 are special - they are local to each CPU.
  20  * As such, the enable set/clear, pending set/clear and active bit
  21  * registers are banked per-cpu for these sources.
  22  */
  23 #include <linux/init.h>
  24 #include <linux/kernel.h>
  25 #include <linux/err.h>
  26 #include <linux/module.h>
  27 #include <linux/list.h>
  28 #include <linux/smp.h>
  29 #include <linux/cpu.h>
  30 #include <linux/cpu_pm.h>
  31 #include <linux/cpumask.h>
  32 #include <linux/io.h>
  33 #include <linux/of.h>
  34 #include <linux/of_address.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/acpi.h>
  37 #include <linux/irqdomain.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/percpu.h>
  40 #include <linux/slab.h>
  41 #include <linux/irqchip.h>
  42 #include <linux/irqchip/chained_irq.h>
  43 #include <linux/irqchip/arm-gic.h>
  44
  45 #include <asm/cputype.h>
  46 #include <asm/irq.h>
  47 #include <asm/exception.h>
  48 #include <asm/smp_plat.h>
  49 #include <asm/virt.h>
  50
  51 #include "irq-gic-common.h"
  52
  53 #ifdef CONFIG_ARM64
  54 #include <asm/cpufeature.h>
  55
  56 static void gic_check_cpu_features(void)
  57 {
  58         WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
  59                         TAINT_CPU_OUT_OF_SPEC,
  60                         "GICv3 system registers enabled, broken firmware!\n");
  61 }
  62 #else
  63 #define gic_check_cpu_features()        do { } while(0)
  64 #endif
  65
  66 union gic_base {
  67         void __iomem *common_base;
  68         void __percpu * __iomem *percpu_base;
  69 };
  70
  71 struct gic_chip_data {
  72         struct irq_chip chip;
  73         union gic_base dist_base;
  74         union gic_base cpu_base;
  75         void __iomem *raw_dist_base;
  76         void __iomem *raw_cpu_base;
  77         u32 percpu_offset;
  78 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  79         u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
  80         u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
  81         u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
  82         u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
  83         u32 __percpu *saved_ppi_enable;
  84         u32 __percpu *saved_ppi_active;
  85         u32 __percpu *saved_ppi_conf;
  86 #endif
  87         struct irq_domain *domain;
  88         unsigned int gic_irqs;
  89 #ifdef CONFIG_GIC_NON_BANKED
  90         void __iomem *(*get_base)(union gic_base *);
  91 #endif
  92 };
  93
  94 #ifdef CONFIG_BL_SWITCHER
  95
  96 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
  97
  98 #define gic_lock_irqsave(f)             \
  99         raw_spin_lock_irqsave(&cpu_map_lock, (f))
 100 #define gic_unlock_irqrestore(f)        \
 101         raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
 102
 103 #define gic_lock()                      raw_spin_lock(&cpu_map_lock)
 104 #define gic_unlock()                    raw_spin_unlock(&cpu_map_lock)
 105
 106 #else
 107
 108 #define gic_lock_irqsave(f)             do { (void)(f); } while(0)
 109 #define gic_unlock_irqrestore(f)        do { (void)(f); } while(0)
 110
 111 #define gic_lock()                      do { } while(0)
 112 #define gic_unlock()                    do { } while(0)
 113
 114 #endif
 115
 116 /*
 117  * The GIC mapping of CPU interfaces does not necessarily match
 118  * the logical CPU numbering.  Let's use a mapping as returned
 119  * by the GIC itself.
 120  */
 121 #define NR_GIC_CPU_IF 8
 122 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 123
 124 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
 125
 126 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 127
 128 static struct gic_kvm_info gic_v2_kvm_info;
 129
 130 #ifdef CONFIG_GIC_NON_BANKED
 131 static void __iomem *gic_get_percpu_base(union gic_base *base)
 132 {
 133         return raw_cpu_read(*base->percpu_base);
 134 }
 135
 136 static void __iomem *gic_get_common_base(union gic_base *base)
 137 {
 138         return base->common_base;
 139 }
 140
 141 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
 142 {
 143         return data->get_base(&data->dist_base);
 144 }
 145
 146 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
 147 {
 148         return data->get_base(&data->cpu_base);
 149 }
 150
 151 static inline void gic_set_base_accessor(struct gic_chip_data *data,
 152                                          void __iomem *(*f)(union gic_base *))
 153 {
 154         data->get_base = f;
 155 }
 156 #else
 157 #define gic_data_dist_base(d)   ((d)->dist_base.common_base)
 158 #define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
 159 #define gic_set_base_accessor(d, f)
 160 #endif
 161
 162 static inline void __iomem *gic_dist_base(struct irq_data *d)
 163 {
 164         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 165         return gic_data_dist_base(gic_data);
 166 }
 167
 168 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 169 {
 170         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 171         return gic_data_cpu_base(gic_data);
 172 }
 173
 174 static inline unsigned int gic_irq(struct irq_data *d)
 175 {
 176         return d->hwirq;
 177 }
 178
 179 static inline bool cascading_gic_irq(struct irq_data *d)
 180 {
 181         void *data = irq_data_get_irq_handler_data(d);
 182
 183         /*
 184          * If handler_data is set, this is a cascading interrupt, and
 185          * it cannot possibly be forwarded.
 186          */
 187         return data != NULL;
 188 }
 189
 190 /*
 191  * Routines to acknowledge, disable and enable interrupts
 192  */
 193 static void gic_poke_irq(struct irq_data *d, u32 offset)
 194 {
 195         u32 mask = 1 << (gic_irq(d) % 32);
 196         writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
 197 }
 198
 199 static int gic_peek_irq(struct irq_data *d, u32 offset)
 200 {
 201         u32 mask = 1 << (gic_irq(d) % 32);
 202         return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
 203 }
 204
 205 static void gic_mask_irq(struct irq_data *d)
 206 {
 207         gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
 208 }
 209
 210 static void gic_eoimode1_mask_irq(struct irq_data *d)
 211 {
 212         gic_mask_irq(d);
 213         /*
 214          * When masking a forwarded interrupt, make sure it is
 215          * deactivated as well.
 216          *
 217          * This ensures that an interrupt that is getting
 218          * disabled/masked will not get "stuck", because there is
 219          * noone to deactivate it (guest is being terminated).
 220          */
 221         if (irqd_is_forwarded_to_vcpu(d))
 222                 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
 223 }
 224
 225 static void gic_unmask_irq(struct irq_data *d)
 226 {
 227         gic_poke_irq(d, GIC_DIST_ENABLE_SET);
 228 }
 229
 230 static void gic_eoi_irq(struct irq_data *d)
 231 {
 232         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 233 }
 234
 235 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 236 {
 237         /* Do not deactivate an IRQ forwarded to a vcpu. */
 238         if (irqd_is_forwarded_to_vcpu(d))
 239                 return;
 240
 241         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
 242 }
 243
 244 static int gic_irq_set_irqchip_state(struct irq_data *d,
 245                                      enum irqchip_irq_state which, bool val)
 246 {
 247         u32 reg;
 248
 249         switch (which) {
 250         case IRQCHIP_STATE_PENDING:
 251                 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
 252                 break;
 253
 254         case IRQCHIP_STATE_ACTIVE:
 255                 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
 256                 break;
 257
 258         case IRQCHIP_STATE_MASKED:
 259                 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
 260                 break;
 261
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         gic_poke_irq(d, reg);
 267         return 0;
 268 }
 269
 270 static int gic_irq_get_irqchip_state(struct irq_data *d,
 271                                       enum irqchip_irq_state which, bool *val)
 272 {
 273         switch (which) {
 274         case IRQCHIP_STATE_PENDING:
 275                 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
 276                 break;
 277
 278         case IRQCHIP_STATE_ACTIVE:
 279                 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
 280                 break;
 281
 282         case IRQCHIP_STATE_MASKED:
 283                 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
 284                 break;
 285
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int gic_set_type(struct irq_data *d, unsigned int type)
 294 {
 295         void __iomem *base = gic_dist_base(d);
 296         unsigned int gicirq = gic_irq(d);
 297
 298         /* Interrupt configuration for SGIs can't be changed */
 299         if (gicirq < 16)
 300                 return -EINVAL;
 301
 302         /* SPIs have restrictions on the supported types */
 303         if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 304                             type != IRQ_TYPE_EDGE_RISING)
 305                 return -EINVAL;
 306
 307         return gic_configure_irq(gicirq, type, base, NULL);
 308 }
 309
 310 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 311 {
 312         /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
 313         if (cascading_gic_irq(d))
 314                 return -EINVAL;
 315
 316         if (vcpu)
 317                 irqd_set_forwarded_to_vcpu(d);
 318         else
 319                 irqd_clr_forwarded_to_vcpu(d);
 320         return 0;
 321 }
 322
 323 #ifdef CONFIG_SMP
 324 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 325                             bool force)
 326 {
 327         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
 328         unsigned int cpu;
 329
 330         if (!force)
 331                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
 332         else
 333                 cpu = cpumask_first(mask_val);
 334
 335         if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
 336                 return -EINVAL;
 337
 338         writeb_relaxed(gic_cpu_map[cpu], reg);
 339         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 340
 341         return IRQ_SET_MASK_OK_DONE;
 342 }
 343 #endif
 344
 345 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 346 {
 347         u32 irqstat, irqnr;
 348         struct gic_chip_data *gic = &gic_data[0];
 349         void __iomem *cpu_base = gic_data_cpu_base(gic);
 350
 351         do {
 352                 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
 353                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 354
 355                 if (likely(irqnr > 15 && irqnr < 1020)) {
 356                         if (static_key_true(&supports_deactivate))
 357                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 358                         isb();
 359                         handle_domain_irq(gic->domain, irqnr, regs);
 360                         continue;
 361                 }
 362                 if (irqnr < 16) {
 363                         writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 364                         if (static_key_true(&supports_deactivate))
 365                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
 366 #ifdef CONFIG_SMP
 367                         /*
 368                          * Ensure any shared data written by the CPU sending
 369                          * the IPI is read after we've read the ACK register
 370                          * on the GIC.
 371                          *
 372                          * Pairs with the write barrier in gic_raise_softirq
 373                          */
 374                         smp_rmb();
 375                         handle_IPI(irqnr, regs);
 376 #endif
 377                         continue;
 378                 }
 379                 break;
 380         } while (1);
 381 }
 382
 383 static void gic_handle_cascade_irq(struct irq_desc *desc)
 384 {
 385         struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
 386         struct irq_chip *chip = irq_desc_get_chip(desc);
 387         unsigned int cascade_irq, gic_irq;
 388         unsigned long status;
 389
 390         chained_irq_enter(chip, desc);
 391
 392         status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
 393
 394         gic_irq = (status & GICC_IAR_INT_ID_MASK);
 395         if (gic_irq == GICC_INT_SPURIOUS)
 396                 goto out;
 397
 398         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
 399         if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
 400                 handle_bad_irq(desc);
 401         } else {
 402                 isb();
 403                 generic_handle_irq(cascade_irq);
 404         }
 405
 406  out:
 407         chained_irq_exit(chip, desc);
 408 }
 409
 410 static const struct irq_chip gic_chip = {
 411         .irq_mask               = gic_mask_irq,
 412         .irq_unmask             = gic_unmask_irq,
 413         .irq_eoi                = gic_eoi_irq,
 414         .irq_set_type           = gic_set_type,
 415         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 416         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 417         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 418                                   IRQCHIP_SKIP_SET_WAKE |
 419                                   IRQCHIP_MASK_ON_SUSPEND,
 420 };
 421
 422 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 423 {
 424         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 425         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
 426                                          &gic_data[gic_nr]);
 427 }
 428
 429 static u8 gic_get_cpumask(struct gic_chip_data *gic)
 430 {
 431         void __iomem *base = gic_data_dist_base(gic);
 432         u32 mask, i;
 433
 434         for (i = mask = 0; i < 32; i += 4) {
 435                 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
 436                 mask |= mask >> 16;
 437                 mask |= mask >> 8;
 438                 if (mask)
 439                         break;
 440         }
 441
 442         if (!mask && num_possible_cpus() > 1)
 443                 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 444
 445         return mask;
 446 }
 447
 448 static void gic_cpu_if_up(struct gic_chip_data *gic)
 449 {
 450         void __iomem *cpu_base = gic_data_cpu_base(gic);
 451         u32 bypass = 0;
 452         u32 mode = 0;
 453
 454         if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
 455                 mode = GIC_CPU_CTRL_EOImodeNS;
 456
 457         /*
 458         * Preserve bypass disable bits to be written back later
 459         */
 460         bypass = readl(cpu_base + GIC_CPU_CTRL);
 461         bypass &= GICC_DIS_BYPASS_MASK;
 462
 463         writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
 464 }
 465
 466
 467 static void gic_dist_init(struct gic_chip_data *gic)
 468 {
 469         unsigned int i;
 470         u32 cpumask;
 471         unsigned int gic_irqs = gic->gic_irqs;
 472         void __iomem *base = gic_data_dist_base(gic);
 473
 474         writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
 475
 476         /*
 477          * Set all global interrupts to this CPU only.
 478          */
 479         cpumask = gic_get_cpumask(gic);
 480         cpumask |= cpumask << 8;
 481         cpumask |= cpumask << 16;
 482         for (i = 32; i < gic_irqs; i += 4)
 483                 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 484
 485         gic_dist_config(base, gic_irqs, NULL);
 486
 487         writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
 488 }
 489
 490 static int gic_cpu_init(struct gic_chip_data *gic)
 491 {
 492         void __iomem *dist_base = gic_data_dist_base(gic);
 493         void __iomem *base = gic_data_cpu_base(gic);
 494         unsigned int cpu_mask, cpu = smp_processor_id();
 495         int i;
 496
 497         /*
 498          * Setting up the CPU map is only relevant for the primary GIC
 499          * because any nested/secondary GICs do not directly interface
 500          * with the CPU(s).
 501          */
 502         if (gic == &gic_data[0]) {
 503                 /*
 504                  * Get what the GIC says our CPU mask is.
 505                  */
 506                 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
 507                         return -EINVAL;
 508
 509                 gic_check_cpu_features();
 510                 cpu_mask = gic_get_cpumask(gic);
 511                 gic_cpu_map[cpu] = cpu_mask;
 512
 513                 /*
 514                  * Clear our mask from the other map entries in case they're
 515                  * still undefined.
 516                  */
 517                 for (i = 0; i < NR_GIC_CPU_IF; i++)
 518                         if (i != cpu)
 519                                 gic_cpu_map[i] &= ~cpu_mask;
 520         }
 521
 522         gic_cpu_config(dist_base, NULL);
 523
 524         writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
 525         gic_cpu_if_up(gic);
 526
 527         return 0;
 528 }
 529
 530 int gic_cpu_if_down(unsigned int gic_nr)
 531 {
 532         void __iomem *cpu_base;
 533         u32 val = 0;
 534
 535         if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
 536                 return -EINVAL;
 537
 538         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 539         val = readl(cpu_base + GIC_CPU_CTRL);
 540         val &= ~GICC_ENABLE;
 541         writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
 542
 543         return 0;
 544 }
 545
 546 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
 547 /*
 548  * Saves the GIC distributor registers during suspend or idle.  Must be called
 549  * with interrupts disabled but before powering down the GIC.  After calling
 550  * this function, no interrupts will be delivered by the GIC, and another
 551  * platform-specific wakeup source must be enabled.
 552  */
 553 void gic_dist_save(struct gic_chip_data *gic)
 554 {
 555         unsigned int gic_irqs;
 556         void __iomem *dist_base;
 557         int i;
 558
 559         if (WARN_ON(!gic))
 560                 return;
 561
 562         gic_irqs = gic->gic_irqs;
 563         dist_base = gic_data_dist_base(gic);
 564
 565         if (!dist_base)
 566                 return;
 567
 568         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 569                 gic->saved_spi_conf[i] =
 570                         readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 571
 572         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 573                 gic->saved_spi_target[i] =
 574                         readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 575
 576         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 577                 gic->saved_spi_enable[i] =
 578                         readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 579
 580         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 581                 gic->saved_spi_active[i] =
 582                         readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 583 }
 584
 585 /*
 586  * Restores the GIC distributor registers during resume or when coming out of
 587  * idle.  Must be called before enabling interrupts.  If a level interrupt
 588  * that occured while the GIC was suspended is still present, it will be
 589  * handled normally, but any edge interrupts that occured will not be seen by
 590  * the GIC and need to be handled by the platform-specific wakeup source.
 591  */
 592 void gic_dist_restore(struct gic_chip_data *gic)
 593 {
 594         unsigned int gic_irqs;
 595         unsigned int i;
 596         void __iomem *dist_base;
 597
 598         if (WARN_ON(!gic))
 599                 return;
 600
 601         gic_irqs = gic->gic_irqs;
 602         dist_base = gic_data_dist_base(gic);
 603
 604         if (!dist_base)
 605                 return;
 606
 607         writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 608
 609         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 610                 writel_relaxed(gic->saved_spi_conf[i],
 611                         dist_base + GIC_DIST_CONFIG + i * 4);
 612
 613         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 614                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 615                         dist_base + GIC_DIST_PRI + i * 4);
 616
 617         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 618                 writel_relaxed(gic->saved_spi_target[i],
 619                         dist_base + GIC_DIST_TARGET + i * 4);
 620
 621         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 622                 writel_relaxed(GICD_INT_EN_CLR_X32,
 623                         dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 624                 writel_relaxed(gic->saved_spi_enable[i],
 625                         dist_base + GIC_DIST_ENABLE_SET + i * 4);
 626         }
 627
 628         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 629                 writel_relaxed(GICD_INT_EN_CLR_X32,
 630                         dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 631                 writel_relaxed(gic->saved_spi_active[i],
 632                         dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 633         }
 634
 635         writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
 636 }
 637
 638 void gic_cpu_save(struct gic_chip_data *gic)
 639 {
 640         int i;
 641         u32 *ptr;
 642         void __iomem *dist_base;
 643         void __iomem *cpu_base;
 644
 645         if (WARN_ON(!gic))
 646                 return;
 647
 648         dist_base = gic_data_dist_base(gic);
 649         cpu_base = gic_data_cpu_base(gic);
 650
 651         if (!dist_base || !cpu_base)
 652                 return;
 653
 654         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 655         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 656                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 657
 658         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 659         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 660                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 661
 662         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 663         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 664                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 665
 666 }
 667
 668 void gic_cpu_restore(struct gic_chip_data *gic)
 669 {
 670         int i;
 671         u32 *ptr;
 672         void __iomem *dist_base;
 673         void __iomem *cpu_base;
 674
 675         if (WARN_ON(!gic))
 676                 return;
 677
 678         dist_base = gic_data_dist_base(gic);
 679         cpu_base = gic_data_cpu_base(gic);
 680
 681         if (!dist_base || !cpu_base)
 682                 return;
 683
 684         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 685         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 686                 writel_relaxed(GICD_INT_EN_CLR_X32,
 687                                dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 688                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
 689         }
 690
 691         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 692         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 693                 writel_relaxed(GICD_INT_EN_CLR_X32,
 694                                dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 695                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 696         }
 697
 698         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 699         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 700                 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 701
 702         for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
 703                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 704                                         dist_base + GIC_DIST_PRI + i * 4);
 705
 706         writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
 707         gic_cpu_if_up(gic);
 708 }
 709
 710 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 711 {
 712         int i;
 713
 714         for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 715 #ifdef CONFIG_GIC_NON_BANKED
 716                 /* Skip over unused GICs */
 717                 if (!gic_data[i].get_base)
 718                         continue;
 719 #endif
 720                 switch (cmd) {
 721                 case CPU_PM_ENTER:
 722                         gic_cpu_save(&gic_data[i]);
 723                         break;
 724                 case CPU_PM_ENTER_FAILED:
 725                 case CPU_PM_EXIT:
 726                         gic_cpu_restore(&gic_data[i]);
 727                         break;
 728                 case CPU_CLUSTER_PM_ENTER:
 729                         gic_dist_save(&gic_data[i]);
 730                         break;
 731                 case CPU_CLUSTER_PM_ENTER_FAILED:
 732                 case CPU_CLUSTER_PM_EXIT:
 733                         gic_dist_restore(&gic_data[i]);
 734                         break;
 735                 }
 736         }
 737
 738         return NOTIFY_OK;
 739 }
 740
 741 static struct notifier_block gic_notifier_block = {
 742         .notifier_call = gic_notifier,
 743 };
 744
 745 static int gic_pm_init(struct gic_chip_data *gic)
 746 {
 747         gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 748                 sizeof(u32));
 749         if (WARN_ON(!gic->saved_ppi_enable))
 750                 return -ENOMEM;
 751
 752         gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 753                 sizeof(u32));
 754         if (WARN_ON(!gic->saved_ppi_active))
 755                 goto free_ppi_enable;
 756
 757         gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
 758                 sizeof(u32));
 759         if (WARN_ON(!gic->saved_ppi_conf))
 760                 goto free_ppi_active;
 761
 762         if (gic == &gic_data[0])
 763                 cpu_pm_register_notifier(&gic_notifier_block);
 764
 765         return 0;
 766
 767 free_ppi_active:
 768         free_percpu(gic->saved_ppi_active);
 769 free_ppi_enable:
 770         free_percpu(gic->saved_ppi_enable);
 771
 772         return -ENOMEM;
 773 }
 774 #else
 775 static int gic_pm_init(struct gic_chip_data *gic)
 776 {
 777         return 0;
 778 }
 779 #endif
 780
 781 #ifdef CONFIG_SMP
 782 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 783 {
 784         int cpu;
 785         unsigned long flags, map = 0;
 786
 787         if (unlikely(nr_cpu_ids == 1)) {
 788                 /* Only one CPU? let's do a self-IPI... */
 789                 writel_relaxed(2 << 24 | irq,
 790                                gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 791                 return;
 792         }
 793
 794         gic_lock_irqsave(flags);
 795
 796         /* Convert our logical CPU mask into a physical one. */
 797         for_each_cpu(cpu, mask)
 798                 map |= gic_cpu_map[cpu];
 799
 800         /*
 801          * Ensure that stores to Normal memory are visible to the
 802          * other CPUs before they observe us issuing the IPI.
 803          */
 804         dmb(ishst);
 805
 806         /* this always happens on GIC0 */
 807         writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 808
 809         gic_unlock_irqrestore(flags);
 810 }
 811 #endif
 812
 813 #ifdef CONFIG_BL_SWITCHER
 814 /*
 815  * gic_send_sgi - send a SGI directly to given CPU interface number
 816  *
 817  * cpu_id: the ID for the destination CPU interface
 818  * irq: the IPI number to send a SGI for
 819  */
 820 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 821 {
 822         BUG_ON(cpu_id >= NR_GIC_CPU_IF);
 823         cpu_id = 1 << cpu_id;
 824         /* this always happens on GIC0 */
 825         writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 826 }
 827
 828 /*
 829  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
 830  *
 831  * @cpu: the logical CPU number to get the GIC ID for.
 832  *
 833  * Return the CPU interface ID for the given logical CPU number,
 834  * or -1 if the CPU number is too large or the interface ID is
 835  * unknown (more than one bit set).
 836  */
 837 int gic_get_cpu_id(unsigned int cpu)
 838 {
 839         unsigned int cpu_bit;
 840
 841         if (cpu >= NR_GIC_CPU_IF)
 842                 return -1;
 843         cpu_bit = gic_cpu_map[cpu];
 844         if (cpu_bit & (cpu_bit - 1))
 845                 return -1;
 846         return __ffs(cpu_bit);
 847 }
 848
 849 /*
 850  * gic_migrate_target - migrate IRQs to another CPU interface
 851  *
 852  * @new_cpu_id: the CPU target ID to migrate IRQs to
 853  *
 854  * Migrate all peripheral interrupts with a target matching the current CPU
 855  * to the interface corresponding to @new_cpu_id.  The CPU interface mapping
 856  * is also updated.  Targets to other CPU interfaces are unchanged.
 857  * This must be called with IRQs locally disabled.
 858  */
 859 void gic_migrate_target(unsigned int new_cpu_id)
 860 {
 861         unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
 862         void __iomem *dist_base;
 863         int i, ror_val, cpu = smp_processor_id();
 864         u32 val, cur_target_mask, active_mask;
 865
 866         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 867
 868         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 869         if (!dist_base)
 870                 return;
 871         gic_irqs = gic_data[gic_nr].gic_irqs;
 872
 873         cur_cpu_id = __ffs(gic_cpu_map[cpu]);
 874         cur_target_mask = 0x01010101 << cur_cpu_id;
 875         ror_val = (cur_cpu_id - new_cpu_id) & 31;
 876
 877         gic_lock();
 878
 879         /* Update the target interface for this logical CPU */
 880         gic_cpu_map[cpu] = 1 << new_cpu_id;
 881
 882         /*
 883          * Find all the peripheral interrupts targetting the current
 884          * CPU interface and migrate them to the new CPU interface.
 885          * We skip DIST_TARGET 0 to 7 as they are read-only.
 886          */
 887         for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
 888                 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 889                 active_mask = val & cur_target_mask;
 890                 if (active_mask) {
 891                         val &= ~active_mask;
 892                         val |= ror32(active_mask, ror_val);
 893                         writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
 894                 }
 895         }
 896
 897         gic_unlock();
 898
 899         /*
 900          * Now let's migrate and clear any potential SGIs that might be
 901          * pending for us (cur_cpu_id).  Since GIC_DIST_SGI_PENDING_SET
 902          * is a banked register, we can only forward the SGI using
 903          * GIC_DIST_SOFTINT.  The original SGI source is lost but Linux
 904          * doesn't use that information anyway.
 905          *
 906          * For the same reason we do not adjust SGI source information
 907          * for previously sent SGIs by us to other CPUs either.
 908          */
 909         for (i = 0; i < 16; i += 4) {
 910                 int j;
 911                 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
 912                 if (!val)
 913                         continue;
 914                 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
 915                 for (j = i; j < i + 4; j++) {
 916                         if (val & 0xff)
 917                                 writel_relaxed((1 << (new_cpu_id + 16)) | j,
 918                                                 dist_base + GIC_DIST_SOFTINT);
 919                         val >>= 8;
 920                 }
 921         }
 922 }
 923
 924 /*
 925  * gic_get_sgir_physaddr - get the physical address for the SGI register
 926  *
 927  * REturn the physical address of the SGI register to be used
 928  * by some early assembly code when the kernel is not yet available.
 929  */
 930 static unsigned long gic_dist_physaddr;
 931
 932 unsigned long gic_get_sgir_physaddr(void)
 933 {
 934         if (!gic_dist_physaddr)
 935                 return 0;
 936         return gic_dist_physaddr + GIC_DIST_SOFTINT;
 937 }
 938
 939 static void __init gic_init_physaddr(struct device_node *node)
 940 {
 941         struct resource res;
 942         if (of_address_to_resource(node, 0, &res) == 0) {
 943                 gic_dist_physaddr = res.start;
 944                 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
 945         }
 946 }
 947
 948 #else
 949 #define gic_init_physaddr(node)  do { } while (0)
 950 #endif
 951
 952 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 953                                 irq_hw_number_t hw)
 954 {
 955         struct gic_chip_data *gic = d->host_data;
 956
 957         if (hw < 32) {
 958                 irq_set_percpu_devid(irq);
 959                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 960                                     handle_percpu_devid_irq, NULL, NULL);
 961                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 962         } else {
 963                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 964                                     handle_fasteoi_irq, NULL, NULL);
 965                 irq_set_probe(irq);
 966                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
 967         }
 968         return 0;
 969 }
 970
 971 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 972 {
 973 }
 974
 975 static int gic_irq_domain_translate(struct irq_domain *d,
 976                                     struct irq_fwspec *fwspec,
 977                                     unsigned long *hwirq,
 978                                     unsigned int *type)
 979 {
 980         if (is_of_node(fwspec->fwnode)) {
 981                 if (fwspec->param_count < 3)
 982                         return -EINVAL;
 983
 984                 /* Get the interrupt number and add 16 to skip over SGIs */
 985                 *hwirq = fwspec->param[1] + 16;
 986
 987                 /*
 988                  * For SPIs, we need to add 16 more to get the GIC irq
 989                  * ID number
 990                  */
 991                 if (!fwspec->param[0])
 992                         *hwirq += 16;
 993
 994                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
 995                 return 0;
 996         }
 997
 998         if (is_fwnode_irqchip(fwspec->fwnode)) {
 999                 if(fwspec->param_count != 2)
1000                         return -EINVAL;
1001
1002                 *hwirq = fwspec->param[0];
1003                 *type = fwspec->param[1];
1004                 return 0;
1005         }
1006
1007         return -EINVAL;
1008 }
1009
1010 static int gic_starting_cpu(unsigned int cpu)
1011 {
1012         gic_cpu_init(&gic_data[0]);
1013         return 0;
1014 }
1015
1016 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1017                                 unsigned int nr_irqs, void *arg)
1018 {
1019         int i, ret;
1020         irq_hw_number_t hwirq;
1021         unsigned int type = IRQ_TYPE_NONE;
1022         struct irq_fwspec *fwspec = arg;
1023
1024         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1025         if (ret)
1026                 return ret;
1027
1028         for (i = 0; i < nr_irqs; i++) {
1029                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1030                 if (ret)
1031                         return ret;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1038         .translate = gic_irq_domain_translate,
1039         .alloc = gic_irq_domain_alloc,
1040         .free = irq_domain_free_irqs_top,
1041 };
1042
1043 static const struct irq_domain_ops gic_irq_domain_ops = {
1044         .map = gic_irq_domain_map,
1045         .unmap = gic_irq_domain_unmap,
1046 };
1047
1048 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1049                           const char *name, bool use_eoimode1)
1050 {
1051         /* Initialize irq_chip */
1052         gic->chip = gic_chip;
1053         gic->chip.name = name;
1054         gic->chip.parent_device = dev;
1055
1056         if (use_eoimode1) {
1057                 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1058                 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1059                 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1060         }
1061
1062 #ifdef CONFIG_SMP
1063         if (gic == &gic_data[0])
1064                 gic->chip.irq_set_affinity = gic_set_affinity;
1065 #endif
1066 }
1067
1068 static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1069                           struct fwnode_handle *handle)
1070 {
1071         irq_hw_number_t hwirq_base;
1072         int gic_irqs, irq_base, ret;
1073
1074         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1075                 /* Frankein-GIC without banked registers... */
1076                 unsigned int cpu;
1077
1078                 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1079                 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1080                 if (WARN_ON(!gic->dist_base.percpu_base ||
1081                             !gic->cpu_base.percpu_base)) {
1082                         ret = -ENOMEM;
1083                         goto error;
1084                 }
1085
1086                 for_each_possible_cpu(cpu) {
1087                         u32 mpidr = cpu_logical_map(cpu);
1088                         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1089                         unsigned long offset = gic->percpu_offset * core_id;
1090                         *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1091                                 gic->raw_dist_base + offset;
1092                         *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1093                                 gic->raw_cpu_base + offset;
1094                 }
1095
1096                 gic_set_base_accessor(gic, gic_get_percpu_base);
1097         } else {
1098                 /* Normal, sane GIC... */
1099                 WARN(gic->percpu_offset,
1100                      "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1101                      gic->percpu_offset);
1102                 gic->dist_base.common_base = gic->raw_dist_base;
1103                 gic->cpu_base.common_base = gic->raw_cpu_base;
1104                 gic_set_base_accessor(gic, gic_get_common_base);
1105         }
1106
1107         /*
1108          * Find out how many interrupts are supported.
1109          * The GIC only supports up to 1020 interrupt sources.
1110          */
1111         gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1112         gic_irqs = (gic_irqs + 1) * 32;
1113         if (gic_irqs > 1020)
1114                 gic_irqs = 1020;
1115         gic->gic_irqs = gic_irqs;
1116
1117         if (handle) {           /* DT/ACPI */
1118                 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1119                                                        &gic_irq_domain_hierarchy_ops,
1120                                                        gic);
1121         } else {                /* Legacy support */
1122                 /*
1123                  * For primary GICs, skip over SGIs.
1124                  * For secondary GICs, skip over PPIs, too.
1125                  */
1126                 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1127                         hwirq_base = 16;
1128                         if (irq_start != -1)
1129                                 irq_start = (irq_start & ~31) + 16;
1130                 } else {
1131                         hwirq_base = 32;
1132                 }
1133
1134                 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1135
1136                 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1137                                            numa_node_id());
1138                 if (irq_base < 0) {
1139                         WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1140                              irq_start);
1141                         irq_base = irq_start;
1142                 }
1143
1144                 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1145                                         hwirq_base, &gic_irq_domain_ops, gic);
1146         }
1147
1148         if (WARN_ON(!gic->domain)) {
1149                 ret = -ENODEV;
1150                 goto error;
1151         }
1152
1153         gic_dist_init(gic);
1154         ret = gic_cpu_init(gic);
1155         if (ret)
1156                 goto error;
1157
1158         ret = gic_pm_init(gic);
1159         if (ret)
1160                 goto error;
1161
1162         return 0;
1163
1164 error:
1165         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1166                 free_percpu(gic->dist_base.percpu_base);
1167                 free_percpu(gic->cpu_base.percpu_base);
1168         }
1169
1170         return ret;
1171 }
1172
1173 static int __init __gic_init_bases(struct gic_chip_data *gic,
1174                                    int irq_start,
1175                                    struct fwnode_handle *handle)
1176 {
1177         char *name;
1178         int i, ret;
1179
1180         if (WARN_ON(!gic || gic->domain))
1181                 return -EINVAL;
1182
1183         if (gic == &gic_data[0]) {
1184                 /*
1185                  * Initialize the CPU interface map to all CPUs.
1186                  * It will be refined as each CPU probes its ID.
1187                  * This is only necessary for the primary GIC.
1188                  */
1189                 for (i = 0; i < NR_GIC_CPU_IF; i++)
1190                         gic_cpu_map[i] = 0xff;
1191 #ifdef CONFIG_SMP
1192                 set_smp_cross_call(gic_raise_softirq);
1193 #endif
1194                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1195                                           "irqchip/arm/gic:starting",
1196                                           gic_starting_cpu, NULL);
1197                 set_handle_irq(gic_handle_irq);
1198                 if (static_key_true(&supports_deactivate))
1199                         pr_info("GIC: Using split EOI/Deactivate mode\n");
1200         }
1201
1202         if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1203                 name = kasprintf(GFP_KERNEL, "GICv2");
1204                 gic_init_chip(gic, NULL, name, true);
1205         } else {
1206                 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1207                 gic_init_chip(gic, NULL, name, false);
1208         }
1209
1210         ret = gic_init_bases(gic, irq_start, handle);
1211         if (ret)
1212                 kfree(name);
1213
1214         return ret;
1215 }
1216
1217 void __init gic_init(unsigned int gic_nr, int irq_start,
1218                      void __iomem *dist_base, void __iomem *cpu_base)
1219 {
1220         struct gic_chip_data *gic;
1221
1222         if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1223                 return;
1224
1225         /*
1226          * Non-DT/ACPI systems won't run a hypervisor, so let's not
1227          * bother with these...
1228          */
1229         static_key_slow_dec(&supports_deactivate);
1230
1231         gic = &gic_data[gic_nr];
1232         gic->raw_dist_base = dist_base;
1233         gic->raw_cpu_base = cpu_base;
1234
1235         __gic_init_bases(gic, irq_start, NULL);
1236 }
1237
1238 static void gic_teardown(struct gic_chip_data *gic)
1239 {
1240         if (WARN_ON(!gic))
1241                 return;
1242
1243         if (gic->raw_dist_base)
1244                 iounmap(gic->raw_dist_base);
1245         if (gic->raw_cpu_base)
1246                 iounmap(gic->raw_cpu_base);
1247 }
1248
1249 #ifdef CONFIG_OF
1250 static int gic_cnt __initdata;
1251
1252 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1253 {
1254         struct resource cpuif_res;
1255
1256         of_address_to_resource(node, 1, &cpuif_res);
1257
1258         if (!is_hyp_mode_available())
1259                 return false;
1260         if (resource_size(&cpuif_res) < SZ_8K)
1261                 return false;
1262         if (resource_size(&cpuif_res) == SZ_128K) {
1263                 u32 val_low, val_high;
1264
1265                 /*
1266                  * Verify that we have the first 4kB of a GIC400
1267                  * aliased over the first 64kB by checking the
1268                  * GICC_IIDR register on both ends.
1269                  */
1270                 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1271                 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1272                 if ((val_low & 0xffff0fff) != 0x0202043B ||
1273                     val_low != val_high)
1274                         return false;
1275
1276                 /*
1277                  * Move the base up by 60kB, so that we have a 8kB
1278                  * contiguous region, which allows us to use GICC_DIR
1279                  * at its normal offset. Please pass me that bucket.
1280                  */
1281                 *base += 0xf000;
1282                 cpuif_res.start += 0xf000;
1283                 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1284                         &cpuif_res.start);
1285         }
1286
1287         return true;
1288 }
1289
1290 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1291 {
1292         if (!gic || !node)
1293                 return -EINVAL;
1294
1295         gic->raw_dist_base = of_iomap(node, 0);
1296         if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1297                 goto error;
1298
1299         gic->raw_cpu_base = of_iomap(node, 1);
1300         if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1301                 goto error;
1302
1303         if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1304                 gic->percpu_offset = 0;
1305
1306         return 0;
1307
1308 error:
1309         gic_teardown(gic);
1310
1311         return -ENOMEM;
1312 }
1313
1314 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1315 {
1316         int ret;
1317
1318         if (!dev || !dev->of_node || !gic || !irq)
1319                 return -EINVAL;
1320
1321         *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1322         if (!*gic)
1323                 return -ENOMEM;
1324
1325         gic_init_chip(*gic, dev, dev->of_node->name, false);
1326
1327         ret = gic_of_setup(*gic, dev->of_node);
1328         if (ret)
1329                 return ret;
1330
1331         ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1332         if (ret) {
1333                 gic_teardown(*gic);
1334                 return ret;
1335         }
1336
1337         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1338
1339         return 0;
1340 }
1341
1342 static void __init gic_of_setup_kvm_info(struct device_node *node)
1343 {
1344         int ret;
1345         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1346         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1347
1348         gic_v2_kvm_info.type = GIC_V2;
1349
1350         gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1351         if (!gic_v2_kvm_info.maint_irq)
1352                 return;
1353
1354         ret = of_address_to_resource(node, 2, vctrl_res);
1355         if (ret)
1356                 return;
1357
1358         ret = of_address_to_resource(node, 3, vcpu_res);
1359         if (ret)
1360                 return;
1361
1362         gic_set_kvm_info(&gic_v2_kvm_info);
1363 }
1364
1365 int __init
1366 gic_of_init(struct device_node *node, struct device_node *parent)
1367 {
1368         struct gic_chip_data *gic;
1369         int irq, ret;
1370
1371         if (WARN_ON(!node))
1372                 return -ENODEV;
1373
1374         if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1375                 return -EINVAL;
1376
1377         gic = &gic_data[gic_cnt];
1378
1379         ret = gic_of_setup(gic, node);
1380         if (ret)
1381                 return ret;
1382
1383         /*
1384          * Disable split EOI/Deactivate if either HYP is not available
1385          * or the CPU interface is too small.
1386          */
1387         if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1388                 static_key_slow_dec(&supports_deactivate);
1389
1390         ret = __gic_init_bases(gic, -1, &node->fwnode);
1391         if (ret) {
1392                 gic_teardown(gic);
1393                 return ret;
1394         }
1395
1396         if (!gic_cnt) {
1397                 gic_init_physaddr(node);
1398                 gic_of_setup_kvm_info(node);
1399         }
1400
1401         if (parent) {
1402                 irq = irq_of_parse_and_map(node, 0);
1403                 gic_cascade_irq(gic_cnt, irq);
1404         }
1405
1406         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1407                 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1408
1409         gic_cnt++;
1410         return 0;
1411 }
1412 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1413 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1414 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1415 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1416 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1417 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1418 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1419 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1420 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1421 #else
1422 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1423 {
1424         return -ENOTSUPP;
1425 }
1426 #endif
1427
1428 #ifdef CONFIG_ACPI
1429 static struct
1430 {
1431         phys_addr_t cpu_phys_base;
1432         u32 maint_irq;
1433         int maint_irq_mode;
1434         phys_addr_t vctrl_base;
1435         phys_addr_t vcpu_base;
1436 } acpi_data __initdata;
1437
1438 static int __init
1439 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1440                         const unsigned long end)
1441 {
1442         struct acpi_madt_generic_interrupt *processor;
1443         phys_addr_t gic_cpu_base;
1444         static int cpu_base_assigned;
1445
1446         processor = (struct acpi_madt_generic_interrupt *)header;
1447
1448         if (BAD_MADT_GICC_ENTRY(processor, end))
1449                 return -EINVAL;
1450
1451         /*
1452          * There is no support for non-banked GICv1/2 register in ACPI spec.
1453          * All CPU interface addresses have to be the same.
1454          */
1455         gic_cpu_base = processor->base_address;
1456         if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1457                 return -EINVAL;
1458
1459         acpi_data.cpu_phys_base = gic_cpu_base;
1460         acpi_data.maint_irq = processor->vgic_interrupt;
1461         acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1462                                     ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1463         acpi_data.vctrl_base = processor->gich_base_address;
1464         acpi_data.vcpu_base = processor->gicv_base_address;
1465
1466         cpu_base_assigned = 1;
1467         return 0;
1468 }
1469
1470 /* The things you have to do to just *count* something... */
1471 static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1472                                   const unsigned long end)
1473 {
1474         return 0;
1475 }
1476
1477 static bool __init acpi_gic_redist_is_present(void)
1478 {
1479         return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1480                                      acpi_dummy_func, 0) > 0;
1481 }
1482
1483 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1484                                      struct acpi_probe_entry *ape)
1485 {
1486         struct acpi_madt_generic_distributor *dist;
1487         dist = (struct acpi_madt_generic_distributor *)header;
1488
1489         return (dist->version == ape->driver_data &&
1490                 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1491                  !acpi_gic_redist_is_present()));
1492 }
1493
1494 #define ACPI_GICV2_DIST_MEM_SIZE        (SZ_4K)
1495 #define ACPI_GIC_CPU_IF_MEM_SIZE        (SZ_8K)
1496 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1497 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1498
1499 static void __init gic_acpi_setup_kvm_info(void)
1500 {
1501         int irq;
1502         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1503         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1504
1505         gic_v2_kvm_info.type = GIC_V2;
1506
1507         if (!acpi_data.vctrl_base)
1508                 return;
1509
1510         vctrl_res->flags = IORESOURCE_MEM;
1511         vctrl_res->start = acpi_data.vctrl_base;
1512         vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1513
1514         if (!acpi_data.vcpu_base)
1515                 return;
1516
1517         vcpu_res->flags = IORESOURCE_MEM;
1518         vcpu_res->start = acpi_data.vcpu_base;
1519         vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1520
1521         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1522                                 acpi_data.maint_irq_mode,
1523                                 ACPI_ACTIVE_HIGH);
1524         if (irq <= 0)
1525                 return;
1526
1527         gic_v2_kvm_info.maint_irq = irq;
1528
1529         gic_set_kvm_info(&gic_v2_kvm_info);
1530 }
1531
1532 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1533                                    const unsigned long end)
1534 {
1535         struct acpi_madt_generic_distributor *dist;
1536         struct fwnode_handle *domain_handle;
1537         struct gic_chip_data *gic = &gic_data[0];
1538         int count, ret;
1539
1540         /* Collect CPU base addresses */
1541         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1542                                       gic_acpi_parse_madt_cpu, 0);
1543         if (count <= 0) {
1544                 pr_err("No valid GICC entries exist\n");
1545                 return -EINVAL;
1546         }
1547
1548         gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1549         if (!gic->raw_cpu_base) {
1550                 pr_err("Unable to map GICC registers\n");
1551                 return -ENOMEM;
1552         }
1553
1554         dist = (struct acpi_madt_generic_distributor *)header;
1555         gic->raw_dist_base = ioremap(dist->base_address,
1556                                      ACPI_GICV2_DIST_MEM_SIZE);
1557         if (!gic->raw_dist_base) {
1558                 pr_err("Unable to map GICD registers\n");
1559                 gic_teardown(gic);
1560                 return -ENOMEM;
1561         }
1562
1563         /*
1564          * Disable split EOI/Deactivate if HYP is not available. ACPI
1565          * guarantees that we'll always have a GICv2, so the CPU
1566          * interface will always be the right size.
1567          */
1568         if (!is_hyp_mode_available())
1569                 static_key_slow_dec(&supports_deactivate);
1570
1571         /*
1572          * Initialize GIC instance zero (no multi-GIC support).
1573          */
1574         domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1575         if (!domain_handle) {
1576                 pr_err("Unable to allocate domain handle\n");
1577                 gic_teardown(gic);
1578                 return -ENOMEM;
1579         }
1580
1581         ret = __gic_init_bases(gic, -1, domain_handle);
1582         if (ret) {
1583                 pr_err("Failed to initialise GIC\n");
1584                 irq_domain_free_fwnode(domain_handle);
1585                 gic_teardown(gic);
1586                 return ret;
1587         }
1588
1589         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1590
1591         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1592                 gicv2m_init(NULL, gic_data[0].domain);
1593
1594         gic_acpi_setup_kvm_info();
1595
1596         return 0;
1597 }
1598 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1599                      gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1600                      gic_v2_acpi_init);
1601 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1602                      gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1603                      gic_v2_acpi_init);
1604 #endif