drivers/irqchip/irq-gic.c

   1 /*
   2  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Interrupt architecture for the GIC:
   9  *
  10  * o There is one Interrupt Distributor, which receives interrupts
  11  *   from system devices and sends them to the Interrupt Controllers.
  12  *
  13  * o There is one CPU Interface per CPU, which sends interrupts sent
  14  *   by the Distributor, and interrupts generated locally, to the
  15  *   associated CPU. The base address of the CPU interface is usually
  16  *   aliased so that the same address points to different chips depending
  17  *   on the CPU it is accessed from.
  18  *
  19  * Note that IRQs 0-31 are special - they are local to each CPU.
  20  * As such, the enable set/clear, pending set/clear and active bit
  21  * registers are banked per-cpu for these sources.
  22  */
  23 #include <linux/init.h>
  24 #include <linux/kernel.h>
  25 #include <linux/err.h>
  26 #include <linux/module.h>
  27 #include <linux/list.h>
  28 #include <linux/smp.h>
  29 #include <linux/cpu.h>
  30 #include <linux/cpu_pm.h>
  31 #include <linux/cpumask.h>
  32 #include <linux/io.h>
  33 #include <linux/of.h>
  34 #include <linux/of_address.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/acpi.h>
  37 #include <linux/irqdomain.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/percpu.h>
  40 #include <linux/slab.h>
  41 #include <linux/irqchip.h>
  42 #include <linux/irqchip/chained_irq.h>
  43 #include <linux/irqchip/arm-gic.h>
  44
  45 #include <asm/cputype.h>
  46 #include <asm/irq.h>
  47 #include <asm/exception.h>
  48 #include <asm/smp_plat.h>
  49 #include <asm/virt.h>
  50
  51 #include "irq-gic-common.h"
  52
  53 #ifdef CONFIG_ARM64
  54 #include <asm/cpufeature.h>
  55
  56 static void gic_check_cpu_features(void)
  57 {
  58         WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
  59                         TAINT_CPU_OUT_OF_SPEC,
  60                         "GICv3 system registers enabled, broken firmware!\n");
  61 }
  62 #else
  63 #define gic_check_cpu_features()        do { } while(0)
  64 #endif
  65
  66 union gic_base {
  67         void __iomem *common_base;
  68         void __percpu * __iomem *percpu_base;
  69 };
  70
  71 struct gic_chip_data {
  72         struct irq_chip chip;
  73         union gic_base dist_base;
  74         union gic_base cpu_base;
  75         void __iomem *raw_dist_base;
  76         void __iomem *raw_cpu_base;
  77         u32 percpu_offset;
  78 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  79         u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
  80         u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
  81         u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
  82         u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
  83         u32 __percpu *saved_ppi_enable;
  84         u32 __percpu *saved_ppi_active;
  85         u32 __percpu *saved_ppi_conf;
  86 #endif
  87         struct irq_domain *domain;
  88         unsigned int gic_irqs;
  89 #ifdef CONFIG_GIC_NON_BANKED
  90         void __iomem *(*get_base)(union gic_base *);
  91 #endif
  92 };
  93
  94 #ifdef CONFIG_BL_SWITCHER
  95
  96 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
  97
  98 #define gic_lock_irqsave(f)             \
  99         raw_spin_lock_irqsave(&cpu_map_lock, (f))
 100 #define gic_unlock_irqrestore(f)        \
 101         raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
 102
 103 #define gic_lock()                      raw_spin_lock(&cpu_map_lock)
 104 #define gic_unlock()                    raw_spin_unlock(&cpu_map_lock)
 105
 106 #else
 107
 108 #define gic_lock_irqsave(f)             do { (void)(f); } while(0)
 109 #define gic_unlock_irqrestore(f)        do { (void)(f); } while(0)
 110
 111 #define gic_lock()                      do { } while(0)
 112 #define gic_unlock()                    do { } while(0)
 113
 114 #endif
 115
 116 /*
 117  * The GIC mapping of CPU interfaces does not necessarily match
 118  * the logical CPU numbering.  Let's use a mapping as returned
 119  * by the GIC itself.
 120  */
 121 #define NR_GIC_CPU_IF 8
 122 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 123
 124 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
 125
 126 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 127
 128 static struct gic_kvm_info gic_v2_kvm_info;
 129
 130 #ifdef CONFIG_GIC_NON_BANKED
 131 static void __iomem *gic_get_percpu_base(union gic_base *base)
 132 {
 133         return raw_cpu_read(*base->percpu_base);
 134 }
 135
 136 static void __iomem *gic_get_common_base(union gic_base *base)
 137 {
 138         return base->common_base;
 139 }
 140
 141 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
 142 {
 143         return data->get_base(&data->dist_base);
 144 }
 145
 146 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
 147 {
 148         return data->get_base(&data->cpu_base);
 149 }
 150
 151 static inline void gic_set_base_accessor(struct gic_chip_data *data,
 152                                          void __iomem *(*f)(union gic_base *))
 153 {
 154         data->get_base = f;
 155 }
 156 #else
 157 #define gic_data_dist_base(d)   ((d)->dist_base.common_base)
 158 #define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
 159 #define gic_set_base_accessor(d, f)
 160 #endif
 161
 162 static inline void __iomem *gic_dist_base(struct irq_data *d)
 163 {
 164         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 165         return gic_data_dist_base(gic_data);
 166 }
 167
 168 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 169 {
 170         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 171         return gic_data_cpu_base(gic_data);
 172 }
 173
 174 static inline unsigned int gic_irq(struct irq_data *d)
 175 {
 176         return d->hwirq;
 177 }
 178
 179 static inline bool cascading_gic_irq(struct irq_data *d)
 180 {
 181         void *data = irq_data_get_irq_handler_data(d);
 182
 183         /*
 184          * If handler_data is set, this is a cascading interrupt, and
 185          * it cannot possibly be forwarded.
 186          */
 187         return data != NULL;
 188 }
 189
 190 /*
 191  * Routines to acknowledge, disable and enable interrupts
 192  */
 193 static void gic_poke_irq(struct irq_data *d, u32 offset)
 194 {
 195         u32 mask = 1 << (gic_irq(d) % 32);
 196         writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
 197 }
 198
 199 static int gic_peek_irq(struct irq_data *d, u32 offset)
 200 {
 201         u32 mask = 1 << (gic_irq(d) % 32);
 202         return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
 203 }
 204
 205 static void gic_mask_irq(struct irq_data *d)
 206 {
 207         gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
 208 }
 209
 210 static void gic_eoimode1_mask_irq(struct irq_data *d)
 211 {
 212         gic_mask_irq(d);
 213         /*
 214          * When masking a forwarded interrupt, make sure it is
 215          * deactivated as well.
 216          *
 217          * This ensures that an interrupt that is getting
 218          * disabled/masked will not get "stuck", because there is
 219          * noone to deactivate it (guest is being terminated).
 220          */
 221         if (irqd_is_forwarded_to_vcpu(d))
 222                 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
 223 }
 224
 225 static void gic_unmask_irq(struct irq_data *d)
 226 {
 227         gic_poke_irq(d, GIC_DIST_ENABLE_SET);
 228 }
 229
 230 static void gic_eoi_irq(struct irq_data *d)
 231 {
 232         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 233 }
 234
 235 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 236 {
 237         /* Do not deactivate an IRQ forwarded to a vcpu. */
 238         if (irqd_is_forwarded_to_vcpu(d))
 239                 return;
 240
 241         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
 242 }
 243
 244 static int gic_irq_set_irqchip_state(struct irq_data *d,
 245                                      enum irqchip_irq_state which, bool val)
 246 {
 247         u32 reg;
 248
 249         switch (which) {
 250         case IRQCHIP_STATE_PENDING:
 251                 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
 252                 break;
 253
 254         case IRQCHIP_STATE_ACTIVE:
 255                 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
 256                 break;
 257
 258         case IRQCHIP_STATE_MASKED:
 259                 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
 260                 break;
 261
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         gic_poke_irq(d, reg);
 267         return 0;
 268 }
 269
 270 static int gic_irq_get_irqchip_state(struct irq_data *d,
 271                                       enum irqchip_irq_state which, bool *val)
 272 {
 273         switch (which) {
 274         case IRQCHIP_STATE_PENDING:
 275                 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
 276                 break;
 277
 278         case IRQCHIP_STATE_ACTIVE:
 279                 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
 280                 break;
 281
 282         case IRQCHIP_STATE_MASKED:
 283                 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
 284                 break;
 285
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int gic_set_type(struct irq_data *d, unsigned int type)
 294 {
 295         void __iomem *base = gic_dist_base(d);
 296         unsigned int gicirq = gic_irq(d);
 297
 298         /* Interrupt configuration for SGIs can't be changed */
 299         if (gicirq < 16)
 300                 return -EINVAL;
 301
 302         /* SPIs have restrictions on the supported types */
 303         if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 304                             type != IRQ_TYPE_EDGE_RISING)
 305                 return -EINVAL;
 306
 307         return gic_configure_irq(gicirq, type, base, NULL);
 308 }
 309
 310 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 311 {
 312         /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
 313         if (cascading_gic_irq(d))
 314                 return -EINVAL;
 315
 316         if (vcpu)
 317                 irqd_set_forwarded_to_vcpu(d);
 318         else
 319                 irqd_clr_forwarded_to_vcpu(d);
 320         return 0;
 321 }
 322
 323 #ifdef CONFIG_SMP
 324 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 325                             bool force)
 326 {
 327         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
 328         unsigned int cpu;
 329
 330         if (!force)
 331                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
 332         else
 333                 cpu = cpumask_first(mask_val);
 334
 335         if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
 336                 return -EINVAL;
 337
 338         writeb_relaxed(gic_cpu_map[cpu], reg);
 339         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 340
 341         return IRQ_SET_MASK_OK_DONE;
 342 }
 343 #endif
 344
 345 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 346 {
 347         u32 irqstat, irqnr;
 348         struct gic_chip_data *gic = &gic_data[0];
 349         void __iomem *cpu_base = gic_data_cpu_base(gic);
 350
 351         do {
 352                 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
 353                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 354
 355                 if (likely(irqnr > 15 && irqnr < 1020)) {
 356                         if (static_branch_likely(&supports_deactivate_key))
 357                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 358                         isb();
 359                         handle_domain_irq(gic->domain, irqnr, regs);
 360                         continue;
 361                 }
 362                 if (irqnr < 16) {
 363                         writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 364                         if (static_branch_likely(&supports_deactivate_key))
 365                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
 366 #ifdef CONFIG_SMP
 367                         /*
 368                          * Ensure any shared data written by the CPU sending
 369                          * the IPI is read after we've read the ACK register
 370                          * on the GIC.
 371                          *
 372                          * Pairs with the write barrier in gic_raise_softirq
 373                          */
 374                         smp_rmb();
 375                         handle_IPI(irqnr, regs);
 376 #endif
 377                         continue;
 378                 }
 379                 break;
 380         } while (1);
 381 }
 382
 383 static void gic_handle_cascade_irq(struct irq_desc *desc)
 384 {
 385         struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
 386         struct irq_chip *chip = irq_desc_get_chip(desc);
 387         unsigned int cascade_irq, gic_irq;
 388         unsigned long status;
 389
 390         chained_irq_enter(chip, desc);
 391
 392         status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
 393
 394         gic_irq = (status & GICC_IAR_INT_ID_MASK);
 395         if (gic_irq == GICC_INT_SPURIOUS)
 396                 goto out;
 397
 398         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
 399         if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
 400                 handle_bad_irq(desc);
 401         } else {
 402                 isb();
 403                 generic_handle_irq(cascade_irq);
 404         }
 405
 406  out:
 407         chained_irq_exit(chip, desc);
 408 }
 409
 410 static const struct irq_chip gic_chip = {
 411         .irq_mask               = gic_mask_irq,
 412         .irq_unmask             = gic_unmask_irq,
 413         .irq_eoi                = gic_eoi_irq,
 414         .irq_set_type           = gic_set_type,
 415         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 416         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 417         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 418                                   IRQCHIP_SKIP_SET_WAKE |
 419                                   IRQCHIP_MASK_ON_SUSPEND,
 420 };
 421
 422 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 423 {
 424         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 425         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
 426                                          &gic_data[gic_nr]);
 427 }
 428
 429 static u8 gic_get_cpumask(struct gic_chip_data *gic)
 430 {
 431         void __iomem *base = gic_data_dist_base(gic);
 432         u32 mask, i;
 433
 434         for (i = mask = 0; i < 32; i += 4) {
 435                 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
 436                 mask |= mask >> 16;
 437                 mask |= mask >> 8;
 438                 if (mask)
 439                         break;
 440         }
 441
 442         if (!mask && num_possible_cpus() > 1)
 443                 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 444
 445         return mask;
 446 }
 447
 448 static bool gic_check_gicv2(void __iomem *base)
 449 {
 450         u32 val = readl_relaxed(base + GIC_CPU_IDENT);
 451         return (val & 0xff0fff) == 0x02043B;
 452 }
 453
 454 static void gic_cpu_if_up(struct gic_chip_data *gic)
 455 {
 456         void __iomem *cpu_base = gic_data_cpu_base(gic);
 457         u32 bypass = 0;
 458         u32 mode = 0;
 459         int i;
 460
 461         if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
 462                 mode = GIC_CPU_CTRL_EOImodeNS;
 463
 464         if (gic_check_gicv2(cpu_base))
 465                 for (i = 0; i < 4; i++)
 466                         writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
 467
 468         /*
 469         * Preserve bypass disable bits to be written back later
 470         */
 471         bypass = readl(cpu_base + GIC_CPU_CTRL);
 472         bypass &= GICC_DIS_BYPASS_MASK;
 473
 474         writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
 475 }
 476
 477
 478 static void gic_dist_init(struct gic_chip_data *gic)
 479 {
 480         unsigned int i;
 481         u32 cpumask;
 482         unsigned int gic_irqs = gic->gic_irqs;
 483         void __iomem *base = gic_data_dist_base(gic);
 484
 485         writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
 486
 487         /*
 488          * Set all global interrupts to this CPU only.
 489          */
 490         cpumask = gic_get_cpumask(gic);
 491         cpumask |= cpumask << 8;
 492         cpumask |= cpumask << 16;
 493         for (i = 32; i < gic_irqs; i += 4)
 494                 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 495
 496         gic_dist_config(base, gic_irqs, NULL);
 497
 498         writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
 499 }
 500
 501 static int gic_cpu_init(struct gic_chip_data *gic)
 502 {
 503         void __iomem *dist_base = gic_data_dist_base(gic);
 504         void __iomem *base = gic_data_cpu_base(gic);
 505         unsigned int cpu_mask, cpu = smp_processor_id();
 506         int i;
 507
 508         /*
 509          * Setting up the CPU map is only relevant for the primary GIC
 510          * because any nested/secondary GICs do not directly interface
 511          * with the CPU(s).
 512          */
 513         if (gic == &gic_data[0]) {
 514                 /*
 515                  * Get what the GIC says our CPU mask is.
 516                  */
 517                 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
 518                         return -EINVAL;
 519
 520                 gic_check_cpu_features();
 521                 cpu_mask = gic_get_cpumask(gic);
 522                 gic_cpu_map[cpu] = cpu_mask;
 523
 524                 /*
 525                  * Clear our mask from the other map entries in case they're
 526                  * still undefined.
 527                  */
 528                 for (i = 0; i < NR_GIC_CPU_IF; i++)
 529                         if (i != cpu)
 530                                 gic_cpu_map[i] &= ~cpu_mask;
 531         }
 532
 533         gic_cpu_config(dist_base, NULL);
 534
 535         writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
 536         gic_cpu_if_up(gic);
 537
 538         return 0;
 539 }
 540
 541 int gic_cpu_if_down(unsigned int gic_nr)
 542 {
 543         void __iomem *cpu_base;
 544         u32 val = 0;
 545
 546         if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
 547                 return -EINVAL;
 548
 549         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 550         val = readl(cpu_base + GIC_CPU_CTRL);
 551         val &= ~GICC_ENABLE;
 552         writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
 553
 554         return 0;
 555 }
 556
 557 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
 558 /*
 559  * Saves the GIC distributor registers during suspend or idle.  Must be called
 560  * with interrupts disabled but before powering down the GIC.  After calling
 561  * this function, no interrupts will be delivered by the GIC, and another
 562  * platform-specific wakeup source must be enabled.
 563  */
 564 void gic_dist_save(struct gic_chip_data *gic)
 565 {
 566         unsigned int gic_irqs;
 567         void __iomem *dist_base;
 568         int i;
 569
 570         if (WARN_ON(!gic))
 571                 return;
 572
 573         gic_irqs = gic->gic_irqs;
 574         dist_base = gic_data_dist_base(gic);
 575
 576         if (!dist_base)
 577                 return;
 578
 579         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 580                 gic->saved_spi_conf[i] =
 581                         readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 582
 583         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 584                 gic->saved_spi_target[i] =
 585                         readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 586
 587         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 588                 gic->saved_spi_enable[i] =
 589                         readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 590
 591         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 592                 gic->saved_spi_active[i] =
 593                         readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 594 }
 595
 596 /*
 597  * Restores the GIC distributor registers during resume or when coming out of
 598  * idle.  Must be called before enabling interrupts.  If a level interrupt
 599  * that occured while the GIC was suspended is still present, it will be
 600  * handled normally, but any edge interrupts that occured will not be seen by
 601  * the GIC and need to be handled by the platform-specific wakeup source.
 602  */
 603 void gic_dist_restore(struct gic_chip_data *gic)
 604 {
 605         unsigned int gic_irqs;
 606         unsigned int i;
 607         void __iomem *dist_base;
 608
 609         if (WARN_ON(!gic))
 610                 return;
 611
 612         gic_irqs = gic->gic_irqs;
 613         dist_base = gic_data_dist_base(gic);
 614
 615         if (!dist_base)
 616                 return;
 617
 618         writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 619
 620         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 621                 writel_relaxed(gic->saved_spi_conf[i],
 622                         dist_base + GIC_DIST_CONFIG + i * 4);
 623
 624         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 625                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 626                         dist_base + GIC_DIST_PRI + i * 4);
 627
 628         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 629                 writel_relaxed(gic->saved_spi_target[i],
 630                         dist_base + GIC_DIST_TARGET + i * 4);
 631
 632         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 633                 writel_relaxed(GICD_INT_EN_CLR_X32,
 634                         dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 635                 writel_relaxed(gic->saved_spi_enable[i],
 636                         dist_base + GIC_DIST_ENABLE_SET + i * 4);
 637         }
 638
 639         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 640                 writel_relaxed(GICD_INT_EN_CLR_X32,
 641                         dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 642                 writel_relaxed(gic->saved_spi_active[i],
 643                         dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 644         }
 645
 646         writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
 647 }
 648
 649 void gic_cpu_save(struct gic_chip_data *gic)
 650 {
 651         int i;
 652         u32 *ptr;
 653         void __iomem *dist_base;
 654         void __iomem *cpu_base;
 655
 656         if (WARN_ON(!gic))
 657                 return;
 658
 659         dist_base = gic_data_dist_base(gic);
 660         cpu_base = gic_data_cpu_base(gic);
 661
 662         if (!dist_base || !cpu_base)
 663                 return;
 664
 665         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 666         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 667                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 668
 669         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 670         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 671                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 672
 673         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 674         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 675                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 676
 677 }
 678
 679 void gic_cpu_restore(struct gic_chip_data *gic)
 680 {
 681         int i;
 682         u32 *ptr;
 683         void __iomem *dist_base;
 684         void __iomem *cpu_base;
 685
 686         if (WARN_ON(!gic))
 687                 return;
 688
 689         dist_base = gic_data_dist_base(gic);
 690         cpu_base = gic_data_cpu_base(gic);
 691
 692         if (!dist_base || !cpu_base)
 693                 return;
 694
 695         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 696         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 697                 writel_relaxed(GICD_INT_EN_CLR_X32,
 698                                dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 699                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
 700         }
 701
 702         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 703         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 704                 writel_relaxed(GICD_INT_EN_CLR_X32,
 705                                dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 706                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 707         }
 708
 709         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 710         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 711                 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 712
 713         for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
 714                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 715                                         dist_base + GIC_DIST_PRI + i * 4);
 716
 717         writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
 718         gic_cpu_if_up(gic);
 719 }
 720
 721 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 722 {
 723         int i;
 724
 725         for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 726 #ifdef CONFIG_GIC_NON_BANKED
 727                 /* Skip over unused GICs */
 728                 if (!gic_data[i].get_base)
 729                         continue;
 730 #endif
 731                 switch (cmd) {
 732                 case CPU_PM_ENTER:
 733                         gic_cpu_save(&gic_data[i]);
 734                         break;
 735                 case CPU_PM_ENTER_FAILED:
 736                 case CPU_PM_EXIT:
 737                         gic_cpu_restore(&gic_data[i]);
 738                         break;
 739                 case CPU_CLUSTER_PM_ENTER:
 740                         gic_dist_save(&gic_data[i]);
 741                         break;
 742                 case CPU_CLUSTER_PM_ENTER_FAILED:
 743                 case CPU_CLUSTER_PM_EXIT:
 744                         gic_dist_restore(&gic_data[i]);
 745                         break;
 746                 }
 747         }
 748
 749         return NOTIFY_OK;
 750 }
 751
 752 static struct notifier_block gic_notifier_block = {
 753         .notifier_call = gic_notifier,
 754 };
 755
 756 static int gic_pm_init(struct gic_chip_data *gic)
 757 {
 758         gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 759                 sizeof(u32));
 760         if (WARN_ON(!gic->saved_ppi_enable))
 761                 return -ENOMEM;
 762
 763         gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 764                 sizeof(u32));
 765         if (WARN_ON(!gic->saved_ppi_active))
 766                 goto free_ppi_enable;
 767
 768         gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
 769                 sizeof(u32));
 770         if (WARN_ON(!gic->saved_ppi_conf))
 771                 goto free_ppi_active;
 772
 773         if (gic == &gic_data[0])
 774                 cpu_pm_register_notifier(&gic_notifier_block);
 775
 776         return 0;
 777
 778 free_ppi_active:
 779         free_percpu(gic->saved_ppi_active);
 780 free_ppi_enable:
 781         free_percpu(gic->saved_ppi_enable);
 782
 783         return -ENOMEM;
 784 }
 785 #else
 786 static int gic_pm_init(struct gic_chip_data *gic)
 787 {
 788         return 0;
 789 }
 790 #endif
 791
 792 #ifdef CONFIG_SMP
 793 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 794 {
 795         int cpu;
 796         unsigned long flags, map = 0;
 797
 798         if (unlikely(nr_cpu_ids == 1)) {
 799                 /* Only one CPU? let's do a self-IPI... */
 800                 writel_relaxed(2 << 24 | irq,
 801                                gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 802                 return;
 803         }
 804
 805         gic_lock_irqsave(flags);
 806
 807         /* Convert our logical CPU mask into a physical one. */
 808         for_each_cpu(cpu, mask)
 809                 map |= gic_cpu_map[cpu];
 810
 811         /*
 812          * Ensure that stores to Normal memory are visible to the
 813          * other CPUs before they observe us issuing the IPI.
 814          */
 815         dmb(ishst);
 816
 817         /* this always happens on GIC0 */
 818         writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 819
 820         gic_unlock_irqrestore(flags);
 821 }
 822 #endif
 823
 824 #ifdef CONFIG_BL_SWITCHER
 825 /*
 826  * gic_send_sgi - send a SGI directly to given CPU interface number
 827  *
 828  * cpu_id: the ID for the destination CPU interface
 829  * irq: the IPI number to send a SGI for
 830  */
 831 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 832 {
 833         BUG_ON(cpu_id >= NR_GIC_CPU_IF);
 834         cpu_id = 1 << cpu_id;
 835         /* this always happens on GIC0 */
 836         writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 837 }
 838
 839 /*
 840  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
 841  *
 842  * @cpu: the logical CPU number to get the GIC ID for.
 843  *
 844  * Return the CPU interface ID for the given logical CPU number,
 845  * or -1 if the CPU number is too large or the interface ID is
 846  * unknown (more than one bit set).
 847  */
 848 int gic_get_cpu_id(unsigned int cpu)
 849 {
 850         unsigned int cpu_bit;
 851
 852         if (cpu >= NR_GIC_CPU_IF)
 853                 return -1;
 854         cpu_bit = gic_cpu_map[cpu];
 855         if (cpu_bit & (cpu_bit - 1))
 856                 return -1;
 857         return __ffs(cpu_bit);
 858 }
 859
 860 /*
 861  * gic_migrate_target - migrate IRQs to another CPU interface
 862  *
 863  * @new_cpu_id: the CPU target ID to migrate IRQs to
 864  *
 865  * Migrate all peripheral interrupts with a target matching the current CPU
 866  * to the interface corresponding to @new_cpu_id.  The CPU interface mapping
 867  * is also updated.  Targets to other CPU interfaces are unchanged.
 868  * This must be called with IRQs locally disabled.
 869  */
 870 void gic_migrate_target(unsigned int new_cpu_id)
 871 {
 872         unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
 873         void __iomem *dist_base;
 874         int i, ror_val, cpu = smp_processor_id();
 875         u32 val, cur_target_mask, active_mask;
 876
 877         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 878
 879         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 880         if (!dist_base)
 881                 return;
 882         gic_irqs = gic_data[gic_nr].gic_irqs;
 883
 884         cur_cpu_id = __ffs(gic_cpu_map[cpu]);
 885         cur_target_mask = 0x01010101 << cur_cpu_id;
 886         ror_val = (cur_cpu_id - new_cpu_id) & 31;
 887
 888         gic_lock();
 889
 890         /* Update the target interface for this logical CPU */
 891         gic_cpu_map[cpu] = 1 << new_cpu_id;
 892
 893         /*
 894          * Find all the peripheral interrupts targetting the current
 895          * CPU interface and migrate them to the new CPU interface.
 896          * We skip DIST_TARGET 0 to 7 as they are read-only.
 897          */
 898         for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
 899                 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 900                 active_mask = val & cur_target_mask;
 901                 if (active_mask) {
 902                         val &= ~active_mask;
 903                         val |= ror32(active_mask, ror_val);
 904                         writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
 905                 }
 906         }
 907
 908         gic_unlock();
 909
 910         /*
 911          * Now let's migrate and clear any potential SGIs that might be
 912          * pending for us (cur_cpu_id).  Since GIC_DIST_SGI_PENDING_SET
 913          * is a banked register, we can only forward the SGI using
 914          * GIC_DIST_SOFTINT.  The original SGI source is lost but Linux
 915          * doesn't use that information anyway.
 916          *
 917          * For the same reason we do not adjust SGI source information
 918          * for previously sent SGIs by us to other CPUs either.
 919          */
 920         for (i = 0; i < 16; i += 4) {
 921                 int j;
 922                 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
 923                 if (!val)
 924                         continue;
 925                 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
 926                 for (j = i; j < i + 4; j++) {
 927                         if (val & 0xff)
 928                                 writel_relaxed((1 << (new_cpu_id + 16)) | j,
 929                                                 dist_base + GIC_DIST_SOFTINT);
 930                         val >>= 8;
 931                 }
 932         }
 933 }
 934
 935 /*
 936  * gic_get_sgir_physaddr - get the physical address for the SGI register
 937  *
 938  * REturn the physical address of the SGI register to be used
 939  * by some early assembly code when the kernel is not yet available.
 940  */
 941 static unsigned long gic_dist_physaddr;
 942
 943 unsigned long gic_get_sgir_physaddr(void)
 944 {
 945         if (!gic_dist_physaddr)
 946                 return 0;
 947         return gic_dist_physaddr + GIC_DIST_SOFTINT;
 948 }
 949
 950 static void __init gic_init_physaddr(struct device_node *node)
 951 {
 952         struct resource res;
 953         if (of_address_to_resource(node, 0, &res) == 0) {
 954                 gic_dist_physaddr = res.start;
 955                 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
 956         }
 957 }
 958
 959 #else
 960 #define gic_init_physaddr(node)  do { } while (0)
 961 #endif
 962
 963 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 964                                 irq_hw_number_t hw)
 965 {
 966         struct gic_chip_data *gic = d->host_data;
 967
 968         if (hw < 32) {
 969                 irq_set_percpu_devid(irq);
 970                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 971                                     handle_percpu_devid_irq, NULL, NULL);
 972                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 973         } else {
 974                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 975                                     handle_fasteoi_irq, NULL, NULL);
 976                 irq_set_probe(irq);
 977                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
 978         }
 979         return 0;
 980 }
 981
 982 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 983 {
 984 }
 985
 986 static int gic_irq_domain_translate(struct irq_domain *d,
 987                                     struct irq_fwspec *fwspec,
 988                                     unsigned long *hwirq,
 989                                     unsigned int *type)
 990 {
 991         if (is_of_node(fwspec->fwnode)) {
 992                 if (fwspec->param_count < 3)
 993                         return -EINVAL;
 994
 995                 /* Get the interrupt number and add 16 to skip over SGIs */
 996                 *hwirq = fwspec->param[1] + 16;
 997
 998                 /*
 999                  * For SPIs, we need to add 16 more to get the GIC irq
1000                  * ID number
1001                  */
1002                 if (!fwspec->param[0])
1003                         *hwirq += 16;
1004
1005                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1006
1007                 /* Make it clear that broken DTs are... broken */
1008                 WARN_ON(*type == IRQ_TYPE_NONE);
1009                 return 0;
1010         }
1011
1012         if (is_fwnode_irqchip(fwspec->fwnode)) {
1013                 if(fwspec->param_count != 2)
1014                         return -EINVAL;
1015
1016                 *hwirq = fwspec->param[0];
1017                 *type = fwspec->param[1];
1018
1019                 WARN_ON(*type == IRQ_TYPE_NONE);
1020                 return 0;
1021         }
1022
1023         return -EINVAL;
1024 }
1025
1026 static int gic_starting_cpu(unsigned int cpu)
1027 {
1028         gic_cpu_init(&gic_data[0]);
1029         return 0;
1030 }
1031
1032 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1033                                 unsigned int nr_irqs, void *arg)
1034 {
1035         int i, ret;
1036         irq_hw_number_t hwirq;
1037         unsigned int type = IRQ_TYPE_NONE;
1038         struct irq_fwspec *fwspec = arg;
1039
1040         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1041         if (ret)
1042                 return ret;
1043
1044         for (i = 0; i < nr_irqs; i++) {
1045                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1046                 if (ret)
1047                         return ret;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1054         .translate = gic_irq_domain_translate,
1055         .alloc = gic_irq_domain_alloc,
1056         .free = irq_domain_free_irqs_top,
1057 };
1058
1059 static const struct irq_domain_ops gic_irq_domain_ops = {
1060         .map = gic_irq_domain_map,
1061         .unmap = gic_irq_domain_unmap,
1062 };
1063
1064 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1065                           const char *name, bool use_eoimode1)
1066 {
1067         /* Initialize irq_chip */
1068         gic->chip = gic_chip;
1069         gic->chip.name = name;
1070         gic->chip.parent_device = dev;
1071
1072         if (use_eoimode1) {
1073                 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1074                 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1075                 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1076         }
1077
1078 #ifdef CONFIG_SMP
1079         if (gic == &gic_data[0])
1080                 gic->chip.irq_set_affinity = gic_set_affinity;
1081 #endif
1082 }
1083
1084 static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1085                           struct fwnode_handle *handle)
1086 {
1087         irq_hw_number_t hwirq_base;
1088         int gic_irqs, irq_base, ret;
1089
1090         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1091                 /* Frankein-GIC without banked registers... */
1092                 unsigned int cpu;
1093
1094                 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1095                 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1096                 if (WARN_ON(!gic->dist_base.percpu_base ||
1097                             !gic->cpu_base.percpu_base)) {
1098                         ret = -ENOMEM;
1099                         goto error;
1100                 }
1101
1102                 for_each_possible_cpu(cpu) {
1103                         u32 mpidr = cpu_logical_map(cpu);
1104                         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1105                         unsigned long offset = gic->percpu_offset * core_id;
1106                         *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1107                                 gic->raw_dist_base + offset;
1108                         *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1109                                 gic->raw_cpu_base + offset;
1110                 }
1111
1112                 gic_set_base_accessor(gic, gic_get_percpu_base);
1113         } else {
1114                 /* Normal, sane GIC... */
1115                 WARN(gic->percpu_offset,
1116                      "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1117                      gic->percpu_offset);
1118                 gic->dist_base.common_base = gic->raw_dist_base;
1119                 gic->cpu_base.common_base = gic->raw_cpu_base;
1120                 gic_set_base_accessor(gic, gic_get_common_base);
1121         }
1122
1123         /*
1124          * Find out how many interrupts are supported.
1125          * The GIC only supports up to 1020 interrupt sources.
1126          */
1127         gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1128         gic_irqs = (gic_irqs + 1) * 32;
1129         if (gic_irqs > 1020)
1130                 gic_irqs = 1020;
1131         gic->gic_irqs = gic_irqs;
1132
1133         if (handle) {           /* DT/ACPI */
1134                 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1135                                                        &gic_irq_domain_hierarchy_ops,
1136                                                        gic);
1137         } else {                /* Legacy support */
1138                 /*
1139                  * For primary GICs, skip over SGIs.
1140                  * For secondary GICs, skip over PPIs, too.
1141                  */
1142                 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1143                         hwirq_base = 16;
1144                         if (irq_start != -1)
1145                                 irq_start = (irq_start & ~31) + 16;
1146                 } else {
1147                         hwirq_base = 32;
1148                 }
1149
1150                 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1151
1152                 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1153                                            numa_node_id());
1154                 if (irq_base < 0) {
1155                         WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1156                              irq_start);
1157                         irq_base = irq_start;
1158                 }
1159
1160                 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1161                                         hwirq_base, &gic_irq_domain_ops, gic);
1162         }
1163
1164         if (WARN_ON(!gic->domain)) {
1165                 ret = -ENODEV;
1166                 goto error;
1167         }
1168
1169         gic_dist_init(gic);
1170         ret = gic_cpu_init(gic);
1171         if (ret)
1172                 goto error;
1173
1174         ret = gic_pm_init(gic);
1175         if (ret)
1176                 goto error;
1177
1178         return 0;
1179
1180 error:
1181         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1182                 free_percpu(gic->dist_base.percpu_base);
1183                 free_percpu(gic->cpu_base.percpu_base);
1184         }
1185
1186         return ret;
1187 }
1188
1189 static int __init __gic_init_bases(struct gic_chip_data *gic,
1190                                    int irq_start,
1191                                    struct fwnode_handle *handle)
1192 {
1193         char *name;
1194         int i, ret;
1195
1196         if (WARN_ON(!gic || gic->domain))
1197                 return -EINVAL;
1198
1199         if (gic == &gic_data[0]) {
1200                 /*
1201                  * Initialize the CPU interface map to all CPUs.
1202                  * It will be refined as each CPU probes its ID.
1203                  * This is only necessary for the primary GIC.
1204                  */
1205                 for (i = 0; i < NR_GIC_CPU_IF; i++)
1206                         gic_cpu_map[i] = 0xff;
1207 #ifdef CONFIG_SMP
1208                 set_smp_cross_call(gic_raise_softirq);
1209 #endif
1210                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1211                                           "irqchip/arm/gic:starting",
1212                                           gic_starting_cpu, NULL);
1213                 set_handle_irq(gic_handle_irq);
1214                 if (static_branch_likely(&supports_deactivate_key))
1215                         pr_info("GIC: Using split EOI/Deactivate mode\n");
1216         }
1217
1218         if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1219                 name = kasprintf(GFP_KERNEL, "GICv2");
1220                 gic_init_chip(gic, NULL, name, true);
1221         } else {
1222                 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1223                 gic_init_chip(gic, NULL, name, false);
1224         }
1225
1226         ret = gic_init_bases(gic, irq_start, handle);
1227         if (ret)
1228                 kfree(name);
1229
1230         return ret;
1231 }
1232
1233 void __init gic_init(unsigned int gic_nr, int irq_start,
1234                      void __iomem *dist_base, void __iomem *cpu_base)
1235 {
1236         struct gic_chip_data *gic;
1237
1238         if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1239                 return;
1240
1241         /*
1242          * Non-DT/ACPI systems won't run a hypervisor, so let's not
1243          * bother with these...
1244          */
1245         static_branch_disable(&supports_deactivate_key);
1246
1247         gic = &gic_data[gic_nr];
1248         gic->raw_dist_base = dist_base;
1249         gic->raw_cpu_base = cpu_base;
1250
1251         __gic_init_bases(gic, irq_start, NULL);
1252 }
1253
1254 static void gic_teardown(struct gic_chip_data *gic)
1255 {
1256         if (WARN_ON(!gic))
1257                 return;
1258
1259         if (gic->raw_dist_base)
1260                 iounmap(gic->raw_dist_base);
1261         if (gic->raw_cpu_base)
1262                 iounmap(gic->raw_cpu_base);
1263 }
1264
1265 #ifdef CONFIG_OF
1266 static int gic_cnt __initdata;
1267 static bool gicv2_force_probe;
1268
1269 static int __init gicv2_force_probe_cfg(char *buf)
1270 {
1271         return strtobool(buf, &gicv2_force_probe);
1272 }
1273 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1274
1275 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1276 {
1277         struct resource cpuif_res;
1278
1279         of_address_to_resource(node, 1, &cpuif_res);
1280
1281         if (!is_hyp_mode_available())
1282                 return false;
1283         if (resource_size(&cpuif_res) < SZ_8K) {
1284                 void __iomem *alt;
1285                 /*
1286                  * Check for a stupid firmware that only exposes the
1287                  * first page of a GICv2.
1288                  */
1289                 if (!gic_check_gicv2(*base))
1290                         return false;
1291
1292                 if (!gicv2_force_probe) {
1293                         pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1294                         return false;
1295                 }
1296
1297                 alt = ioremap(cpuif_res.start, SZ_8K);
1298                 if (!alt)
1299                         return false;
1300                 if (!gic_check_gicv2(alt + SZ_4K)) {
1301                         /*
1302                          * The first page was that of a GICv2, and
1303                          * the second was *something*. Let's trust it
1304                          * to be a GICv2, and update the mapping.
1305                          */
1306                         pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1307                                 &cpuif_res.start);
1308                         iounmap(*base);
1309                         *base = alt;
1310                         return true;
1311                 }
1312
1313                 /*
1314                  * We detected *two* initial GICv2 pages in a
1315                  * row. Could be a GICv2 aliased over two 64kB
1316                  * pages. Update the resource, map the iospace, and
1317                  * pray.
1318                  */
1319                 iounmap(alt);
1320                 alt = ioremap(cpuif_res.start, SZ_128K);
1321                 if (!alt)
1322                         return false;
1323                 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1324                         &cpuif_res.start);
1325                 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1326                 iounmap(*base);
1327                 *base = alt;
1328         }
1329         if (resource_size(&cpuif_res) == SZ_128K) {
1330                 /*
1331                  * Verify that we have the first 4kB of a GICv2
1332                  * aliased over the first 64kB by checking the
1333                  * GICC_IIDR register on both ends.
1334                  */
1335                 if (!gic_check_gicv2(*base) ||
1336                     !gic_check_gicv2(*base + 0xf000))
1337                         return false;
1338
1339                 /*
1340                  * Move the base up by 60kB, so that we have a 8kB
1341                  * contiguous region, which allows us to use GICC_DIR
1342                  * at its normal offset. Please pass me that bucket.
1343                  */
1344                 *base += 0xf000;
1345                 cpuif_res.start += 0xf000;
1346                 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1347                         &cpuif_res.start);
1348         }
1349
1350         return true;
1351 }
1352
1353 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1354 {
1355         if (!gic || !node)
1356                 return -EINVAL;
1357
1358         gic->raw_dist_base = of_iomap(node, 0);
1359         if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1360                 goto error;
1361
1362         gic->raw_cpu_base = of_iomap(node, 1);
1363         if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1364                 goto error;
1365
1366         if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1367                 gic->percpu_offset = 0;
1368
1369         return 0;
1370
1371 error:
1372         gic_teardown(gic);
1373
1374         return -ENOMEM;
1375 }
1376
1377 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1378 {
1379         int ret;
1380
1381         if (!dev || !dev->of_node || !gic || !irq)
1382                 return -EINVAL;
1383
1384         *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1385         if (!*gic)
1386                 return -ENOMEM;
1387
1388         gic_init_chip(*gic, dev, dev->of_node->name, false);
1389
1390         ret = gic_of_setup(*gic, dev->of_node);
1391         if (ret)
1392                 return ret;
1393
1394         ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1395         if (ret) {
1396                 gic_teardown(*gic);
1397                 return ret;
1398         }
1399
1400         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1401
1402         return 0;
1403 }
1404
1405 static void __init gic_of_setup_kvm_info(struct device_node *node)
1406 {
1407         int ret;
1408         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1409         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1410
1411         gic_v2_kvm_info.type = GIC_V2;
1412
1413         gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1414         if (!gic_v2_kvm_info.maint_irq)
1415                 return;
1416
1417         ret = of_address_to_resource(node, 2, vctrl_res);
1418         if (ret)
1419                 return;
1420
1421         ret = of_address_to_resource(node, 3, vcpu_res);
1422         if (ret)
1423                 return;
1424
1425         if (static_branch_likely(&supports_deactivate_key))
1426                 gic_set_kvm_info(&gic_v2_kvm_info);
1427 }
1428
1429 int __init
1430 gic_of_init(struct device_node *node, struct device_node *parent)
1431 {
1432         struct gic_chip_data *gic;
1433         int irq, ret;
1434
1435         if (WARN_ON(!node))
1436                 return -ENODEV;
1437
1438         if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1439                 return -EINVAL;
1440
1441         gic = &gic_data[gic_cnt];
1442
1443         ret = gic_of_setup(gic, node);
1444         if (ret)
1445                 return ret;
1446
1447         /*
1448          * Disable split EOI/Deactivate if either HYP is not available
1449          * or the CPU interface is too small.
1450          */
1451         if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1452                 static_branch_disable(&supports_deactivate_key);
1453
1454         ret = __gic_init_bases(gic, -1, &node->fwnode);
1455         if (ret) {
1456                 gic_teardown(gic);
1457                 return ret;
1458         }
1459
1460         if (!gic_cnt) {
1461                 gic_init_physaddr(node);
1462                 gic_of_setup_kvm_info(node);
1463         }
1464
1465         if (parent) {
1466                 irq = irq_of_parse_and_map(node, 0);
1467                 gic_cascade_irq(gic_cnt, irq);
1468         }
1469
1470         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1471                 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1472
1473         gic_cnt++;
1474         return 0;
1475 }
1476 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1477 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1478 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1479 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1480 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1481 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1482 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1483 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1484 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1485 #else
1486 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1487 {
1488         return -ENOTSUPP;
1489 }
1490 #endif
1491
1492 #ifdef CONFIG_ACPI
1493 static struct
1494 {
1495         phys_addr_t cpu_phys_base;
1496         u32 maint_irq;
1497         int maint_irq_mode;
1498         phys_addr_t vctrl_base;
1499         phys_addr_t vcpu_base;
1500 } acpi_data __initdata;
1501
1502 static int __init
1503 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1504                         const unsigned long end)
1505 {
1506         struct acpi_madt_generic_interrupt *processor;
1507         phys_addr_t gic_cpu_base;
1508         static int cpu_base_assigned;
1509
1510         processor = (struct acpi_madt_generic_interrupt *)header;
1511
1512         if (BAD_MADT_GICC_ENTRY(processor, end))
1513                 return -EINVAL;
1514
1515         /*
1516          * There is no support for non-banked GICv1/2 register in ACPI spec.
1517          * All CPU interface addresses have to be the same.
1518          */
1519         gic_cpu_base = processor->base_address;
1520         if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1521                 return -EINVAL;
1522
1523         acpi_data.cpu_phys_base = gic_cpu_base;
1524         acpi_data.maint_irq = processor->vgic_interrupt;
1525         acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1526                                     ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1527         acpi_data.vctrl_base = processor->gich_base_address;
1528         acpi_data.vcpu_base = processor->gicv_base_address;
1529
1530         cpu_base_assigned = 1;
1531         return 0;
1532 }
1533
1534 /* The things you have to do to just *count* something... */
1535 static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1536                                   const unsigned long end)
1537 {
1538         return 0;
1539 }
1540
1541 static bool __init acpi_gic_redist_is_present(void)
1542 {
1543         return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1544                                      acpi_dummy_func, 0) > 0;
1545 }
1546
1547 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1548                                      struct acpi_probe_entry *ape)
1549 {
1550         struct acpi_madt_generic_distributor *dist;
1551         dist = (struct acpi_madt_generic_distributor *)header;
1552
1553         return (dist->version == ape->driver_data &&
1554                 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1555                  !acpi_gic_redist_is_present()));
1556 }
1557
1558 #define ACPI_GICV2_DIST_MEM_SIZE        (SZ_4K)
1559 #define ACPI_GIC_CPU_IF_MEM_SIZE        (SZ_8K)
1560 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1561 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1562
1563 static void __init gic_acpi_setup_kvm_info(void)
1564 {
1565         int irq;
1566         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1567         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1568
1569         gic_v2_kvm_info.type = GIC_V2;
1570
1571         if (!acpi_data.vctrl_base)
1572                 return;
1573
1574         vctrl_res->flags = IORESOURCE_MEM;
1575         vctrl_res->start = acpi_data.vctrl_base;
1576         vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1577
1578         if (!acpi_data.vcpu_base)
1579                 return;
1580
1581         vcpu_res->flags = IORESOURCE_MEM;
1582         vcpu_res->start = acpi_data.vcpu_base;
1583         vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1584
1585         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1586                                 acpi_data.maint_irq_mode,
1587                                 ACPI_ACTIVE_HIGH);
1588         if (irq <= 0)
1589                 return;
1590
1591         gic_v2_kvm_info.maint_irq = irq;
1592
1593         gic_set_kvm_info(&gic_v2_kvm_info);
1594 }
1595
1596 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1597                                    const unsigned long end)
1598 {
1599         struct acpi_madt_generic_distributor *dist;
1600         struct fwnode_handle *domain_handle;
1601         struct gic_chip_data *gic = &gic_data[0];
1602         int count, ret;
1603
1604         /* Collect CPU base addresses */
1605         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1606                                       gic_acpi_parse_madt_cpu, 0);
1607         if (count <= 0) {
1608                 pr_err("No valid GICC entries exist\n");
1609                 return -EINVAL;
1610         }
1611
1612         gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1613         if (!gic->raw_cpu_base) {
1614                 pr_err("Unable to map GICC registers\n");
1615                 return -ENOMEM;
1616         }
1617
1618         dist = (struct acpi_madt_generic_distributor *)header;
1619         gic->raw_dist_base = ioremap(dist->base_address,
1620                                      ACPI_GICV2_DIST_MEM_SIZE);
1621         if (!gic->raw_dist_base) {
1622                 pr_err("Unable to map GICD registers\n");
1623                 gic_teardown(gic);
1624                 return -ENOMEM;
1625         }
1626
1627         /*
1628          * Disable split EOI/Deactivate if HYP is not available. ACPI
1629          * guarantees that we'll always have a GICv2, so the CPU
1630          * interface will always be the right size.
1631          */
1632         if (!is_hyp_mode_available())
1633                 static_branch_disable(&supports_deactivate_key);
1634
1635         /*
1636          * Initialize GIC instance zero (no multi-GIC support).
1637          */
1638         domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1639         if (!domain_handle) {
1640                 pr_err("Unable to allocate domain handle\n");
1641                 gic_teardown(gic);
1642                 return -ENOMEM;
1643         }
1644
1645         ret = __gic_init_bases(gic, -1, domain_handle);
1646         if (ret) {
1647                 pr_err("Failed to initialise GIC\n");
1648                 irq_domain_free_fwnode(domain_handle);
1649                 gic_teardown(gic);
1650                 return ret;
1651         }
1652
1653         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1654
1655         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1656                 gicv2m_init(NULL, gic_data[0].domain);
1657
1658         if (static_branch_likely(&supports_deactivate_key))
1659                 gic_acpi_setup_kvm_info();
1660
1661         return 0;
1662 }
1663 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1664                      gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1665                      gic_v2_acpi_init);
1666 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1667                      gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1668                      gic_v2_acpi_init);
1669 #endif