drivers/irqchip/irq-gic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   4  *
   5  * Interrupt architecture for the GIC:
   6  *
   7  * o There is one Interrupt Distributor, which receives interrupts
   8  *   from system devices and sends them to the Interrupt Controllers.
   9  *
  10  * o There is one CPU Interface per CPU, which sends interrupts sent
  11  *   by the Distributor, and interrupts generated locally, to the
  12  *   associated CPU. The base address of the CPU interface is usually
  13  *   aliased so that the same address points to different chips depending
  14  *   on the CPU it is accessed from.
  15  *
  16  * Note that IRQs 0-31 are special - they are local to each CPU.
  17  * As such, the enable set/clear, pending set/clear and active bit
  18  * registers are banked per-cpu for these sources.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/module.h>
  24 #include <linux/list.h>
  25 #include <linux/smp.h>
  26 #include <linux/cpu.h>
  27 #include <linux/cpu_pm.h>
  28 #include <linux/cpumask.h>
  29 #include <linux/io.h>
  30 #include <linux/of.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/acpi.h>
  34 #include <linux/irqdomain.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/percpu.h>
  37 #include <linux/slab.h>
  38 #include <linux/irqchip.h>
  39 #include <linux/irqchip/chained_irq.h>
  40 #include <linux/irqchip/arm-gic.h>
  41
  42 #include <asm/cputype.h>
  43 #include <asm/irq.h>
  44 #include <asm/exception.h>
  45 #include <asm/smp_plat.h>
  46 #include <asm/virt.h>
  47
  48 #include "irq-gic-common.h"
  49
  50 #ifdef CONFIG_ARM64
  51 #include <asm/cpufeature.h>
  52
  53 static void gic_check_cpu_features(void)
  54 {
  55         WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
  56                         TAINT_CPU_OUT_OF_SPEC,
  57                         "GICv3 system registers enabled, broken firmware!\n");
  58 }
  59 #else
  60 #define gic_check_cpu_features()        do { } while(0)
  61 #endif
  62
  63 union gic_base {
  64         void __iomem *common_base;
  65         void __percpu * __iomem *percpu_base;
  66 };
  67
  68 struct gic_chip_data {
  69         struct irq_chip chip;
  70         union gic_base dist_base;
  71         union gic_base cpu_base;
  72         void __iomem *raw_dist_base;
  73         void __iomem *raw_cpu_base;
  74         u32 percpu_offset;
  75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  76         u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
  77         u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
  78         u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
  79         u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
  80         u32 __percpu *saved_ppi_enable;
  81         u32 __percpu *saved_ppi_active;
  82         u32 __percpu *saved_ppi_conf;
  83 #endif
  84         struct irq_domain *domain;
  85         unsigned int gic_irqs;
  86 };
  87
  88 #ifdef CONFIG_BL_SWITCHER
  89
  90 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
  91
  92 #define gic_lock_irqsave(f)             \
  93         raw_spin_lock_irqsave(&cpu_map_lock, (f))
  94 #define gic_unlock_irqrestore(f)        \
  95         raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
  96
  97 #define gic_lock()                      raw_spin_lock(&cpu_map_lock)
  98 #define gic_unlock()                    raw_spin_unlock(&cpu_map_lock)
  99
 100 #else
 101
 102 #define gic_lock_irqsave(f)             do { (void)(f); } while(0)
 103 #define gic_unlock_irqrestore(f)        do { (void)(f); } while(0)
 104
 105 #define gic_lock()                      do { } while(0)
 106 #define gic_unlock()                    do { } while(0)
 107
 108 #endif
 109
 110 static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
 111
 112 /*
 113  * The GIC mapping of CPU interfaces does not necessarily match
 114  * the logical CPU numbering.  Let's use a mapping as returned
 115  * by the GIC itself.
 116  */
 117 #define NR_GIC_CPU_IF 8
 118 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 119
 120 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
 121
 122 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 123
 124 static struct gic_kvm_info gic_v2_kvm_info;
 125
 126 static DEFINE_PER_CPU(u32, sgi_intid);
 127
 128 #ifdef CONFIG_GIC_NON_BANKED
 129 static DEFINE_STATIC_KEY_FALSE(frankengic_key);
 130
 131 static void enable_frankengic(void)
 132 {
 133         static_branch_enable(&frankengic_key);
 134 }
 135
 136 static inline void __iomem *__get_base(union gic_base *base)
 137 {
 138         if (static_branch_unlikely(&frankengic_key))
 139                 return raw_cpu_read(*base->percpu_base);
 140
 141         return base->common_base;
 142 }
 143
 144 #define gic_data_dist_base(d)   __get_base(&(d)->dist_base)
 145 #define gic_data_cpu_base(d)    __get_base(&(d)->cpu_base)
 146 #else
 147 #define gic_data_dist_base(d)   ((d)->dist_base.common_base)
 148 #define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
 149 #define enable_frankengic()     do { } while(0)
 150 #endif
 151
 152 static inline void __iomem *gic_dist_base(struct irq_data *d)
 153 {
 154         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 155         return gic_data_dist_base(gic_data);
 156 }
 157
 158 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 159 {
 160         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 161         return gic_data_cpu_base(gic_data);
 162 }
 163
 164 static inline unsigned int gic_irq(struct irq_data *d)
 165 {
 166         return d->hwirq;
 167 }
 168
 169 static inline bool cascading_gic_irq(struct irq_data *d)
 170 {
 171         void *data = irq_data_get_irq_handler_data(d);
 172
 173         /*
 174          * If handler_data is set, this is a cascading interrupt, and
 175          * it cannot possibly be forwarded.
 176          */
 177         return data != NULL;
 178 }
 179
 180 /*
 181  * Routines to acknowledge, disable and enable interrupts
 182  */
 183 static void gic_poke_irq(struct irq_data *d, u32 offset)
 184 {
 185         u32 mask = 1 << (gic_irq(d) % 32);
 186         writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
 187 }
 188
 189 static int gic_peek_irq(struct irq_data *d, u32 offset)
 190 {
 191         u32 mask = 1 << (gic_irq(d) % 32);
 192         return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
 193 }
 194
 195 static void gic_mask_irq(struct irq_data *d)
 196 {
 197         gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
 198 }
 199
 200 static void gic_eoimode1_mask_irq(struct irq_data *d)
 201 {
 202         gic_mask_irq(d);
 203         /*
 204          * When masking a forwarded interrupt, make sure it is
 205          * deactivated as well.
 206          *
 207          * This ensures that an interrupt that is getting
 208          * disabled/masked will not get "stuck", because there is
 209          * noone to deactivate it (guest is being terminated).
 210          */
 211         if (irqd_is_forwarded_to_vcpu(d))
 212                 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
 213 }
 214
 215 static void gic_unmask_irq(struct irq_data *d)
 216 {
 217         gic_poke_irq(d, GIC_DIST_ENABLE_SET);
 218 }
 219
 220 static void gic_eoi_irq(struct irq_data *d)
 221 {
 222         u32 hwirq = gic_irq(d);
 223
 224         if (hwirq < 16)
 225                 hwirq = this_cpu_read(sgi_intid);
 226
 227         writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
 228 }
 229
 230 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 231 {
 232         u32 hwirq = gic_irq(d);
 233
 234         /* Do not deactivate an IRQ forwarded to a vcpu. */
 235         if (irqd_is_forwarded_to_vcpu(d))
 236                 return;
 237
 238         if (hwirq < 16)
 239                 hwirq = this_cpu_read(sgi_intid);
 240
 241         writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
 242 }
 243
 244 static int gic_irq_set_irqchip_state(struct irq_data *d,
 245                                      enum irqchip_irq_state which, bool val)
 246 {
 247         u32 reg;
 248
 249         switch (which) {
 250         case IRQCHIP_STATE_PENDING:
 251                 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
 252                 break;
 253
 254         case IRQCHIP_STATE_ACTIVE:
 255                 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
 256                 break;
 257
 258         case IRQCHIP_STATE_MASKED:
 259                 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
 260                 break;
 261
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         gic_poke_irq(d, reg);
 267         return 0;
 268 }
 269
 270 static int gic_irq_get_irqchip_state(struct irq_data *d,
 271                                       enum irqchip_irq_state which, bool *val)
 272 {
 273         switch (which) {
 274         case IRQCHIP_STATE_PENDING:
 275                 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
 276                 break;
 277
 278         case IRQCHIP_STATE_ACTIVE:
 279                 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
 280                 break;
 281
 282         case IRQCHIP_STATE_MASKED:
 283                 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
 284                 break;
 285
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int gic_set_type(struct irq_data *d, unsigned int type)
 294 {
 295         void __iomem *base = gic_dist_base(d);
 296         unsigned int gicirq = gic_irq(d);
 297         int ret;
 298
 299         /* Interrupt configuration for SGIs can't be changed */
 300         if (gicirq < 16)
 301                 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
 302
 303         /* SPIs have restrictions on the supported types */
 304         if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 305                             type != IRQ_TYPE_EDGE_RISING)
 306                 return -EINVAL;
 307
 308         ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
 309         if (ret && gicirq < 32) {
 310                 /* Misconfigured PPIs are usually not fatal */
 311                 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
 312                 ret = 0;
 313         }
 314
 315         return ret;
 316 }
 317
 318 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 319 {
 320         /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
 321         if (cascading_gic_irq(d) || gic_irq(d) < 16)
 322                 return -EINVAL;
 323
 324         if (vcpu)
 325                 irqd_set_forwarded_to_vcpu(d);
 326         else
 327                 irqd_clr_forwarded_to_vcpu(d);
 328         return 0;
 329 }
 330
 331 static int gic_retrigger(struct irq_data *data)
 332 {
 333         return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
 334 }
 335
 336 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 337 {
 338         u32 irqstat, irqnr;
 339         struct gic_chip_data *gic = &gic_data[0];
 340         void __iomem *cpu_base = gic_data_cpu_base(gic);
 341
 342         do {
 343                 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
 344                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 345
 346                 if (unlikely(irqnr >= 1020))
 347                         break;
 348
 349                 if (static_branch_likely(&supports_deactivate_key))
 350                         writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 351                 isb();
 352
 353                 /*
 354                  * Ensure any shared data written by the CPU sending the IPI
 355                  * is read after we've read the ACK register on the GIC.
 356                  *
 357                  * Pairs with the write barrier in gic_ipi_send_mask
 358                  */
 359                 if (irqnr <= 15) {
 360                         smp_rmb();
 361
 362                         /*
 363                          * The GIC encodes the source CPU in GICC_IAR,
 364                          * leading to the deactivation to fail if not
 365                          * written back as is to GICC_EOI.  Stash the INTID
 366                          * away for gic_eoi_irq() to write back.  This only
 367                          * works because we don't nest SGIs...
 368                          */
 369                         this_cpu_write(sgi_intid, irqstat);
 370                 }
 371
 372                 handle_domain_irq(gic->domain, irqnr, regs);
 373         } while (1);
 374 }
 375
 376 static void gic_handle_cascade_irq(struct irq_desc *desc)
 377 {
 378         struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
 379         struct irq_chip *chip = irq_desc_get_chip(desc);
 380         unsigned int cascade_irq, gic_irq;
 381         unsigned long status;
 382
 383         chained_irq_enter(chip, desc);
 384
 385         status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
 386
 387         gic_irq = (status & GICC_IAR_INT_ID_MASK);
 388         if (gic_irq == GICC_INT_SPURIOUS)
 389                 goto out;
 390
 391         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
 392         if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
 393                 handle_bad_irq(desc);
 394         } else {
 395                 isb();
 396                 generic_handle_irq(cascade_irq);
 397         }
 398
 399  out:
 400         chained_irq_exit(chip, desc);
 401 }
 402
 403 static const struct irq_chip gic_chip = {
 404         .irq_mask               = gic_mask_irq,
 405         .irq_unmask             = gic_unmask_irq,
 406         .irq_eoi                = gic_eoi_irq,
 407         .irq_set_type           = gic_set_type,
 408         .irq_retrigger          = gic_retrigger,
 409         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 410         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 411         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 412                                   IRQCHIP_SKIP_SET_WAKE |
 413                                   IRQCHIP_MASK_ON_SUSPEND,
 414 };
 415
 416 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 417 {
 418         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 419         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
 420                                          &gic_data[gic_nr]);
 421 }
 422
 423 static u8 gic_get_cpumask(struct gic_chip_data *gic)
 424 {
 425         void __iomem *base = gic_data_dist_base(gic);
 426         u32 mask, i;
 427
 428         for (i = mask = 0; i < 32; i += 4) {
 429                 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
 430                 mask |= mask >> 16;
 431                 mask |= mask >> 8;
 432                 if (mask)
 433                         break;
 434         }
 435
 436         if (!mask && num_possible_cpus() > 1)
 437                 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 438
 439         return mask;
 440 }
 441
 442 static bool gic_check_gicv2(void __iomem *base)
 443 {
 444         u32 val = readl_relaxed(base + GIC_CPU_IDENT);
 445         return (val & 0xff0fff) == 0x02043B;
 446 }
 447
 448 static void gic_cpu_if_up(struct gic_chip_data *gic)
 449 {
 450         void __iomem *cpu_base = gic_data_cpu_base(gic);
 451         u32 bypass = 0;
 452         u32 mode = 0;
 453         int i;
 454
 455         if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
 456                 mode = GIC_CPU_CTRL_EOImodeNS;
 457
 458         if (gic_check_gicv2(cpu_base))
 459                 for (i = 0; i < 4; i++)
 460                         writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
 461
 462         /*
 463         * Preserve bypass disable bits to be written back later
 464         */
 465         bypass = readl(cpu_base + GIC_CPU_CTRL);
 466         bypass &= GICC_DIS_BYPASS_MASK;
 467
 468         writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
 469 }
 470
 471
 472 static void gic_dist_init(struct gic_chip_data *gic)
 473 {
 474         unsigned int i;
 475         u32 cpumask;
 476         unsigned int gic_irqs = gic->gic_irqs;
 477         void __iomem *base = gic_data_dist_base(gic);
 478
 479         writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
 480
 481         /*
 482          * Set all global interrupts to this CPU only.
 483          */
 484         cpumask = gic_get_cpumask(gic);
 485         cpumask |= cpumask << 8;
 486         cpumask |= cpumask << 16;
 487         for (i = 32; i < gic_irqs; i += 4)
 488                 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 489
 490         gic_dist_config(base, gic_irqs, NULL);
 491
 492         writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
 493 }
 494
 495 static int gic_cpu_init(struct gic_chip_data *gic)
 496 {
 497         void __iomem *dist_base = gic_data_dist_base(gic);
 498         void __iomem *base = gic_data_cpu_base(gic);
 499         unsigned int cpu_mask, cpu = smp_processor_id();
 500         int i;
 501
 502         /*
 503          * Setting up the CPU map is only relevant for the primary GIC
 504          * because any nested/secondary GICs do not directly interface
 505          * with the CPU(s).
 506          */
 507         if (gic == &gic_data[0]) {
 508                 /*
 509                  * Get what the GIC says our CPU mask is.
 510                  */
 511                 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
 512                         return -EINVAL;
 513
 514                 gic_check_cpu_features();
 515                 cpu_mask = gic_get_cpumask(gic);
 516                 gic_cpu_map[cpu] = cpu_mask;
 517
 518                 /*
 519                  * Clear our mask from the other map entries in case they're
 520                  * still undefined.
 521                  */
 522                 for (i = 0; i < NR_GIC_CPU_IF; i++)
 523                         if (i != cpu)
 524                                 gic_cpu_map[i] &= ~cpu_mask;
 525         }
 526
 527         gic_cpu_config(dist_base, 32, NULL);
 528
 529         writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
 530         gic_cpu_if_up(gic);
 531
 532         return 0;
 533 }
 534
 535 int gic_cpu_if_down(unsigned int gic_nr)
 536 {
 537         void __iomem *cpu_base;
 538         u32 val = 0;
 539
 540         if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
 541                 return -EINVAL;
 542
 543         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 544         val = readl(cpu_base + GIC_CPU_CTRL);
 545         val &= ~GICC_ENABLE;
 546         writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
 547
 548         return 0;
 549 }
 550
 551 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
 552 /*
 553  * Saves the GIC distributor registers during suspend or idle.  Must be called
 554  * with interrupts disabled but before powering down the GIC.  After calling
 555  * this function, no interrupts will be delivered by the GIC, and another
 556  * platform-specific wakeup source must be enabled.
 557  */
 558 void gic_dist_save(struct gic_chip_data *gic)
 559 {
 560         unsigned int gic_irqs;
 561         void __iomem *dist_base;
 562         int i;
 563
 564         if (WARN_ON(!gic))
 565                 return;
 566
 567         gic_irqs = gic->gic_irqs;
 568         dist_base = gic_data_dist_base(gic);
 569
 570         if (!dist_base)
 571                 return;
 572
 573         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 574                 gic->saved_spi_conf[i] =
 575                         readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 576
 577         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 578                 gic->saved_spi_target[i] =
 579                         readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 580
 581         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 582                 gic->saved_spi_enable[i] =
 583                         readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 584
 585         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 586                 gic->saved_spi_active[i] =
 587                         readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 588 }
 589
 590 /*
 591  * Restores the GIC distributor registers during resume or when coming out of
 592  * idle.  Must be called before enabling interrupts.  If a level interrupt
 593  * that occurred while the GIC was suspended is still present, it will be
 594  * handled normally, but any edge interrupts that occurred will not be seen by
 595  * the GIC and need to be handled by the platform-specific wakeup source.
 596  */
 597 void gic_dist_restore(struct gic_chip_data *gic)
 598 {
 599         unsigned int gic_irqs;
 600         unsigned int i;
 601         void __iomem *dist_base;
 602
 603         if (WARN_ON(!gic))
 604                 return;
 605
 606         gic_irqs = gic->gic_irqs;
 607         dist_base = gic_data_dist_base(gic);
 608
 609         if (!dist_base)
 610                 return;
 611
 612         writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 613
 614         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 615                 writel_relaxed(gic->saved_spi_conf[i],
 616                         dist_base + GIC_DIST_CONFIG + i * 4);
 617
 618         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 619                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 620                         dist_base + GIC_DIST_PRI + i * 4);
 621
 622         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 623                 writel_relaxed(gic->saved_spi_target[i],
 624                         dist_base + GIC_DIST_TARGET + i * 4);
 625
 626         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 627                 writel_relaxed(GICD_INT_EN_CLR_X32,
 628                         dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 629                 writel_relaxed(gic->saved_spi_enable[i],
 630                         dist_base + GIC_DIST_ENABLE_SET + i * 4);
 631         }
 632
 633         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 634                 writel_relaxed(GICD_INT_EN_CLR_X32,
 635                         dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 636                 writel_relaxed(gic->saved_spi_active[i],
 637                         dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 638         }
 639
 640         writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
 641 }
 642
 643 void gic_cpu_save(struct gic_chip_data *gic)
 644 {
 645         int i;
 646         u32 *ptr;
 647         void __iomem *dist_base;
 648         void __iomem *cpu_base;
 649
 650         if (WARN_ON(!gic))
 651                 return;
 652
 653         dist_base = gic_data_dist_base(gic);
 654         cpu_base = gic_data_cpu_base(gic);
 655
 656         if (!dist_base || !cpu_base)
 657                 return;
 658
 659         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 660         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 661                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 662
 663         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 664         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 665                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 666
 667         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 668         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 669                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 670
 671 }
 672
 673 void gic_cpu_restore(struct gic_chip_data *gic)
 674 {
 675         int i;
 676         u32 *ptr;
 677         void __iomem *dist_base;
 678         void __iomem *cpu_base;
 679
 680         if (WARN_ON(!gic))
 681                 return;
 682
 683         dist_base = gic_data_dist_base(gic);
 684         cpu_base = gic_data_cpu_base(gic);
 685
 686         if (!dist_base || !cpu_base)
 687                 return;
 688
 689         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 690         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 691                 writel_relaxed(GICD_INT_EN_CLR_X32,
 692                                dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 693                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
 694         }
 695
 696         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 697         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 698                 writel_relaxed(GICD_INT_EN_CLR_X32,
 699                                dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 700                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 701         }
 702
 703         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 704         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 705                 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 706
 707         for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
 708                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 709                                         dist_base + GIC_DIST_PRI + i * 4);
 710
 711         writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
 712         gic_cpu_if_up(gic);
 713 }
 714
 715 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 716 {
 717         int i;
 718
 719         for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 720                 switch (cmd) {
 721                 case CPU_PM_ENTER:
 722                         gic_cpu_save(&gic_data[i]);
 723                         break;
 724                 case CPU_PM_ENTER_FAILED:
 725                 case CPU_PM_EXIT:
 726                         gic_cpu_restore(&gic_data[i]);
 727                         break;
 728                 case CPU_CLUSTER_PM_ENTER:
 729                         gic_dist_save(&gic_data[i]);
 730                         break;
 731                 case CPU_CLUSTER_PM_ENTER_FAILED:
 732                 case CPU_CLUSTER_PM_EXIT:
 733                         gic_dist_restore(&gic_data[i]);
 734                         break;
 735                 }
 736         }
 737
 738         return NOTIFY_OK;
 739 }
 740
 741 static struct notifier_block gic_notifier_block = {
 742         .notifier_call = gic_notifier,
 743 };
 744
 745 static int gic_pm_init(struct gic_chip_data *gic)
 746 {
 747         gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 748                 sizeof(u32));
 749         if (WARN_ON(!gic->saved_ppi_enable))
 750                 return -ENOMEM;
 751
 752         gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 753                 sizeof(u32));
 754         if (WARN_ON(!gic->saved_ppi_active))
 755                 goto free_ppi_enable;
 756
 757         gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
 758                 sizeof(u32));
 759         if (WARN_ON(!gic->saved_ppi_conf))
 760                 goto free_ppi_active;
 761
 762         if (gic == &gic_data[0])
 763                 cpu_pm_register_notifier(&gic_notifier_block);
 764
 765         return 0;
 766
 767 free_ppi_active:
 768         free_percpu(gic->saved_ppi_active);
 769 free_ppi_enable:
 770         free_percpu(gic->saved_ppi_enable);
 771
 772         return -ENOMEM;
 773 }
 774 #else
 775 static int gic_pm_init(struct gic_chip_data *gic)
 776 {
 777         return 0;
 778 }
 779 #endif
 780
 781 #ifdef CONFIG_SMP
 782 static void rmw_writeb(u8 bval, void __iomem *addr)
 783 {
 784         static DEFINE_RAW_SPINLOCK(rmw_lock);
 785         unsigned long offset = (unsigned long)addr & 3UL;
 786         unsigned long shift = offset * 8;
 787         unsigned long flags;
 788         u32 val;
 789
 790         raw_spin_lock_irqsave(&rmw_lock, flags);
 791
 792         addr -= offset;
 793         val = readl_relaxed(addr);
 794         val &= ~GENMASK(shift + 7, shift);
 795         val |= bval << shift;
 796         writel_relaxed(val, addr);
 797
 798         raw_spin_unlock_irqrestore(&rmw_lock, flags);
 799 }
 800
 801 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 802                             bool force)
 803 {
 804         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
 805         unsigned int cpu;
 806
 807         if (!force)
 808                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
 809         else
 810                 cpu = cpumask_first(mask_val);
 811
 812         if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
 813                 return -EINVAL;
 814
 815         if (static_branch_unlikely(&needs_rmw_access))
 816                 rmw_writeb(gic_cpu_map[cpu], reg);
 817         else
 818                 writeb_relaxed(gic_cpu_map[cpu], reg);
 819         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 820
 821         return IRQ_SET_MASK_OK_DONE;
 822 }
 823
 824 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 825 {
 826         int cpu;
 827         unsigned long flags, map = 0;
 828
 829         if (unlikely(nr_cpu_ids == 1)) {
 830                 /* Only one CPU? let's do a self-IPI... */
 831                 writel_relaxed(2 << 24 | d->hwirq,
 832                                gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 833                 return;
 834         }
 835
 836         gic_lock_irqsave(flags);
 837
 838         /* Convert our logical CPU mask into a physical one. */
 839         for_each_cpu(cpu, mask)
 840                 map |= gic_cpu_map[cpu];
 841
 842         /*
 843          * Ensure that stores to Normal memory are visible to the
 844          * other CPUs before they observe us issuing the IPI.
 845          */
 846         dmb(ishst);
 847
 848         /* this always happens on GIC0 */
 849         writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 850
 851         gic_unlock_irqrestore(flags);
 852 }
 853
 854 static int gic_starting_cpu(unsigned int cpu)
 855 {
 856         gic_cpu_init(&gic_data[0]);
 857         return 0;
 858 }
 859
 860 static __init void gic_smp_init(void)
 861 {
 862         struct irq_fwspec sgi_fwspec = {
 863                 .fwnode         = gic_data[0].domain->fwnode,
 864                 .param_count    = 1,
 865         };
 866         int base_sgi;
 867
 868         cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
 869                                   "irqchip/arm/gic:starting",
 870                                   gic_starting_cpu, NULL);
 871
 872         base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
 873                                            NUMA_NO_NODE, &sgi_fwspec,
 874                                            false, NULL);
 875         if (WARN_ON(base_sgi <= 0))
 876                 return;
 877
 878         set_smp_ipi_range(base_sgi, 8);
 879 }
 880 #else
 881 #define gic_smp_init()          do { } while(0)
 882 #define gic_set_affinity        NULL
 883 #define gic_ipi_send_mask       NULL
 884 #endif
 885
 886 #ifdef CONFIG_BL_SWITCHER
 887 /*
 888  * gic_send_sgi - send a SGI directly to given CPU interface number
 889  *
 890  * cpu_id: the ID for the destination CPU interface
 891  * irq: the IPI number to send a SGI for
 892  */
 893 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 894 {
 895         BUG_ON(cpu_id >= NR_GIC_CPU_IF);
 896         cpu_id = 1 << cpu_id;
 897         /* this always happens on GIC0 */
 898         writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 899 }
 900
 901 /*
 902  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
 903  *
 904  * @cpu: the logical CPU number to get the GIC ID for.
 905  *
 906  * Return the CPU interface ID for the given logical CPU number,
 907  * or -1 if the CPU number is too large or the interface ID is
 908  * unknown (more than one bit set).
 909  */
 910 int gic_get_cpu_id(unsigned int cpu)
 911 {
 912         unsigned int cpu_bit;
 913
 914         if (cpu >= NR_GIC_CPU_IF)
 915                 return -1;
 916         cpu_bit = gic_cpu_map[cpu];
 917         if (cpu_bit & (cpu_bit - 1))
 918                 return -1;
 919         return __ffs(cpu_bit);
 920 }
 921
 922 /*
 923  * gic_migrate_target - migrate IRQs to another CPU interface
 924  *
 925  * @new_cpu_id: the CPU target ID to migrate IRQs to
 926  *
 927  * Migrate all peripheral interrupts with a target matching the current CPU
 928  * to the interface corresponding to @new_cpu_id.  The CPU interface mapping
 929  * is also updated.  Targets to other CPU interfaces are unchanged.
 930  * This must be called with IRQs locally disabled.
 931  */
 932 void gic_migrate_target(unsigned int new_cpu_id)
 933 {
 934         unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
 935         void __iomem *dist_base;
 936         int i, ror_val, cpu = smp_processor_id();
 937         u32 val, cur_target_mask, active_mask;
 938
 939         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 940
 941         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 942         if (!dist_base)
 943                 return;
 944         gic_irqs = gic_data[gic_nr].gic_irqs;
 945
 946         cur_cpu_id = __ffs(gic_cpu_map[cpu]);
 947         cur_target_mask = 0x01010101 << cur_cpu_id;
 948         ror_val = (cur_cpu_id - new_cpu_id) & 31;
 949
 950         gic_lock();
 951
 952         /* Update the target interface for this logical CPU */
 953         gic_cpu_map[cpu] = 1 << new_cpu_id;
 954
 955         /*
 956          * Find all the peripheral interrupts targeting the current
 957          * CPU interface and migrate them to the new CPU interface.
 958          * We skip DIST_TARGET 0 to 7 as they are read-only.
 959          */
 960         for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
 961                 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 962                 active_mask = val & cur_target_mask;
 963                 if (active_mask) {
 964                         val &= ~active_mask;
 965                         val |= ror32(active_mask, ror_val);
 966                         writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
 967                 }
 968         }
 969
 970         gic_unlock();
 971
 972         /*
 973          * Now let's migrate and clear any potential SGIs that might be
 974          * pending for us (cur_cpu_id).  Since GIC_DIST_SGI_PENDING_SET
 975          * is a banked register, we can only forward the SGI using
 976          * GIC_DIST_SOFTINT.  The original SGI source is lost but Linux
 977          * doesn't use that information anyway.
 978          *
 979          * For the same reason we do not adjust SGI source information
 980          * for previously sent SGIs by us to other CPUs either.
 981          */
 982         for (i = 0; i < 16; i += 4) {
 983                 int j;
 984                 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
 985                 if (!val)
 986                         continue;
 987                 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
 988                 for (j = i; j < i + 4; j++) {
 989                         if (val & 0xff)
 990                                 writel_relaxed((1 << (new_cpu_id + 16)) | j,
 991                                                 dist_base + GIC_DIST_SOFTINT);
 992                         val >>= 8;
 993                 }
 994         }
 995 }
 996
 997 /*
 998  * gic_get_sgir_physaddr - get the physical address for the SGI register
 999  *
1000  * REturn the physical address of the SGI register to be used
1001  * by some early assembly code when the kernel is not yet available.
1002  */
1003 static unsigned long gic_dist_physaddr;
1004
1005 unsigned long gic_get_sgir_physaddr(void)
1006 {
1007         if (!gic_dist_physaddr)
1008                 return 0;
1009         return gic_dist_physaddr + GIC_DIST_SOFTINT;
1010 }
1011
1012 static void __init gic_init_physaddr(struct device_node *node)
1013 {
1014         struct resource res;
1015         if (of_address_to_resource(node, 0, &res) == 0) {
1016                 gic_dist_physaddr = res.start;
1017                 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
1018         }
1019 }
1020
1021 #else
1022 #define gic_init_physaddr(node)  do { } while (0)
1023 #endif
1024
1025 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1026                                 irq_hw_number_t hw)
1027 {
1028         struct gic_chip_data *gic = d->host_data;
1029         struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1030
1031         switch (hw) {
1032         case 0 ... 15:
1033                 irq_set_percpu_devid(irq);
1034                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1035                                     handle_percpu_devid_fasteoi_ipi,
1036                                     NULL, NULL);
1037                 break;
1038         case 16 ... 31:
1039                 irq_set_percpu_devid(irq);
1040                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1041                                     handle_percpu_devid_irq, NULL, NULL);
1042                 break;
1043         default:
1044                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1045                                     handle_fasteoi_irq, NULL, NULL);
1046                 irq_set_probe(irq);
1047                 irqd_set_single_target(irqd);
1048                 break;
1049         }
1050
1051         /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1052         irqd_set_handle_enforce_irqctx(irqd);
1053         return 0;
1054 }
1055
1056 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
1057 {
1058 }
1059
1060 static int gic_irq_domain_translate(struct irq_domain *d,
1061                                     struct irq_fwspec *fwspec,
1062                                     unsigned long *hwirq,
1063                                     unsigned int *type)
1064 {
1065         if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1066                 *hwirq = fwspec->param[0];
1067                 *type = IRQ_TYPE_EDGE_RISING;
1068                 return 0;
1069         }
1070
1071         if (is_of_node(fwspec->fwnode)) {
1072                 if (fwspec->param_count < 3)
1073                         return -EINVAL;
1074
1075                 switch (fwspec->param[0]) {
1076                 case 0:                 /* SPI */
1077                         *hwirq = fwspec->param[1] + 32;
1078                         break;
1079                 case 1:                 /* PPI */
1080                         *hwirq = fwspec->param[1] + 16;
1081                         break;
1082                 default:
1083                         return -EINVAL;
1084                 }
1085
1086                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1087
1088                 /* Make it clear that broken DTs are... broken */
1089                 WARN_ON(*type == IRQ_TYPE_NONE);
1090                 return 0;
1091         }
1092
1093         if (is_fwnode_irqchip(fwspec->fwnode)) {
1094                 if(fwspec->param_count != 2)
1095                         return -EINVAL;
1096
1097                 if (fwspec->param[0] < 16) {
1098                         pr_err(FW_BUG "Illegal GSI%d translation request\n",
1099                                fwspec->param[0]);
1100                         return -EINVAL;
1101                 }
1102
1103                 *hwirq = fwspec->param[0];
1104                 *type = fwspec->param[1];
1105
1106                 WARN_ON(*type == IRQ_TYPE_NONE);
1107                 return 0;
1108         }
1109
1110         return -EINVAL;
1111 }
1112
1113 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1114                                 unsigned int nr_irqs, void *arg)
1115 {
1116         int i, ret;
1117         irq_hw_number_t hwirq;
1118         unsigned int type = IRQ_TYPE_NONE;
1119         struct irq_fwspec *fwspec = arg;
1120
1121         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1122         if (ret)
1123                 return ret;
1124
1125         for (i = 0; i < nr_irqs; i++) {
1126                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1127                 if (ret)
1128                         return ret;
1129         }
1130
1131         return 0;
1132 }
1133
1134 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1135         .translate = gic_irq_domain_translate,
1136         .alloc = gic_irq_domain_alloc,
1137         .free = irq_domain_free_irqs_top,
1138 };
1139
1140 static const struct irq_domain_ops gic_irq_domain_ops = {
1141         .map = gic_irq_domain_map,
1142         .unmap = gic_irq_domain_unmap,
1143 };
1144
1145 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1146                           const char *name, bool use_eoimode1)
1147 {
1148         /* Initialize irq_chip */
1149         gic->chip = gic_chip;
1150         gic->chip.name = name;
1151         gic->chip.parent_device = dev;
1152
1153         if (use_eoimode1) {
1154                 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1155                 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1156                 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1157         }
1158
1159         if (gic == &gic_data[0]) {
1160                 gic->chip.irq_set_affinity = gic_set_affinity;
1161                 gic->chip.ipi_send_mask = gic_ipi_send_mask;
1162         }
1163 }
1164
1165 static int gic_init_bases(struct gic_chip_data *gic,
1166                           struct fwnode_handle *handle)
1167 {
1168         int gic_irqs, ret;
1169
1170         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1171                 /* Frankein-GIC without banked registers... */
1172                 unsigned int cpu;
1173
1174                 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1175                 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1176                 if (WARN_ON(!gic->dist_base.percpu_base ||
1177                             !gic->cpu_base.percpu_base)) {
1178                         ret = -ENOMEM;
1179                         goto error;
1180                 }
1181
1182                 for_each_possible_cpu(cpu) {
1183                         u32 mpidr = cpu_logical_map(cpu);
1184                         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1185                         unsigned long offset = gic->percpu_offset * core_id;
1186                         *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1187                                 gic->raw_dist_base + offset;
1188                         *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1189                                 gic->raw_cpu_base + offset;
1190                 }
1191
1192                 enable_frankengic();
1193         } else {
1194                 /* Normal, sane GIC... */
1195                 WARN(gic->percpu_offset,
1196                      "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1197                      gic->percpu_offset);
1198                 gic->dist_base.common_base = gic->raw_dist_base;
1199                 gic->cpu_base.common_base = gic->raw_cpu_base;
1200         }
1201
1202         /*
1203          * Find out how many interrupts are supported.
1204          * The GIC only supports up to 1020 interrupt sources.
1205          */
1206         gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1207         gic_irqs = (gic_irqs + 1) * 32;
1208         if (gic_irqs > 1020)
1209                 gic_irqs = 1020;
1210         gic->gic_irqs = gic_irqs;
1211
1212         if (handle) {           /* DT/ACPI */
1213                 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1214                                                        &gic_irq_domain_hierarchy_ops,
1215                                                        gic);
1216         } else {                /* Legacy support */
1217                 /*
1218                  * For primary GICs, skip over SGIs.
1219                  * No secondary GIC support whatsoever.
1220                  */
1221                 int irq_base;
1222
1223                 gic_irqs -= 16; /* calculate # of irqs to allocate */
1224
1225                 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1226                                            numa_node_id());
1227                 if (irq_base < 0) {
1228                         WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1229                         irq_base = 16;
1230                 }
1231
1232                 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1233                                                     16, &gic_irq_domain_ops, gic);
1234         }
1235
1236         if (WARN_ON(!gic->domain)) {
1237                 ret = -ENODEV;
1238                 goto error;
1239         }
1240
1241         gic_dist_init(gic);
1242         ret = gic_cpu_init(gic);
1243         if (ret)
1244                 goto error;
1245
1246         ret = gic_pm_init(gic);
1247         if (ret)
1248                 goto error;
1249
1250         return 0;
1251
1252 error:
1253         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1254                 free_percpu(gic->dist_base.percpu_base);
1255                 free_percpu(gic->cpu_base.percpu_base);
1256         }
1257
1258         return ret;
1259 }
1260
1261 static int __init __gic_init_bases(struct gic_chip_data *gic,
1262                                    struct fwnode_handle *handle)
1263 {
1264         char *name;
1265         int i, ret;
1266
1267         if (WARN_ON(!gic || gic->domain))
1268                 return -EINVAL;
1269
1270         if (gic == &gic_data[0]) {
1271                 /*
1272                  * Initialize the CPU interface map to all CPUs.
1273                  * It will be refined as each CPU probes its ID.
1274                  * This is only necessary for the primary GIC.
1275                  */
1276                 for (i = 0; i < NR_GIC_CPU_IF; i++)
1277                         gic_cpu_map[i] = 0xff;
1278
1279                 set_handle_irq(gic_handle_irq);
1280                 if (static_branch_likely(&supports_deactivate_key))
1281                         pr_info("GIC: Using split EOI/Deactivate mode\n");
1282         }
1283
1284         if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1285                 name = kasprintf(GFP_KERNEL, "GICv2");
1286                 gic_init_chip(gic, NULL, name, true);
1287         } else {
1288                 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1289                 gic_init_chip(gic, NULL, name, false);
1290         }
1291
1292         ret = gic_init_bases(gic, handle);
1293         if (ret)
1294                 kfree(name);
1295         else if (gic == &gic_data[0])
1296                 gic_smp_init();
1297
1298         return ret;
1299 }
1300
1301 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1302 {
1303         struct gic_chip_data *gic;
1304
1305         /*
1306          * Non-DT/ACPI systems won't run a hypervisor, so let's not
1307          * bother with these...
1308          */
1309         static_branch_disable(&supports_deactivate_key);
1310
1311         gic = &gic_data[0];
1312         gic->raw_dist_base = dist_base;
1313         gic->raw_cpu_base = cpu_base;
1314
1315         __gic_init_bases(gic, NULL);
1316 }
1317
1318 static void gic_teardown(struct gic_chip_data *gic)
1319 {
1320         if (WARN_ON(!gic))
1321                 return;
1322
1323         if (gic->raw_dist_base)
1324                 iounmap(gic->raw_dist_base);
1325         if (gic->raw_cpu_base)
1326                 iounmap(gic->raw_cpu_base);
1327 }
1328
1329 #ifdef CONFIG_OF
1330 static int gic_cnt __initdata;
1331 static bool gicv2_force_probe;
1332
1333 static int __init gicv2_force_probe_cfg(char *buf)
1334 {
1335         return strtobool(buf, &gicv2_force_probe);
1336 }
1337 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1338
1339 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1340 {
1341         struct resource cpuif_res;
1342
1343         of_address_to_resource(node, 1, &cpuif_res);
1344
1345         if (!is_hyp_mode_available())
1346                 return false;
1347         if (resource_size(&cpuif_res) < SZ_8K) {
1348                 void __iomem *alt;
1349                 /*
1350                  * Check for a stupid firmware that only exposes the
1351                  * first page of a GICv2.
1352                  */
1353                 if (!gic_check_gicv2(*base))
1354                         return false;
1355
1356                 if (!gicv2_force_probe) {
1357                         pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1358                         return false;
1359                 }
1360
1361                 alt = ioremap(cpuif_res.start, SZ_8K);
1362                 if (!alt)
1363                         return false;
1364                 if (!gic_check_gicv2(alt + SZ_4K)) {
1365                         /*
1366                          * The first page was that of a GICv2, and
1367                          * the second was *something*. Let's trust it
1368                          * to be a GICv2, and update the mapping.
1369                          */
1370                         pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1371                                 &cpuif_res.start);
1372                         iounmap(*base);
1373                         *base = alt;
1374                         return true;
1375                 }
1376
1377                 /*
1378                  * We detected *two* initial GICv2 pages in a
1379                  * row. Could be a GICv2 aliased over two 64kB
1380                  * pages. Update the resource, map the iospace, and
1381                  * pray.
1382                  */
1383                 iounmap(alt);
1384                 alt = ioremap(cpuif_res.start, SZ_128K);
1385                 if (!alt)
1386                         return false;
1387                 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1388                         &cpuif_res.start);
1389                 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1390                 iounmap(*base);
1391                 *base = alt;
1392         }
1393         if (resource_size(&cpuif_res) == SZ_128K) {
1394                 /*
1395                  * Verify that we have the first 4kB of a GICv2
1396                  * aliased over the first 64kB by checking the
1397                  * GICC_IIDR register on both ends.
1398                  */
1399                 if (!gic_check_gicv2(*base) ||
1400                     !gic_check_gicv2(*base + 0xf000))
1401                         return false;
1402
1403                 /*
1404                  * Move the base up by 60kB, so that we have a 8kB
1405                  * contiguous region, which allows us to use GICC_DIR
1406                  * at its normal offset. Please pass me that bucket.
1407                  */
1408                 *base += 0xf000;
1409                 cpuif_res.start += 0xf000;
1410                 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1411                         &cpuif_res.start);
1412         }
1413
1414         return true;
1415 }
1416
1417 static bool gic_enable_rmw_access(void *data)
1418 {
1419         /*
1420          * The EMEV2 class of machines has a broken interconnect, and
1421          * locks up on accesses that are less than 32bit. So far, only
1422          * the affinity setting requires it.
1423          */
1424         if (of_machine_is_compatible("renesas,emev2")) {
1425                 static_branch_enable(&needs_rmw_access);
1426                 return true;
1427         }
1428
1429         return false;
1430 }
1431
1432 static const struct gic_quirk gic_quirks[] = {
1433         {
1434                 .desc           = "broken byte access",
1435                 .compatible     = "arm,pl390",
1436                 .init           = gic_enable_rmw_access,
1437         },
1438         { },
1439 };
1440
1441 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1442 {
1443         if (!gic || !node)
1444                 return -EINVAL;
1445
1446         gic->raw_dist_base = of_iomap(node, 0);
1447         if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1448                 goto error;
1449
1450         gic->raw_cpu_base = of_iomap(node, 1);
1451         if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1452                 goto error;
1453
1454         if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1455                 gic->percpu_offset = 0;
1456
1457         gic_enable_of_quirks(node, gic_quirks, gic);
1458
1459         return 0;
1460
1461 error:
1462         gic_teardown(gic);
1463
1464         return -ENOMEM;
1465 }
1466
1467 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1468 {
1469         int ret;
1470
1471         if (!dev || !dev->of_node || !gic || !irq)
1472                 return -EINVAL;
1473
1474         *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1475         if (!*gic)
1476                 return -ENOMEM;
1477
1478         gic_init_chip(*gic, dev, dev->of_node->name, false);
1479
1480         ret = gic_of_setup(*gic, dev->of_node);
1481         if (ret)
1482                 return ret;
1483
1484         ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1485         if (ret) {
1486                 gic_teardown(*gic);
1487                 return ret;
1488         }
1489
1490         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1491
1492         return 0;
1493 }
1494
1495 static void __init gic_of_setup_kvm_info(struct device_node *node)
1496 {
1497         int ret;
1498         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1499         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1500
1501         gic_v2_kvm_info.type = GIC_V2;
1502
1503         gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1504         if (!gic_v2_kvm_info.maint_irq)
1505                 return;
1506
1507         ret = of_address_to_resource(node, 2, vctrl_res);
1508         if (ret)
1509                 return;
1510
1511         ret = of_address_to_resource(node, 3, vcpu_res);
1512         if (ret)
1513                 return;
1514
1515         if (static_branch_likely(&supports_deactivate_key))
1516                 gic_set_kvm_info(&gic_v2_kvm_info);
1517 }
1518
1519 int __init
1520 gic_of_init(struct device_node *node, struct device_node *parent)
1521 {
1522         struct gic_chip_data *gic;
1523         int irq, ret;
1524
1525         if (WARN_ON(!node))
1526                 return -ENODEV;
1527
1528         if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1529                 return -EINVAL;
1530
1531         gic = &gic_data[gic_cnt];
1532
1533         ret = gic_of_setup(gic, node);
1534         if (ret)
1535                 return ret;
1536
1537         /*
1538          * Disable split EOI/Deactivate if either HYP is not available
1539          * or the CPU interface is too small.
1540          */
1541         if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1542                 static_branch_disable(&supports_deactivate_key);
1543
1544         ret = __gic_init_bases(gic, &node->fwnode);
1545         if (ret) {
1546                 gic_teardown(gic);
1547                 return ret;
1548         }
1549
1550         if (!gic_cnt) {
1551                 gic_init_physaddr(node);
1552                 gic_of_setup_kvm_info(node);
1553         }
1554
1555         if (parent) {
1556                 irq = irq_of_parse_and_map(node, 0);
1557                 gic_cascade_irq(gic_cnt, irq);
1558         }
1559
1560         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1561                 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1562
1563         gic_cnt++;
1564         return 0;
1565 }
1566 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1567 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1568 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1569 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1570 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1571 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1572 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1573 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1574 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1575 #else
1576 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1577 {
1578         return -ENOTSUPP;
1579 }
1580 #endif
1581
1582 #ifdef CONFIG_ACPI
1583 static struct
1584 {
1585         phys_addr_t cpu_phys_base;
1586         u32 maint_irq;
1587         int maint_irq_mode;
1588         phys_addr_t vctrl_base;
1589         phys_addr_t vcpu_base;
1590 } acpi_data __initdata;
1591
1592 static int __init
1593 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1594                         const unsigned long end)
1595 {
1596         struct acpi_madt_generic_interrupt *processor;
1597         phys_addr_t gic_cpu_base;
1598         static int cpu_base_assigned;
1599
1600         processor = (struct acpi_madt_generic_interrupt *)header;
1601
1602         if (BAD_MADT_GICC_ENTRY(processor, end))
1603                 return -EINVAL;
1604
1605         /*
1606          * There is no support for non-banked GICv1/2 register in ACPI spec.
1607          * All CPU interface addresses have to be the same.
1608          */
1609         gic_cpu_base = processor->base_address;
1610         if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1611                 return -EINVAL;
1612
1613         acpi_data.cpu_phys_base = gic_cpu_base;
1614         acpi_data.maint_irq = processor->vgic_interrupt;
1615         acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1616                                     ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1617         acpi_data.vctrl_base = processor->gich_base_address;
1618         acpi_data.vcpu_base = processor->gicv_base_address;
1619
1620         cpu_base_assigned = 1;
1621         return 0;
1622 }
1623
1624 /* The things you have to do to just *count* something... */
1625 static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1626                                   const unsigned long end)
1627 {
1628         return 0;
1629 }
1630
1631 static bool __init acpi_gic_redist_is_present(void)
1632 {
1633         return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1634                                      acpi_dummy_func, 0) > 0;
1635 }
1636
1637 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1638                                      struct acpi_probe_entry *ape)
1639 {
1640         struct acpi_madt_generic_distributor *dist;
1641         dist = (struct acpi_madt_generic_distributor *)header;
1642
1643         return (dist->version == ape->driver_data &&
1644                 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1645                  !acpi_gic_redist_is_present()));
1646 }
1647
1648 #define ACPI_GICV2_DIST_MEM_SIZE        (SZ_4K)
1649 #define ACPI_GIC_CPU_IF_MEM_SIZE        (SZ_8K)
1650 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1651 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1652
1653 static void __init gic_acpi_setup_kvm_info(void)
1654 {
1655         int irq;
1656         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1657         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1658
1659         gic_v2_kvm_info.type = GIC_V2;
1660
1661         if (!acpi_data.vctrl_base)
1662                 return;
1663
1664         vctrl_res->flags = IORESOURCE_MEM;
1665         vctrl_res->start = acpi_data.vctrl_base;
1666         vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1667
1668         if (!acpi_data.vcpu_base)
1669                 return;
1670
1671         vcpu_res->flags = IORESOURCE_MEM;
1672         vcpu_res->start = acpi_data.vcpu_base;
1673         vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1674
1675         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1676                                 acpi_data.maint_irq_mode,
1677                                 ACPI_ACTIVE_HIGH);
1678         if (irq <= 0)
1679                 return;
1680
1681         gic_v2_kvm_info.maint_irq = irq;
1682
1683         gic_set_kvm_info(&gic_v2_kvm_info);
1684 }
1685
1686 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1687                                    const unsigned long end)
1688 {
1689         struct acpi_madt_generic_distributor *dist;
1690         struct fwnode_handle *domain_handle;
1691         struct gic_chip_data *gic = &gic_data[0];
1692         int count, ret;
1693
1694         /* Collect CPU base addresses */
1695         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1696                                       gic_acpi_parse_madt_cpu, 0);
1697         if (count <= 0) {
1698                 pr_err("No valid GICC entries exist\n");
1699                 return -EINVAL;
1700         }
1701
1702         gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1703         if (!gic->raw_cpu_base) {
1704                 pr_err("Unable to map GICC registers\n");
1705                 return -ENOMEM;
1706         }
1707
1708         dist = (struct acpi_madt_generic_distributor *)header;
1709         gic->raw_dist_base = ioremap(dist->base_address,
1710                                      ACPI_GICV2_DIST_MEM_SIZE);
1711         if (!gic->raw_dist_base) {
1712                 pr_err("Unable to map GICD registers\n");
1713                 gic_teardown(gic);
1714                 return -ENOMEM;
1715         }
1716
1717         /*
1718          * Disable split EOI/Deactivate if HYP is not available. ACPI
1719          * guarantees that we'll always have a GICv2, so the CPU
1720          * interface will always be the right size.
1721          */
1722         if (!is_hyp_mode_available())
1723                 static_branch_disable(&supports_deactivate_key);
1724
1725         /*
1726          * Initialize GIC instance zero (no multi-GIC support).
1727          */
1728         domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1729         if (!domain_handle) {
1730                 pr_err("Unable to allocate domain handle\n");
1731                 gic_teardown(gic);
1732                 return -ENOMEM;
1733         }
1734
1735         ret = __gic_init_bases(gic, domain_handle);
1736         if (ret) {
1737                 pr_err("Failed to initialise GIC\n");
1738                 irq_domain_free_fwnode(domain_handle);
1739                 gic_teardown(gic);
1740                 return ret;
1741         }
1742
1743         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1744
1745         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1746                 gicv2m_init(NULL, gic_data[0].domain);
1747
1748         if (static_branch_likely(&supports_deactivate_key))
1749                 gic_acpi_setup_kvm_info();
1750
1751         return 0;
1752 }
1753 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1754                      gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1755                      gic_v2_acpi_init);
1756 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1757                      gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1758                      gic_v2_acpi_init);
1759 #endif