drivers/irqchip/irq-gic.c

   1 /*
   2  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Interrupt architecture for the GIC:
   9  *
  10  * o There is one Interrupt Distributor, which receives interrupts
  11  *   from system devices and sends them to the Interrupt Controllers.
  12  *
  13  * o There is one CPU Interface per CPU, which sends interrupts sent
  14  *   by the Distributor, and interrupts generated locally, to the
  15  *   associated CPU. The base address of the CPU interface is usually
  16  *   aliased so that the same address points to different chips depending
  17  *   on the CPU it is accessed from.
  18  *
  19  * Note that IRQs 0-31 are special - they are local to each CPU.
  20  * As such, the enable set/clear, pending set/clear and active bit
  21  * registers are banked per-cpu for these sources.
  22  */
  23 #include <linux/init.h>
  24 #include <linux/kernel.h>
  25 #include <linux/err.h>
  26 #include <linux/module.h>
  27 #include <linux/list.h>
  28 #include <linux/smp.h>
  29 #include <linux/cpu.h>
  30 #include <linux/cpu_pm.h>
  31 #include <linux/cpumask.h>
  32 #include <linux/io.h>
  33 #include <linux/of.h>
  34 #include <linux/of_address.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/acpi.h>
  37 #include <linux/irqdomain.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/percpu.h>
  40 #include <linux/slab.h>
  41 #include <linux/irqchip.h>
  42 #include <linux/irqchip/chained_irq.h>
  43 #include <linux/irqchip/arm-gic.h>
  44
  45 #include <asm/cputype.h>
  46 #include <asm/irq.h>
  47 #include <asm/exception.h>
  48 #include <asm/smp_plat.h>
  49 #include <asm/virt.h>
  50
  51 #include "irq-gic-common.h"
  52
  53 #ifdef CONFIG_ARM64
  54 #include <asm/cpufeature.h>
  55
  56 static void gic_check_cpu_features(void)
  57 {
  58         WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
  59                         TAINT_CPU_OUT_OF_SPEC,
  60                         "GICv3 system registers enabled, broken firmware!\n");
  61 }
  62 #else
  63 #define gic_check_cpu_features()        do { } while(0)
  64 #endif
  65
  66 union gic_base {
  67         void __iomem *common_base;
  68         void __percpu * __iomem *percpu_base;
  69 };
  70
  71 struct gic_chip_data {
  72         struct irq_chip chip;
  73         union gic_base dist_base;
  74         union gic_base cpu_base;
  75         void __iomem *raw_dist_base;
  76         void __iomem *raw_cpu_base;
  77         u32 percpu_offset;
  78 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  79         u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
  80         u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
  81         u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
  82         u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
  83         u32 __percpu *saved_ppi_enable;
  84         u32 __percpu *saved_ppi_active;
  85         u32 __percpu *saved_ppi_conf;
  86 #endif
  87         struct irq_domain *domain;
  88         unsigned int gic_irqs;
  89 #ifdef CONFIG_GIC_NON_BANKED
  90         void __iomem *(*get_base)(union gic_base *);
  91 #endif
  92 };
  93
  94 #ifdef CONFIG_BL_SWITCHER
  95
  96 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
  97
  98 #define gic_lock_irqsave(f)             \
  99         raw_spin_lock_irqsave(&cpu_map_lock, (f))
 100 #define gic_unlock_irqrestore(f)        \
 101         raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
 102
 103 #define gic_lock()                      raw_spin_lock(&cpu_map_lock)
 104 #define gic_unlock()                    raw_spin_unlock(&cpu_map_lock)
 105
 106 #else
 107
 108 #define gic_lock_irqsave(f)             do { (void)(f); } while(0)
 109 #define gic_unlock_irqrestore(f)        do { (void)(f); } while(0)
 110
 111 #define gic_lock()                      do { } while(0)
 112 #define gic_unlock()                    do { } while(0)
 113
 114 #endif
 115
 116 /*
 117  * The GIC mapping of CPU interfaces does not necessarily match
 118  * the logical CPU numbering.  Let's use a mapping as returned
 119  * by the GIC itself.
 120  */
 121 #define NR_GIC_CPU_IF 8
 122 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 123
 124 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
 125
 126 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 127
 128 static struct gic_kvm_info gic_v2_kvm_info;
 129
 130 #ifdef CONFIG_GIC_NON_BANKED
 131 static void __iomem *gic_get_percpu_base(union gic_base *base)
 132 {
 133         return raw_cpu_read(*base->percpu_base);
 134 }
 135
 136 static void __iomem *gic_get_common_base(union gic_base *base)
 137 {
 138         return base->common_base;
 139 }
 140
 141 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
 142 {
 143         return data->get_base(&data->dist_base);
 144 }
 145
 146 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
 147 {
 148         return data->get_base(&data->cpu_base);
 149 }
 150
 151 static inline void gic_set_base_accessor(struct gic_chip_data *data,
 152                                          void __iomem *(*f)(union gic_base *))
 153 {
 154         data->get_base = f;
 155 }
 156 #else
 157 #define gic_data_dist_base(d)   ((d)->dist_base.common_base)
 158 #define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
 159 #define gic_set_base_accessor(d, f)
 160 #endif
 161
 162 static inline void __iomem *gic_dist_base(struct irq_data *d)
 163 {
 164         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 165         return gic_data_dist_base(gic_data);
 166 }
 167
 168 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 169 {
 170         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 171         return gic_data_cpu_base(gic_data);
 172 }
 173
 174 static inline unsigned int gic_irq(struct irq_data *d)
 175 {
 176         return d->hwirq;
 177 }
 178
 179 static inline bool cascading_gic_irq(struct irq_data *d)
 180 {
 181         void *data = irq_data_get_irq_handler_data(d);
 182
 183         /*
 184          * If handler_data is set, this is a cascading interrupt, and
 185          * it cannot possibly be forwarded.
 186          */
 187         return data != NULL;
 188 }
 189
 190 /*
 191  * Routines to acknowledge, disable and enable interrupts
 192  */
 193 static void gic_poke_irq(struct irq_data *d, u32 offset)
 194 {
 195         u32 mask = 1 << (gic_irq(d) % 32);
 196         writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
 197 }
 198
 199 static int gic_peek_irq(struct irq_data *d, u32 offset)
 200 {
 201         u32 mask = 1 << (gic_irq(d) % 32);
 202         return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
 203 }
 204
 205 static void gic_mask_irq(struct irq_data *d)
 206 {
 207         gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
 208 }
 209
 210 static void gic_eoimode1_mask_irq(struct irq_data *d)
 211 {
 212         gic_mask_irq(d);
 213         /*
 214          * When masking a forwarded interrupt, make sure it is
 215          * deactivated as well.
 216          *
 217          * This ensures that an interrupt that is getting
 218          * disabled/masked will not get "stuck", because there is
 219          * noone to deactivate it (guest is being terminated).
 220          */
 221         if (irqd_is_forwarded_to_vcpu(d))
 222                 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
 223 }
 224
 225 static void gic_unmask_irq(struct irq_data *d)
 226 {
 227         gic_poke_irq(d, GIC_DIST_ENABLE_SET);
 228 }
 229
 230 static void gic_eoi_irq(struct irq_data *d)
 231 {
 232         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 233 }
 234
 235 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 236 {
 237         /* Do not deactivate an IRQ forwarded to a vcpu. */
 238         if (irqd_is_forwarded_to_vcpu(d))
 239                 return;
 240
 241         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
 242 }
 243
 244 static int gic_irq_set_irqchip_state(struct irq_data *d,
 245                                      enum irqchip_irq_state which, bool val)
 246 {
 247         u32 reg;
 248
 249         switch (which) {
 250         case IRQCHIP_STATE_PENDING:
 251                 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
 252                 break;
 253
 254         case IRQCHIP_STATE_ACTIVE:
 255                 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
 256                 break;
 257
 258         case IRQCHIP_STATE_MASKED:
 259                 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
 260                 break;
 261
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         gic_poke_irq(d, reg);
 267         return 0;
 268 }
 269
 270 static int gic_irq_get_irqchip_state(struct irq_data *d,
 271                                       enum irqchip_irq_state which, bool *val)
 272 {
 273         switch (which) {
 274         case IRQCHIP_STATE_PENDING:
 275                 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
 276                 break;
 277
 278         case IRQCHIP_STATE_ACTIVE:
 279                 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
 280                 break;
 281
 282         case IRQCHIP_STATE_MASKED:
 283                 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
 284                 break;
 285
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int gic_set_type(struct irq_data *d, unsigned int type)
 294 {
 295         void __iomem *base = gic_dist_base(d);
 296         unsigned int gicirq = gic_irq(d);
 297
 298         /* Interrupt configuration for SGIs can't be changed */
 299         if (gicirq < 16)
 300                 return -EINVAL;
 301
 302         /* SPIs have restrictions on the supported types */
 303         if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 304                             type != IRQ_TYPE_EDGE_RISING)
 305                 return -EINVAL;
 306
 307         return gic_configure_irq(gicirq, type, base, NULL);
 308 }
 309
 310 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 311 {
 312         /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
 313         if (cascading_gic_irq(d))
 314                 return -EINVAL;
 315
 316         if (vcpu)
 317                 irqd_set_forwarded_to_vcpu(d);
 318         else
 319                 irqd_clr_forwarded_to_vcpu(d);
 320         return 0;
 321 }
 322
 323 #ifdef CONFIG_SMP
 324 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 325                             bool force)
 326 {
 327         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
 328         unsigned int cpu;
 329
 330         if (!force)
 331                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
 332         else
 333                 cpu = cpumask_first(mask_val);
 334
 335         if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
 336                 return -EINVAL;
 337
 338         writeb_relaxed(gic_cpu_map[cpu], reg);
 339
 340         return IRQ_SET_MASK_OK_DONE;
 341 }
 342 #endif
 343
 344 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 345 {
 346         u32 irqstat, irqnr;
 347         struct gic_chip_data *gic = &gic_data[0];
 348         void __iomem *cpu_base = gic_data_cpu_base(gic);
 349
 350         do {
 351                 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
 352                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 353
 354                 if (likely(irqnr > 15 && irqnr < 1020)) {
 355                         if (static_key_true(&supports_deactivate))
 356                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 357                         handle_domain_irq(gic->domain, irqnr, regs);
 358                         continue;
 359                 }
 360                 if (irqnr < 16) {
 361                         writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 362                         if (static_key_true(&supports_deactivate))
 363                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
 364 #ifdef CONFIG_SMP
 365                         /*
 366                          * Ensure any shared data written by the CPU sending
 367                          * the IPI is read after we've read the ACK register
 368                          * on the GIC.
 369                          *
 370                          * Pairs with the write barrier in gic_raise_softirq
 371                          */
 372                         smp_rmb();
 373                         handle_IPI(irqnr, regs);
 374 #endif
 375                         continue;
 376                 }
 377                 break;
 378         } while (1);
 379 }
 380
 381 static void gic_handle_cascade_irq(struct irq_desc *desc)
 382 {
 383         struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
 384         struct irq_chip *chip = irq_desc_get_chip(desc);
 385         unsigned int cascade_irq, gic_irq;
 386         unsigned long status;
 387
 388         chained_irq_enter(chip, desc);
 389
 390         status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
 391
 392         gic_irq = (status & GICC_IAR_INT_ID_MASK);
 393         if (gic_irq == GICC_INT_SPURIOUS)
 394                 goto out;
 395
 396         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
 397         if (unlikely(gic_irq < 32 || gic_irq > 1020))
 398                 handle_bad_irq(desc);
 399         else
 400                 generic_handle_irq(cascade_irq);
 401
 402  out:
 403         chained_irq_exit(chip, desc);
 404 }
 405
 406 static struct irq_chip gic_chip = {
 407         .irq_mask               = gic_mask_irq,
 408         .irq_unmask             = gic_unmask_irq,
 409         .irq_eoi                = gic_eoi_irq,
 410         .irq_set_type           = gic_set_type,
 411         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 412         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 413         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 414                                   IRQCHIP_SKIP_SET_WAKE |
 415                                   IRQCHIP_MASK_ON_SUSPEND,
 416 };
 417
 418 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 419 {
 420         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 421         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
 422                                          &gic_data[gic_nr]);
 423 }
 424
 425 static u8 gic_get_cpumask(struct gic_chip_data *gic)
 426 {
 427         void __iomem *base = gic_data_dist_base(gic);
 428         u32 mask, i;
 429
 430         for (i = mask = 0; i < 32; i += 4) {
 431                 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
 432                 mask |= mask >> 16;
 433                 mask |= mask >> 8;
 434                 if (mask)
 435                         break;
 436         }
 437
 438         if (!mask && num_possible_cpus() > 1)
 439                 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 440
 441         return mask;
 442 }
 443
 444 static void gic_cpu_if_up(struct gic_chip_data *gic)
 445 {
 446         void __iomem *cpu_base = gic_data_cpu_base(gic);
 447         u32 bypass = 0;
 448         u32 mode = 0;
 449
 450         if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
 451                 mode = GIC_CPU_CTRL_EOImodeNS;
 452
 453         /*
 454         * Preserve bypass disable bits to be written back later
 455         */
 456         bypass = readl(cpu_base + GIC_CPU_CTRL);
 457         bypass &= GICC_DIS_BYPASS_MASK;
 458
 459         writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
 460 }
 461
 462
 463 static void gic_dist_init(struct gic_chip_data *gic)
 464 {
 465         unsigned int i;
 466         u32 cpumask;
 467         unsigned int gic_irqs = gic->gic_irqs;
 468         void __iomem *base = gic_data_dist_base(gic);
 469
 470         writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
 471
 472         /*
 473          * Set all global interrupts to this CPU only.
 474          */
 475         cpumask = gic_get_cpumask(gic);
 476         cpumask |= cpumask << 8;
 477         cpumask |= cpumask << 16;
 478         for (i = 32; i < gic_irqs; i += 4)
 479                 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 480
 481         gic_dist_config(base, gic_irqs, NULL);
 482
 483         writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
 484 }
 485
 486 static int gic_cpu_init(struct gic_chip_data *gic)
 487 {
 488         void __iomem *dist_base = gic_data_dist_base(gic);
 489         void __iomem *base = gic_data_cpu_base(gic);
 490         unsigned int cpu_mask, cpu = smp_processor_id();
 491         int i;
 492
 493         /*
 494          * Setting up the CPU map is only relevant for the primary GIC
 495          * because any nested/secondary GICs do not directly interface
 496          * with the CPU(s).
 497          */
 498         if (gic == &gic_data[0]) {
 499                 /*
 500                  * Get what the GIC says our CPU mask is.
 501                  */
 502                 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
 503                         return -EINVAL;
 504
 505                 gic_check_cpu_features();
 506                 cpu_mask = gic_get_cpumask(gic);
 507                 gic_cpu_map[cpu] = cpu_mask;
 508
 509                 /*
 510                  * Clear our mask from the other map entries in case they're
 511                  * still undefined.
 512                  */
 513                 for (i = 0; i < NR_GIC_CPU_IF; i++)
 514                         if (i != cpu)
 515                                 gic_cpu_map[i] &= ~cpu_mask;
 516         }
 517
 518         gic_cpu_config(dist_base, NULL);
 519
 520         writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
 521         gic_cpu_if_up(gic);
 522
 523         return 0;
 524 }
 525
 526 int gic_cpu_if_down(unsigned int gic_nr)
 527 {
 528         void __iomem *cpu_base;
 529         u32 val = 0;
 530
 531         if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
 532                 return -EINVAL;
 533
 534         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 535         val = readl(cpu_base + GIC_CPU_CTRL);
 536         val &= ~GICC_ENABLE;
 537         writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
 538
 539         return 0;
 540 }
 541
 542 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
 543 /*
 544  * Saves the GIC distributor registers during suspend or idle.  Must be called
 545  * with interrupts disabled but before powering down the GIC.  After calling
 546  * this function, no interrupts will be delivered by the GIC, and another
 547  * platform-specific wakeup source must be enabled.
 548  */
 549 void gic_dist_save(struct gic_chip_data *gic)
 550 {
 551         unsigned int gic_irqs;
 552         void __iomem *dist_base;
 553         int i;
 554
 555         if (WARN_ON(!gic))
 556                 return;
 557
 558         gic_irqs = gic->gic_irqs;
 559         dist_base = gic_data_dist_base(gic);
 560
 561         if (!dist_base)
 562                 return;
 563
 564         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 565                 gic->saved_spi_conf[i] =
 566                         readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 567
 568         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 569                 gic->saved_spi_target[i] =
 570                         readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 571
 572         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 573                 gic->saved_spi_enable[i] =
 574                         readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 575
 576         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 577                 gic->saved_spi_active[i] =
 578                         readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 579 }
 580
 581 /*
 582  * Restores the GIC distributor registers during resume or when coming out of
 583  * idle.  Must be called before enabling interrupts.  If a level interrupt
 584  * that occured while the GIC was suspended is still present, it will be
 585  * handled normally, but any edge interrupts that occured will not be seen by
 586  * the GIC and need to be handled by the platform-specific wakeup source.
 587  */
 588 void gic_dist_restore(struct gic_chip_data *gic)
 589 {
 590         unsigned int gic_irqs;
 591         unsigned int i;
 592         void __iomem *dist_base;
 593
 594         if (WARN_ON(!gic))
 595                 return;
 596
 597         gic_irqs = gic->gic_irqs;
 598         dist_base = gic_data_dist_base(gic);
 599
 600         if (!dist_base)
 601                 return;
 602
 603         writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 604
 605         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 606                 writel_relaxed(gic->saved_spi_conf[i],
 607                         dist_base + GIC_DIST_CONFIG + i * 4);
 608
 609         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 610                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 611                         dist_base + GIC_DIST_PRI + i * 4);
 612
 613         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 614                 writel_relaxed(gic->saved_spi_target[i],
 615                         dist_base + GIC_DIST_TARGET + i * 4);
 616
 617         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 618                 writel_relaxed(GICD_INT_EN_CLR_X32,
 619                         dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 620                 writel_relaxed(gic->saved_spi_enable[i],
 621                         dist_base + GIC_DIST_ENABLE_SET + i * 4);
 622         }
 623
 624         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 625                 writel_relaxed(GICD_INT_EN_CLR_X32,
 626                         dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 627                 writel_relaxed(gic->saved_spi_active[i],
 628                         dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 629         }
 630
 631         writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
 632 }
 633
 634 void gic_cpu_save(struct gic_chip_data *gic)
 635 {
 636         int i;
 637         u32 *ptr;
 638         void __iomem *dist_base;
 639         void __iomem *cpu_base;
 640
 641         if (WARN_ON(!gic))
 642                 return;
 643
 644         dist_base = gic_data_dist_base(gic);
 645         cpu_base = gic_data_cpu_base(gic);
 646
 647         if (!dist_base || !cpu_base)
 648                 return;
 649
 650         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 651         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 652                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 653
 654         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 655         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 656                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 657
 658         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 659         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 660                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 661
 662 }
 663
 664 void gic_cpu_restore(struct gic_chip_data *gic)
 665 {
 666         int i;
 667         u32 *ptr;
 668         void __iomem *dist_base;
 669         void __iomem *cpu_base;
 670
 671         if (WARN_ON(!gic))
 672                 return;
 673
 674         dist_base = gic_data_dist_base(gic);
 675         cpu_base = gic_data_cpu_base(gic);
 676
 677         if (!dist_base || !cpu_base)
 678                 return;
 679
 680         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 681         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 682                 writel_relaxed(GICD_INT_EN_CLR_X32,
 683                                dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 684                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
 685         }
 686
 687         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 688         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 689                 writel_relaxed(GICD_INT_EN_CLR_X32,
 690                                dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 691                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 692         }
 693
 694         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 695         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 696                 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 697
 698         for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
 699                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 700                                         dist_base + GIC_DIST_PRI + i * 4);
 701
 702         writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
 703         gic_cpu_if_up(gic);
 704 }
 705
 706 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 707 {
 708         int i;
 709
 710         for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 711 #ifdef CONFIG_GIC_NON_BANKED
 712                 /* Skip over unused GICs */
 713                 if (!gic_data[i].get_base)
 714                         continue;
 715 #endif
 716                 switch (cmd) {
 717                 case CPU_PM_ENTER:
 718                         gic_cpu_save(&gic_data[i]);
 719                         break;
 720                 case CPU_PM_ENTER_FAILED:
 721                 case CPU_PM_EXIT:
 722                         gic_cpu_restore(&gic_data[i]);
 723                         break;
 724                 case CPU_CLUSTER_PM_ENTER:
 725                         gic_dist_save(&gic_data[i]);
 726                         break;
 727                 case CPU_CLUSTER_PM_ENTER_FAILED:
 728                 case CPU_CLUSTER_PM_EXIT:
 729                         gic_dist_restore(&gic_data[i]);
 730                         break;
 731                 }
 732         }
 733
 734         return NOTIFY_OK;
 735 }
 736
 737 static struct notifier_block gic_notifier_block = {
 738         .notifier_call = gic_notifier,
 739 };
 740
 741 static int gic_pm_init(struct gic_chip_data *gic)
 742 {
 743         gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 744                 sizeof(u32));
 745         if (WARN_ON(!gic->saved_ppi_enable))
 746                 return -ENOMEM;
 747
 748         gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 749                 sizeof(u32));
 750         if (WARN_ON(!gic->saved_ppi_active))
 751                 goto free_ppi_enable;
 752
 753         gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
 754                 sizeof(u32));
 755         if (WARN_ON(!gic->saved_ppi_conf))
 756                 goto free_ppi_active;
 757
 758         if (gic == &gic_data[0])
 759                 cpu_pm_register_notifier(&gic_notifier_block);
 760
 761         return 0;
 762
 763 free_ppi_active:
 764         free_percpu(gic->saved_ppi_active);
 765 free_ppi_enable:
 766         free_percpu(gic->saved_ppi_enable);
 767
 768         return -ENOMEM;
 769 }
 770 #else
 771 static int gic_pm_init(struct gic_chip_data *gic)
 772 {
 773         return 0;
 774 }
 775 #endif
 776
 777 #ifdef CONFIG_SMP
 778 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 779 {
 780         int cpu;
 781         unsigned long flags, map = 0;
 782
 783         if (unlikely(nr_cpu_ids == 1)) {
 784                 /* Only one CPU? let's do a self-IPI... */
 785                 writel_relaxed(2 << 24 | irq,
 786                                gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 787                 return;
 788         }
 789
 790         gic_lock_irqsave(flags);
 791
 792         /* Convert our logical CPU mask into a physical one. */
 793         for_each_cpu(cpu, mask)
 794                 map |= gic_cpu_map[cpu];
 795
 796         /*
 797          * Ensure that stores to Normal memory are visible to the
 798          * other CPUs before they observe us issuing the IPI.
 799          */
 800         dmb(ishst);
 801
 802         /* this always happens on GIC0 */
 803         writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 804
 805         gic_unlock_irqrestore(flags);
 806 }
 807 #endif
 808
 809 #ifdef CONFIG_BL_SWITCHER
 810 /*
 811  * gic_send_sgi - send a SGI directly to given CPU interface number
 812  *
 813  * cpu_id: the ID for the destination CPU interface
 814  * irq: the IPI number to send a SGI for
 815  */
 816 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 817 {
 818         BUG_ON(cpu_id >= NR_GIC_CPU_IF);
 819         cpu_id = 1 << cpu_id;
 820         /* this always happens on GIC0 */
 821         writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 822 }
 823
 824 /*
 825  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
 826  *
 827  * @cpu: the logical CPU number to get the GIC ID for.
 828  *
 829  * Return the CPU interface ID for the given logical CPU number,
 830  * or -1 if the CPU number is too large or the interface ID is
 831  * unknown (more than one bit set).
 832  */
 833 int gic_get_cpu_id(unsigned int cpu)
 834 {
 835         unsigned int cpu_bit;
 836
 837         if (cpu >= NR_GIC_CPU_IF)
 838                 return -1;
 839         cpu_bit = gic_cpu_map[cpu];
 840         if (cpu_bit & (cpu_bit - 1))
 841                 return -1;
 842         return __ffs(cpu_bit);
 843 }
 844
 845 /*
 846  * gic_migrate_target - migrate IRQs to another CPU interface
 847  *
 848  * @new_cpu_id: the CPU target ID to migrate IRQs to
 849  *
 850  * Migrate all peripheral interrupts with a target matching the current CPU
 851  * to the interface corresponding to @new_cpu_id.  The CPU interface mapping
 852  * is also updated.  Targets to other CPU interfaces are unchanged.
 853  * This must be called with IRQs locally disabled.
 854  */
 855 void gic_migrate_target(unsigned int new_cpu_id)
 856 {
 857         unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
 858         void __iomem *dist_base;
 859         int i, ror_val, cpu = smp_processor_id();
 860         u32 val, cur_target_mask, active_mask;
 861
 862         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 863
 864         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 865         if (!dist_base)
 866                 return;
 867         gic_irqs = gic_data[gic_nr].gic_irqs;
 868
 869         cur_cpu_id = __ffs(gic_cpu_map[cpu]);
 870         cur_target_mask = 0x01010101 << cur_cpu_id;
 871         ror_val = (cur_cpu_id - new_cpu_id) & 31;
 872
 873         gic_lock();
 874
 875         /* Update the target interface for this logical CPU */
 876         gic_cpu_map[cpu] = 1 << new_cpu_id;
 877
 878         /*
 879          * Find all the peripheral interrupts targetting the current
 880          * CPU interface and migrate them to the new CPU interface.
 881          * We skip DIST_TARGET 0 to 7 as they are read-only.
 882          */
 883         for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
 884                 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 885                 active_mask = val & cur_target_mask;
 886                 if (active_mask) {
 887                         val &= ~active_mask;
 888                         val |= ror32(active_mask, ror_val);
 889                         writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
 890                 }
 891         }
 892
 893         gic_unlock();
 894
 895         /*
 896          * Now let's migrate and clear any potential SGIs that might be
 897          * pending for us (cur_cpu_id).  Since GIC_DIST_SGI_PENDING_SET
 898          * is a banked register, we can only forward the SGI using
 899          * GIC_DIST_SOFTINT.  The original SGI source is lost but Linux
 900          * doesn't use that information anyway.
 901          *
 902          * For the same reason we do not adjust SGI source information
 903          * for previously sent SGIs by us to other CPUs either.
 904          */
 905         for (i = 0; i < 16; i += 4) {
 906                 int j;
 907                 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
 908                 if (!val)
 909                         continue;
 910                 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
 911                 for (j = i; j < i + 4; j++) {
 912                         if (val & 0xff)
 913                                 writel_relaxed((1 << (new_cpu_id + 16)) | j,
 914                                                 dist_base + GIC_DIST_SOFTINT);
 915                         val >>= 8;
 916                 }
 917         }
 918 }
 919
 920 /*
 921  * gic_get_sgir_physaddr - get the physical address for the SGI register
 922  *
 923  * REturn the physical address of the SGI register to be used
 924  * by some early assembly code when the kernel is not yet available.
 925  */
 926 static unsigned long gic_dist_physaddr;
 927
 928 unsigned long gic_get_sgir_physaddr(void)
 929 {
 930         if (!gic_dist_physaddr)
 931                 return 0;
 932         return gic_dist_physaddr + GIC_DIST_SOFTINT;
 933 }
 934
 935 static void __init gic_init_physaddr(struct device_node *node)
 936 {
 937         struct resource res;
 938         if (of_address_to_resource(node, 0, &res) == 0) {
 939                 gic_dist_physaddr = res.start;
 940                 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
 941         }
 942 }
 943
 944 #else
 945 #define gic_init_physaddr(node)  do { } while (0)
 946 #endif
 947
 948 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 949                                 irq_hw_number_t hw)
 950 {
 951         struct gic_chip_data *gic = d->host_data;
 952
 953         if (hw < 32) {
 954                 irq_set_percpu_devid(irq);
 955                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 956                                     handle_percpu_devid_irq, NULL, NULL);
 957                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 958         } else {
 959                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 960                                     handle_fasteoi_irq, NULL, NULL);
 961                 irq_set_probe(irq);
 962         }
 963         return 0;
 964 }
 965
 966 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 967 {
 968 }
 969
 970 static int gic_irq_domain_translate(struct irq_domain *d,
 971                                     struct irq_fwspec *fwspec,
 972                                     unsigned long *hwirq,
 973                                     unsigned int *type)
 974 {
 975         if (is_of_node(fwspec->fwnode)) {
 976                 if (fwspec->param_count < 3)
 977                         return -EINVAL;
 978
 979                 /* Get the interrupt number and add 16 to skip over SGIs */
 980                 *hwirq = fwspec->param[1] + 16;
 981
 982                 /*
 983                  * For SPIs, we need to add 16 more to get the GIC irq
 984                  * ID number
 985                  */
 986                 if (!fwspec->param[0])
 987                         *hwirq += 16;
 988
 989                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
 990                 return 0;
 991         }
 992
 993         if (is_fwnode_irqchip(fwspec->fwnode)) {
 994                 if(fwspec->param_count != 2)
 995                         return -EINVAL;
 996
 997                 *hwirq = fwspec->param[0];
 998                 *type = fwspec->param[1];
 999                 return 0;
1000         }
1001
1002         return -EINVAL;
1003 }
1004
1005 static int gic_starting_cpu(unsigned int cpu)
1006 {
1007         gic_cpu_init(&gic_data[0]);
1008         return 0;
1009 }
1010
1011 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1012                                 unsigned int nr_irqs, void *arg)
1013 {
1014         int i, ret;
1015         irq_hw_number_t hwirq;
1016         unsigned int type = IRQ_TYPE_NONE;
1017         struct irq_fwspec *fwspec = arg;
1018
1019         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1020         if (ret)
1021                 return ret;
1022
1023         for (i = 0; i < nr_irqs; i++)
1024                 gic_irq_domain_map(domain, virq + i, hwirq + i);
1025
1026         return 0;
1027 }
1028
1029 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1030         .translate = gic_irq_domain_translate,
1031         .alloc = gic_irq_domain_alloc,
1032         .free = irq_domain_free_irqs_top,
1033 };
1034
1035 static const struct irq_domain_ops gic_irq_domain_ops = {
1036         .map = gic_irq_domain_map,
1037         .unmap = gic_irq_domain_unmap,
1038 };
1039
1040 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1041                           const char *name, bool use_eoimode1)
1042 {
1043         /* Initialize irq_chip */
1044         gic->chip = gic_chip;
1045         gic->chip.name = name;
1046         gic->chip.parent_device = dev;
1047
1048         if (use_eoimode1) {
1049                 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1050                 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1051                 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1052         }
1053
1054 #ifdef CONFIG_SMP
1055         if (gic == &gic_data[0])
1056                 gic->chip.irq_set_affinity = gic_set_affinity;
1057 #endif
1058 }
1059
1060 static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1061                           struct fwnode_handle *handle)
1062 {
1063         irq_hw_number_t hwirq_base;
1064         int gic_irqs, irq_base, ret;
1065
1066         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1067                 /* Frankein-GIC without banked registers... */
1068                 unsigned int cpu;
1069
1070                 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1071                 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1072                 if (WARN_ON(!gic->dist_base.percpu_base ||
1073                             !gic->cpu_base.percpu_base)) {
1074                         ret = -ENOMEM;
1075                         goto error;
1076                 }
1077
1078                 for_each_possible_cpu(cpu) {
1079                         u32 mpidr = cpu_logical_map(cpu);
1080                         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1081                         unsigned long offset = gic->percpu_offset * core_id;
1082                         *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1083                                 gic->raw_dist_base + offset;
1084                         *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1085                                 gic->raw_cpu_base + offset;
1086                 }
1087
1088                 gic_set_base_accessor(gic, gic_get_percpu_base);
1089         } else {
1090                 /* Normal, sane GIC... */
1091                 WARN(gic->percpu_offset,
1092                      "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1093                      gic->percpu_offset);
1094                 gic->dist_base.common_base = gic->raw_dist_base;
1095                 gic->cpu_base.common_base = gic->raw_cpu_base;
1096                 gic_set_base_accessor(gic, gic_get_common_base);
1097         }
1098
1099         /*
1100          * Find out how many interrupts are supported.
1101          * The GIC only supports up to 1020 interrupt sources.
1102          */
1103         gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1104         gic_irqs = (gic_irqs + 1) * 32;
1105         if (gic_irqs > 1020)
1106                 gic_irqs = 1020;
1107         gic->gic_irqs = gic_irqs;
1108
1109         if (handle) {           /* DT/ACPI */
1110                 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1111                                                        &gic_irq_domain_hierarchy_ops,
1112                                                        gic);
1113         } else {                /* Legacy support */
1114                 /*
1115                  * For primary GICs, skip over SGIs.
1116                  * For secondary GICs, skip over PPIs, too.
1117                  */
1118                 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1119                         hwirq_base = 16;
1120                         if (irq_start != -1)
1121                                 irq_start = (irq_start & ~31) + 16;
1122                 } else {
1123                         hwirq_base = 32;
1124                 }
1125
1126                 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1127
1128                 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1129                                            numa_node_id());
1130                 if (irq_base < 0) {
1131                         WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1132                              irq_start);
1133                         irq_base = irq_start;
1134                 }
1135
1136                 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1137                                         hwirq_base, &gic_irq_domain_ops, gic);
1138         }
1139
1140         if (WARN_ON(!gic->domain)) {
1141                 ret = -ENODEV;
1142                 goto error;
1143         }
1144
1145         gic_dist_init(gic);
1146         ret = gic_cpu_init(gic);
1147         if (ret)
1148                 goto error;
1149
1150         ret = gic_pm_init(gic);
1151         if (ret)
1152                 goto error;
1153
1154         return 0;
1155
1156 error:
1157         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1158                 free_percpu(gic->dist_base.percpu_base);
1159                 free_percpu(gic->cpu_base.percpu_base);
1160         }
1161
1162         return ret;
1163 }
1164
1165 static int __init __gic_init_bases(struct gic_chip_data *gic,
1166                                    int irq_start,
1167                                    struct fwnode_handle *handle)
1168 {
1169         char *name;
1170         int i, ret;
1171
1172         if (WARN_ON(!gic || gic->domain))
1173                 return -EINVAL;
1174
1175         if (gic == &gic_data[0]) {
1176                 /*
1177                  * Initialize the CPU interface map to all CPUs.
1178                  * It will be refined as each CPU probes its ID.
1179                  * This is only necessary for the primary GIC.
1180                  */
1181                 for (i = 0; i < NR_GIC_CPU_IF; i++)
1182                         gic_cpu_map[i] = 0xff;
1183 #ifdef CONFIG_SMP
1184                 set_smp_cross_call(gic_raise_softirq);
1185 #endif
1186                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1187                                           "AP_IRQ_GIC_STARTING",
1188                                           gic_starting_cpu, NULL);
1189                 set_handle_irq(gic_handle_irq);
1190                 if (static_key_true(&supports_deactivate))
1191                         pr_info("GIC: Using split EOI/Deactivate mode\n");
1192         }
1193
1194         if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1195                 name = kasprintf(GFP_KERNEL, "GICv2");
1196                 gic_init_chip(gic, NULL, name, true);
1197         } else {
1198                 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1199                 gic_init_chip(gic, NULL, name, false);
1200         }
1201
1202         ret = gic_init_bases(gic, irq_start, handle);
1203         if (ret)
1204                 kfree(name);
1205
1206         return ret;
1207 }
1208
1209 void __init gic_init(unsigned int gic_nr, int irq_start,
1210                      void __iomem *dist_base, void __iomem *cpu_base)
1211 {
1212         struct gic_chip_data *gic;
1213
1214         if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1215                 return;
1216
1217         /*
1218          * Non-DT/ACPI systems won't run a hypervisor, so let's not
1219          * bother with these...
1220          */
1221         static_key_slow_dec(&supports_deactivate);
1222
1223         gic = &gic_data[gic_nr];
1224         gic->raw_dist_base = dist_base;
1225         gic->raw_cpu_base = cpu_base;
1226
1227         __gic_init_bases(gic, irq_start, NULL);
1228 }
1229
1230 static void gic_teardown(struct gic_chip_data *gic)
1231 {
1232         if (WARN_ON(!gic))
1233                 return;
1234
1235         if (gic->raw_dist_base)
1236                 iounmap(gic->raw_dist_base);
1237         if (gic->raw_cpu_base)
1238                 iounmap(gic->raw_cpu_base);
1239 }
1240
1241 #ifdef CONFIG_OF
1242 static int gic_cnt __initdata;
1243
1244 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1245 {
1246         struct resource cpuif_res;
1247
1248         of_address_to_resource(node, 1, &cpuif_res);
1249
1250         if (!is_hyp_mode_available())
1251                 return false;
1252         if (resource_size(&cpuif_res) < SZ_8K)
1253                 return false;
1254         if (resource_size(&cpuif_res) == SZ_128K) {
1255                 u32 val_low, val_high;
1256
1257                 /*
1258                  * Verify that we have the first 4kB of a GIC400
1259                  * aliased over the first 64kB by checking the
1260                  * GICC_IIDR register on both ends.
1261                  */
1262                 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1263                 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1264                 if ((val_low & 0xffff0fff) != 0x0202043B ||
1265                     val_low != val_high)
1266                         return false;
1267
1268                 /*
1269                  * Move the base up by 60kB, so that we have a 8kB
1270                  * contiguous region, which allows us to use GICC_DIR
1271                  * at its normal offset. Please pass me that bucket.
1272                  */
1273                 *base += 0xf000;
1274                 cpuif_res.start += 0xf000;
1275                 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1276                         &cpuif_res.start);
1277         }
1278
1279         return true;
1280 }
1281
1282 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1283 {
1284         if (!gic || !node)
1285                 return -EINVAL;
1286
1287         gic->raw_dist_base = of_iomap(node, 0);
1288         if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1289                 goto error;
1290
1291         gic->raw_cpu_base = of_iomap(node, 1);
1292         if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1293                 goto error;
1294
1295         if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1296                 gic->percpu_offset = 0;
1297
1298         return 0;
1299
1300 error:
1301         gic_teardown(gic);
1302
1303         return -ENOMEM;
1304 }
1305
1306 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1307 {
1308         int ret;
1309
1310         if (!dev || !dev->of_node || !gic || !irq)
1311                 return -EINVAL;
1312
1313         *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1314         if (!*gic)
1315                 return -ENOMEM;
1316
1317         gic_init_chip(*gic, dev, dev->of_node->name, false);
1318
1319         ret = gic_of_setup(*gic, dev->of_node);
1320         if (ret)
1321                 return ret;
1322
1323         ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1324         if (ret) {
1325                 gic_teardown(*gic);
1326                 return ret;
1327         }
1328
1329         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1330
1331         return 0;
1332 }
1333
1334 static void __init gic_of_setup_kvm_info(struct device_node *node)
1335 {
1336         int ret;
1337         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1338         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1339
1340         gic_v2_kvm_info.type = GIC_V2;
1341
1342         gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1343         if (!gic_v2_kvm_info.maint_irq)
1344                 return;
1345
1346         ret = of_address_to_resource(node, 2, vctrl_res);
1347         if (ret)
1348                 return;
1349
1350         ret = of_address_to_resource(node, 3, vcpu_res);
1351         if (ret)
1352                 return;
1353
1354         gic_set_kvm_info(&gic_v2_kvm_info);
1355 }
1356
1357 int __init
1358 gic_of_init(struct device_node *node, struct device_node *parent)
1359 {
1360         struct gic_chip_data *gic;
1361         int irq, ret;
1362
1363         if (WARN_ON(!node))
1364                 return -ENODEV;
1365
1366         if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1367                 return -EINVAL;
1368
1369         gic = &gic_data[gic_cnt];
1370
1371         ret = gic_of_setup(gic, node);
1372         if (ret)
1373                 return ret;
1374
1375         /*
1376          * Disable split EOI/Deactivate if either HYP is not available
1377          * or the CPU interface is too small.
1378          */
1379         if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1380                 static_key_slow_dec(&supports_deactivate);
1381
1382         ret = __gic_init_bases(gic, -1, &node->fwnode);
1383         if (ret) {
1384                 gic_teardown(gic);
1385                 return ret;
1386         }
1387
1388         if (!gic_cnt) {
1389                 gic_init_physaddr(node);
1390                 gic_of_setup_kvm_info(node);
1391         }
1392
1393         if (parent) {
1394                 irq = irq_of_parse_and_map(node, 0);
1395                 gic_cascade_irq(gic_cnt, irq);
1396         }
1397
1398         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1399                 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1400
1401         gic_cnt++;
1402         return 0;
1403 }
1404 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1405 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1406 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1407 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1408 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1409 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1410 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1411 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1412 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1413 #else
1414 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1415 {
1416         return -ENOTSUPP;
1417 }
1418 #endif
1419
1420 #ifdef CONFIG_ACPI
1421 static struct
1422 {
1423         phys_addr_t cpu_phys_base;
1424         u32 maint_irq;
1425         int maint_irq_mode;
1426         phys_addr_t vctrl_base;
1427         phys_addr_t vcpu_base;
1428 } acpi_data __initdata;
1429
1430 static int __init
1431 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1432                         const unsigned long end)
1433 {
1434         struct acpi_madt_generic_interrupt *processor;
1435         phys_addr_t gic_cpu_base;
1436         static int cpu_base_assigned;
1437
1438         processor = (struct acpi_madt_generic_interrupt *)header;
1439
1440         if (BAD_MADT_GICC_ENTRY(processor, end))
1441                 return -EINVAL;
1442
1443         /*
1444          * There is no support for non-banked GICv1/2 register in ACPI spec.
1445          * All CPU interface addresses have to be the same.
1446          */
1447         gic_cpu_base = processor->base_address;
1448         if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1449                 return -EINVAL;
1450
1451         acpi_data.cpu_phys_base = gic_cpu_base;
1452         acpi_data.maint_irq = processor->vgic_interrupt;
1453         acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1454                                     ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1455         acpi_data.vctrl_base = processor->gich_base_address;
1456         acpi_data.vcpu_base = processor->gicv_base_address;
1457
1458         cpu_base_assigned = 1;
1459         return 0;
1460 }
1461
1462 /* The things you have to do to just *count* something... */
1463 static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1464                                   const unsigned long end)
1465 {
1466         return 0;
1467 }
1468
1469 static bool __init acpi_gic_redist_is_present(void)
1470 {
1471         return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1472                                      acpi_dummy_func, 0) > 0;
1473 }
1474
1475 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1476                                      struct acpi_probe_entry *ape)
1477 {
1478         struct acpi_madt_generic_distributor *dist;
1479         dist = (struct acpi_madt_generic_distributor *)header;
1480
1481         return (dist->version == ape->driver_data &&
1482                 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1483                  !acpi_gic_redist_is_present()));
1484 }
1485
1486 #define ACPI_GICV2_DIST_MEM_SIZE        (SZ_4K)
1487 #define ACPI_GIC_CPU_IF_MEM_SIZE        (SZ_8K)
1488 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1489 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1490
1491 static void __init gic_acpi_setup_kvm_info(void)
1492 {
1493         int irq;
1494         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1495         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1496
1497         gic_v2_kvm_info.type = GIC_V2;
1498
1499         if (!acpi_data.vctrl_base)
1500                 return;
1501
1502         vctrl_res->flags = IORESOURCE_MEM;
1503         vctrl_res->start = acpi_data.vctrl_base;
1504         vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1505
1506         if (!acpi_data.vcpu_base)
1507                 return;
1508
1509         vcpu_res->flags = IORESOURCE_MEM;
1510         vcpu_res->start = acpi_data.vcpu_base;
1511         vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1512
1513         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1514                                 acpi_data.maint_irq_mode,
1515                                 ACPI_ACTIVE_HIGH);
1516         if (irq <= 0)
1517                 return;
1518
1519         gic_v2_kvm_info.maint_irq = irq;
1520
1521         gic_set_kvm_info(&gic_v2_kvm_info);
1522 }
1523
1524 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1525                                    const unsigned long end)
1526 {
1527         struct acpi_madt_generic_distributor *dist;
1528         struct fwnode_handle *domain_handle;
1529         struct gic_chip_data *gic = &gic_data[0];
1530         int count, ret;
1531
1532         /* Collect CPU base addresses */
1533         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1534                                       gic_acpi_parse_madt_cpu, 0);
1535         if (count <= 0) {
1536                 pr_err("No valid GICC entries exist\n");
1537                 return -EINVAL;
1538         }
1539
1540         gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1541         if (!gic->raw_cpu_base) {
1542                 pr_err("Unable to map GICC registers\n");
1543                 return -ENOMEM;
1544         }
1545
1546         dist = (struct acpi_madt_generic_distributor *)header;
1547         gic->raw_dist_base = ioremap(dist->base_address,
1548                                      ACPI_GICV2_DIST_MEM_SIZE);
1549         if (!gic->raw_dist_base) {
1550                 pr_err("Unable to map GICD registers\n");
1551                 gic_teardown(gic);
1552                 return -ENOMEM;
1553         }
1554
1555         /*
1556          * Disable split EOI/Deactivate if HYP is not available. ACPI
1557          * guarantees that we'll always have a GICv2, so the CPU
1558          * interface will always be the right size.
1559          */
1560         if (!is_hyp_mode_available())
1561                 static_key_slow_dec(&supports_deactivate);
1562
1563         /*
1564          * Initialize GIC instance zero (no multi-GIC support).
1565          */
1566         domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1567         if (!domain_handle) {
1568                 pr_err("Unable to allocate domain handle\n");
1569                 gic_teardown(gic);
1570                 return -ENOMEM;
1571         }
1572
1573         ret = __gic_init_bases(gic, -1, domain_handle);
1574         if (ret) {
1575                 pr_err("Failed to initialise GIC\n");
1576                 irq_domain_free_fwnode(domain_handle);
1577                 gic_teardown(gic);
1578                 return ret;
1579         }
1580
1581         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1582
1583         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1584                 gicv2m_init(NULL, gic_data[0].domain);
1585
1586         gic_acpi_setup_kvm_info();
1587
1588         return 0;
1589 }
1590 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1591                      gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1592                      gic_v2_acpi_init);
1593 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1594                      gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1595                      gic_v2_acpi_init);
1596 #endif