1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #define pr_fmt(fmt) "GICv3: " fmt
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/percpu.h>
19 #include <linux/refcount.h>
20 #include <linux/slab.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
27 #include <asm/cputype.h>
28 #include <asm/exception.h>
29 #include <asm/smp_plat.h>
32 #include "irq-gic-common.h"
34 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
38 #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2)
40 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
42 struct redist_region {
43 void __iomem *redist_base;
44 phys_addr_t phys_base;
48 struct gic_chip_data {
49 struct fwnode_handle *fwnode;
50 void __iomem *dist_base;
51 struct redist_region *redist_regions;
53 struct irq_domain *domain;
55 u32 nr_redist_regions;
59 struct partition_desc **ppi_descs;
62 static struct gic_chip_data gic_data __read_mostly;
63 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
65 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
66 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
67 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
70 * The behaviours of RPR and PMR registers differ depending on the value of
71 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
72 * distributor and redistributors depends on whether security is enabled in the
75 * When security is enabled, non-secure priority values from the (re)distributor
76 * are presented to the GIC CPUIF as follow:
77 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
79 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
80 * EL1 are subject to a similar operation thus matching the priorities presented
81 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
82 * these values are unchanched by the GIC.
84 * see GICv3/GICv4 Architecture Specification (IHI0069D):
85 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
87 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
90 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
93 * Global static key controlling whether an update to PMR allowing more
94 * interrupts requires to be propagated to the redistributor (DSB SY).
95 * And this needs to be exported for modules to be able to enable
98 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
99 EXPORT_SYMBOL(gic_pmr_sync);
101 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
102 EXPORT_SYMBOL(gic_nonsecure_priorities);
105 * When the Non-secure world has access to group 0 interrupts (as a
106 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
107 * return the Distributor's view of the interrupt priority.
109 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
110 * written by software is moved to the Non-secure range by the Distributor.
112 * If both are true (which is when gic_nonsecure_priorities gets enabled),
113 * we need to shift down the priority programmed by software to match it
114 * against the value returned by ICC_RPR_EL1.
116 #define GICD_INT_RPR_PRI(priority) \
118 u32 __priority = (priority); \
119 if (static_branch_unlikely(&gic_nonsecure_priorities)) \
120 __priority = 0x80 | (__priority >> 1); \
125 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
126 static refcount_t *ppi_nmi_refs;
128 static struct gic_kvm_info gic_v3_kvm_info;
129 static DEFINE_PER_CPU(bool, has_rss);
131 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
132 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
133 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
134 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
136 /* Our default, arbitrary priority value. Linux only uses one anyway. */
137 #define DEFAULT_PMR_VALUE 0xf0
139 enum gic_intid_range {
149 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
158 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
160 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
162 case 8192 ... GENMASK(23, 0):
165 return __INVALID_RANGE__;
169 static enum gic_intid_range get_intid_range(struct irq_data *d)
171 return __get_intid_range(d->hwirq);
174 static inline unsigned int gic_irq(struct irq_data *d)
179 static inline bool gic_irq_in_rdist(struct irq_data *d)
181 switch (get_intid_range(d)) {
191 static inline void __iomem *gic_dist_base(struct irq_data *d)
193 switch (get_intid_range(d)) {
197 /* SGI+PPI -> SGI_base for this CPU */
198 return gic_data_rdist_sgi_base();
202 /* SPI -> dist_base */
203 return gic_data.dist_base;
210 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
212 u32 count = 1000000; /* 1s! */
214 while (readl_relaxed(base + GICD_CTLR) & bit) {
217 pr_err_ratelimited("RWP timeout, gone fishing\n");
225 /* Wait for completion of a distributor change */
226 static void gic_dist_wait_for_rwp(void)
228 gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
231 /* Wait for completion of a redistributor change */
232 static void gic_redist_wait_for_rwp(void)
234 gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
239 static u64 __maybe_unused gic_read_iar(void)
241 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
242 return gic_read_iar_cavium_thunderx();
244 return gic_read_iar_common();
248 static void gic_enable_redist(bool enable)
251 u32 count = 1000000; /* 1s! */
254 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
257 rbase = gic_data_rdist_rd_base();
259 val = readl_relaxed(rbase + GICR_WAKER);
261 /* Wake up this CPU redistributor */
262 val &= ~GICR_WAKER_ProcessorSleep;
264 val |= GICR_WAKER_ProcessorSleep;
265 writel_relaxed(val, rbase + GICR_WAKER);
267 if (!enable) { /* Check that GICR_WAKER is writeable */
268 val = readl_relaxed(rbase + GICR_WAKER);
269 if (!(val & GICR_WAKER_ProcessorSleep))
270 return; /* No PM support in this redistributor */
274 val = readl_relaxed(rbase + GICR_WAKER);
275 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
281 pr_err_ratelimited("redistributor failed to %s...\n",
282 enable ? "wakeup" : "sleep");
286 * Routines to disable, enable, EOI and route interrupts
288 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
290 switch (get_intid_range(d)) {
298 * Contrary to the ESPI range, the EPPI range is contiguous
299 * to the PPI range in the registers, so let's adjust the
300 * displacement accordingly. Consistency is overrated.
302 *index = d->hwirq - EPPI_BASE_INTID + 32;
305 *index = d->hwirq - ESPI_BASE_INTID;
308 return GICD_ISENABLERnE;
310 return GICD_ICENABLERnE;
312 return GICD_ISPENDRnE;
314 return GICD_ICPENDRnE;
316 return GICD_ISACTIVERnE;
318 return GICD_ICACTIVERnE;
319 case GICD_IPRIORITYR:
320 return GICD_IPRIORITYRnE;
324 return GICD_IROUTERnE;
338 static int gic_peek_irq(struct irq_data *d, u32 offset)
343 offset = convert_offset_index(d, offset, &index);
344 mask = 1 << (index % 32);
346 if (gic_irq_in_rdist(d))
347 base = gic_data_rdist_sgi_base();
349 base = gic_data.dist_base;
351 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
354 static void gic_poke_irq(struct irq_data *d, u32 offset)
356 void (*rwp_wait)(void);
360 offset = convert_offset_index(d, offset, &index);
361 mask = 1 << (index % 32);
363 if (gic_irq_in_rdist(d)) {
364 base = gic_data_rdist_sgi_base();
365 rwp_wait = gic_redist_wait_for_rwp;
367 base = gic_data.dist_base;
368 rwp_wait = gic_dist_wait_for_rwp;
371 writel_relaxed(mask, base + offset + (index / 32) * 4);
375 static void gic_mask_irq(struct irq_data *d)
377 gic_poke_irq(d, GICD_ICENABLER);
380 static void gic_eoimode1_mask_irq(struct irq_data *d)
384 * When masking a forwarded interrupt, make sure it is
385 * deactivated as well.
387 * This ensures that an interrupt that is getting
388 * disabled/masked will not get "stuck", because there is
389 * noone to deactivate it (guest is being terminated).
391 if (irqd_is_forwarded_to_vcpu(d))
392 gic_poke_irq(d, GICD_ICACTIVER);
395 static void gic_unmask_irq(struct irq_data *d)
397 gic_poke_irq(d, GICD_ISENABLER);
400 static inline bool gic_supports_nmi(void)
402 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
403 static_branch_likely(&supports_pseudo_nmis);
406 static int gic_irq_set_irqchip_state(struct irq_data *d,
407 enum irqchip_irq_state which, bool val)
411 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
415 case IRQCHIP_STATE_PENDING:
416 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
419 case IRQCHIP_STATE_ACTIVE:
420 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
423 case IRQCHIP_STATE_MASKED:
424 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
431 gic_poke_irq(d, reg);
435 static int gic_irq_get_irqchip_state(struct irq_data *d,
436 enum irqchip_irq_state which, bool *val)
438 if (d->hwirq >= 8192) /* PPI/SPI only */
442 case IRQCHIP_STATE_PENDING:
443 *val = gic_peek_irq(d, GICD_ISPENDR);
446 case IRQCHIP_STATE_ACTIVE:
447 *val = gic_peek_irq(d, GICD_ISACTIVER);
450 case IRQCHIP_STATE_MASKED:
451 *val = !gic_peek_irq(d, GICD_ISENABLER);
461 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
463 void __iomem *base = gic_dist_base(d);
466 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
468 writeb_relaxed(prio, base + offset + index);
471 static u32 gic_get_ppi_index(struct irq_data *d)
473 switch (get_intid_range(d)) {
475 return d->hwirq - 16;
477 return d->hwirq - EPPI_BASE_INTID + 16;
483 static int gic_irq_nmi_setup(struct irq_data *d)
485 struct irq_desc *desc = irq_to_desc(d->irq);
487 if (!gic_supports_nmi())
490 if (gic_peek_irq(d, GICD_ISENABLER)) {
491 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
496 * A secondary irq_chip should be in charge of LPI request,
497 * it should not be possible to get there
499 if (WARN_ON(gic_irq(d) >= 8192))
502 /* desc lock should already be held */
503 if (gic_irq_in_rdist(d)) {
504 u32 idx = gic_get_ppi_index(d);
506 /* Setting up PPI as NMI, only switch handler for first NMI */
507 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
508 refcount_set(&ppi_nmi_refs[idx], 1);
509 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
512 desc->handle_irq = handle_fasteoi_nmi;
515 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
520 static void gic_irq_nmi_teardown(struct irq_data *d)
522 struct irq_desc *desc = irq_to_desc(d->irq);
524 if (WARN_ON(!gic_supports_nmi()))
527 if (gic_peek_irq(d, GICD_ISENABLER)) {
528 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
533 * A secondary irq_chip should be in charge of LPI request,
534 * it should not be possible to get there
536 if (WARN_ON(gic_irq(d) >= 8192))
539 /* desc lock should already be held */
540 if (gic_irq_in_rdist(d)) {
541 u32 idx = gic_get_ppi_index(d);
543 /* Tearing down NMI, only switch handler for last NMI */
544 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
545 desc->handle_irq = handle_percpu_devid_irq;
547 desc->handle_irq = handle_fasteoi_irq;
550 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
553 static void gic_eoi_irq(struct irq_data *d)
555 gic_write_eoir(gic_irq(d));
558 static void gic_eoimode1_eoi_irq(struct irq_data *d)
561 * No need to deactivate an LPI, or an interrupt that
562 * is is getting forwarded to a vcpu.
564 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
566 gic_write_dir(gic_irq(d));
569 static int gic_set_type(struct irq_data *d, unsigned int type)
571 enum gic_intid_range range;
572 unsigned int irq = gic_irq(d);
573 void (*rwp_wait)(void);
578 range = get_intid_range(d);
580 /* Interrupt configuration for SGIs can't be changed */
581 if (range == SGI_RANGE)
582 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
584 /* SPIs have restrictions on the supported types */
585 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
586 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
589 if (gic_irq_in_rdist(d)) {
590 base = gic_data_rdist_sgi_base();
591 rwp_wait = gic_redist_wait_for_rwp;
593 base = gic_data.dist_base;
594 rwp_wait = gic_dist_wait_for_rwp;
597 offset = convert_offset_index(d, GICD_ICFGR, &index);
599 ret = gic_configure_irq(index, type, base + offset, rwp_wait);
600 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
601 /* Misconfigured PPIs are usually not fatal */
602 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
609 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
611 if (get_intid_range(d) == SGI_RANGE)
615 irqd_set_forwarded_to_vcpu(d);
617 irqd_clr_forwarded_to_vcpu(d);
621 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
625 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
626 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
627 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
628 MPIDR_AFFINITY_LEVEL(mpidr, 0));
633 static void gic_deactivate_unhandled(u32 irqnr)
635 if (static_branch_likely(&supports_deactivate_key)) {
637 gic_write_dir(irqnr);
639 gic_write_eoir(irqnr);
643 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
645 bool irqs_enabled = interrupts_enabled(regs);
651 if (static_branch_likely(&supports_deactivate_key))
652 gic_write_eoir(irqnr);
654 * Leave the PSR.I bit set to prevent other NMIs to be
655 * received while handling this one.
656 * PSR.I will be restored when we ERET to the
657 * interrupted context.
659 err = handle_domain_nmi(gic_data.domain, irqnr, regs);
661 gic_deactivate_unhandled(irqnr);
667 static u32 do_read_iar(struct pt_regs *regs)
671 if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
675 * We were in a context with IRQs disabled. However, the
676 * entry code has set PMR to a value that allows any
677 * interrupt to be acknowledged, and not just NMIs. This can
678 * lead to surprising effects if the NMI has been retired in
679 * the meantime, and that there is an IRQ pending. The IRQ
680 * would then be taken in NMI context, something that nobody
681 * wants to debug twice.
683 * Until we sort this, drop PMR again to a level that will
684 * actually only allow NMIs before reading IAR, and then
685 * restore it to what it was.
687 pmr = gic_read_pmr();
691 iar = gic_read_iar();
695 iar = gic_read_iar();
701 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
705 irqnr = do_read_iar(regs);
707 /* Check for special IDs first */
708 if ((irqnr >= 1020 && irqnr <= 1023))
711 if (gic_supports_nmi() &&
712 unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
713 gic_handle_nmi(irqnr, regs);
717 if (gic_prio_masking_enabled()) {
719 gic_arch_enable_irqs();
722 if (static_branch_likely(&supports_deactivate_key))
723 gic_write_eoir(irqnr);
727 if (handle_domain_irq(gic_data.domain, irqnr, regs)) {
728 WARN_ONCE(true, "Unexpected interrupt received!\n");
729 gic_deactivate_unhandled(irqnr);
733 static u32 gic_get_pribits(void)
737 pribits = gic_read_ctlr();
738 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
739 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
745 static bool gic_has_group0(void)
750 old_pmr = gic_read_pmr();
753 * Let's find out if Group0 is under control of EL3 or not by
754 * setting the highest possible, non-zero priority in PMR.
756 * If SCR_EL3.FIQ is set, the priority gets shifted down in
757 * order for the CPU interface to set bit 7, and keep the
758 * actual priority in the non-secure range. In the process, it
759 * looses the least significant bit and the actual priority
760 * becomes 0x80. Reading it back returns 0, indicating that
761 * we're don't have access to Group0.
763 gic_write_pmr(BIT(8 - gic_get_pribits()));
764 val = gic_read_pmr();
766 gic_write_pmr(old_pmr);
771 static void __init gic_dist_init(void)
775 void __iomem *base = gic_data.dist_base;
778 /* Disable the distributor */
779 writel_relaxed(0, base + GICD_CTLR);
780 gic_dist_wait_for_rwp();
783 * Configure SPIs as non-secure Group-1. This will only matter
784 * if the GIC only has a single security state. This will not
785 * do the right thing if the kernel is running in secure mode,
786 * but that's not the intended use case anyway.
788 for (i = 32; i < GIC_LINE_NR; i += 32)
789 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
791 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
792 for (i = 0; i < GIC_ESPI_NR; i += 32) {
793 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
794 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
797 for (i = 0; i < GIC_ESPI_NR; i += 32)
798 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
800 for (i = 0; i < GIC_ESPI_NR; i += 16)
801 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
803 for (i = 0; i < GIC_ESPI_NR; i += 4)
804 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
806 /* Now do the common stuff, and wait for the distributor to drain */
807 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
809 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
810 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
811 pr_info("Enabling SGIs without active state\n");
812 val |= GICD_CTLR_nASSGIreq;
815 /* Enable distributor with ARE, Group1 */
816 writel_relaxed(val, base + GICD_CTLR);
819 * Set all global interrupts to the boot CPU only. ARE must be
822 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
823 for (i = 32; i < GIC_LINE_NR; i++)
824 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
826 for (i = 0; i < GIC_ESPI_NR; i++)
827 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
830 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
835 for (i = 0; i < gic_data.nr_redist_regions; i++) {
836 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
840 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
841 if (reg != GIC_PIDR2_ARCH_GICv3 &&
842 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
843 pr_warn("No redistributor present @%p\n", ptr);
848 typer = gic_read_typer(ptr + GICR_TYPER);
849 ret = fn(gic_data.redist_regions + i, ptr);
853 if (gic_data.redist_regions[i].single_redist)
856 if (gic_data.redist_stride) {
857 ptr += gic_data.redist_stride;
859 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
860 if (typer & GICR_TYPER_VLPIS)
861 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
863 } while (!(typer & GICR_TYPER_LAST));
866 return ret ? -ENODEV : 0;
869 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
871 unsigned long mpidr = cpu_logical_map(smp_processor_id());
876 * Convert affinity to a 32bit value that can be matched to
877 * GICR_TYPER bits [63:32].
879 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
880 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
881 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
882 MPIDR_AFFINITY_LEVEL(mpidr, 0));
884 typer = gic_read_typer(ptr + GICR_TYPER);
885 if ((typer >> 32) == aff) {
886 u64 offset = ptr - region->redist_base;
887 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
888 gic_data_rdist_rd_base() = ptr;
889 gic_data_rdist()->phys_base = region->phys_base + offset;
891 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
892 smp_processor_id(), mpidr,
893 (int)(region - gic_data.redist_regions),
894 &gic_data_rdist()->phys_base);
902 static int gic_populate_rdist(void)
904 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
907 /* We couldn't even deal with ourselves... */
908 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
910 (unsigned long)cpu_logical_map(smp_processor_id()));
914 static int __gic_update_rdist_properties(struct redist_region *region,
917 u64 typer = gic_read_typer(ptr + GICR_TYPER);
919 /* Boot-time cleanip */
920 if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
923 /* Deactivate any present vPE */
924 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
925 if (val & GICR_VPENDBASER_Valid)
926 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
927 ptr + SZ_128K + GICR_VPENDBASER);
929 /* Mark the VPE table as invalid */
930 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
931 val &= ~GICR_VPROPBASER_4_1_VALID;
932 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
935 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
937 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
938 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
939 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
940 gic_data.rdists.has_rvpeid);
941 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
943 /* Detect non-sensical configurations */
944 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
945 gic_data.rdists.has_direct_lpi = false;
946 gic_data.rdists.has_vlpis = false;
947 gic_data.rdists.has_rvpeid = false;
950 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
955 static void gic_update_rdist_properties(void)
957 gic_data.ppi_nr = UINT_MAX;
958 gic_iterate_rdists(__gic_update_rdist_properties);
959 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
961 pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
962 if (gic_data.rdists.has_vlpis)
963 pr_info("GICv4 features: %s%s%s\n",
964 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
965 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
966 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
969 /* Check whether it's single security state view */
970 static inline bool gic_dist_security_disabled(void)
972 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
975 static void gic_cpu_sys_reg_init(void)
977 int i, cpu = smp_processor_id();
978 u64 mpidr = cpu_logical_map(cpu);
979 u64 need_rss = MPIDR_RS(mpidr);
984 * Need to check that the SRE bit has actually been set. If
985 * not, it means that SRE is disabled at EL2. We're going to
986 * die painfully, and there is nothing we can do about it.
988 * Kindly inform the luser.
990 if (!gic_enable_sre())
991 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
993 pribits = gic_get_pribits();
995 group0 = gic_has_group0();
997 /* Set priority mask register */
998 if (!gic_prio_masking_enabled()) {
999 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
1000 } else if (gic_supports_nmi()) {
1002 * Mismatch configuration with boot CPU, the system is likely
1003 * to die as interrupt masking will not work properly on all
1006 * The boot CPU calls this function before enabling NMI support,
1007 * and as a result we'll never see this warning in the boot path
1010 if (static_branch_unlikely(&gic_nonsecure_priorities))
1011 WARN_ON(!group0 || gic_dist_security_disabled());
1013 WARN_ON(group0 && !gic_dist_security_disabled());
1017 * Some firmwares hand over to the kernel with the BPR changed from
1018 * its reset value (and with a value large enough to prevent
1019 * any pre-emptive interrupts from working at all). Writing a zero
1020 * to BPR restores is reset value.
1024 if (static_branch_likely(&supports_deactivate_key)) {
1025 /* EOI drops priority only (mode 1) */
1026 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1028 /* EOI deactivates interrupt too (mode 0) */
1029 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1032 /* Always whack Group0 before Group1 */
1037 write_gicreg(0, ICC_AP0R3_EL1);
1038 write_gicreg(0, ICC_AP0R2_EL1);
1041 write_gicreg(0, ICC_AP0R1_EL1);
1045 write_gicreg(0, ICC_AP0R0_EL1);
1054 write_gicreg(0, ICC_AP1R3_EL1);
1055 write_gicreg(0, ICC_AP1R2_EL1);
1058 write_gicreg(0, ICC_AP1R1_EL1);
1062 write_gicreg(0, ICC_AP1R0_EL1);
1067 /* ... and let's hit the road... */
1068 gic_write_grpen1(1);
1070 /* Keep the RSS capability status in per_cpu variable */
1071 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1073 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1074 for_each_online_cpu(i) {
1075 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1077 need_rss |= MPIDR_RS(cpu_logical_map(i));
1078 if (need_rss && (!have_rss))
1079 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1080 cpu, (unsigned long)mpidr,
1081 i, (unsigned long)cpu_logical_map(i));
1085 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1086 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1087 * UNPREDICTABLE choice of :
1088 * - The write is ignored.
1089 * - The RS field is treated as 0.
1091 if (need_rss && (!gic_data.has_rss))
1092 pr_crit_once("RSS is required but GICD doesn't support it\n");
1095 static bool gicv3_nolpi;
1097 static int __init gicv3_nolpi_cfg(char *buf)
1099 return strtobool(buf, &gicv3_nolpi);
1101 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1103 static int gic_dist_supports_lpis(void)
1105 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1106 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1110 static void gic_cpu_init(void)
1112 void __iomem *rbase;
1115 /* Register ourselves with the rest of the world */
1116 if (gic_populate_rdist())
1119 gic_enable_redist(true);
1121 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1122 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1123 "Distributor has extended ranges, but CPU%d doesn't\n",
1124 smp_processor_id());
1126 rbase = gic_data_rdist_sgi_base();
1128 /* Configure SGIs/PPIs as non-secure Group-1 */
1129 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1130 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1132 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1134 /* initialise system registers */
1135 gic_cpu_sys_reg_init();
1140 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1141 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1143 static int gic_starting_cpu(unsigned int cpu)
1147 if (gic_dist_supports_lpis())
1153 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1154 unsigned long cluster_id)
1156 int next_cpu, cpu = *base_cpu;
1157 unsigned long mpidr = cpu_logical_map(cpu);
1160 while (cpu < nr_cpu_ids) {
1161 tlist |= 1 << (mpidr & 0xf);
1163 next_cpu = cpumask_next(cpu, mask);
1164 if (next_cpu >= nr_cpu_ids)
1168 mpidr = cpu_logical_map(cpu);
1170 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1180 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1181 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1182 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1184 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1188 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1189 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1190 irq << ICC_SGI1R_SGI_ID_SHIFT |
1191 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
1192 MPIDR_TO_SGI_RS(cluster_id) |
1193 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1195 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1196 gic_write_sgi1r(val);
1199 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1203 if (WARN_ON(d->hwirq >= 16))
1207 * Ensure that stores to Normal memory are visible to the
1208 * other CPUs before issuing the IPI.
1212 for_each_cpu(cpu, mask) {
1213 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1216 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1217 gic_send_sgi(cluster_id, tlist, d->hwirq);
1220 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1224 static void __init gic_smp_init(void)
1226 struct irq_fwspec sgi_fwspec = {
1227 .fwnode = gic_data.fwnode,
1232 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1233 "irqchip/arm/gicv3:starting",
1234 gic_starting_cpu, NULL);
1236 /* Register all 8 non-secure SGIs */
1237 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
1238 NUMA_NO_NODE, &sgi_fwspec,
1240 if (WARN_ON(base_sgi <= 0))
1243 set_smp_ipi_range(base_sgi, 8);
1246 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1256 cpu = cpumask_first(mask_val);
1258 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1260 if (cpu >= nr_cpu_ids)
1263 if (gic_irq_in_rdist(d))
1266 /* If interrupt was enabled, disable it first */
1267 enabled = gic_peek_irq(d, GICD_ISENABLER);
1271 offset = convert_offset_index(d, GICD_IROUTER, &index);
1272 reg = gic_dist_base(d) + offset + (index * 8);
1273 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1275 gic_write_irouter(val, reg);
1278 * If the interrupt was enabled, enabled it again. Otherwise,
1279 * just wait for the distributor to have digested our changes.
1284 gic_dist_wait_for_rwp();
1286 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1288 return IRQ_SET_MASK_OK_DONE;
1291 #define gic_set_affinity NULL
1292 #define gic_ipi_send_mask NULL
1293 #define gic_smp_init() do { } while(0)
1296 static int gic_retrigger(struct irq_data *data)
1298 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1301 #ifdef CONFIG_CPU_PM
1302 static int gic_cpu_pm_notifier(struct notifier_block *self,
1303 unsigned long cmd, void *v)
1305 if (cmd == CPU_PM_EXIT) {
1306 if (gic_dist_security_disabled())
1307 gic_enable_redist(true);
1308 gic_cpu_sys_reg_init();
1309 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1310 gic_write_grpen1(0);
1311 gic_enable_redist(false);
1316 static struct notifier_block gic_cpu_pm_notifier_block = {
1317 .notifier_call = gic_cpu_pm_notifier,
1320 static void gic_cpu_pm_init(void)
1322 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1326 static inline void gic_cpu_pm_init(void) { }
1327 #endif /* CONFIG_CPU_PM */
1329 static struct irq_chip gic_chip = {
1331 .irq_mask = gic_mask_irq,
1332 .irq_unmask = gic_unmask_irq,
1333 .irq_eoi = gic_eoi_irq,
1334 .irq_set_type = gic_set_type,
1335 .irq_set_affinity = gic_set_affinity,
1336 .irq_retrigger = gic_retrigger,
1337 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1338 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1339 .irq_nmi_setup = gic_irq_nmi_setup,
1340 .irq_nmi_teardown = gic_irq_nmi_teardown,
1341 .ipi_send_mask = gic_ipi_send_mask,
1342 .flags = IRQCHIP_SET_TYPE_MASKED |
1343 IRQCHIP_SKIP_SET_WAKE |
1344 IRQCHIP_MASK_ON_SUSPEND,
1347 static struct irq_chip gic_eoimode1_chip = {
1349 .irq_mask = gic_eoimode1_mask_irq,
1350 .irq_unmask = gic_unmask_irq,
1351 .irq_eoi = gic_eoimode1_eoi_irq,
1352 .irq_set_type = gic_set_type,
1353 .irq_set_affinity = gic_set_affinity,
1354 .irq_retrigger = gic_retrigger,
1355 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1356 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1357 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1358 .irq_nmi_setup = gic_irq_nmi_setup,
1359 .irq_nmi_teardown = gic_irq_nmi_teardown,
1360 .ipi_send_mask = gic_ipi_send_mask,
1361 .flags = IRQCHIP_SET_TYPE_MASKED |
1362 IRQCHIP_SKIP_SET_WAKE |
1363 IRQCHIP_MASK_ON_SUSPEND,
1366 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1369 struct irq_chip *chip = &gic_chip;
1370 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1372 if (static_branch_likely(&supports_deactivate_key))
1373 chip = &gic_eoimode1_chip;
1375 switch (__get_intid_range(hw)) {
1377 irq_set_percpu_devid(irq);
1378 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1379 handle_percpu_devid_fasteoi_ipi,
1385 irq_set_percpu_devid(irq);
1386 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1387 handle_percpu_devid_irq, NULL, NULL);
1392 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1393 handle_fasteoi_irq, NULL, NULL);
1395 irqd_set_single_target(irqd);
1399 if (!gic_dist_supports_lpis())
1401 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1402 handle_fasteoi_irq, NULL, NULL);
1409 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1410 irqd_set_handle_enforce_irqctx(irqd);
1414 static int gic_irq_domain_translate(struct irq_domain *d,
1415 struct irq_fwspec *fwspec,
1416 unsigned long *hwirq,
1419 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1420 *hwirq = fwspec->param[0];
1421 *type = IRQ_TYPE_EDGE_RISING;
1425 if (is_of_node(fwspec->fwnode)) {
1426 if (fwspec->param_count < 3)
1429 switch (fwspec->param[0]) {
1431 *hwirq = fwspec->param[1] + 32;
1434 *hwirq = fwspec->param[1] + 16;
1437 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1440 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1442 case GIC_IRQ_TYPE_LPI: /* LPI */
1443 *hwirq = fwspec->param[1];
1445 case GIC_IRQ_TYPE_PARTITION:
1446 *hwirq = fwspec->param[1];
1447 if (fwspec->param[1] >= 16)
1448 *hwirq += EPPI_BASE_INTID - 16;
1456 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1459 * Make it clear that broken DTs are... broken.
1460 * Partitioned PPIs are an unfortunate exception.
1462 WARN_ON(*type == IRQ_TYPE_NONE &&
1463 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1467 if (is_fwnode_irqchip(fwspec->fwnode)) {
1468 if(fwspec->param_count != 2)
1471 if (fwspec->param[0] < 16) {
1472 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1477 *hwirq = fwspec->param[0];
1478 *type = fwspec->param[1];
1480 WARN_ON(*type == IRQ_TYPE_NONE);
1487 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1488 unsigned int nr_irqs, void *arg)
1491 irq_hw_number_t hwirq;
1492 unsigned int type = IRQ_TYPE_NONE;
1493 struct irq_fwspec *fwspec = arg;
1495 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1499 for (i = 0; i < nr_irqs; i++) {
1500 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1508 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1509 unsigned int nr_irqs)
1513 for (i = 0; i < nr_irqs; i++) {
1514 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1515 irq_set_handler(virq + i, NULL);
1516 irq_domain_reset_irq_data(d);
1520 static int gic_irq_domain_select(struct irq_domain *d,
1521 struct irq_fwspec *fwspec,
1522 enum irq_domain_bus_token bus_token)
1525 if (fwspec->fwnode != d->fwnode)
1528 /* If this is not DT, then we have a single domain */
1529 if (!is_of_node(fwspec->fwnode))
1533 * If this is a PPI and we have a 4th (non-null) parameter,
1534 * then we need to match the partition domain.
1536 if (fwspec->param_count >= 4 &&
1537 fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
1539 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1541 return d == gic_data.domain;
1544 static const struct irq_domain_ops gic_irq_domain_ops = {
1545 .translate = gic_irq_domain_translate,
1546 .alloc = gic_irq_domain_alloc,
1547 .free = gic_irq_domain_free,
1548 .select = gic_irq_domain_select,
1551 static int partition_domain_translate(struct irq_domain *d,
1552 struct irq_fwspec *fwspec,
1553 unsigned long *hwirq,
1556 struct device_node *np;
1559 if (!gic_data.ppi_descs)
1562 np = of_find_node_by_phandle(fwspec->param[3]);
1566 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1567 of_node_to_fwnode(np));
1572 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1577 static const struct irq_domain_ops partition_domain_ops = {
1578 .translate = partition_domain_translate,
1579 .select = gic_irq_domain_select,
1582 static bool gic_enable_quirk_msm8996(void *data)
1584 struct gic_chip_data *d = data;
1586 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1591 static bool gic_enable_quirk_mtk_gicr(void *data)
1593 struct gic_chip_data *d = data;
1595 d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE;
1600 static bool gic_enable_quirk_cavium_38539(void *data)
1602 struct gic_chip_data *d = data;
1604 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1609 static bool gic_enable_quirk_hip06_07(void *data)
1611 struct gic_chip_data *d = data;
1614 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1615 * not being an actual ARM implementation). The saving grace is
1616 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1617 * HIP07 doesn't even have a proper IIDR, and still pretends to
1618 * have ESPI. In both cases, put them right.
1620 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1621 /* Zero both ESPI and the RES0 field next to it... */
1622 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1629 static const struct gic_quirk gic_quirks[] = {
1631 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1632 .compatible = "qcom,msm8996-gic-v3",
1633 .init = gic_enable_quirk_msm8996,
1636 .desc = "GICv3: Mediatek Chromebook GICR save problem",
1637 .property = "mediatek,broken-save-restore-fw",
1638 .init = gic_enable_quirk_mtk_gicr,
1641 .desc = "GICv3: HIP06 erratum 161010803",
1644 .init = gic_enable_quirk_hip06_07,
1647 .desc = "GICv3: HIP07 erratum 161010803",
1650 .init = gic_enable_quirk_hip06_07,
1654 * Reserved register accesses generate a Synchronous
1655 * External Abort. This erratum applies to:
1656 * - ThunderX: CN88xx
1657 * - OCTEON TX: CN83xx, CN81xx
1658 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1660 .desc = "GICv3: Cavium erratum 38539",
1663 .init = gic_enable_quirk_cavium_38539,
1669 static void gic_enable_nmi_support(void)
1673 if (!gic_prio_masking_enabled())
1676 if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) {
1677 pr_warn("Skipping NMI enable due to firmware issues\n");
1681 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1685 for (i = 0; i < gic_data.ppi_nr; i++)
1686 refcount_set(&ppi_nmi_refs[i], 0);
1689 * Linux itself doesn't use 1:N distribution, so has no need to
1690 * set PMHE. The only reason to have it set is if EL3 requires it
1691 * (and we can't change it).
1693 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1694 static_branch_enable(&gic_pmr_sync);
1696 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1697 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
1700 * How priority values are used by the GIC depends on two things:
1701 * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1702 * and if Group 0 interrupts can be delivered to Linux in the non-secure
1703 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1704 * the ICC_PMR_EL1 register and the priority that software assigns to
1707 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1708 * -----------------------------------------------------------
1709 * 1 | - | unchanged | unchanged
1710 * -----------------------------------------------------------
1711 * 0 | 1 | non-secure | non-secure
1712 * -----------------------------------------------------------
1713 * 0 | 0 | unchanged | non-secure
1715 * where non-secure means that the value is right-shifted by one and the
1716 * MSB bit set, to make it fit in the non-secure priority range.
1718 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1719 * are both either modified or unchanged, we can use the same set of
1722 * In the last case, where only the interrupt priorities are modified to
1723 * be in the non-secure range, we use a different PMR value to mask IRQs
1724 * and the rest of the values that we use remain unchanged.
1726 if (gic_has_group0() && !gic_dist_security_disabled())
1727 static_branch_enable(&gic_nonsecure_priorities);
1729 static_branch_enable(&supports_pseudo_nmis);
1731 if (static_branch_likely(&supports_deactivate_key))
1732 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1734 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1737 static int __init gic_init_bases(void __iomem *dist_base,
1738 struct redist_region *rdist_regs,
1739 u32 nr_redist_regions,
1741 struct fwnode_handle *handle)
1746 if (!is_hyp_mode_available())
1747 static_branch_disable(&supports_deactivate_key);
1749 if (static_branch_likely(&supports_deactivate_key))
1750 pr_info("GIC: Using split EOI/Deactivate mode\n");
1752 gic_data.fwnode = handle;
1753 gic_data.dist_base = dist_base;
1754 gic_data.redist_regions = rdist_regs;
1755 gic_data.nr_redist_regions = nr_redist_regions;
1756 gic_data.redist_stride = redist_stride;
1759 * Find out how many interrupts are supported.
1761 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1762 gic_data.rdists.gicd_typer = typer;
1764 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1765 gic_quirks, &gic_data);
1767 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1768 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1771 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1772 * architecture spec (which says that reserved registers are RES0).
1774 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1775 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1777 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1779 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1780 gic_data.rdists.has_rvpeid = true;
1781 gic_data.rdists.has_vlpis = true;
1782 gic_data.rdists.has_direct_lpi = true;
1783 gic_data.rdists.has_vpend_valid_dirty = true;
1785 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1790 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1792 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1793 pr_info("Distributor has %sRange Selector support\n",
1794 gic_data.has_rss ? "" : "no ");
1796 if (typer & GICD_TYPER_MBIS) {
1797 err = mbi_init(handle, gic_data.domain);
1799 pr_err("Failed to initialize MBIs\n");
1802 set_handle_irq(gic_handle_irq);
1804 gic_update_rdist_properties();
1811 if (gic_dist_supports_lpis()) {
1812 its_init(handle, &gic_data.rdists, gic_data.domain);
1815 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1816 gicv2m_init(handle, gic_data.domain);
1819 gic_enable_nmi_support();
1824 if (gic_data.domain)
1825 irq_domain_remove(gic_data.domain);
1826 free_percpu(gic_data.rdists.rdist);
1830 static int __init gic_validate_dist_version(void __iomem *dist_base)
1832 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1834 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1840 /* Create all possible partitions at boot time */
1841 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1843 struct device_node *parts_node, *child_part;
1844 int part_idx = 0, i;
1846 struct partition_affinity *parts;
1848 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1852 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1853 if (!gic_data.ppi_descs)
1856 nr_parts = of_get_child_count(parts_node);
1861 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1862 if (WARN_ON(!parts))
1865 for_each_child_of_node(parts_node, child_part) {
1866 struct partition_affinity *part;
1869 part = &parts[part_idx];
1871 part->partition_id = of_node_to_fwnode(child_part);
1873 pr_info("GIC: PPI partition %pOFn[%d] { ",
1874 child_part, part_idx);
1876 n = of_property_count_elems_of_size(child_part, "affinity",
1880 for (i = 0; i < n; i++) {
1883 struct device_node *cpu_node;
1885 err = of_property_read_u32_index(child_part, "affinity",
1890 cpu_node = of_find_node_by_phandle(cpu_phandle);
1891 if (WARN_ON(!cpu_node))
1894 cpu = of_cpu_node_to_id(cpu_node);
1895 if (WARN_ON(cpu < 0)) {
1896 of_node_put(cpu_node);
1900 pr_cont("%pOF[%d] ", cpu_node, cpu);
1902 cpumask_set_cpu(cpu, &part->mask);
1903 of_node_put(cpu_node);
1910 for (i = 0; i < gic_data.ppi_nr; i++) {
1912 struct partition_desc *desc;
1913 struct irq_fwspec ppi_fwspec = {
1914 .fwnode = gic_data.fwnode,
1917 [0] = GIC_IRQ_TYPE_PARTITION,
1919 [2] = IRQ_TYPE_NONE,
1923 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1926 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1927 irq, &partition_domain_ops);
1931 gic_data.ppi_descs[i] = desc;
1935 of_node_put(parts_node);
1938 static void __init gic_of_setup_kvm_info(struct device_node *node)
1944 gic_v3_kvm_info.type = GIC_V3;
1946 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1947 if (!gic_v3_kvm_info.maint_irq)
1950 if (of_property_read_u32(node, "#redistributor-regions",
1954 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1955 ret = of_address_to_resource(node, gicv_idx, &r);
1957 gic_v3_kvm_info.vcpu = r;
1959 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1960 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
1961 gic_set_kvm_info(&gic_v3_kvm_info);
1964 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1966 void __iomem *dist_base;
1967 struct redist_region *rdist_regs;
1969 u32 nr_redist_regions;
1972 dist_base = of_iomap(node, 0);
1974 pr_err("%pOF: unable to map gic dist registers\n", node);
1978 err = gic_validate_dist_version(dist_base);
1980 pr_err("%pOF: no distributor detected, giving up\n", node);
1981 goto out_unmap_dist;
1984 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1985 nr_redist_regions = 1;
1987 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1991 goto out_unmap_dist;
1994 for (i = 0; i < nr_redist_regions; i++) {
1995 struct resource res;
1998 ret = of_address_to_resource(node, 1 + i, &res);
1999 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
2000 if (ret || !rdist_regs[i].redist_base) {
2001 pr_err("%pOF: couldn't map region %d\n", node, i);
2003 goto out_unmap_rdist;
2005 rdist_regs[i].phys_base = res.start;
2008 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
2011 gic_enable_of_quirks(node, gic_quirks, &gic_data);
2013 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
2014 redist_stride, &node->fwnode);
2016 goto out_unmap_rdist;
2018 gic_populate_ppi_partitions(node);
2020 if (static_branch_likely(&supports_deactivate_key))
2021 gic_of_setup_kvm_info(node);
2025 for (i = 0; i < nr_redist_regions; i++)
2026 if (rdist_regs[i].redist_base)
2027 iounmap(rdist_regs[i].redist_base);
2034 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2039 void __iomem *dist_base;
2040 struct redist_region *redist_regs;
2041 u32 nr_redist_regions;
2046 phys_addr_t vcpu_base;
2047 } acpi_data __initdata;
2050 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2052 static int count = 0;
2054 acpi_data.redist_regs[count].phys_base = phys_base;
2055 acpi_data.redist_regs[count].redist_base = redist_base;
2056 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2061 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2062 const unsigned long end)
2064 struct acpi_madt_generic_redistributor *redist =
2065 (struct acpi_madt_generic_redistributor *)header;
2066 void __iomem *redist_base;
2068 redist_base = ioremap(redist->base_address, redist->length);
2070 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2074 gic_acpi_register_redist(redist->base_address, redist_base);
2079 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2080 const unsigned long end)
2082 struct acpi_madt_generic_interrupt *gicc =
2083 (struct acpi_madt_generic_interrupt *)header;
2084 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2085 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2086 void __iomem *redist_base;
2088 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2089 if (!(gicc->flags & ACPI_MADT_ENABLED))
2092 redist_base = ioremap(gicc->gicr_base_address, size);
2096 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2100 static int __init gic_acpi_collect_gicr_base(void)
2102 acpi_tbl_entry_handler redist_parser;
2103 enum acpi_madt_type type;
2105 if (acpi_data.single_redist) {
2106 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2107 redist_parser = gic_acpi_parse_madt_gicc;
2109 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2110 redist_parser = gic_acpi_parse_madt_redist;
2113 /* Collect redistributor base addresses in GICR entries */
2114 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2117 pr_info("No valid GICR entries exist\n");
2121 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2122 const unsigned long end)
2124 /* Subtable presence means that redist exists, that's it */
2128 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2129 const unsigned long end)
2131 struct acpi_madt_generic_interrupt *gicc =
2132 (struct acpi_madt_generic_interrupt *)header;
2135 * If GICC is enabled and has valid gicr base address, then it means
2136 * GICR base is presented via GICC
2138 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2139 acpi_data.enabled_rdists++;
2144 * It's perfectly valid firmware can pass disabled GICC entry, driver
2145 * should not treat as errors, skip the entry instead of probe fail.
2147 if (!(gicc->flags & ACPI_MADT_ENABLED))
2153 static int __init gic_acpi_count_gicr_regions(void)
2158 * Count how many redistributor regions we have. It is not allowed
2159 * to mix redistributor description, GICR and GICC subtables have to be
2160 * mutually exclusive.
2162 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2163 gic_acpi_match_gicr, 0);
2165 acpi_data.single_redist = false;
2169 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2170 gic_acpi_match_gicc, 0);
2172 acpi_data.single_redist = true;
2173 count = acpi_data.enabled_rdists;
2179 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2180 struct acpi_probe_entry *ape)
2182 struct acpi_madt_generic_distributor *dist;
2185 dist = (struct acpi_madt_generic_distributor *)header;
2186 if (dist->version != ape->driver_data)
2189 /* We need to do that exercise anyway, the sooner the better */
2190 count = gic_acpi_count_gicr_regions();
2194 acpi_data.nr_redist_regions = count;
2198 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2199 const unsigned long end)
2201 struct acpi_madt_generic_interrupt *gicc =
2202 (struct acpi_madt_generic_interrupt *)header;
2204 static int first_madt = true;
2206 /* Skip unusable CPUs */
2207 if (!(gicc->flags & ACPI_MADT_ENABLED))
2210 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2211 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2216 acpi_data.maint_irq = gicc->vgic_interrupt;
2217 acpi_data.maint_irq_mode = maint_irq_mode;
2218 acpi_data.vcpu_base = gicc->gicv_base_address;
2224 * The maintenance interrupt and GICV should be the same for every CPU
2226 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2227 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2228 (acpi_data.vcpu_base != gicc->gicv_base_address))
2234 static bool __init gic_acpi_collect_virt_info(void)
2238 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2239 gic_acpi_parse_virt_madt_gicc, 0);
2244 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2245 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2246 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2248 static void __init gic_acpi_setup_kvm_info(void)
2252 if (!gic_acpi_collect_virt_info()) {
2253 pr_warn("Unable to get hardware information used for virtualization\n");
2257 gic_v3_kvm_info.type = GIC_V3;
2259 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2260 acpi_data.maint_irq_mode,
2265 gic_v3_kvm_info.maint_irq = irq;
2267 if (acpi_data.vcpu_base) {
2268 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2270 vcpu->flags = IORESOURCE_MEM;
2271 vcpu->start = acpi_data.vcpu_base;
2272 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2275 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2276 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2277 gic_set_kvm_info(&gic_v3_kvm_info);
2281 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2283 struct acpi_madt_generic_distributor *dist;
2284 struct fwnode_handle *domain_handle;
2288 /* Get distributor base address */
2289 dist = (struct acpi_madt_generic_distributor *)header;
2290 acpi_data.dist_base = ioremap(dist->base_address,
2291 ACPI_GICV3_DIST_MEM_SIZE);
2292 if (!acpi_data.dist_base) {
2293 pr_err("Unable to map GICD registers\n");
2297 err = gic_validate_dist_version(acpi_data.dist_base);
2299 pr_err("No distributor detected at @%p, giving up\n",
2300 acpi_data.dist_base);
2301 goto out_dist_unmap;
2304 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2305 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2306 if (!acpi_data.redist_regs) {
2308 goto out_dist_unmap;
2311 err = gic_acpi_collect_gicr_base();
2313 goto out_redist_unmap;
2315 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2316 if (!domain_handle) {
2318 goto out_redist_unmap;
2321 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2322 acpi_data.nr_redist_regions, 0, domain_handle);
2324 goto out_fwhandle_free;
2326 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2328 if (static_branch_likely(&supports_deactivate_key))
2329 gic_acpi_setup_kvm_info();
2334 irq_domain_free_fwnode(domain_handle);
2336 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2337 if (acpi_data.redist_regs[i].redist_base)
2338 iounmap(acpi_data.redist_regs[i].redist_base);
2339 kfree(acpi_data.redist_regs);
2341 iounmap(acpi_data.dist_base);
2344 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2345 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2347 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2348 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2350 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2351 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,