drivers/irqchip/irq-gic-v3-its.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/acpi_iort.h>
   9 #include <linux/bitmap.h>
  10 #include <linux/cpu.h>
  11 #include <linux/crash_dump.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-iommu.h>
  14 #include <linux/efi.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/list.h>
  18 #include <linux/log2.h>
  19 #include <linux/memblock.h>
  20 #include <linux/mm.h>
  21 #include <linux/msi.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_pci.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/percpu.h>
  28 #include <linux/slab.h>
  29 #include <linux/syscore_ops.h>
  30
  31 #include <linux/irqchip.h>
  32 #include <linux/irqchip/arm-gic-v3.h>
  33 #include <linux/irqchip/arm-gic-v4.h>
  34
  35 #include <asm/cputype.h>
  36 #include <asm/exception.h>
  37
  38 #include "irq-gic-common.h"
  39
  40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  41 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  42 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144       (1ULL << 2)
  43
  44 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  45 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED      (1 << 1)
  46
  47 static u32 lpi_id_bits;
  48
  49 /*
  50  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
  51  * deal with (one configuration byte per interrupt). PENDBASE has to
  52  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
  53  */
  54 #define LPI_NRBITS              lpi_id_bits
  55 #define LPI_PROPBASE_SZ         ALIGN(BIT(LPI_NRBITS), SZ_64K)
  56 #define LPI_PENDBASE_SZ         ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
  57
  58 #define LPI_PROP_DEFAULT_PRIO   GICD_INT_DEF_PRI
  59
  60 /*
  61  * Collection structure - just an ID, and a redistributor address to
  62  * ping. We use one per CPU as a bag of interrupts assigned to this
  63  * CPU.
  64  */
  65 struct its_collection {
  66         u64                     target_address;
  67         u16                     col_id;
  68 };
  69
  70 /*
  71  * The ITS_BASER structure - contains memory information, cached
  72  * value of BASER register configuration and ITS page size.
  73  */
  74 struct its_baser {
  75         void            *base;
  76         u64             val;
  77         u32             order;
  78         u32             psz;
  79 };
  80
  81 struct its_device;
  82
  83 /*
  84  * The ITS structure - contains most of the infrastructure, with the
  85  * top-level MSI domain, the command queue, the collections, and the
  86  * list of devices writing to it.
  87  *
  88  * dev_alloc_lock has to be taken for device allocations, while the
  89  * spinlock must be taken to parse data structures such as the device
  90  * list.
  91  */
  92 struct its_node {
  93         raw_spinlock_t          lock;
  94         struct mutex            dev_alloc_lock;
  95         struct list_head        entry;
  96         void __iomem            *base;
  97         phys_addr_t             phys_base;
  98         struct its_cmd_block    *cmd_base;
  99         struct its_cmd_block    *cmd_write;
 100         struct its_baser        tables[GITS_BASER_NR_REGS];
 101         struct its_collection   *collections;
 102         struct fwnode_handle    *fwnode_handle;
 103         u64                     (*get_msi_base)(struct its_device *its_dev);
 104         u64                     cbaser_save;
 105         u32                     ctlr_save;
 106         struct list_head        its_device_list;
 107         u64                     flags;
 108         unsigned long           list_nr;
 109         u32                     ite_size;
 110         u32                     device_ids;
 111         int                     numa_node;
 112         unsigned int            msi_domain_flags;
 113         u32                     pre_its_base; /* for Socionext Synquacer */
 114         bool                    is_v4;
 115         int                     vlpi_redist_offset;
 116 };
 117
 118 #define ITS_ITT_ALIGN           SZ_256
 119
 120 /* The maximum number of VPEID bits supported by VLPI commands */
 121 #define ITS_MAX_VPEID_BITS      (16)
 122 #define ITS_MAX_VPEID           (1 << (ITS_MAX_VPEID_BITS))
 123
 124 /* Convert page order to size in bytes */
 125 #define PAGE_ORDER_TO_SIZE(o)   (PAGE_SIZE << (o))
 126
 127 struct event_lpi_map {
 128         unsigned long           *lpi_map;
 129         u16                     *col_map;
 130         irq_hw_number_t         lpi_base;
 131         int                     nr_lpis;
 132         struct mutex            vlpi_lock;
 133         struct its_vm           *vm;
 134         struct its_vlpi_map     *vlpi_maps;
 135         int                     nr_vlpis;
 136 };
 137
 138 /*
 139  * The ITS view of a device - belongs to an ITS, owns an interrupt
 140  * translation table, and a list of interrupts.  If it some of its
 141  * LPIs are injected into a guest (GICv4), the event_map.vm field
 142  * indicates which one.
 143  */
 144 struct its_device {
 145         struct list_head        entry;
 146         struct its_node         *its;
 147         struct event_lpi_map    event_map;
 148         void                    *itt;
 149         u32                     nr_ites;
 150         u32                     device_id;
 151         bool                    shared;
 152 };
 153
 154 static struct {
 155         raw_spinlock_t          lock;
 156         struct its_device       *dev;
 157         struct its_vpe          **vpes;
 158         int                     next_victim;
 159 } vpe_proxy;
 160
 161 static LIST_HEAD(its_nodes);
 162 static DEFINE_RAW_SPINLOCK(its_lock);
 163 static struct rdists *gic_rdists;
 164 static struct irq_domain *its_parent;
 165
 166 static unsigned long its_list_map;
 167 static u16 vmovp_seq_num;
 168 static DEFINE_RAW_SPINLOCK(vmovp_lock);
 169
 170 static DEFINE_IDA(its_vpeid_ida);
 171
 172 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 173 #define gic_data_rdist_cpu(cpu)         (per_cpu_ptr(gic_rdists->rdist, cpu))
 174 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 175 #define gic_data_rdist_vlpi_base()      (gic_data_rdist_rd_base() + SZ_128K)
 176
 177 static u16 get_its_list(struct its_vm *vm)
 178 {
 179         struct its_node *its;
 180         unsigned long its_list = 0;
 181
 182         list_for_each_entry(its, &its_nodes, entry) {
 183                 if (!its->is_v4)
 184                         continue;
 185
 186                 if (vm->vlpi_count[its->list_nr])
 187                         __set_bit(its->list_nr, &its_list);
 188         }
 189
 190         return (u16)its_list;
 191 }
 192
 193 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 194                                                u32 event)
 195 {
 196         struct its_node *its = its_dev->its;
 197
 198         return its->collections + its_dev->event_map.col_map[event];
 199 }
 200
 201 static struct its_collection *valid_col(struct its_collection *col)
 202 {
 203         if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
 204                 return NULL;
 205
 206         return col;
 207 }
 208
 209 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
 210 {
 211         if (valid_col(its->collections + vpe->col_idx))
 212                 return vpe;
 213
 214         return NULL;
 215 }
 216
 217 /*
 218  * ITS command descriptors - parameters to be encoded in a command
 219  * block.
 220  */
 221 struct its_cmd_desc {
 222         union {
 223                 struct {
 224                         struct its_device *dev;
 225                         u32 event_id;
 226                 } its_inv_cmd;
 227
 228                 struct {
 229                         struct its_device *dev;
 230                         u32 event_id;
 231                 } its_clear_cmd;
 232
 233                 struct {
 234                         struct its_device *dev;
 235                         u32 event_id;
 236                 } its_int_cmd;
 237
 238                 struct {
 239                         struct its_device *dev;
 240                         int valid;
 241                 } its_mapd_cmd;
 242
 243                 struct {
 244                         struct its_collection *col;
 245                         int valid;
 246                 } its_mapc_cmd;
 247
 248                 struct {
 249                         struct its_device *dev;
 250                         u32 phys_id;
 251                         u32 event_id;
 252                 } its_mapti_cmd;
 253
 254                 struct {
 255                         struct its_device *dev;
 256                         struct its_collection *col;
 257                         u32 event_id;
 258                 } its_movi_cmd;
 259
 260                 struct {
 261                         struct its_device *dev;
 262                         u32 event_id;
 263                 } its_discard_cmd;
 264
 265                 struct {
 266                         struct its_collection *col;
 267                 } its_invall_cmd;
 268
 269                 struct {
 270                         struct its_vpe *vpe;
 271                 } its_vinvall_cmd;
 272
 273                 struct {
 274                         struct its_vpe *vpe;
 275                         struct its_collection *col;
 276                         bool valid;
 277                 } its_vmapp_cmd;
 278
 279                 struct {
 280                         struct its_vpe *vpe;
 281                         struct its_device *dev;
 282                         u32 virt_id;
 283                         u32 event_id;
 284                         bool db_enabled;
 285                 } its_vmapti_cmd;
 286
 287                 struct {
 288                         struct its_vpe *vpe;
 289                         struct its_device *dev;
 290                         u32 event_id;
 291                         bool db_enabled;
 292                 } its_vmovi_cmd;
 293
 294                 struct {
 295                         struct its_vpe *vpe;
 296                         struct its_collection *col;
 297                         u16 seq_num;
 298                         u16 its_list;
 299                 } its_vmovp_cmd;
 300         };
 301 };
 302
 303 /*
 304  * The ITS command block, which is what the ITS actually parses.
 305  */
 306 struct its_cmd_block {
 307         u64     raw_cmd[4];
 308 };
 309
 310 #define ITS_CMD_QUEUE_SZ                SZ_64K
 311 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 312
 313 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
 314                                                     struct its_cmd_block *,
 315                                                     struct its_cmd_desc *);
 316
 317 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
 318                                               struct its_cmd_block *,
 319                                               struct its_cmd_desc *);
 320
 321 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
 322 {
 323         u64 mask = GENMASK_ULL(h, l);
 324         *raw_cmd &= ~mask;
 325         *raw_cmd |= (val << l) & mask;
 326 }
 327
 328 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 329 {
 330         its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
 331 }
 332
 333 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 334 {
 335         its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
 336 }
 337
 338 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 339 {
 340         its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
 341 }
 342
 343 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 344 {
 345         its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
 346 }
 347
 348 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 349 {
 350         its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
 351 }
 352
 353 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 354 {
 355         its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
 356 }
 357
 358 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 359 {
 360         its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
 361 }
 362
 363 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 364 {
 365         its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
 366 }
 367
 368 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 369 {
 370         its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
 371 }
 372
 373 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
 374 {
 375         its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
 376 }
 377
 378 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
 379 {
 380         its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
 381 }
 382
 383 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
 384 {
 385         its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
 386 }
 387
 388 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
 389 {
 390         its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
 391 }
 392
 393 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
 394 {
 395         its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
 396 }
 397
 398 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
 399 {
 400         its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
 401 }
 402
 403 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
 404 {
 405         its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
 406 }
 407
 408 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
 409 {
 410         its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
 411 }
 412
 413 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 414 {
 415         /* Let's fixup BE commands */
 416         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 417         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 418         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 419         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 420 }
 421
 422 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
 423                                                  struct its_cmd_block *cmd,
 424                                                  struct its_cmd_desc *desc)
 425 {
 426         unsigned long itt_addr;
 427         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 428
 429         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 430         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 431
 432         its_encode_cmd(cmd, GITS_CMD_MAPD);
 433         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 434         its_encode_size(cmd, size - 1);
 435         its_encode_itt(cmd, itt_addr);
 436         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 437
 438         its_fixup_cmd(cmd);
 439
 440         return NULL;
 441 }
 442
 443 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
 444                                                  struct its_cmd_block *cmd,
 445                                                  struct its_cmd_desc *desc)
 446 {
 447         its_encode_cmd(cmd, GITS_CMD_MAPC);
 448         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 449         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 450         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 451
 452         its_fixup_cmd(cmd);
 453
 454         return desc->its_mapc_cmd.col;
 455 }
 456
 457 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
 458                                                   struct its_cmd_block *cmd,
 459                                                   struct its_cmd_desc *desc)
 460 {
 461         struct its_collection *col;
 462
 463         col = dev_event_to_col(desc->its_mapti_cmd.dev,
 464                                desc->its_mapti_cmd.event_id);
 465
 466         its_encode_cmd(cmd, GITS_CMD_MAPTI);
 467         its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
 468         its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
 469         its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
 470         its_encode_collection(cmd, col->col_id);
 471
 472         its_fixup_cmd(cmd);
 473
 474         return valid_col(col);
 475 }
 476
 477 static struct its_collection *its_build_movi_cmd(struct its_node *its,
 478                                                  struct its_cmd_block *cmd,
 479                                                  struct its_cmd_desc *desc)
 480 {
 481         struct its_collection *col;
 482
 483         col = dev_event_to_col(desc->its_movi_cmd.dev,
 484                                desc->its_movi_cmd.event_id);
 485
 486         its_encode_cmd(cmd, GITS_CMD_MOVI);
 487         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 488         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 489         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 490
 491         its_fixup_cmd(cmd);
 492
 493         return valid_col(col);
 494 }
 495
 496 static struct its_collection *its_build_discard_cmd(struct its_node *its,
 497                                                     struct its_cmd_block *cmd,
 498                                                     struct its_cmd_desc *desc)
 499 {
 500         struct its_collection *col;
 501
 502         col = dev_event_to_col(desc->its_discard_cmd.dev,
 503                                desc->its_discard_cmd.event_id);
 504
 505         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 506         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 507         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 508
 509         its_fixup_cmd(cmd);
 510
 511         return valid_col(col);
 512 }
 513
 514 static struct its_collection *its_build_inv_cmd(struct its_node *its,
 515                                                 struct its_cmd_block *cmd,
 516                                                 struct its_cmd_desc *desc)
 517 {
 518         struct its_collection *col;
 519
 520         col = dev_event_to_col(desc->its_inv_cmd.dev,
 521                                desc->its_inv_cmd.event_id);
 522
 523         its_encode_cmd(cmd, GITS_CMD_INV);
 524         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 525         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 526
 527         its_fixup_cmd(cmd);
 528
 529         return valid_col(col);
 530 }
 531
 532 static struct its_collection *its_build_int_cmd(struct its_node *its,
 533                                                 struct its_cmd_block *cmd,
 534                                                 struct its_cmd_desc *desc)
 535 {
 536         struct its_collection *col;
 537
 538         col = dev_event_to_col(desc->its_int_cmd.dev,
 539                                desc->its_int_cmd.event_id);
 540
 541         its_encode_cmd(cmd, GITS_CMD_INT);
 542         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 543         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 544
 545         its_fixup_cmd(cmd);
 546
 547         return valid_col(col);
 548 }
 549
 550 static struct its_collection *its_build_clear_cmd(struct its_node *its,
 551                                                   struct its_cmd_block *cmd,
 552                                                   struct its_cmd_desc *desc)
 553 {
 554         struct its_collection *col;
 555
 556         col = dev_event_to_col(desc->its_clear_cmd.dev,
 557                                desc->its_clear_cmd.event_id);
 558
 559         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 560         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 561         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 562
 563         its_fixup_cmd(cmd);
 564
 565         return valid_col(col);
 566 }
 567
 568 static struct its_collection *its_build_invall_cmd(struct its_node *its,
 569                                                    struct its_cmd_block *cmd,
 570                                                    struct its_cmd_desc *desc)
 571 {
 572         its_encode_cmd(cmd, GITS_CMD_INVALL);
 573         its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
 574
 575         its_fixup_cmd(cmd);
 576
 577         return desc->its_invall_cmd.col;
 578 }
 579
 580 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
 581                                              struct its_cmd_block *cmd,
 582                                              struct its_cmd_desc *desc)
 583 {
 584         its_encode_cmd(cmd, GITS_CMD_VINVALL);
 585         its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
 586
 587         its_fixup_cmd(cmd);
 588
 589         return valid_vpe(its, desc->its_vinvall_cmd.vpe);
 590 }
 591
 592 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
 593                                            struct its_cmd_block *cmd,
 594                                            struct its_cmd_desc *desc)
 595 {
 596         unsigned long vpt_addr;
 597         u64 target;
 598
 599         vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
 600         target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
 601
 602         its_encode_cmd(cmd, GITS_CMD_VMAPP);
 603         its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
 604         its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
 605         its_encode_target(cmd, target);
 606         its_encode_vpt_addr(cmd, vpt_addr);
 607         its_encode_vpt_size(cmd, LPI_NRBITS - 1);
 608
 609         its_fixup_cmd(cmd);
 610
 611         return valid_vpe(its, desc->its_vmapp_cmd.vpe);
 612 }
 613
 614 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
 615                                             struct its_cmd_block *cmd,
 616                                             struct its_cmd_desc *desc)
 617 {
 618         u32 db;
 619
 620         if (desc->its_vmapti_cmd.db_enabled)
 621                 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
 622         else
 623                 db = 1023;
 624
 625         its_encode_cmd(cmd, GITS_CMD_VMAPTI);
 626         its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
 627         its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
 628         its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
 629         its_encode_db_phys_id(cmd, db);
 630         its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
 631
 632         its_fixup_cmd(cmd);
 633
 634         return valid_vpe(its, desc->its_vmapti_cmd.vpe);
 635 }
 636
 637 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
 638                                            struct its_cmd_block *cmd,
 639                                            struct its_cmd_desc *desc)
 640 {
 641         u32 db;
 642
 643         if (desc->its_vmovi_cmd.db_enabled)
 644                 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
 645         else
 646                 db = 1023;
 647
 648         its_encode_cmd(cmd, GITS_CMD_VMOVI);
 649         its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
 650         its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
 651         its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
 652         its_encode_db_phys_id(cmd, db);
 653         its_encode_db_valid(cmd, true);
 654
 655         its_fixup_cmd(cmd);
 656
 657         return valid_vpe(its, desc->its_vmovi_cmd.vpe);
 658 }
 659
 660 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
 661                                            struct its_cmd_block *cmd,
 662                                            struct its_cmd_desc *desc)
 663 {
 664         u64 target;
 665
 666         target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
 667         its_encode_cmd(cmd, GITS_CMD_VMOVP);
 668         its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
 669         its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
 670         its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
 671         its_encode_target(cmd, target);
 672
 673         its_fixup_cmd(cmd);
 674
 675         return valid_vpe(its, desc->its_vmovp_cmd.vpe);
 676 }
 677
 678 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 679                                  struct its_cmd_block *ptr)
 680 {
 681         return (ptr - its->cmd_base) * sizeof(*ptr);
 682 }
 683
 684 static int its_queue_full(struct its_node *its)
 685 {
 686         int widx;
 687         int ridx;
 688
 689         widx = its->cmd_write - its->cmd_base;
 690         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 691
 692         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 693         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 694                 return 1;
 695
 696         return 0;
 697 }
 698
 699 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 700 {
 701         struct its_cmd_block *cmd;
 702         u32 count = 1000000;    /* 1s! */
 703
 704         while (its_queue_full(its)) {
 705                 count--;
 706                 if (!count) {
 707                         pr_err_ratelimited("ITS queue not draining\n");
 708                         return NULL;
 709                 }
 710                 cpu_relax();
 711                 udelay(1);
 712         }
 713
 714         cmd = its->cmd_write++;
 715
 716         /* Handle queue wrapping */
 717         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 718                 its->cmd_write = its->cmd_base;
 719
 720         /* Clear command  */
 721         cmd->raw_cmd[0] = 0;
 722         cmd->raw_cmd[1] = 0;
 723         cmd->raw_cmd[2] = 0;
 724         cmd->raw_cmd[3] = 0;
 725
 726         return cmd;
 727 }
 728
 729 static struct its_cmd_block *its_post_commands(struct its_node *its)
 730 {
 731         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 732
 733         writel_relaxed(wr, its->base + GITS_CWRITER);
 734
 735         return its->cmd_write;
 736 }
 737
 738 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 739 {
 740         /*
 741          * Make sure the commands written to memory are observable by
 742          * the ITS.
 743          */
 744         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 745                 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
 746         else
 747                 dsb(ishst);
 748 }
 749
 750 static int its_wait_for_range_completion(struct its_node *its,
 751                                          u64    prev_idx,
 752                                          struct its_cmd_block *to)
 753 {
 754         u64 rd_idx, to_idx, linear_idx;
 755         u32 count = 1000000;    /* 1s! */
 756
 757         /* Linearize to_idx if the command set has wrapped around */
 758         to_idx = its_cmd_ptr_to_offset(its, to);
 759         if (to_idx < prev_idx)
 760                 to_idx += ITS_CMD_QUEUE_SZ;
 761
 762         linear_idx = prev_idx;
 763
 764         while (1) {
 765                 s64 delta;
 766
 767                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 768
 769                 /*
 770                  * Compute the read pointer progress, taking the
 771                  * potential wrap-around into account.
 772                  */
 773                 delta = rd_idx - prev_idx;
 774                 if (rd_idx < prev_idx)
 775                         delta += ITS_CMD_QUEUE_SZ;
 776
 777                 linear_idx += delta;
 778                 if (linear_idx >= to_idx)
 779                         break;
 780
 781                 count--;
 782                 if (!count) {
 783                         pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
 784                                            to_idx, linear_idx);
 785                         return -1;
 786                 }
 787                 prev_idx = rd_idx;
 788                 cpu_relax();
 789                 udelay(1);
 790         }
 791
 792         return 0;
 793 }
 794
 795 /* Warning, macro hell follows */
 796 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)       \
 797 void name(struct its_node *its,                                         \
 798           buildtype builder,                                            \
 799           struct its_cmd_desc *desc)                                    \
 800 {                                                                       \
 801         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;                \
 802         synctype *sync_obj;                                             \
 803         unsigned long flags;                                            \
 804         u64 rd_idx;                                                     \
 805                                                                         \
 806         raw_spin_lock_irqsave(&its->lock, flags);                       \
 807                                                                         \
 808         cmd = its_allocate_entry(its);                                  \
 809         if (!cmd) {             /* We're soooooo screewed... */         \
 810                 raw_spin_unlock_irqrestore(&its->lock, flags);          \
 811                 return;                                                 \
 812         }                                                               \
 813         sync_obj = builder(its, cmd, desc);                             \
 814         its_flush_cmd(its, cmd);                                        \
 815                                                                         \
 816         if (sync_obj) {                                                 \
 817                 sync_cmd = its_allocate_entry(its);                     \
 818                 if (!sync_cmd)                                          \
 819                         goto post;                                      \
 820                                                                         \
 821                 buildfn(its, sync_cmd, sync_obj);                       \
 822                 its_flush_cmd(its, sync_cmd);                           \
 823         }                                                               \
 824                                                                         \
 825 post:                                                                   \
 826         rd_idx = readl_relaxed(its->base + GITS_CREADR);                \
 827         next_cmd = its_post_commands(its);                              \
 828         raw_spin_unlock_irqrestore(&its->lock, flags);                  \
 829                                                                         \
 830         if (its_wait_for_range_completion(its, rd_idx, next_cmd))       \
 831                 pr_err_ratelimited("ITS cmd %ps failed\n", builder);    \
 832 }
 833
 834 static void its_build_sync_cmd(struct its_node *its,
 835                                struct its_cmd_block *sync_cmd,
 836                                struct its_collection *sync_col)
 837 {
 838         its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 839         its_encode_target(sync_cmd, sync_col->target_address);
 840
 841         its_fixup_cmd(sync_cmd);
 842 }
 843
 844 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
 845                              struct its_collection, its_build_sync_cmd)
 846
 847 static void its_build_vsync_cmd(struct its_node *its,
 848                                 struct its_cmd_block *sync_cmd,
 849                                 struct its_vpe *sync_vpe)
 850 {
 851         its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
 852         its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
 853
 854         its_fixup_cmd(sync_cmd);
 855 }
 856
 857 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
 858                              struct its_vpe, its_build_vsync_cmd)
 859
 860 static void its_send_int(struct its_device *dev, u32 event_id)
 861 {
 862         struct its_cmd_desc desc;
 863
 864         desc.its_int_cmd.dev = dev;
 865         desc.its_int_cmd.event_id = event_id;
 866
 867         its_send_single_command(dev->its, its_build_int_cmd, &desc);
 868 }
 869
 870 static void its_send_clear(struct its_device *dev, u32 event_id)
 871 {
 872         struct its_cmd_desc desc;
 873
 874         desc.its_clear_cmd.dev = dev;
 875         desc.its_clear_cmd.event_id = event_id;
 876
 877         its_send_single_command(dev->its, its_build_clear_cmd, &desc);
 878 }
 879
 880 static void its_send_inv(struct its_device *dev, u32 event_id)
 881 {
 882         struct its_cmd_desc desc;
 883
 884         desc.its_inv_cmd.dev = dev;
 885         desc.its_inv_cmd.event_id = event_id;
 886
 887         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 888 }
 889
 890 static void its_send_mapd(struct its_device *dev, int valid)
 891 {
 892         struct its_cmd_desc desc;
 893
 894         desc.its_mapd_cmd.dev = dev;
 895         desc.its_mapd_cmd.valid = !!valid;
 896
 897         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 898 }
 899
 900 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 901                           int valid)
 902 {
 903         struct its_cmd_desc desc;
 904
 905         desc.its_mapc_cmd.col = col;
 906         desc.its_mapc_cmd.valid = !!valid;
 907
 908         its_send_single_command(its, its_build_mapc_cmd, &desc);
 909 }
 910
 911 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
 912 {
 913         struct its_cmd_desc desc;
 914
 915         desc.its_mapti_cmd.dev = dev;
 916         desc.its_mapti_cmd.phys_id = irq_id;
 917         desc.its_mapti_cmd.event_id = id;
 918
 919         its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
 920 }
 921
 922 static void its_send_movi(struct its_device *dev,
 923                           struct its_collection *col, u32 id)
 924 {
 925         struct its_cmd_desc desc;
 926
 927         desc.its_movi_cmd.dev = dev;
 928         desc.its_movi_cmd.col = col;
 929         desc.its_movi_cmd.event_id = id;
 930
 931         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 932 }
 933
 934 static void its_send_discard(struct its_device *dev, u32 id)
 935 {
 936         struct its_cmd_desc desc;
 937
 938         desc.its_discard_cmd.dev = dev;
 939         desc.its_discard_cmd.event_id = id;
 940
 941         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 942 }
 943
 944 static void its_send_invall(struct its_node *its, struct its_collection *col)
 945 {
 946         struct its_cmd_desc desc;
 947
 948         desc.its_invall_cmd.col = col;
 949
 950         its_send_single_command(its, its_build_invall_cmd, &desc);
 951 }
 952
 953 static void its_send_vmapti(struct its_device *dev, u32 id)
 954 {
 955         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
 956         struct its_cmd_desc desc;
 957
 958         desc.its_vmapti_cmd.vpe = map->vpe;
 959         desc.its_vmapti_cmd.dev = dev;
 960         desc.its_vmapti_cmd.virt_id = map->vintid;
 961         desc.its_vmapti_cmd.event_id = id;
 962         desc.its_vmapti_cmd.db_enabled = map->db_enabled;
 963
 964         its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
 965 }
 966
 967 static void its_send_vmovi(struct its_device *dev, u32 id)
 968 {
 969         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
 970         struct its_cmd_desc desc;
 971
 972         desc.its_vmovi_cmd.vpe = map->vpe;
 973         desc.its_vmovi_cmd.dev = dev;
 974         desc.its_vmovi_cmd.event_id = id;
 975         desc.its_vmovi_cmd.db_enabled = map->db_enabled;
 976
 977         its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
 978 }
 979
 980 static void its_send_vmapp(struct its_node *its,
 981                            struct its_vpe *vpe, bool valid)
 982 {
 983         struct its_cmd_desc desc;
 984
 985         desc.its_vmapp_cmd.vpe = vpe;
 986         desc.its_vmapp_cmd.valid = valid;
 987         desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
 988
 989         its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
 990 }
 991
 992 static void its_send_vmovp(struct its_vpe *vpe)
 993 {
 994         struct its_cmd_desc desc = {};
 995         struct its_node *its;
 996         unsigned long flags;
 997         int col_id = vpe->col_idx;
 998
 999         desc.its_vmovp_cmd.vpe = vpe;
1000
1001         if (!its_list_map) {
1002                 its = list_first_entry(&its_nodes, struct its_node, entry);
1003                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1004                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1005                 return;
1006         }
1007
1008         /*
1009          * Yet another marvel of the architecture. If using the
1010          * its_list "feature", we need to make sure that all ITSs
1011          * receive all VMOVP commands in the same order. The only way
1012          * to guarantee this is to make vmovp a serialization point.
1013          *
1014          * Wall <-- Head.
1015          */
1016         raw_spin_lock_irqsave(&vmovp_lock, flags);
1017
1018         desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1019         desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1020
1021         /* Emit VMOVPs */
1022         list_for_each_entry(its, &its_nodes, entry) {
1023                 if (!its->is_v4)
1024                         continue;
1025
1026                 if (!vpe->its_vm->vlpi_count[its->list_nr])
1027                         continue;
1028
1029                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1030                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1031         }
1032
1033         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1034 }
1035
1036 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1037 {
1038         struct its_cmd_desc desc;
1039
1040         desc.its_vinvall_cmd.vpe = vpe;
1041         its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1042 }
1043
1044 /*
1045  * irqchip functions - assumes MSI, mostly.
1046  */
1047
1048 static inline u32 its_get_event_id(struct irq_data *d)
1049 {
1050         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1051         return d->hwirq - its_dev->event_map.lpi_base;
1052 }
1053
1054 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1055 {
1056         irq_hw_number_t hwirq;
1057         void *va;
1058         u8 *cfg;
1059
1060         if (irqd_is_forwarded_to_vcpu(d)) {
1061                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1062                 u32 event = its_get_event_id(d);
1063                 struct its_vlpi_map *map;
1064
1065                 va = page_address(its_dev->event_map.vm->vprop_page);
1066                 map = &its_dev->event_map.vlpi_maps[event];
1067                 hwirq = map->vintid;
1068
1069                 /* Remember the updated property */
1070                 map->properties &= ~clr;
1071                 map->properties |= set | LPI_PROP_GROUP1;
1072         } else {
1073                 va = gic_rdists->prop_table_va;
1074                 hwirq = d->hwirq;
1075         }
1076
1077         cfg = va + hwirq - 8192;
1078         *cfg &= ~clr;
1079         *cfg |= set | LPI_PROP_GROUP1;
1080
1081         /*
1082          * Make the above write visible to the redistributors.
1083          * And yes, we're flushing exactly: One. Single. Byte.
1084          * Humpf...
1085          */
1086         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1087                 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1088         else
1089                 dsb(ishst);
1090 }
1091
1092 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1093 {
1094         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1095
1096         lpi_write_config(d, clr, set);
1097         its_send_inv(its_dev, its_get_event_id(d));
1098 }
1099
1100 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1101 {
1102         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1103         u32 event = its_get_event_id(d);
1104
1105         if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1106                 return;
1107
1108         its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1109
1110         /*
1111          * More fun with the architecture:
1112          *
1113          * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1114          * value or to 1023, depending on the enable bit. But that
1115          * would be issueing a mapping for an /existing/ DevID+EventID
1116          * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1117          * to the /same/ vPE, using this opportunity to adjust the
1118          * doorbell. Mouahahahaha. We loves it, Precious.
1119          */
1120         its_send_vmovi(its_dev, event);
1121 }
1122
1123 static void its_mask_irq(struct irq_data *d)
1124 {
1125         if (irqd_is_forwarded_to_vcpu(d))
1126                 its_vlpi_set_doorbell(d, false);
1127
1128         lpi_update_config(d, LPI_PROP_ENABLED, 0);
1129 }
1130
1131 static void its_unmask_irq(struct irq_data *d)
1132 {
1133         if (irqd_is_forwarded_to_vcpu(d))
1134                 its_vlpi_set_doorbell(d, true);
1135
1136         lpi_update_config(d, 0, LPI_PROP_ENABLED);
1137 }
1138
1139 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1140                             bool force)
1141 {
1142         unsigned int cpu;
1143         const struct cpumask *cpu_mask = cpu_online_mask;
1144         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1145         struct its_collection *target_col;
1146         u32 id = its_get_event_id(d);
1147
1148         /* A forwarded interrupt should use irq_set_vcpu_affinity */
1149         if (irqd_is_forwarded_to_vcpu(d))
1150                 return -EINVAL;
1151
1152        /* lpi cannot be routed to a redistributor that is on a foreign node */
1153         if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1154                 if (its_dev->its->numa_node >= 0) {
1155                         cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1156                         if (!cpumask_intersects(mask_val, cpu_mask))
1157                                 return -EINVAL;
1158                 }
1159         }
1160
1161         cpu = cpumask_any_and(mask_val, cpu_mask);
1162
1163         if (cpu >= nr_cpu_ids)
1164                 return -EINVAL;
1165
1166         /* don't set the affinity when the target cpu is same as current one */
1167         if (cpu != its_dev->event_map.col_map[id]) {
1168                 target_col = &its_dev->its->collections[cpu];
1169                 its_send_movi(its_dev, target_col, id);
1170                 its_dev->event_map.col_map[id] = cpu;
1171                 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1172         }
1173
1174         return IRQ_SET_MASK_OK_DONE;
1175 }
1176
1177 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1178 {
1179         struct its_node *its = its_dev->its;
1180
1181         return its->phys_base + GITS_TRANSLATER;
1182 }
1183
1184 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1185 {
1186         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1187         struct its_node *its;
1188         u64 addr;
1189
1190         its = its_dev->its;
1191         addr = its->get_msi_base(its_dev);
1192
1193         msg->address_lo         = lower_32_bits(addr);
1194         msg->address_hi         = upper_32_bits(addr);
1195         msg->data               = its_get_event_id(d);
1196
1197         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1198 }
1199
1200 static int its_irq_set_irqchip_state(struct irq_data *d,
1201                                      enum irqchip_irq_state which,
1202                                      bool state)
1203 {
1204         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1205         u32 event = its_get_event_id(d);
1206
1207         if (which != IRQCHIP_STATE_PENDING)
1208                 return -EINVAL;
1209
1210         if (state)
1211                 its_send_int(its_dev, event);
1212         else
1213                 its_send_clear(its_dev, event);
1214
1215         return 0;
1216 }
1217
1218 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1219 {
1220         unsigned long flags;
1221
1222         /* Not using the ITS list? Everything is always mapped. */
1223         if (!its_list_map)
1224                 return;
1225
1226         raw_spin_lock_irqsave(&vmovp_lock, flags);
1227
1228         /*
1229          * If the VM wasn't mapped yet, iterate over the vpes and get
1230          * them mapped now.
1231          */
1232         vm->vlpi_count[its->list_nr]++;
1233
1234         if (vm->vlpi_count[its->list_nr] == 1) {
1235                 int i;
1236
1237                 for (i = 0; i < vm->nr_vpes; i++) {
1238                         struct its_vpe *vpe = vm->vpes[i];
1239                         struct irq_data *d = irq_get_irq_data(vpe->irq);
1240
1241                         /* Map the VPE to the first possible CPU */
1242                         vpe->col_idx = cpumask_first(cpu_online_mask);
1243                         its_send_vmapp(its, vpe, true);
1244                         its_send_vinvall(its, vpe);
1245                         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1246                 }
1247         }
1248
1249         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1250 }
1251
1252 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1253 {
1254         unsigned long flags;
1255
1256         /* Not using the ITS list? Everything is always mapped. */
1257         if (!its_list_map)
1258                 return;
1259
1260         raw_spin_lock_irqsave(&vmovp_lock, flags);
1261
1262         if (!--vm->vlpi_count[its->list_nr]) {
1263                 int i;
1264
1265                 for (i = 0; i < vm->nr_vpes; i++)
1266                         its_send_vmapp(its, vm->vpes[i], false);
1267         }
1268
1269         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1270 }
1271
1272 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1273 {
1274         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1275         u32 event = its_get_event_id(d);
1276         int ret = 0;
1277
1278         if (!info->map)
1279                 return -EINVAL;
1280
1281         mutex_lock(&its_dev->event_map.vlpi_lock);
1282
1283         if (!its_dev->event_map.vm) {
1284                 struct its_vlpi_map *maps;
1285
1286                 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1287                                GFP_KERNEL);
1288                 if (!maps) {
1289                         ret = -ENOMEM;
1290                         goto out;
1291                 }
1292
1293                 its_dev->event_map.vm = info->map->vm;
1294                 its_dev->event_map.vlpi_maps = maps;
1295         } else if (its_dev->event_map.vm != info->map->vm) {
1296                 ret = -EINVAL;
1297                 goto out;
1298         }
1299
1300         /* Get our private copy of the mapping information */
1301         its_dev->event_map.vlpi_maps[event] = *info->map;
1302
1303         if (irqd_is_forwarded_to_vcpu(d)) {
1304                 /* Already mapped, move it around */
1305                 its_send_vmovi(its_dev, event);
1306         } else {
1307                 /* Ensure all the VPEs are mapped on this ITS */
1308                 its_map_vm(its_dev->its, info->map->vm);
1309
1310                 /*
1311                  * Flag the interrupt as forwarded so that we can
1312                  * start poking the virtual property table.
1313                  */
1314                 irqd_set_forwarded_to_vcpu(d);
1315
1316                 /* Write out the property to the prop table */
1317                 lpi_write_config(d, 0xff, info->map->properties);
1318
1319                 /* Drop the physical mapping */
1320                 its_send_discard(its_dev, event);
1321
1322                 /* and install the virtual one */
1323                 its_send_vmapti(its_dev, event);
1324
1325                 /* Increment the number of VLPIs */
1326                 its_dev->event_map.nr_vlpis++;
1327         }
1328
1329 out:
1330         mutex_unlock(&its_dev->event_map.vlpi_lock);
1331         return ret;
1332 }
1333
1334 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1335 {
1336         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1337         u32 event = its_get_event_id(d);
1338         int ret = 0;
1339
1340         mutex_lock(&its_dev->event_map.vlpi_lock);
1341
1342         if (!its_dev->event_map.vm ||
1343             !its_dev->event_map.vlpi_maps[event].vm) {
1344                 ret = -EINVAL;
1345                 goto out;
1346         }
1347
1348         /* Copy our mapping information to the incoming request */
1349         *info->map = its_dev->event_map.vlpi_maps[event];
1350
1351 out:
1352         mutex_unlock(&its_dev->event_map.vlpi_lock);
1353         return ret;
1354 }
1355
1356 static int its_vlpi_unmap(struct irq_data *d)
1357 {
1358         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1359         u32 event = its_get_event_id(d);
1360         int ret = 0;
1361
1362         mutex_lock(&its_dev->event_map.vlpi_lock);
1363
1364         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1365                 ret = -EINVAL;
1366                 goto out;
1367         }
1368
1369         /* Drop the virtual mapping */
1370         its_send_discard(its_dev, event);
1371
1372         /* and restore the physical one */
1373         irqd_clr_forwarded_to_vcpu(d);
1374         its_send_mapti(its_dev, d->hwirq, event);
1375         lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1376                                     LPI_PROP_ENABLED |
1377                                     LPI_PROP_GROUP1));
1378
1379         /* Potentially unmap the VM from this ITS */
1380         its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1381
1382         /*
1383          * Drop the refcount and make the device available again if
1384          * this was the last VLPI.
1385          */
1386         if (!--its_dev->event_map.nr_vlpis) {
1387                 its_dev->event_map.vm = NULL;
1388                 kfree(its_dev->event_map.vlpi_maps);
1389         }
1390
1391 out:
1392         mutex_unlock(&its_dev->event_map.vlpi_lock);
1393         return ret;
1394 }
1395
1396 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1397 {
1398         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1399
1400         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1401                 return -EINVAL;
1402
1403         if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1404                 lpi_update_config(d, 0xff, info->config);
1405         else
1406                 lpi_write_config(d, 0xff, info->config);
1407         its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1408
1409         return 0;
1410 }
1411
1412 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1413 {
1414         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1415         struct its_cmd_info *info = vcpu_info;
1416
1417         /* Need a v4 ITS */
1418         if (!its_dev->its->is_v4)
1419                 return -EINVAL;
1420
1421         /* Unmap request? */
1422         if (!info)
1423                 return its_vlpi_unmap(d);
1424
1425         switch (info->cmd_type) {
1426         case MAP_VLPI:
1427                 return its_vlpi_map(d, info);
1428
1429         case GET_VLPI:
1430                 return its_vlpi_get(d, info);
1431
1432         case PROP_UPDATE_VLPI:
1433         case PROP_UPDATE_AND_INV_VLPI:
1434                 return its_vlpi_prop_update(d, info);
1435
1436         default:
1437                 return -EINVAL;
1438         }
1439 }
1440
1441 static struct irq_chip its_irq_chip = {
1442         .name                   = "ITS",
1443         .irq_mask               = its_mask_irq,
1444         .irq_unmask             = its_unmask_irq,
1445         .irq_eoi                = irq_chip_eoi_parent,
1446         .irq_set_affinity       = its_set_affinity,
1447         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
1448         .irq_set_irqchip_state  = its_irq_set_irqchip_state,
1449         .irq_set_vcpu_affinity  = its_irq_set_vcpu_affinity,
1450 };
1451
1452
1453 /*
1454  * How we allocate LPIs:
1455  *
1456  * lpi_range_list contains ranges of LPIs that are to available to
1457  * allocate from. To allocate LPIs, just pick the first range that
1458  * fits the required allocation, and reduce it by the required
1459  * amount. Once empty, remove the range from the list.
1460  *
1461  * To free a range of LPIs, add a free range to the list, sort it and
1462  * merge the result if the new range happens to be adjacent to an
1463  * already free block.
1464  *
1465  * The consequence of the above is that allocation is cost is low, but
1466  * freeing is expensive. We assumes that freeing rarely occurs.
1467  */
1468 #define ITS_MAX_LPI_NRBITS      16 /* 64K LPIs */
1469
1470 static DEFINE_MUTEX(lpi_range_lock);
1471 static LIST_HEAD(lpi_range_list);
1472
1473 struct lpi_range {
1474         struct list_head        entry;
1475         u32                     base_id;
1476         u32                     span;
1477 };
1478
1479 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1480 {
1481         struct lpi_range *range;
1482
1483         range = kmalloc(sizeof(*range), GFP_KERNEL);
1484         if (range) {
1485                 range->base_id = base;
1486                 range->span = span;
1487         }
1488
1489         return range;
1490 }
1491
1492 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1493 {
1494         struct lpi_range *range, *tmp;
1495         int err = -ENOSPC;
1496
1497         mutex_lock(&lpi_range_lock);
1498
1499         list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1500                 if (range->span >= nr_lpis) {
1501                         *base = range->base_id;
1502                         range->base_id += nr_lpis;
1503                         range->span -= nr_lpis;
1504
1505                         if (range->span == 0) {
1506                                 list_del(&range->entry);
1507                                 kfree(range);
1508                         }
1509
1510                         err = 0;
1511                         break;
1512                 }
1513         }
1514
1515         mutex_unlock(&lpi_range_lock);
1516
1517         pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1518         return err;
1519 }
1520
1521 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1522 {
1523         if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1524                 return;
1525         if (a->base_id + a->span != b->base_id)
1526                 return;
1527         b->base_id = a->base_id;
1528         b->span += a->span;
1529         list_del(&a->entry);
1530         kfree(a);
1531 }
1532
1533 static int free_lpi_range(u32 base, u32 nr_lpis)
1534 {
1535         struct lpi_range *new, *old;
1536
1537         new = mk_lpi_range(base, nr_lpis);
1538         if (!new)
1539                 return -ENOMEM;
1540
1541         mutex_lock(&lpi_range_lock);
1542
1543         list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1544                 if (old->base_id < base)
1545                         break;
1546         }
1547         /*
1548          * old is the last element with ->base_id smaller than base,
1549          * so new goes right after it. If there are no elements with
1550          * ->base_id smaller than base, &old->entry ends up pointing
1551          * at the head of the list, and inserting new it the start of
1552          * the list is the right thing to do in that case as well.
1553          */
1554         list_add(&new->entry, &old->entry);
1555         /*
1556          * Now check if we can merge with the preceding and/or
1557          * following ranges.
1558          */
1559         merge_lpi_ranges(old, new);
1560         merge_lpi_ranges(new, list_next_entry(new, entry));
1561
1562         mutex_unlock(&lpi_range_lock);
1563         return 0;
1564 }
1565
1566 static int __init its_lpi_init(u32 id_bits)
1567 {
1568         u32 lpis = (1UL << id_bits) - 8192;
1569         u32 numlpis;
1570         int err;
1571
1572         numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1573
1574         if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1575                 lpis = numlpis;
1576                 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1577                         lpis);
1578         }
1579
1580         /*
1581          * Initializing the allocator is just the same as freeing the
1582          * full range of LPIs.
1583          */
1584         err = free_lpi_range(8192, lpis);
1585         pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1586         return err;
1587 }
1588
1589 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1590 {
1591         unsigned long *bitmap = NULL;
1592         int err = 0;
1593
1594         do {
1595                 err = alloc_lpi_range(nr_irqs, base);
1596                 if (!err)
1597                         break;
1598
1599                 nr_irqs /= 2;
1600         } while (nr_irqs > 0);
1601
1602         if (!nr_irqs)
1603                 err = -ENOSPC;
1604
1605         if (err)
1606                 goto out;
1607
1608         bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1609         if (!bitmap)
1610                 goto out;
1611
1612         *nr_ids = nr_irqs;
1613
1614 out:
1615         if (!bitmap)
1616                 *base = *nr_ids = 0;
1617
1618         return bitmap;
1619 }
1620
1621 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1622 {
1623         WARN_ON(free_lpi_range(base, nr_ids));
1624         kfree(bitmap);
1625 }
1626
1627 static void gic_reset_prop_table(void *va)
1628 {
1629         /* Priority 0xa0, Group-1, disabled */
1630         memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1631
1632         /* Make sure the GIC will observe the written configuration */
1633         gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1634 }
1635
1636 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1637 {
1638         struct page *prop_page;
1639
1640         prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1641         if (!prop_page)
1642                 return NULL;
1643
1644         gic_reset_prop_table(page_address(prop_page));
1645
1646         return prop_page;
1647 }
1648
1649 static void its_free_prop_table(struct page *prop_page)
1650 {
1651         free_pages((unsigned long)page_address(prop_page),
1652                    get_order(LPI_PROPBASE_SZ));
1653 }
1654
1655 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1656 {
1657         phys_addr_t start, end, addr_end;
1658         u64 i;
1659
1660         /*
1661          * We don't bother checking for a kdump kernel as by
1662          * construction, the LPI tables are out of this kernel's
1663          * memory map.
1664          */
1665         if (is_kdump_kernel())
1666                 return true;
1667
1668         addr_end = addr + size - 1;
1669
1670         for_each_reserved_mem_region(i, &start, &end) {
1671                 if (addr >= start && addr_end <= end)
1672                         return true;
1673         }
1674
1675         /* Not found, not a good sign... */
1676         pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1677                 &addr, &addr_end);
1678         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1679         return false;
1680 }
1681
1682 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1683 {
1684         if (efi_enabled(EFI_CONFIG_TABLES))
1685                 return efi_mem_reserve_persistent(addr, size);
1686
1687         return 0;
1688 }
1689
1690 static int __init its_setup_lpi_prop_table(void)
1691 {
1692         if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1693                 u64 val;
1694
1695                 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1696                 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1697
1698                 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1699                 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1700                                                      LPI_PROPBASE_SZ,
1701                                                      MEMREMAP_WB);
1702                 gic_reset_prop_table(gic_rdists->prop_table_va);
1703         } else {
1704                 struct page *page;
1705
1706                 lpi_id_bits = min_t(u32,
1707                                     GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1708                                     ITS_MAX_LPI_NRBITS);
1709                 page = its_allocate_prop_table(GFP_NOWAIT);
1710                 if (!page) {
1711                         pr_err("Failed to allocate PROPBASE\n");
1712                         return -ENOMEM;
1713                 }
1714
1715                 gic_rdists->prop_table_pa = page_to_phys(page);
1716                 gic_rdists->prop_table_va = page_address(page);
1717                 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1718                                           LPI_PROPBASE_SZ));
1719         }
1720
1721         pr_info("GICv3: using LPI property table @%pa\n",
1722                 &gic_rdists->prop_table_pa);
1723
1724         return its_lpi_init(lpi_id_bits);
1725 }
1726
1727 static const char *its_base_type_string[] = {
1728         [GITS_BASER_TYPE_DEVICE]        = "Devices",
1729         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
1730         [GITS_BASER_TYPE_RESERVED3]     = "Reserved (3)",
1731         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
1732         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
1733         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
1734         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
1735 };
1736
1737 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1738 {
1739         u32 idx = baser - its->tables;
1740
1741         return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1742 }
1743
1744 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1745                             u64 val)
1746 {
1747         u32 idx = baser - its->tables;
1748
1749         gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1750         baser->val = its_read_baser(its, baser);
1751 }
1752
1753 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1754                            u64 cache, u64 shr, u32 psz, u32 order,
1755                            bool indirect)
1756 {
1757         u64 val = its_read_baser(its, baser);
1758         u64 esz = GITS_BASER_ENTRY_SIZE(val);
1759         u64 type = GITS_BASER_TYPE(val);
1760         u64 baser_phys, tmp;
1761         u32 alloc_pages;
1762         struct page *page;
1763         void *base;
1764
1765 retry_alloc_baser:
1766         alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1767         if (alloc_pages > GITS_BASER_PAGES_MAX) {
1768                 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1769                         &its->phys_base, its_base_type_string[type],
1770                         alloc_pages, GITS_BASER_PAGES_MAX);
1771                 alloc_pages = GITS_BASER_PAGES_MAX;
1772                 order = get_order(GITS_BASER_PAGES_MAX * psz);
1773         }
1774
1775         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1776         if (!page)
1777                 return -ENOMEM;
1778
1779         base = (void *)page_address(page);
1780         baser_phys = virt_to_phys(base);
1781
1782         /* Check if the physical address of the memory is above 48bits */
1783         if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1784
1785                 /* 52bit PA is supported only when PageSize=64K */
1786                 if (psz != SZ_64K) {
1787                         pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1788                         free_pages((unsigned long)base, order);
1789                         return -ENXIO;
1790                 }
1791
1792                 /* Convert 52bit PA to 48bit field */
1793                 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1794         }
1795
1796 retry_baser:
1797         val = (baser_phys                                        |
1798                 (type << GITS_BASER_TYPE_SHIFT)                  |
1799                 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)       |
1800                 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)    |
1801                 cache                                            |
1802                 shr                                              |
1803                 GITS_BASER_VALID);
1804
1805         val |=  indirect ? GITS_BASER_INDIRECT : 0x0;
1806
1807         switch (psz) {
1808         case SZ_4K:
1809                 val |= GITS_BASER_PAGE_SIZE_4K;
1810                 break;
1811         case SZ_16K:
1812                 val |= GITS_BASER_PAGE_SIZE_16K;
1813                 break;
1814         case SZ_64K:
1815                 val |= GITS_BASER_PAGE_SIZE_64K;
1816                 break;
1817         }
1818
1819         its_write_baser(its, baser, val);
1820         tmp = baser->val;
1821
1822         if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1823                 /*
1824                  * Shareability didn't stick. Just use
1825                  * whatever the read reported, which is likely
1826                  * to be the only thing this redistributor
1827                  * supports. If that's zero, make it
1828                  * non-cacheable as well.
1829                  */
1830                 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1831                 if (!shr) {
1832                         cache = GITS_BASER_nC;
1833                         gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1834                 }
1835                 goto retry_baser;
1836         }
1837
1838         if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1839                 /*
1840                  * Page size didn't stick. Let's try a smaller
1841                  * size and retry. If we reach 4K, then
1842                  * something is horribly wrong...
1843                  */
1844                 free_pages((unsigned long)base, order);
1845                 baser->base = NULL;
1846
1847                 switch (psz) {
1848                 case SZ_16K:
1849                         psz = SZ_4K;
1850                         goto retry_alloc_baser;
1851                 case SZ_64K:
1852                         psz = SZ_16K;
1853                         goto retry_alloc_baser;
1854                 }
1855         }
1856
1857         if (val != tmp) {
1858                 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1859                        &its->phys_base, its_base_type_string[type],
1860                        val, tmp);
1861                 free_pages((unsigned long)base, order);
1862                 return -ENXIO;
1863         }
1864
1865         baser->order = order;
1866         baser->base = base;
1867         baser->psz = psz;
1868         tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1869
1870         pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1871                 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1872                 its_base_type_string[type],
1873                 (unsigned long)virt_to_phys(base),
1874                 indirect ? "indirect" : "flat", (int)esz,
1875                 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1876
1877         return 0;
1878 }
1879
1880 static bool its_parse_indirect_baser(struct its_node *its,
1881                                      struct its_baser *baser,
1882                                      u32 psz, u32 *order, u32 ids)
1883 {
1884         u64 tmp = its_read_baser(its, baser);
1885         u64 type = GITS_BASER_TYPE(tmp);
1886         u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1887         u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1888         u32 new_order = *order;
1889         bool indirect = false;
1890
1891         /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1892         if ((esz << ids) > (psz * 2)) {
1893                 /*
1894                  * Find out whether hw supports a single or two-level table by
1895                  * table by reading bit at offset '62' after writing '1' to it.
1896                  */
1897                 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1898                 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1899
1900                 if (indirect) {
1901                         /*
1902                          * The size of the lvl2 table is equal to ITS page size
1903                          * which is 'psz'. For computing lvl1 table size,
1904                          * subtract ID bits that sparse lvl2 table from 'ids'
1905                          * which is reported by ITS hardware times lvl1 table
1906                          * entry size.
1907                          */
1908                         ids -= ilog2(psz / (int)esz);
1909                         esz = GITS_LVL1_ENTRY_SIZE;
1910                 }
1911         }
1912
1913         /*
1914          * Allocate as many entries as required to fit the
1915          * range of device IDs that the ITS can grok... The ID
1916          * space being incredibly sparse, this results in a
1917          * massive waste of memory if two-level device table
1918          * feature is not supported by hardware.
1919          */
1920         new_order = max_t(u32, get_order(esz << ids), new_order);
1921         if (new_order >= MAX_ORDER) {
1922                 new_order = MAX_ORDER - 1;
1923                 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1924                 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1925                         &its->phys_base, its_base_type_string[type],
1926                         its->device_ids, ids);
1927         }
1928
1929         *order = new_order;
1930
1931         return indirect;
1932 }
1933
1934 static void its_free_tables(struct its_node *its)
1935 {
1936         int i;
1937
1938         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1939                 if (its->tables[i].base) {
1940                         free_pages((unsigned long)its->tables[i].base,
1941                                    its->tables[i].order);
1942                         its->tables[i].base = NULL;
1943                 }
1944         }
1945 }
1946
1947 static int its_alloc_tables(struct its_node *its)
1948 {
1949         u64 shr = GITS_BASER_InnerShareable;
1950         u64 cache = GITS_BASER_RaWaWb;
1951         u32 psz = SZ_64K;
1952         int err, i;
1953
1954         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1955                 /* erratum 24313: ignore memory access type */
1956                 cache = GITS_BASER_nCnB;
1957
1958         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1959                 struct its_baser *baser = its->tables + i;
1960                 u64 val = its_read_baser(its, baser);
1961                 u64 type = GITS_BASER_TYPE(val);
1962                 u32 order = get_order(psz);
1963                 bool indirect = false;
1964
1965                 switch (type) {
1966                 case GITS_BASER_TYPE_NONE:
1967                         continue;
1968
1969                 case GITS_BASER_TYPE_DEVICE:
1970                         indirect = its_parse_indirect_baser(its, baser,
1971                                                             psz, &order,
1972                                                             its->device_ids);
1973                         break;
1974
1975                 case GITS_BASER_TYPE_VCPU:
1976                         indirect = its_parse_indirect_baser(its, baser,
1977                                                             psz, &order,
1978                                                             ITS_MAX_VPEID_BITS);
1979                         break;
1980                 }
1981
1982                 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1983                 if (err < 0) {
1984                         its_free_tables(its);
1985                         return err;
1986                 }
1987
1988                 /* Update settings which will be used for next BASERn */
1989                 psz = baser->psz;
1990                 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1991                 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1992         }
1993
1994         return 0;
1995 }
1996
1997 static int its_alloc_collections(struct its_node *its)
1998 {
1999         int i;
2000
2001         its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2002                                    GFP_KERNEL);
2003         if (!its->collections)
2004                 return -ENOMEM;
2005
2006         for (i = 0; i < nr_cpu_ids; i++)
2007                 its->collections[i].target_address = ~0ULL;
2008
2009         return 0;
2010 }
2011
2012 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2013 {
2014         struct page *pend_page;
2015
2016         pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2017                                 get_order(LPI_PENDBASE_SZ));
2018         if (!pend_page)
2019                 return NULL;
2020
2021         /* Make sure the GIC will observe the zero-ed page */
2022         gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2023
2024         return pend_page;
2025 }
2026
2027 static void its_free_pending_table(struct page *pt)
2028 {
2029         free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2030 }
2031
2032 /*
2033  * Booting with kdump and LPIs enabled is generally fine. Any other
2034  * case is wrong in the absence of firmware/EFI support.
2035  */
2036 static bool enabled_lpis_allowed(void)
2037 {
2038         phys_addr_t addr;
2039         u64 val;
2040
2041         /* Check whether the property table is in a reserved region */
2042         val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2043         addr = val & GENMASK_ULL(51, 12);
2044
2045         return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2046 }
2047
2048 static int __init allocate_lpi_tables(void)
2049 {
2050         u64 val;
2051         int err, cpu;
2052
2053         /*
2054          * If LPIs are enabled while we run this from the boot CPU,
2055          * flag the RD tables as pre-allocated if the stars do align.
2056          */
2057         val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2058         if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2059                 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2060                                       RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2061                 pr_info("GICv3: Using preallocated redistributor tables\n");
2062         }
2063
2064         err = its_setup_lpi_prop_table();
2065         if (err)
2066                 return err;
2067
2068         /*
2069          * We allocate all the pending tables anyway, as we may have a
2070          * mix of RDs that have had LPIs enabled, and some that
2071          * don't. We'll free the unused ones as each CPU comes online.
2072          */
2073         for_each_possible_cpu(cpu) {
2074                 struct page *pend_page;
2075
2076                 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2077                 if (!pend_page) {
2078                         pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2079                         return -ENOMEM;
2080                 }
2081
2082                 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2083         }
2084
2085         return 0;
2086 }
2087
2088 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2089 {
2090         u32 count = 1000000;    /* 1s! */
2091         bool clean;
2092         u64 val;
2093
2094         val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2095         val &= ~GICR_VPENDBASER_Valid;
2096         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2097
2098         do {
2099                 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2100                 clean = !(val & GICR_VPENDBASER_Dirty);
2101                 if (!clean) {
2102                         count--;
2103                         cpu_relax();
2104                         udelay(1);
2105                 }
2106         } while (!clean && count);
2107
2108         return val;
2109 }
2110
2111 static void its_cpu_init_lpis(void)
2112 {
2113         void __iomem *rbase = gic_data_rdist_rd_base();
2114         struct page *pend_page;
2115         phys_addr_t paddr;
2116         u64 val, tmp;
2117
2118         if (gic_data_rdist()->lpi_enabled)
2119                 return;
2120
2121         val = readl_relaxed(rbase + GICR_CTLR);
2122         if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2123             (val & GICR_CTLR_ENABLE_LPIS)) {
2124                 /*
2125                  * Check that we get the same property table on all
2126                  * RDs. If we don't, this is hopeless.
2127                  */
2128                 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2129                 paddr &= GENMASK_ULL(51, 12);
2130                 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2131                         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2132
2133                 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2134                 paddr &= GENMASK_ULL(51, 16);
2135
2136                 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2137                 its_free_pending_table(gic_data_rdist()->pend_page);
2138                 gic_data_rdist()->pend_page = NULL;
2139
2140                 goto out;
2141         }
2142
2143         pend_page = gic_data_rdist()->pend_page;
2144         paddr = page_to_phys(pend_page);
2145         WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2146
2147         /* set PROPBASE */
2148         val = (gic_rdists->prop_table_pa |
2149                GICR_PROPBASER_InnerShareable |
2150                GICR_PROPBASER_RaWaWb |
2151                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2152
2153         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2154         tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2155
2156         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2157                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2158                         /*
2159                          * The HW reports non-shareable, we must
2160                          * remove the cacheability attributes as
2161                          * well.
2162                          */
2163                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2164                                  GICR_PROPBASER_CACHEABILITY_MASK);
2165                         val |= GICR_PROPBASER_nC;
2166                         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2167                 }
2168                 pr_info_once("GIC: using cache flushing for LPI property table\n");
2169                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2170         }
2171
2172         /* set PENDBASE */
2173         val = (page_to_phys(pend_page) |
2174                GICR_PENDBASER_InnerShareable |
2175                GICR_PENDBASER_RaWaWb);
2176
2177         gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2178         tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2179
2180         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2181                 /*
2182                  * The HW reports non-shareable, we must remove the
2183                  * cacheability attributes as well.
2184                  */
2185                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2186                          GICR_PENDBASER_CACHEABILITY_MASK);
2187                 val |= GICR_PENDBASER_nC;
2188                 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2189         }
2190
2191         /* Enable LPIs */
2192         val = readl_relaxed(rbase + GICR_CTLR);
2193         val |= GICR_CTLR_ENABLE_LPIS;
2194         writel_relaxed(val, rbase + GICR_CTLR);
2195
2196         if (gic_rdists->has_vlpis) {
2197                 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2198
2199                 /*
2200                  * It's possible for CPU to receive VLPIs before it is
2201                  * sheduled as a vPE, especially for the first CPU, and the
2202                  * VLPI with INTID larger than 2^(IDbits+1) will be considered
2203                  * as out of range and dropped by GIC.
2204                  * So we initialize IDbits to known value to avoid VLPI drop.
2205                  */
2206                 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2207                 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2208                         smp_processor_id(), val);
2209                 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2210
2211                 /*
2212                  * Also clear Valid bit of GICR_VPENDBASER, in case some
2213                  * ancient programming gets left in and has possibility of
2214                  * corrupting memory.
2215                  */
2216                 val = its_clear_vpend_valid(vlpi_base);
2217                 WARN_ON(val & GICR_VPENDBASER_Dirty);
2218         }
2219
2220         /* Make sure the GIC has seen the above */
2221         dsb(sy);
2222 out:
2223         gic_data_rdist()->lpi_enabled = true;
2224         pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2225                 smp_processor_id(),
2226                 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2227                 &paddr);
2228 }
2229
2230 static void its_cpu_init_collection(struct its_node *its)
2231 {
2232         int cpu = smp_processor_id();
2233         u64 target;
2234
2235         /* avoid cross node collections and its mapping */
2236         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2237                 struct device_node *cpu_node;
2238
2239                 cpu_node = of_get_cpu_node(cpu, NULL);
2240                 if (its->numa_node != NUMA_NO_NODE &&
2241                         its->numa_node != of_node_to_nid(cpu_node))
2242                         return;
2243         }
2244
2245         /*
2246          * We now have to bind each collection to its target
2247          * redistributor.
2248          */
2249         if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2250                 /*
2251                  * This ITS wants the physical address of the
2252                  * redistributor.
2253                  */
2254                 target = gic_data_rdist()->phys_base;
2255         } else {
2256                 /* This ITS wants a linear CPU number. */
2257                 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2258                 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2259         }
2260
2261         /* Perform collection mapping */
2262         its->collections[cpu].target_address = target;
2263         its->collections[cpu].col_id = cpu;
2264
2265         its_send_mapc(its, &its->collections[cpu], 1);
2266         its_send_invall(its, &its->collections[cpu]);
2267 }
2268
2269 static void its_cpu_init_collections(void)
2270 {
2271         struct its_node *its;
2272
2273         raw_spin_lock(&its_lock);
2274
2275         list_for_each_entry(its, &its_nodes, entry)
2276                 its_cpu_init_collection(its);
2277
2278         raw_spin_unlock(&its_lock);
2279 }
2280
2281 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2282 {
2283         struct its_device *its_dev = NULL, *tmp;
2284         unsigned long flags;
2285
2286         raw_spin_lock_irqsave(&its->lock, flags);
2287
2288         list_for_each_entry(tmp, &its->its_device_list, entry) {
2289                 if (tmp->device_id == dev_id) {
2290                         its_dev = tmp;
2291                         break;
2292                 }
2293         }
2294
2295         raw_spin_unlock_irqrestore(&its->lock, flags);
2296
2297         return its_dev;
2298 }
2299
2300 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2301 {
2302         int i;
2303
2304         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2305                 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2306                         return &its->tables[i];
2307         }
2308
2309         return NULL;
2310 }
2311
2312 static bool its_alloc_table_entry(struct its_node *its,
2313                                   struct its_baser *baser, u32 id)
2314 {
2315         struct page *page;
2316         u32 esz, idx;
2317         __le64 *table;
2318
2319         /* Don't allow device id that exceeds single, flat table limit */
2320         esz = GITS_BASER_ENTRY_SIZE(baser->val);
2321         if (!(baser->val & GITS_BASER_INDIRECT))
2322                 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2323
2324         /* Compute 1st level table index & check if that exceeds table limit */
2325         idx = id >> ilog2(baser->psz / esz);
2326         if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2327                 return false;
2328
2329         table = baser->base;
2330
2331         /* Allocate memory for 2nd level table */
2332         if (!table[idx]) {
2333                 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2334                                         get_order(baser->psz));
2335                 if (!page)
2336                         return false;
2337
2338                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2339                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2340                         gic_flush_dcache_to_poc(page_address(page), baser->psz);
2341
2342                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2343
2344                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2345                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2346                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2347
2348                 /* Ensure updated table contents are visible to ITS hardware */
2349                 dsb(sy);
2350         }
2351
2352         return true;
2353 }
2354
2355 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2356 {
2357         struct its_baser *baser;
2358
2359         baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2360
2361         /* Don't allow device id that exceeds ITS hardware limit */
2362         if (!baser)
2363                 return (ilog2(dev_id) < its->device_ids);
2364
2365         return its_alloc_table_entry(its, baser, dev_id);
2366 }
2367
2368 static bool its_alloc_vpe_table(u32 vpe_id)
2369 {
2370         struct its_node *its;
2371
2372         /*
2373          * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2374          * could try and only do it on ITSs corresponding to devices
2375          * that have interrupts targeted at this VPE, but the
2376          * complexity becomes crazy (and you have tons of memory
2377          * anyway, right?).
2378          */
2379         list_for_each_entry(its, &its_nodes, entry) {
2380                 struct its_baser *baser;
2381
2382                 if (!its->is_v4)
2383                         continue;
2384
2385                 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2386                 if (!baser)
2387                         return false;
2388
2389                 if (!its_alloc_table_entry(its, baser, vpe_id))
2390                         return false;
2391         }
2392
2393         return true;
2394 }
2395
2396 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2397                                             int nvecs, bool alloc_lpis)
2398 {
2399         struct its_device *dev;
2400         unsigned long *lpi_map = NULL;
2401         unsigned long flags;
2402         u16 *col_map = NULL;
2403         void *itt;
2404         int lpi_base;
2405         int nr_lpis;
2406         int nr_ites;
2407         int sz;
2408
2409         if (!its_alloc_device_table(its, dev_id))
2410                 return NULL;
2411
2412         if (WARN_ON(!is_power_of_2(nvecs)))
2413                 nvecs = roundup_pow_of_two(nvecs);
2414
2415         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2416         /*
2417          * Even if the device wants a single LPI, the ITT must be
2418          * sized as a power of two (and you need at least one bit...).
2419          */
2420         nr_ites = max(2, nvecs);
2421         sz = nr_ites * its->ite_size;
2422         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2423         itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2424         if (alloc_lpis) {
2425                 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2426                 if (lpi_map)
2427                         col_map = kcalloc(nr_lpis, sizeof(*col_map),
2428                                           GFP_KERNEL);
2429         } else {
2430                 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2431                 nr_lpis = 0;
2432                 lpi_base = 0;
2433         }
2434
2435         if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
2436                 kfree(dev);
2437                 kfree(itt);
2438                 kfree(lpi_map);
2439                 kfree(col_map);
2440                 return NULL;
2441         }
2442
2443         gic_flush_dcache_to_poc(itt, sz);
2444
2445         dev->its = its;
2446         dev->itt = itt;
2447         dev->nr_ites = nr_ites;
2448         dev->event_map.lpi_map = lpi_map;
2449         dev->event_map.col_map = col_map;
2450         dev->event_map.lpi_base = lpi_base;
2451         dev->event_map.nr_lpis = nr_lpis;
2452         mutex_init(&dev->event_map.vlpi_lock);
2453         dev->device_id = dev_id;
2454         INIT_LIST_HEAD(&dev->entry);
2455
2456         raw_spin_lock_irqsave(&its->lock, flags);
2457         list_add(&dev->entry, &its->its_device_list);
2458         raw_spin_unlock_irqrestore(&its->lock, flags);
2459
2460         /* Map device to its ITT */
2461         its_send_mapd(dev, 1);
2462
2463         return dev;
2464 }
2465
2466 static void its_free_device(struct its_device *its_dev)
2467 {
2468         unsigned long flags;
2469
2470         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2471         list_del(&its_dev->entry);
2472         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2473         kfree(its_dev->itt);
2474         kfree(its_dev);
2475 }
2476
2477 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2478 {
2479         int idx;
2480
2481         /* Find a free LPI region in lpi_map and allocate them. */
2482         idx = bitmap_find_free_region(dev->event_map.lpi_map,
2483                                       dev->event_map.nr_lpis,
2484                                       get_count_order(nvecs));
2485         if (idx < 0)
2486                 return -ENOSPC;
2487
2488         *hwirq = dev->event_map.lpi_base + idx;
2489
2490         return 0;
2491 }
2492
2493 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2494                            int nvec, msi_alloc_info_t *info)
2495 {
2496         struct its_node *its;
2497         struct its_device *its_dev;
2498         struct msi_domain_info *msi_info;
2499         u32 dev_id;
2500         int err = 0;
2501
2502         /*
2503          * We ignore "dev" entirely, and rely on the dev_id that has
2504          * been passed via the scratchpad. This limits this domain's
2505          * usefulness to upper layers that definitely know that they
2506          * are built on top of the ITS.
2507          */
2508         dev_id = info->scratchpad[0].ul;
2509
2510         msi_info = msi_get_domain_info(domain);
2511         its = msi_info->data;
2512
2513         if (!gic_rdists->has_direct_lpi &&
2514             vpe_proxy.dev &&
2515             vpe_proxy.dev->its == its &&
2516             dev_id == vpe_proxy.dev->device_id) {
2517                 /* Bad luck. Get yourself a better implementation */
2518                 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2519                           dev_id);
2520                 return -EINVAL;
2521         }
2522
2523         mutex_lock(&its->dev_alloc_lock);
2524         its_dev = its_find_device(its, dev_id);
2525         if (its_dev) {
2526                 /*
2527                  * We already have seen this ID, probably through
2528                  * another alias (PCI bridge of some sort). No need to
2529                  * create the device.
2530                  */
2531                 its_dev->shared = true;
2532                 pr_debug("Reusing ITT for devID %x\n", dev_id);
2533                 goto out;
2534         }
2535
2536         its_dev = its_create_device(its, dev_id, nvec, true);
2537         if (!its_dev) {
2538                 err = -ENOMEM;
2539                 goto out;
2540         }
2541
2542         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2543 out:
2544         mutex_unlock(&its->dev_alloc_lock);
2545         info->scratchpad[0].ptr = its_dev;
2546         return err;
2547 }
2548
2549 static struct msi_domain_ops its_msi_domain_ops = {
2550         .msi_prepare    = its_msi_prepare,
2551 };
2552
2553 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2554                                     unsigned int virq,
2555                                     irq_hw_number_t hwirq)
2556 {
2557         struct irq_fwspec fwspec;
2558
2559         if (irq_domain_get_of_node(domain->parent)) {
2560                 fwspec.fwnode = domain->parent->fwnode;
2561                 fwspec.param_count = 3;
2562                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2563                 fwspec.param[1] = hwirq;
2564                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2565         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2566                 fwspec.fwnode = domain->parent->fwnode;
2567                 fwspec.param_count = 2;
2568                 fwspec.param[0] = hwirq;
2569                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2570         } else {
2571                 return -EINVAL;
2572         }
2573
2574         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2575 }
2576
2577 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2578                                 unsigned int nr_irqs, void *args)
2579 {
2580         msi_alloc_info_t *info = args;
2581         struct its_device *its_dev = info->scratchpad[0].ptr;
2582         struct its_node *its = its_dev->its;
2583         struct irq_data *irqd;
2584         irq_hw_number_t hwirq;
2585         int err;
2586         int i;
2587
2588         err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2589         if (err)
2590                 return err;
2591
2592         err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2593         if (err)
2594                 return err;
2595
2596         for (i = 0; i < nr_irqs; i++) {
2597                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2598                 if (err)
2599                         return err;
2600
2601                 irq_domain_set_hwirq_and_chip(domain, virq + i,
2602                                               hwirq + i, &its_irq_chip, its_dev);
2603                 irqd = irq_get_irq_data(virq + i);
2604                 irqd_set_single_target(irqd);
2605                 irqd_set_affinity_on_activate(irqd);
2606                 pr_debug("ID:%d pID:%d vID:%d\n",
2607                          (int)(hwirq + i - its_dev->event_map.lpi_base),
2608                          (int)(hwirq + i), virq + i);
2609         }
2610
2611         return 0;
2612 }
2613
2614 static int its_irq_domain_activate(struct irq_domain *domain,
2615                                    struct irq_data *d, bool reserve)
2616 {
2617         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2618         u32 event = its_get_event_id(d);
2619         const struct cpumask *cpu_mask = cpu_online_mask;
2620         int cpu;
2621
2622         /* get the cpu_mask of local node */
2623         if (its_dev->its->numa_node >= 0)
2624                 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2625
2626         /* Bind the LPI to the first possible CPU */
2627         cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2628         if (cpu >= nr_cpu_ids) {
2629                 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2630                         return -EINVAL;
2631
2632                 cpu = cpumask_first(cpu_online_mask);
2633         }
2634
2635         its_dev->event_map.col_map[event] = cpu;
2636         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2637
2638         /* Map the GIC IRQ and event to the device */
2639         its_send_mapti(its_dev, d->hwirq, event);
2640         return 0;
2641 }
2642
2643 static void its_irq_domain_deactivate(struct irq_domain *domain,
2644                                       struct irq_data *d)
2645 {
2646         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2647         u32 event = its_get_event_id(d);
2648
2649         /* Stop the delivery of interrupts */
2650         its_send_discard(its_dev, event);
2651 }
2652
2653 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2654                                 unsigned int nr_irqs)
2655 {
2656         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2657         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2658         struct its_node *its = its_dev->its;
2659         int i;
2660
2661         bitmap_release_region(its_dev->event_map.lpi_map,
2662                               its_get_event_id(irq_domain_get_irq_data(domain, virq)),
2663                               get_count_order(nr_irqs));
2664
2665         for (i = 0; i < nr_irqs; i++) {
2666                 struct irq_data *data = irq_domain_get_irq_data(domain,
2667                                                                 virq + i);
2668                 /* Nuke the entry in the domain */
2669                 irq_domain_reset_irq_data(data);
2670         }
2671
2672         mutex_lock(&its->dev_alloc_lock);
2673
2674         /*
2675          * If all interrupts have been freed, start mopping the
2676          * floor. This is conditionned on the device not being shared.
2677          */
2678         if (!its_dev->shared &&
2679             bitmap_empty(its_dev->event_map.lpi_map,
2680                          its_dev->event_map.nr_lpis)) {
2681                 its_lpi_free(its_dev->event_map.lpi_map,
2682                              its_dev->event_map.lpi_base,
2683                              its_dev->event_map.nr_lpis);
2684                 kfree(its_dev->event_map.col_map);
2685
2686                 /* Unmap device/itt */
2687                 its_send_mapd(its_dev, 0);
2688                 its_free_device(its_dev);
2689         }
2690
2691         mutex_unlock(&its->dev_alloc_lock);
2692
2693         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2694 }
2695
2696 static const struct irq_domain_ops its_domain_ops = {
2697         .alloc                  = its_irq_domain_alloc,
2698         .free                   = its_irq_domain_free,
2699         .activate               = its_irq_domain_activate,
2700         .deactivate             = its_irq_domain_deactivate,
2701 };
2702
2703 /*
2704  * This is insane.
2705  *
2706  * If a GICv4 doesn't implement Direct LPIs (which is extremely
2707  * likely), the only way to perform an invalidate is to use a fake
2708  * device to issue an INV command, implying that the LPI has first
2709  * been mapped to some event on that device. Since this is not exactly
2710  * cheap, we try to keep that mapping around as long as possible, and
2711  * only issue an UNMAP if we're short on available slots.
2712  *
2713  * Broken by design(tm).
2714  */
2715 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2716 {
2717         /* Already unmapped? */
2718         if (vpe->vpe_proxy_event == -1)
2719                 return;
2720
2721         its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2722         vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2723
2724         /*
2725          * We don't track empty slots at all, so let's move the
2726          * next_victim pointer if we can quickly reuse that slot
2727          * instead of nuking an existing entry. Not clear that this is
2728          * always a win though, and this might just generate a ripple
2729          * effect... Let's just hope VPEs don't migrate too often.
2730          */
2731         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2732                 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2733
2734         vpe->vpe_proxy_event = -1;
2735 }
2736
2737 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2738 {
2739         if (!gic_rdists->has_direct_lpi) {
2740                 unsigned long flags;
2741
2742                 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2743                 its_vpe_db_proxy_unmap_locked(vpe);
2744                 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2745         }
2746 }
2747
2748 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2749 {
2750         /* Already mapped? */
2751         if (vpe->vpe_proxy_event != -1)
2752                 return;
2753
2754         /* This slot was already allocated. Kick the other VPE out. */
2755         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2756                 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2757
2758         /* Map the new VPE instead */
2759         vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2760         vpe->vpe_proxy_event = vpe_proxy.next_victim;
2761         vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2762
2763         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2764         its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2765 }
2766
2767 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2768 {
2769         unsigned long flags;
2770         struct its_collection *target_col;
2771
2772         if (gic_rdists->has_direct_lpi) {
2773                 void __iomem *rdbase;
2774
2775                 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2776                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2777                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2778                         cpu_relax();
2779
2780                 return;
2781         }
2782
2783         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2784
2785         its_vpe_db_proxy_map_locked(vpe);
2786
2787         target_col = &vpe_proxy.dev->its->collections[to];
2788         its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2789         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2790
2791         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2792 }
2793
2794 static int its_vpe_set_affinity(struct irq_data *d,
2795                                 const struct cpumask *mask_val,
2796                                 bool force)
2797 {
2798         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2799         int cpu = cpumask_first(mask_val);
2800
2801         /*
2802          * Changing affinity is mega expensive, so let's be as lazy as
2803          * we can and only do it if we really have to. Also, if mapped
2804          * into the proxy device, we need to move the doorbell
2805          * interrupt to its new location.
2806          */
2807         if (vpe->col_idx != cpu) {
2808                 int from = vpe->col_idx;
2809
2810                 vpe->col_idx = cpu;
2811                 its_send_vmovp(vpe);
2812                 its_vpe_db_proxy_move(vpe, from, cpu);
2813         }
2814
2815         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2816
2817         return IRQ_SET_MASK_OK_DONE;
2818 }
2819
2820 static void its_vpe_schedule(struct its_vpe *vpe)
2821 {
2822         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2823         u64 val;
2824
2825         /* Schedule the VPE */
2826         val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2827                 GENMASK_ULL(51, 12);
2828         val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2829         val |= GICR_VPROPBASER_RaWb;
2830         val |= GICR_VPROPBASER_InnerShareable;
2831         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2832
2833         val  = virt_to_phys(page_address(vpe->vpt_page)) &
2834                 GENMASK_ULL(51, 16);
2835         val |= GICR_VPENDBASER_RaWaWb;
2836         val |= GICR_VPENDBASER_NonShareable;
2837         /*
2838          * There is no good way of finding out if the pending table is
2839          * empty as we can race against the doorbell interrupt very
2840          * easily. So in the end, vpe->pending_last is only an
2841          * indication that the vcpu has something pending, not one
2842          * that the pending table is empty. A good implementation
2843          * would be able to read its coarse map pretty quickly anyway,
2844          * making this a tolerable issue.
2845          */
2846         val |= GICR_VPENDBASER_PendingLast;
2847         val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2848         val |= GICR_VPENDBASER_Valid;
2849         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2850 }
2851
2852 static void its_vpe_deschedule(struct its_vpe *vpe)
2853 {
2854         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2855         u64 val;
2856
2857         val = its_clear_vpend_valid(vlpi_base);
2858
2859         if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2860                 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2861                 vpe->idai = false;
2862                 vpe->pending_last = true;
2863         } else {
2864                 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2865                 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2866         }
2867 }
2868
2869 static void its_vpe_invall(struct its_vpe *vpe)
2870 {
2871         struct its_node *its;
2872
2873         list_for_each_entry(its, &its_nodes, entry) {
2874                 if (!its->is_v4)
2875                         continue;
2876
2877                 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2878                         continue;
2879
2880                 /*
2881                  * Sending a VINVALL to a single ITS is enough, as all
2882                  * we need is to reach the redistributors.
2883                  */
2884                 its_send_vinvall(its, vpe);
2885                 return;
2886         }
2887 }
2888
2889 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2890 {
2891         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2892         struct its_cmd_info *info = vcpu_info;
2893
2894         switch (info->cmd_type) {
2895         case SCHEDULE_VPE:
2896                 its_vpe_schedule(vpe);
2897                 return 0;
2898
2899         case DESCHEDULE_VPE:
2900                 its_vpe_deschedule(vpe);
2901                 return 0;
2902
2903         case INVALL_VPE:
2904                 its_vpe_invall(vpe);
2905                 return 0;
2906
2907         default:
2908                 return -EINVAL;
2909         }
2910 }
2911
2912 static void its_vpe_send_cmd(struct its_vpe *vpe,
2913                              void (*cmd)(struct its_device *, u32))
2914 {
2915         unsigned long flags;
2916
2917         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2918
2919         its_vpe_db_proxy_map_locked(vpe);
2920         cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2921
2922         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2923 }
2924
2925 static void its_vpe_send_inv(struct irq_data *d)
2926 {
2927         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2928
2929         if (gic_rdists->has_direct_lpi) {
2930                 void __iomem *rdbase;
2931
2932                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2933                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2934                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2935                         cpu_relax();
2936         } else {
2937                 its_vpe_send_cmd(vpe, its_send_inv);
2938         }
2939 }
2940
2941 static void its_vpe_mask_irq(struct irq_data *d)
2942 {
2943         /*
2944          * We need to unmask the LPI, which is described by the parent
2945          * irq_data. Instead of calling into the parent (which won't
2946          * exactly do the right thing, let's simply use the
2947          * parent_data pointer. Yes, I'm naughty.
2948          */
2949         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2950         its_vpe_send_inv(d);
2951 }
2952
2953 static void its_vpe_unmask_irq(struct irq_data *d)
2954 {
2955         /* Same hack as above... */
2956         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2957         its_vpe_send_inv(d);
2958 }
2959
2960 static int its_vpe_set_irqchip_state(struct irq_data *d,
2961                                      enum irqchip_irq_state which,
2962                                      bool state)
2963 {
2964         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2965
2966         if (which != IRQCHIP_STATE_PENDING)
2967                 return -EINVAL;
2968
2969         if (gic_rdists->has_direct_lpi) {
2970                 void __iomem *rdbase;
2971
2972                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2973                 if (state) {
2974                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2975                 } else {
2976                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2977                         while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2978                                 cpu_relax();
2979                 }
2980         } else {
2981                 if (state)
2982                         its_vpe_send_cmd(vpe, its_send_int);
2983                 else
2984                         its_vpe_send_cmd(vpe, its_send_clear);
2985         }
2986
2987         return 0;
2988 }
2989
2990 static int its_vpe_retrigger(struct irq_data *d)
2991 {
2992         return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
2993 }
2994
2995 static struct irq_chip its_vpe_irq_chip = {
2996         .name                   = "GICv4-vpe",
2997         .irq_mask               = its_vpe_mask_irq,
2998         .irq_unmask             = its_vpe_unmask_irq,
2999         .irq_eoi                = irq_chip_eoi_parent,
3000         .irq_set_affinity       = its_vpe_set_affinity,
3001         .irq_retrigger          = its_vpe_retrigger,
3002         .irq_set_irqchip_state  = its_vpe_set_irqchip_state,
3003         .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
3004 };
3005
3006 static int its_vpe_id_alloc(void)
3007 {
3008         return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
3009 }
3010
3011 static void its_vpe_id_free(u16 id)
3012 {
3013         ida_simple_remove(&its_vpeid_ida, id);
3014 }
3015
3016 static int its_vpe_init(struct its_vpe *vpe)
3017 {
3018         struct page *vpt_page;
3019         int vpe_id;
3020
3021         /* Allocate vpe_id */
3022         vpe_id = its_vpe_id_alloc();
3023         if (vpe_id < 0)
3024                 return vpe_id;
3025
3026         /* Allocate VPT */
3027         vpt_page = its_allocate_pending_table(GFP_KERNEL);
3028         if (!vpt_page) {
3029                 its_vpe_id_free(vpe_id);
3030                 return -ENOMEM;
3031         }
3032
3033         if (!its_alloc_vpe_table(vpe_id)) {
3034                 its_vpe_id_free(vpe_id);
3035                 its_free_pending_table(vpt_page);
3036                 return -ENOMEM;
3037         }
3038
3039         vpe->vpe_id = vpe_id;
3040         vpe->vpt_page = vpt_page;
3041         vpe->vpe_proxy_event = -1;
3042
3043         return 0;
3044 }
3045
3046 static void its_vpe_teardown(struct its_vpe *vpe)
3047 {
3048         its_vpe_db_proxy_unmap(vpe);
3049         its_vpe_id_free(vpe->vpe_id);
3050         its_free_pending_table(vpe->vpt_page);
3051 }
3052
3053 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3054                                     unsigned int virq,
3055                                     unsigned int nr_irqs)
3056 {
3057         struct its_vm *vm = domain->host_data;
3058         int i;
3059
3060         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3061
3062         for (i = 0; i < nr_irqs; i++) {
3063                 struct irq_data *data = irq_domain_get_irq_data(domain,
3064                                                                 virq + i);
3065                 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3066
3067                 BUG_ON(vm != vpe->its_vm);
3068
3069                 clear_bit(data->hwirq, vm->db_bitmap);
3070                 its_vpe_teardown(vpe);
3071                 irq_domain_reset_irq_data(data);
3072         }
3073
3074         if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3075                 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3076                 its_free_prop_table(vm->vprop_page);
3077         }
3078 }
3079
3080 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3081                                     unsigned int nr_irqs, void *args)
3082 {
3083         struct its_vm *vm = args;
3084         unsigned long *bitmap;
3085         struct page *vprop_page;
3086         int base, nr_ids, i, err = 0;
3087
3088         BUG_ON(!vm);
3089
3090         bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3091         if (!bitmap)
3092                 return -ENOMEM;
3093
3094         if (nr_ids < nr_irqs) {
3095                 its_lpi_free(bitmap, base, nr_ids);
3096                 return -ENOMEM;
3097         }
3098
3099         vprop_page = its_allocate_prop_table(GFP_KERNEL);
3100         if (!vprop_page) {
3101                 its_lpi_free(bitmap, base, nr_ids);
3102                 return -ENOMEM;
3103         }
3104
3105         vm->db_bitmap = bitmap;
3106         vm->db_lpi_base = base;
3107         vm->nr_db_lpis = nr_ids;
3108         vm->vprop_page = vprop_page;
3109
3110         for (i = 0; i < nr_irqs; i++) {
3111                 vm->vpes[i]->vpe_db_lpi = base + i;
3112                 err = its_vpe_init(vm->vpes[i]);
3113                 if (err)
3114                         break;
3115                 err = its_irq_gic_domain_alloc(domain, virq + i,
3116                                                vm->vpes[i]->vpe_db_lpi);
3117                 if (err)
3118                         break;
3119                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3120                                               &its_vpe_irq_chip, vm->vpes[i]);
3121                 set_bit(i, bitmap);
3122         }
3123
3124         if (err) {
3125                 if (i > 0)
3126                         its_vpe_irq_domain_free(domain, virq, i);
3127
3128                 its_lpi_free(bitmap, base, nr_ids);
3129                 its_free_prop_table(vprop_page);
3130         }
3131
3132         return err;
3133 }
3134
3135 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3136                                        struct irq_data *d, bool reserve)
3137 {
3138         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3139         struct its_node *its;
3140
3141         /* If we use the list map, we issue VMAPP on demand... */
3142         if (its_list_map)
3143                 return 0;
3144
3145         /* Map the VPE to the first possible CPU */
3146         vpe->col_idx = cpumask_first(cpu_online_mask);
3147
3148         list_for_each_entry(its, &its_nodes, entry) {
3149                 if (!its->is_v4)
3150                         continue;
3151
3152                 its_send_vmapp(its, vpe, true);
3153                 its_send_vinvall(its, vpe);
3154         }
3155
3156         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3157
3158         return 0;
3159 }
3160
3161 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3162                                           struct irq_data *d)
3163 {
3164         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3165         struct its_node *its;
3166
3167         /*
3168          * If we use the list map, we unmap the VPE once no VLPIs are
3169          * associated with the VM.
3170          */
3171         if (its_list_map)
3172                 return;
3173
3174         list_for_each_entry(its, &its_nodes, entry) {
3175                 if (!its->is_v4)
3176                         continue;
3177
3178                 its_send_vmapp(its, vpe, false);
3179         }
3180 }
3181
3182 static const struct irq_domain_ops its_vpe_domain_ops = {
3183         .alloc                  = its_vpe_irq_domain_alloc,
3184         .free                   = its_vpe_irq_domain_free,
3185         .activate               = its_vpe_irq_domain_activate,
3186         .deactivate             = its_vpe_irq_domain_deactivate,
3187 };
3188
3189 static int its_force_quiescent(void __iomem *base)
3190 {
3191         u32 count = 1000000;    /* 1s */
3192         u32 val;
3193
3194         val = readl_relaxed(base + GITS_CTLR);
3195         /*
3196          * GIC architecture specification requires the ITS to be both
3197          * disabled and quiescent for writes to GITS_BASER<n> or
3198          * GITS_CBASER to not have UNPREDICTABLE results.
3199          */
3200         if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3201                 return 0;
3202
3203         /* Disable the generation of all interrupts to this ITS */
3204         val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3205         writel_relaxed(val, base + GITS_CTLR);
3206
3207         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3208         while (1) {
3209                 val = readl_relaxed(base + GITS_CTLR);
3210                 if (val & GITS_CTLR_QUIESCENT)
3211                         return 0;
3212
3213                 count--;
3214                 if (!count)
3215                         return -EBUSY;
3216
3217                 cpu_relax();
3218                 udelay(1);
3219         }
3220 }
3221
3222 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3223 {
3224         struct its_node *its = data;
3225
3226         /* erratum 22375: only alloc 8MB table size */
3227         its->device_ids = 0x14;         /* 20 bits, 8MB */
3228         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3229
3230         return true;
3231 }
3232
3233 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3234 {
3235         struct its_node *its = data;
3236
3237         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3238
3239         return true;
3240 }
3241
3242 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3243 {
3244         struct its_node *its = data;
3245
3246         /* On QDF2400, the size of the ITE is 16Bytes */
3247         its->ite_size = 16;
3248
3249         return true;
3250 }
3251
3252 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3253 {
3254         struct its_node *its = its_dev->its;
3255
3256         /*
3257          * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3258          * which maps 32-bit writes targeted at a separate window of
3259          * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3260          * with device ID taken from bits [device_id_bits + 1:2] of
3261          * the window offset.
3262          */
3263         return its->pre_its_base + (its_dev->device_id << 2);
3264 }
3265
3266 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3267 {
3268         struct its_node *its = data;
3269         u32 pre_its_window[2];
3270         u32 ids;
3271
3272         if (!fwnode_property_read_u32_array(its->fwnode_handle,
3273                                            "socionext,synquacer-pre-its",
3274                                            pre_its_window,
3275                                            ARRAY_SIZE(pre_its_window))) {
3276
3277                 its->pre_its_base = pre_its_window[0];
3278                 its->get_msi_base = its_irq_get_msi_base_pre_its;
3279
3280                 ids = ilog2(pre_its_window[1]) - 2;
3281                 if (its->device_ids > ids)
3282                         its->device_ids = ids;
3283
3284                 /* the pre-ITS breaks isolation, so disable MSI remapping */
3285                 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3286                 return true;
3287         }
3288         return false;
3289 }
3290
3291 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3292 {
3293         struct its_node *its = data;
3294
3295         /*
3296          * Hip07 insists on using the wrong address for the VLPI
3297          * page. Trick it into doing the right thing...
3298          */
3299         its->vlpi_redist_offset = SZ_128K;
3300         return true;
3301 }
3302
3303 static const struct gic_quirk its_quirks[] = {
3304 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3305         {
3306                 .desc   = "ITS: Cavium errata 22375, 24313",
3307                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
3308                 .mask   = 0xffff0fff,
3309                 .init   = its_enable_quirk_cavium_22375,
3310         },
3311 #endif
3312 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3313         {
3314                 .desc   = "ITS: Cavium erratum 23144",
3315                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
3316                 .mask   = 0xffff0fff,
3317                 .init   = its_enable_quirk_cavium_23144,
3318         },
3319 #endif
3320 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3321         {
3322                 .desc   = "ITS: QDF2400 erratum 0065",
3323                 .iidr   = 0x00001070, /* QDF2400 ITS rev 1.x */
3324                 .mask   = 0xffffffff,
3325                 .init   = its_enable_quirk_qdf2400_e0065,
3326         },
3327 #endif
3328 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3329         {
3330                 /*
3331                  * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3332                  * implementation, but with a 'pre-ITS' added that requires
3333                  * special handling in software.
3334                  */
3335                 .desc   = "ITS: Socionext Synquacer pre-ITS",
3336                 .iidr   = 0x0001143b,
3337                 .mask   = 0xffffffff,
3338                 .init   = its_enable_quirk_socionext_synquacer,
3339         },
3340 #endif
3341 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3342         {
3343                 .desc   = "ITS: Hip07 erratum 161600802",
3344                 .iidr   = 0x00000004,
3345                 .mask   = 0xffffffff,
3346                 .init   = its_enable_quirk_hip07_161600802,
3347         },
3348 #endif
3349         {
3350         }
3351 };
3352
3353 static void its_enable_quirks(struct its_node *its)
3354 {
3355         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3356
3357         gic_enable_quirks(iidr, its_quirks, its);
3358 }
3359
3360 static int its_save_disable(void)
3361 {
3362         struct its_node *its;
3363         int err = 0;
3364
3365         raw_spin_lock(&its_lock);
3366         list_for_each_entry(its, &its_nodes, entry) {
3367                 void __iomem *base;
3368
3369                 base = its->base;
3370                 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3371                 err = its_force_quiescent(base);
3372                 if (err) {
3373                         pr_err("ITS@%pa: failed to quiesce: %d\n",
3374                                &its->phys_base, err);
3375                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3376                         goto err;
3377                 }
3378
3379                 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3380         }
3381
3382 err:
3383         if (err) {
3384                 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3385                         void __iomem *base;
3386
3387                         base = its->base;
3388                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3389                 }
3390         }
3391         raw_spin_unlock(&its_lock);
3392
3393         return err;
3394 }
3395
3396 static void its_restore_enable(void)
3397 {
3398         struct its_node *its;
3399         int ret;
3400
3401         raw_spin_lock(&its_lock);
3402         list_for_each_entry(its, &its_nodes, entry) {
3403                 void __iomem *base;
3404                 int i;
3405
3406                 base = its->base;
3407
3408                 /*
3409                  * Make sure that the ITS is disabled. If it fails to quiesce,
3410                  * don't restore it since writing to CBASER or BASER<n>
3411                  * registers is undefined according to the GIC v3 ITS
3412                  * Specification.
3413                  *
3414                  * Firmware resuming with the ITS enabled is terminally broken.
3415                  */
3416                 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
3417                 ret = its_force_quiescent(base);
3418                 if (ret) {
3419                         pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3420                                &its->phys_base, ret);
3421                         continue;
3422                 }
3423
3424                 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3425
3426                 /*
3427                  * Writing CBASER resets CREADR to 0, so make CWRITER and
3428                  * cmd_write line up with it.
3429                  */
3430                 its->cmd_write = its->cmd_base;
3431                 gits_write_cwriter(0, base + GITS_CWRITER);
3432
3433                 /* Restore GITS_BASER from the value cache. */
3434                 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3435                         struct its_baser *baser = &its->tables[i];
3436
3437                         if (!(baser->val & GITS_BASER_VALID))
3438                                 continue;
3439
3440                         its_write_baser(its, baser, baser->val);
3441                 }
3442                 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3443
3444                 /*
3445                  * Reinit the collection if it's stored in the ITS. This is
3446                  * indicated by the col_id being less than the HCC field.
3447                  * CID < HCC as specified in the GIC v3 Documentation.
3448                  */
3449                 if (its->collections[smp_processor_id()].col_id <
3450                     GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3451                         its_cpu_init_collection(its);
3452         }
3453         raw_spin_unlock(&its_lock);
3454 }
3455
3456 static struct syscore_ops its_syscore_ops = {
3457         .suspend = its_save_disable,
3458         .resume = its_restore_enable,
3459 };
3460
3461 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3462 {
3463         struct irq_domain *inner_domain;
3464         struct msi_domain_info *info;
3465
3466         info = kzalloc(sizeof(*info), GFP_KERNEL);
3467         if (!info)
3468                 return -ENOMEM;
3469
3470         inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3471         if (!inner_domain) {
3472                 kfree(info);
3473                 return -ENOMEM;
3474         }
3475
3476         inner_domain->parent = its_parent;
3477         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3478         inner_domain->flags |= its->msi_domain_flags;
3479         info->ops = &its_msi_domain_ops;
3480         info->data = its;
3481         inner_domain->host_data = info;
3482
3483         return 0;
3484 }
3485
3486 static int its_init_vpe_domain(void)
3487 {
3488         struct its_node *its;
3489         u32 devid;
3490         int entries;
3491
3492         if (gic_rdists->has_direct_lpi) {
3493                 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3494                 return 0;
3495         }
3496
3497         /* Any ITS will do, even if not v4 */
3498         its = list_first_entry(&its_nodes, struct its_node, entry);
3499
3500         entries = roundup_pow_of_two(nr_cpu_ids);
3501         vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3502                                  GFP_KERNEL);
3503         if (!vpe_proxy.vpes) {
3504                 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3505                 return -ENOMEM;
3506         }
3507
3508         /* Use the last possible DevID */
3509         devid = GENMASK(its->device_ids - 1, 0);
3510         vpe_proxy.dev = its_create_device(its, devid, entries, false);
3511         if (!vpe_proxy.dev) {
3512                 kfree(vpe_proxy.vpes);
3513                 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3514                 return -ENOMEM;
3515         }
3516
3517         BUG_ON(entries > vpe_proxy.dev->nr_ites);
3518
3519         raw_spin_lock_init(&vpe_proxy.lock);
3520         vpe_proxy.next_victim = 0;
3521         pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3522                 devid, vpe_proxy.dev->nr_ites);
3523
3524         return 0;
3525 }
3526
3527 static int __init its_compute_its_list_map(struct resource *res,
3528                                            void __iomem *its_base)
3529 {
3530         int its_number;
3531         u32 ctlr;
3532
3533         /*
3534          * This is assumed to be done early enough that we're
3535          * guaranteed to be single-threaded, hence no
3536          * locking. Should this change, we should address
3537          * this.
3538          */
3539         its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3540         if (its_number >= GICv4_ITS_LIST_MAX) {
3541                 pr_err("ITS@%pa: No ITSList entry available!\n",
3542                        &res->start);
3543                 return -EINVAL;
3544         }
3545
3546         ctlr = readl_relaxed(its_base + GITS_CTLR);
3547         ctlr &= ~GITS_CTLR_ITS_NUMBER;
3548         ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3549         writel_relaxed(ctlr, its_base + GITS_CTLR);
3550         ctlr = readl_relaxed(its_base + GITS_CTLR);
3551         if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3552                 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3553                 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3554         }
3555
3556         if (test_and_set_bit(its_number, &its_list_map)) {
3557                 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3558                        &res->start, its_number);
3559                 return -EINVAL;
3560         }
3561
3562         return its_number;
3563 }
3564
3565 static int __init its_probe_one(struct resource *res,
3566                                 struct fwnode_handle *handle, int numa_node)
3567 {
3568         struct its_node *its;
3569         void __iomem *its_base;
3570         u32 val, ctlr;
3571         u64 baser, tmp, typer;
3572         struct page *page;
3573         int err;
3574
3575         its_base = ioremap(res->start, resource_size(res));
3576         if (!its_base) {
3577                 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3578                 return -ENOMEM;
3579         }
3580
3581         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3582         if (val != 0x30 && val != 0x40) {
3583                 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3584                 err = -ENODEV;
3585                 goto out_unmap;
3586         }
3587
3588         err = its_force_quiescent(its_base);
3589         if (err) {
3590                 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3591                 goto out_unmap;
3592         }
3593
3594         pr_info("ITS %pR\n", res);
3595
3596         its = kzalloc(sizeof(*its), GFP_KERNEL);
3597         if (!its) {
3598                 err = -ENOMEM;
3599                 goto out_unmap;
3600         }
3601
3602         raw_spin_lock_init(&its->lock);
3603         mutex_init(&its->dev_alloc_lock);
3604         INIT_LIST_HEAD(&its->entry);
3605         INIT_LIST_HEAD(&its->its_device_list);
3606         typer = gic_read_typer(its_base + GITS_TYPER);
3607         its->base = its_base;
3608         its->phys_base = res->start;
3609         its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3610         its->device_ids = GITS_TYPER_DEVBITS(typer);
3611         its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3612         if (its->is_v4) {
3613                 if (!(typer & GITS_TYPER_VMOVP)) {
3614                         err = its_compute_its_list_map(res, its_base);
3615                         if (err < 0)
3616                                 goto out_free_its;
3617
3618                         its->list_nr = err;
3619
3620                         pr_info("ITS@%pa: Using ITS number %d\n",
3621                                 &res->start, err);
3622                 } else {
3623                         pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3624                 }
3625         }
3626
3627         its->numa_node = numa_node;
3628
3629         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3630                                 get_order(ITS_CMD_QUEUE_SZ));
3631         if (!page) {
3632                 err = -ENOMEM;
3633                 goto out_free_its;
3634         }
3635         its->cmd_base = (void *)page_address(page);
3636         its->cmd_write = its->cmd_base;
3637         its->fwnode_handle = handle;
3638         its->get_msi_base = its_irq_get_msi_base;
3639         its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3640
3641         its_enable_quirks(its);
3642
3643         err = its_alloc_tables(its);
3644         if (err)
3645                 goto out_free_cmd;
3646
3647         err = its_alloc_collections(its);
3648         if (err)
3649                 goto out_free_tables;
3650
3651         baser = (virt_to_phys(its->cmd_base)    |
3652                  GITS_CBASER_RaWaWb             |
3653                  GITS_CBASER_InnerShareable     |
3654                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3655                  GITS_CBASER_VALID);
3656
3657         gits_write_cbaser(baser, its->base + GITS_CBASER);
3658         tmp = gits_read_cbaser(its->base + GITS_CBASER);
3659
3660         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3661                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3662                         /*
3663                          * The HW reports non-shareable, we must
3664                          * remove the cacheability attributes as
3665                          * well.
3666                          */
3667                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3668                                    GITS_CBASER_CACHEABILITY_MASK);
3669                         baser |= GITS_CBASER_nC;
3670                         gits_write_cbaser(baser, its->base + GITS_CBASER);
3671                 }
3672                 pr_info("ITS: using cache flushing for cmd queue\n");
3673                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3674         }
3675
3676         gits_write_cwriter(0, its->base + GITS_CWRITER);
3677         ctlr = readl_relaxed(its->base + GITS_CTLR);
3678         ctlr |= GITS_CTLR_ENABLE;
3679         if (its->is_v4)
3680                 ctlr |= GITS_CTLR_ImDe;
3681         writel_relaxed(ctlr, its->base + GITS_CTLR);
3682
3683         err = its_init_domain(handle, its);
3684         if (err)
3685                 goto out_free_tables;
3686
3687         raw_spin_lock(&its_lock);
3688         list_add(&its->entry, &its_nodes);
3689         raw_spin_unlock(&its_lock);
3690
3691         return 0;
3692
3693 out_free_tables:
3694         its_free_tables(its);
3695 out_free_cmd:
3696         free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3697 out_free_its:
3698         kfree(its);
3699 out_unmap:
3700         iounmap(its_base);
3701         pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3702         return err;
3703 }
3704
3705 static bool gic_rdists_supports_plpis(void)
3706 {
3707         return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3708 }
3709
3710 static int redist_disable_lpis(void)
3711 {
3712         void __iomem *rbase = gic_data_rdist_rd_base();
3713         u64 timeout = USEC_PER_SEC;
3714         u64 val;
3715
3716         if (!gic_rdists_supports_plpis()) {
3717                 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3718                 return -ENXIO;
3719         }
3720
3721         val = readl_relaxed(rbase + GICR_CTLR);
3722         if (!(val & GICR_CTLR_ENABLE_LPIS))
3723                 return 0;
3724
3725         /*
3726          * If coming via a CPU hotplug event, we don't need to disable
3727          * LPIs before trying to re-enable them. They are already
3728          * configured and all is well in the world.
3729          *
3730          * If running with preallocated tables, there is nothing to do.
3731          */
3732         if (gic_data_rdist()->lpi_enabled ||
3733             (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3734                 return 0;
3735
3736         /*
3737          * From that point on, we only try to do some damage control.
3738          */
3739         pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3740                 smp_processor_id());
3741         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3742
3743         /* Disable LPIs */
3744         val &= ~GICR_CTLR_ENABLE_LPIS;
3745         writel_relaxed(val, rbase + GICR_CTLR);
3746
3747         /* Make sure any change to GICR_CTLR is observable by the GIC */
3748         dsb(sy);
3749
3750         /*
3751          * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3752          * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3753          * Error out if we time out waiting for RWP to clear.
3754          */
3755         while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3756                 if (!timeout) {
3757                         pr_err("CPU%d: Timeout while disabling LPIs\n",
3758                                smp_processor_id());
3759                         return -ETIMEDOUT;
3760                 }
3761                 udelay(1);
3762                 timeout--;
3763         }
3764
3765         /*
3766          * After it has been written to 1, it is IMPLEMENTATION
3767          * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3768          * cleared to 0. Error out if clearing the bit failed.
3769          */
3770         if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3771                 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3772                 return -EBUSY;
3773         }
3774
3775         return 0;
3776 }
3777
3778 int its_cpu_init(void)
3779 {
3780         if (!list_empty(&its_nodes)) {
3781                 int ret;
3782
3783                 ret = redist_disable_lpis();
3784                 if (ret)
3785                         return ret;
3786
3787                 its_cpu_init_lpis();
3788                 its_cpu_init_collections();
3789         }
3790
3791         return 0;
3792 }
3793
3794 static const struct of_device_id its_device_id[] = {
3795         {       .compatible     = "arm,gic-v3-its",     },
3796         {},
3797 };
3798
3799 static int __init its_of_probe(struct device_node *node)
3800 {
3801         struct device_node *np;
3802         struct resource res;
3803
3804         for (np = of_find_matching_node(node, its_device_id); np;
3805              np = of_find_matching_node(np, its_device_id)) {
3806                 if (!of_device_is_available(np))
3807                         continue;
3808                 if (!of_property_read_bool(np, "msi-controller")) {
3809                         pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3810                                 np);
3811                         continue;
3812                 }
3813
3814                 if (of_address_to_resource(np, 0, &res)) {
3815                         pr_warn("%pOF: no regs?\n", np);
3816                         continue;
3817                 }
3818
3819                 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3820         }
3821         return 0;
3822 }
3823
3824 #ifdef CONFIG_ACPI
3825
3826 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3827
3828 #ifdef CONFIG_ACPI_NUMA
3829 struct its_srat_map {
3830         /* numa node id */
3831         u32     numa_node;
3832         /* GIC ITS ID */
3833         u32     its_id;
3834 };
3835
3836 static struct its_srat_map *its_srat_maps __initdata;
3837 static int its_in_srat __initdata;
3838
3839 static int __init acpi_get_its_numa_node(u32 its_id)
3840 {
3841         int i;
3842
3843         for (i = 0; i < its_in_srat; i++) {
3844                 if (its_id == its_srat_maps[i].its_id)
3845                         return its_srat_maps[i].numa_node;
3846         }
3847         return NUMA_NO_NODE;
3848 }
3849
3850 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3851                                           const unsigned long end)
3852 {
3853         return 0;
3854 }
3855
3856 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3857                          const unsigned long end)
3858 {
3859         int node;
3860         struct acpi_srat_gic_its_affinity *its_affinity;
3861
3862         its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3863         if (!its_affinity)
3864                 return -EINVAL;
3865
3866         if (its_affinity->header.length < sizeof(*its_affinity)) {
3867                 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3868                         its_affinity->header.length);
3869                 return -EINVAL;
3870         }
3871
3872         node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3873
3874         if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3875                 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3876                 return 0;
3877         }
3878
3879         its_srat_maps[its_in_srat].numa_node = node;
3880         its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3881         its_in_srat++;
3882         pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3883                 its_affinity->proximity_domain, its_affinity->its_id, node);
3884
3885         return 0;
3886 }
3887
3888 static void __init acpi_table_parse_srat_its(void)
3889 {
3890         int count;
3891
3892         count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3893                         sizeof(struct acpi_table_srat),
3894                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3895                         gic_acpi_match_srat_its, 0);
3896         if (count <= 0)
3897                 return;
3898
3899         its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3900                                       GFP_KERNEL);
3901         if (!its_srat_maps) {
3902                 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3903                 return;
3904         }
3905
3906         acpi_table_parse_entries(ACPI_SIG_SRAT,
3907                         sizeof(struct acpi_table_srat),
3908                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3909                         gic_acpi_parse_srat_its, 0);
3910 }
3911
3912 /* free the its_srat_maps after ITS probing */
3913 static void __init acpi_its_srat_maps_free(void)
3914 {
3915         kfree(its_srat_maps);
3916 }
3917 #else
3918 static void __init acpi_table_parse_srat_its(void)      { }
3919 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3920 static void __init acpi_its_srat_maps_free(void) { }
3921 #endif
3922
3923 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3924                                           const unsigned long end)
3925 {
3926         struct acpi_madt_generic_translator *its_entry;
3927         struct fwnode_handle *dom_handle;
3928         struct resource res;
3929         int err;
3930
3931         its_entry = (struct acpi_madt_generic_translator *)header;
3932         memset(&res, 0, sizeof(res));
3933         res.start = its_entry->base_address;
3934         res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3935         res.flags = IORESOURCE_MEM;
3936
3937         dom_handle = irq_domain_alloc_fwnode(&res.start);
3938         if (!dom_handle) {
3939                 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3940                        &res.start);
3941                 return -ENOMEM;
3942         }
3943
3944         err = iort_register_domain_token(its_entry->translation_id, res.start,
3945                                          dom_handle);
3946         if (err) {
3947                 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3948                        &res.start, its_entry->translation_id);
3949                 goto dom_err;
3950         }
3951
3952         err = its_probe_one(&res, dom_handle,
3953                         acpi_get_its_numa_node(its_entry->translation_id));
3954         if (!err)
3955                 return 0;
3956
3957         iort_deregister_domain_token(its_entry->translation_id);
3958 dom_err:
3959         irq_domain_free_fwnode(dom_handle);
3960         return err;
3961 }
3962
3963 static void __init its_acpi_probe(void)
3964 {
3965         acpi_table_parse_srat_its();
3966         acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3967                               gic_acpi_parse_madt_its, 0);
3968         acpi_its_srat_maps_free();
3969 }
3970 #else
3971 static void __init its_acpi_probe(void) { }
3972 #endif
3973
3974 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3975                     struct irq_domain *parent_domain)
3976 {
3977         struct device_node *of_node;
3978         struct its_node *its;
3979         bool has_v4 = false;
3980         int err;
3981
3982         its_parent = parent_domain;
3983         of_node = to_of_node(handle);
3984         if (of_node)
3985                 its_of_probe(of_node);
3986         else
3987                 its_acpi_probe();
3988
3989         if (list_empty(&its_nodes)) {
3990                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3991                 return -ENXIO;
3992         }
3993
3994         gic_rdists = rdists;
3995
3996         err = allocate_lpi_tables();
3997         if (err)
3998                 return err;
3999
4000         list_for_each_entry(its, &its_nodes, entry)
4001                 has_v4 |= its->is_v4;
4002
4003         if (has_v4 & rdists->has_vlpis) {
4004                 if (its_init_vpe_domain() ||
4005                     its_init_v4(parent_domain, &its_vpe_domain_ops)) {
4006                         rdists->has_vlpis = false;
4007                         pr_err("ITS: Disabling GICv4 support\n");
4008                 }
4009         }
4010
4011         register_syscore_ops(&its_syscore_ops);
4012
4013         return 0;
4014 }