2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/bitmap.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/log2.h>
24 #include <linux/msi.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/of_platform.h>
30 #include <linux/percpu.h>
31 #include <linux/slab.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
36 #include <asm/cacheflush.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
40 #include "irq-gic-common.h"
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
46 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
49 * Collection structure - just an ID, and a redistributor address to
50 * ping. We use one per CPU as a bag of interrupts assigned to this
53 struct its_collection {
59 * The ITS structure - contains most of the infrastructure, with the
60 * top-level MSI domain, the command queue, the collections, and the
61 * list of devices writing to it.
65 struct list_head entry;
67 unsigned long phys_base;
68 struct its_cmd_block *cmd_base;
69 struct its_cmd_block *cmd_write;
73 } tables[GITS_BASER_NR_REGS];
74 struct its_collection *collections;
75 struct list_head its_device_list;
81 #define ITS_ITT_ALIGN SZ_256
83 /* Convert page order to size in bytes */
84 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
86 struct event_lpi_map {
87 unsigned long *lpi_map;
89 irq_hw_number_t lpi_base;
94 * The ITS view of a device - belongs to an ITS, a collection, owns an
95 * interrupt translation table, and a list of interrupts.
98 struct list_head entry;
100 struct event_lpi_map event_map;
106 static LIST_HEAD(its_nodes);
107 static DEFINE_SPINLOCK(its_lock);
108 static struct device_node *gic_root_node;
109 static struct rdists *gic_rdists;
111 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
112 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
114 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
117 struct its_node *its = its_dev->its;
119 return its->collections + its_dev->event_map.col_map[event];
123 * ITS command descriptors - parameters to be encoded in a command
126 struct its_cmd_desc {
129 struct its_device *dev;
134 struct its_device *dev;
139 struct its_device *dev;
144 struct its_collection *col;
149 struct its_device *dev;
155 struct its_device *dev;
156 struct its_collection *col;
161 struct its_device *dev;
166 struct its_collection *col;
172 * The ITS command block, which is what the ITS actually parses.
174 struct its_cmd_block {
178 #define ITS_CMD_QUEUE_SZ SZ_64K
179 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
181 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
182 struct its_cmd_desc *);
184 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
186 cmd->raw_cmd[0] &= ~0xffUL;
187 cmd->raw_cmd[0] |= cmd_nr;
190 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
192 cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
193 cmd->raw_cmd[0] |= ((u64)devid) << 32;
196 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
198 cmd->raw_cmd[1] &= ~0xffffffffUL;
199 cmd->raw_cmd[1] |= id;
202 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
204 cmd->raw_cmd[1] &= 0xffffffffUL;
205 cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
208 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
210 cmd->raw_cmd[1] &= ~0x1fUL;
211 cmd->raw_cmd[1] |= size & 0x1f;
214 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
216 cmd->raw_cmd[2] &= ~0xffffffffffffUL;
217 cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
220 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
222 cmd->raw_cmd[2] &= ~(1UL << 63);
223 cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
226 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
228 cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
229 cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
232 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
234 cmd->raw_cmd[2] &= ~0xffffUL;
235 cmd->raw_cmd[2] |= col;
238 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
240 /* Let's fixup BE commands */
241 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
242 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
243 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
244 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
247 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
248 struct its_cmd_desc *desc)
250 unsigned long itt_addr;
251 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
253 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
254 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
256 its_encode_cmd(cmd, GITS_CMD_MAPD);
257 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
258 its_encode_size(cmd, size - 1);
259 its_encode_itt(cmd, itt_addr);
260 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
267 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
268 struct its_cmd_desc *desc)
270 its_encode_cmd(cmd, GITS_CMD_MAPC);
271 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
272 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
273 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
277 return desc->its_mapc_cmd.col;
280 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
281 struct its_cmd_desc *desc)
283 struct its_collection *col;
285 col = dev_event_to_col(desc->its_mapvi_cmd.dev,
286 desc->its_mapvi_cmd.event_id);
288 its_encode_cmd(cmd, GITS_CMD_MAPVI);
289 its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
290 its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
291 its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
292 its_encode_collection(cmd, col->col_id);
299 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
300 struct its_cmd_desc *desc)
302 struct its_collection *col;
304 col = dev_event_to_col(desc->its_movi_cmd.dev,
305 desc->its_movi_cmd.event_id);
307 its_encode_cmd(cmd, GITS_CMD_MOVI);
308 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
309 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
310 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
317 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
318 struct its_cmd_desc *desc)
320 struct its_collection *col;
322 col = dev_event_to_col(desc->its_discard_cmd.dev,
323 desc->its_discard_cmd.event_id);
325 its_encode_cmd(cmd, GITS_CMD_DISCARD);
326 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
327 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
334 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
335 struct its_cmd_desc *desc)
337 struct its_collection *col;
339 col = dev_event_to_col(desc->its_inv_cmd.dev,
340 desc->its_inv_cmd.event_id);
342 its_encode_cmd(cmd, GITS_CMD_INV);
343 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
344 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
351 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
352 struct its_cmd_desc *desc)
354 its_encode_cmd(cmd, GITS_CMD_INVALL);
355 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
362 static u64 its_cmd_ptr_to_offset(struct its_node *its,
363 struct its_cmd_block *ptr)
365 return (ptr - its->cmd_base) * sizeof(*ptr);
368 static int its_queue_full(struct its_node *its)
373 widx = its->cmd_write - its->cmd_base;
374 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
376 /* This is incredibly unlikely to happen, unless the ITS locks up. */
377 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
383 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
385 struct its_cmd_block *cmd;
386 u32 count = 1000000; /* 1s! */
388 while (its_queue_full(its)) {
391 pr_err_ratelimited("ITS queue not draining\n");
398 cmd = its->cmd_write++;
400 /* Handle queue wrapping */
401 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
402 its->cmd_write = its->cmd_base;
407 static struct its_cmd_block *its_post_commands(struct its_node *its)
409 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
411 writel_relaxed(wr, its->base + GITS_CWRITER);
413 return its->cmd_write;
416 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
419 * Make sure the commands written to memory are observable by
422 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
423 __flush_dcache_area(cmd, sizeof(*cmd));
428 static void its_wait_for_range_completion(struct its_node *its,
429 struct its_cmd_block *from,
430 struct its_cmd_block *to)
432 u64 rd_idx, from_idx, to_idx;
433 u32 count = 1000000; /* 1s! */
435 from_idx = its_cmd_ptr_to_offset(its, from);
436 to_idx = its_cmd_ptr_to_offset(its, to);
439 rd_idx = readl_relaxed(its->base + GITS_CREADR);
440 if (rd_idx >= to_idx || rd_idx < from_idx)
445 pr_err_ratelimited("ITS queue timeout\n");
453 static void its_send_single_command(struct its_node *its,
454 its_cmd_builder_t builder,
455 struct its_cmd_desc *desc)
457 struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
458 struct its_collection *sync_col;
461 raw_spin_lock_irqsave(&its->lock, flags);
463 cmd = its_allocate_entry(its);
464 if (!cmd) { /* We're soooooo screewed... */
465 pr_err_ratelimited("ITS can't allocate, dropping command\n");
466 raw_spin_unlock_irqrestore(&its->lock, flags);
469 sync_col = builder(cmd, desc);
470 its_flush_cmd(its, cmd);
473 sync_cmd = its_allocate_entry(its);
475 pr_err_ratelimited("ITS can't SYNC, skipping\n");
478 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
479 its_encode_target(sync_cmd, sync_col->target_address);
480 its_fixup_cmd(sync_cmd);
481 its_flush_cmd(its, sync_cmd);
485 next_cmd = its_post_commands(its);
486 raw_spin_unlock_irqrestore(&its->lock, flags);
488 its_wait_for_range_completion(its, cmd, next_cmd);
491 static void its_send_inv(struct its_device *dev, u32 event_id)
493 struct its_cmd_desc desc;
495 desc.its_inv_cmd.dev = dev;
496 desc.its_inv_cmd.event_id = event_id;
498 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
501 static void its_send_mapd(struct its_device *dev, int valid)
503 struct its_cmd_desc desc;
505 desc.its_mapd_cmd.dev = dev;
506 desc.its_mapd_cmd.valid = !!valid;
508 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
511 static void its_send_mapc(struct its_node *its, struct its_collection *col,
514 struct its_cmd_desc desc;
516 desc.its_mapc_cmd.col = col;
517 desc.its_mapc_cmd.valid = !!valid;
519 its_send_single_command(its, its_build_mapc_cmd, &desc);
522 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
524 struct its_cmd_desc desc;
526 desc.its_mapvi_cmd.dev = dev;
527 desc.its_mapvi_cmd.phys_id = irq_id;
528 desc.its_mapvi_cmd.event_id = id;
530 its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
533 static void its_send_movi(struct its_device *dev,
534 struct its_collection *col, u32 id)
536 struct its_cmd_desc desc;
538 desc.its_movi_cmd.dev = dev;
539 desc.its_movi_cmd.col = col;
540 desc.its_movi_cmd.event_id = id;
542 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
545 static void its_send_discard(struct its_device *dev, u32 id)
547 struct its_cmd_desc desc;
549 desc.its_discard_cmd.dev = dev;
550 desc.its_discard_cmd.event_id = id;
552 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
555 static void its_send_invall(struct its_node *its, struct its_collection *col)
557 struct its_cmd_desc desc;
559 desc.its_invall_cmd.col = col;
561 its_send_single_command(its, its_build_invall_cmd, &desc);
565 * irqchip functions - assumes MSI, mostly.
568 static inline u32 its_get_event_id(struct irq_data *d)
570 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
571 return d->hwirq - its_dev->event_map.lpi_base;
574 static void lpi_set_config(struct irq_data *d, bool enable)
576 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
577 irq_hw_number_t hwirq = d->hwirq;
578 u32 id = its_get_event_id(d);
579 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
582 *cfg |= LPI_PROP_ENABLED;
584 *cfg &= ~LPI_PROP_ENABLED;
587 * Make the above write visible to the redistributors.
588 * And yes, we're flushing exactly: One. Single. Byte.
591 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
592 __flush_dcache_area(cfg, sizeof(*cfg));
595 its_send_inv(its_dev, id);
598 static void its_mask_irq(struct irq_data *d)
600 lpi_set_config(d, false);
603 static void its_unmask_irq(struct irq_data *d)
605 lpi_set_config(d, true);
608 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
612 const struct cpumask *cpu_mask = cpu_online_mask;
613 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
614 struct its_collection *target_col;
615 u32 id = its_get_event_id(d);
617 /* lpi cannot be routed to a redistributor that is on a foreign node */
618 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
619 if (its_dev->its->numa_node >= 0) {
620 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
621 if (!cpumask_intersects(mask_val, cpu_mask))
626 cpu = cpumask_any_and(mask_val, cpu_mask);
628 if (cpu >= nr_cpu_ids)
631 target_col = &its_dev->its->collections[cpu];
632 its_send_movi(its_dev, target_col, id);
633 its_dev->event_map.col_map[id] = cpu;
635 return IRQ_SET_MASK_OK_DONE;
638 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
640 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
641 struct its_node *its;
645 addr = its->phys_base + GITS_TRANSLATER;
647 msg->address_lo = addr & ((1UL << 32) - 1);
648 msg->address_hi = addr >> 32;
649 msg->data = its_get_event_id(d);
652 static struct irq_chip its_irq_chip = {
654 .irq_mask = its_mask_irq,
655 .irq_unmask = its_unmask_irq,
656 .irq_eoi = irq_chip_eoi_parent,
657 .irq_set_affinity = its_set_affinity,
658 .irq_compose_msi_msg = its_irq_compose_msi_msg,
662 * How we allocate LPIs:
664 * The GIC has id_bits bits for interrupt identifiers. From there, we
665 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
666 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
669 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
671 #define IRQS_PER_CHUNK_SHIFT 5
672 #define IRQS_PER_CHUNK (1UL << IRQS_PER_CHUNK_SHIFT)
674 static unsigned long *lpi_bitmap;
675 static u32 lpi_chunks;
676 static DEFINE_SPINLOCK(lpi_lock);
678 static int its_lpi_to_chunk(int lpi)
680 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
683 static int its_chunk_to_lpi(int chunk)
685 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
688 static int its_lpi_init(u32 id_bits)
690 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
692 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
699 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
703 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
705 unsigned long *bitmap = NULL;
710 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
712 spin_lock(&lpi_lock);
715 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
717 if (chunk_id < lpi_chunks)
721 } while (nr_chunks > 0);
726 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
731 for (i = 0; i < nr_chunks; i++)
732 set_bit(chunk_id + i, lpi_bitmap);
734 *base = its_chunk_to_lpi(chunk_id);
735 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
738 spin_unlock(&lpi_lock);
746 static void its_lpi_free(struct event_lpi_map *map)
748 int base = map->lpi_base;
749 int nr_ids = map->nr_lpis;
752 spin_lock(&lpi_lock);
754 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
755 int chunk = its_lpi_to_chunk(lpi);
756 BUG_ON(chunk > lpi_chunks);
757 if (test_bit(chunk, lpi_bitmap)) {
758 clear_bit(chunk, lpi_bitmap);
760 pr_err("Bad LPI chunk %d\n", chunk);
764 spin_unlock(&lpi_lock);
771 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
772 * deal with (one configuration byte per interrupt). PENDBASE has to
773 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
775 #define LPI_PROPBASE_SZ SZ_64K
776 #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
779 * This is how many bits of ID we need, including the useless ones.
781 #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
783 #define LPI_PROP_DEFAULT_PRIO 0xa0
785 static int __init its_alloc_lpi_tables(void)
789 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
790 get_order(LPI_PROPBASE_SZ));
791 if (!gic_rdists->prop_page) {
792 pr_err("Failed to allocate PROPBASE\n");
796 paddr = page_to_phys(gic_rdists->prop_page);
797 pr_info("GIC: using LPI property table @%pa\n", &paddr);
799 /* Priority 0xa0, Group-1, disabled */
800 memset(page_address(gic_rdists->prop_page),
801 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
804 /* Make sure the GIC will observe the written configuration */
805 __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
810 static const char *its_base_type_string[] = {
811 [GITS_BASER_TYPE_DEVICE] = "Devices",
812 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
813 [GITS_BASER_TYPE_CPU] = "Physical CPUs",
814 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
815 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
816 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
817 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
820 static void its_free_tables(struct its_node *its)
824 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
825 if (its->tables[i].base) {
826 free_pages((unsigned long)its->tables[i].base,
827 its->tables[i].order);
828 its->tables[i].base = NULL;
833 static int its_alloc_tables(const char *node_name, struct its_node *its)
838 u64 shr = GITS_BASER_InnerShareable;
843 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
845 * erratum 22375: only alloc 8MB table size
846 * erratum 24313: ignore memory access type
849 ids = 0x14; /* 20 bits, 8MB */
851 cache = GITS_BASER_WaWb;
852 typer = readq_relaxed(its->base + GITS_TYPER);
853 ids = GITS_TYPER_DEVBITS(typer);
856 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
857 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
858 u64 type = GITS_BASER_TYPE(val);
859 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
860 int order = get_order(psz);
865 if (type == GITS_BASER_TYPE_NONE)
869 * Allocate as many entries as required to fit the
870 * range of device IDs that the ITS can grok... The ID
871 * space being incredibly sparse, this results in a
872 * massive waste of memory.
874 * For other tables, only allocate a single page.
876 if (type == GITS_BASER_TYPE_DEVICE) {
878 * 'order' was initialized earlier to the default page
879 * granule of the the ITS. We can't have an allocation
880 * smaller than that. If the requested allocation
881 * is smaller, round up to the default page granule.
883 order = max(get_order((1UL << ids) * entry_size),
885 if (order >= MAX_ORDER) {
886 order = MAX_ORDER - 1;
887 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
893 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
894 if (alloc_pages > GITS_BASER_PAGES_MAX) {
895 alloc_pages = GITS_BASER_PAGES_MAX;
896 order = get_order(GITS_BASER_PAGES_MAX * psz);
897 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
898 node_name, order, alloc_pages);
901 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
907 its->tables[i].base = base;
908 its->tables[i].order = order;
911 val = (virt_to_phys(base) |
912 (type << GITS_BASER_TYPE_SHIFT) |
913 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
920 val |= GITS_BASER_PAGE_SIZE_4K;
923 val |= GITS_BASER_PAGE_SIZE_16K;
926 val |= GITS_BASER_PAGE_SIZE_64K;
930 val |= alloc_pages - 1;
932 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
933 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
935 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
937 * Shareability didn't stick. Just use
938 * whatever the read reported, which is likely
939 * to be the only thing this redistributor
940 * supports. If that's zero, make it
941 * non-cacheable as well.
943 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
945 cache = GITS_BASER_nC;
946 __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
951 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
953 * Page size didn't stick. Let's try a smaller
954 * size and retry. If we reach 4K, then
955 * something is horribly wrong...
957 free_pages((unsigned long)base, order);
958 its->tables[i].base = NULL;
963 goto retry_alloc_baser;
966 goto retry_alloc_baser;
971 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
973 (unsigned long) val, (unsigned long) tmp);
978 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
979 (int)(PAGE_ORDER_TO_SIZE(order) / entry_size),
980 its_base_type_string[type],
981 (unsigned long)virt_to_phys(base),
982 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
988 its_free_tables(its);
993 static int its_alloc_collections(struct its_node *its)
995 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
997 if (!its->collections)
1003 static void its_cpu_init_lpis(void)
1005 void __iomem *rbase = gic_data_rdist_rd_base();
1006 struct page *pend_page;
1009 /* If we didn't allocate the pending table yet, do it now */
1010 pend_page = gic_data_rdist()->pend_page;
1014 * The pending pages have to be at least 64kB aligned,
1015 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1017 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
1018 get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
1020 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1021 smp_processor_id());
1025 /* Make sure the GIC will observe the zero-ed page */
1026 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1028 paddr = page_to_phys(pend_page);
1029 pr_info("CPU%d: using LPI pending table @%pa\n",
1030 smp_processor_id(), &paddr);
1031 gic_data_rdist()->pend_page = pend_page;
1035 val = readl_relaxed(rbase + GICR_CTLR);
1036 val &= ~GICR_CTLR_ENABLE_LPIS;
1037 writel_relaxed(val, rbase + GICR_CTLR);
1040 * Make sure any change to the table is observable by the GIC.
1045 val = (page_to_phys(gic_rdists->prop_page) |
1046 GICR_PROPBASER_InnerShareable |
1047 GICR_PROPBASER_WaWb |
1048 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1050 writeq_relaxed(val, rbase + GICR_PROPBASER);
1051 tmp = readq_relaxed(rbase + GICR_PROPBASER);
1053 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1054 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1056 * The HW reports non-shareable, we must
1057 * remove the cacheability attributes as
1060 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1061 GICR_PROPBASER_CACHEABILITY_MASK);
1062 val |= GICR_PROPBASER_nC;
1063 writeq_relaxed(val, rbase + GICR_PROPBASER);
1065 pr_info_once("GIC: using cache flushing for LPI property table\n");
1066 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1070 val = (page_to_phys(pend_page) |
1071 GICR_PENDBASER_InnerShareable |
1072 GICR_PENDBASER_WaWb);
1074 writeq_relaxed(val, rbase + GICR_PENDBASER);
1075 tmp = readq_relaxed(rbase + GICR_PENDBASER);
1077 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1079 * The HW reports non-shareable, we must remove the
1080 * cacheability attributes as well.
1082 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1083 GICR_PENDBASER_CACHEABILITY_MASK);
1084 val |= GICR_PENDBASER_nC;
1085 writeq_relaxed(val, rbase + GICR_PENDBASER);
1089 val = readl_relaxed(rbase + GICR_CTLR);
1090 val |= GICR_CTLR_ENABLE_LPIS;
1091 writel_relaxed(val, rbase + GICR_CTLR);
1093 /* Make sure the GIC has seen the above */
1097 static void its_cpu_init_collection(void)
1099 struct its_node *its;
1102 spin_lock(&its_lock);
1103 cpu = smp_processor_id();
1105 list_for_each_entry(its, &its_nodes, entry) {
1108 /* avoid cross node collections and its mapping */
1109 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1110 struct device_node *cpu_node;
1112 cpu_node = of_get_cpu_node(cpu, NULL);
1113 if (its->numa_node != NUMA_NO_NODE &&
1114 its->numa_node != of_node_to_nid(cpu_node))
1119 * We now have to bind each collection to its target
1122 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1124 * This ITS wants the physical address of the
1127 target = gic_data_rdist()->phys_base;
1130 * This ITS wants a linear CPU number.
1132 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1133 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1136 /* Perform collection mapping */
1137 its->collections[cpu].target_address = target;
1138 its->collections[cpu].col_id = cpu;
1140 its_send_mapc(its, &its->collections[cpu], 1);
1141 its_send_invall(its, &its->collections[cpu]);
1144 spin_unlock(&its_lock);
1147 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1149 struct its_device *its_dev = NULL, *tmp;
1150 unsigned long flags;
1152 raw_spin_lock_irqsave(&its->lock, flags);
1154 list_for_each_entry(tmp, &its->its_device_list, entry) {
1155 if (tmp->device_id == dev_id) {
1161 raw_spin_unlock_irqrestore(&its->lock, flags);
1166 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1169 struct its_device *dev;
1170 unsigned long *lpi_map;
1171 unsigned long flags;
1172 u16 *col_map = NULL;
1179 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1181 * We allocate at least one chunk worth of LPIs bet device,
1182 * and thus that many ITEs. The device may require less though.
1184 nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs));
1185 sz = nr_ites * its->ite_size;
1186 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1187 itt = kzalloc(sz, GFP_KERNEL);
1188 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1190 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1192 if (!dev || !itt || !lpi_map || !col_map) {
1200 __flush_dcache_area(itt, sz);
1204 dev->nr_ites = nr_ites;
1205 dev->event_map.lpi_map = lpi_map;
1206 dev->event_map.col_map = col_map;
1207 dev->event_map.lpi_base = lpi_base;
1208 dev->event_map.nr_lpis = nr_lpis;
1209 dev->device_id = dev_id;
1210 INIT_LIST_HEAD(&dev->entry);
1212 raw_spin_lock_irqsave(&its->lock, flags);
1213 list_add(&dev->entry, &its->its_device_list);
1214 raw_spin_unlock_irqrestore(&its->lock, flags);
1216 /* Map device to its ITT */
1217 its_send_mapd(dev, 1);
1222 static void its_free_device(struct its_device *its_dev)
1224 unsigned long flags;
1226 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1227 list_del(&its_dev->entry);
1228 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1229 kfree(its_dev->itt);
1233 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
1237 idx = bitmap_find_free_region(dev->event_map.lpi_map,
1238 dev->event_map.nr_lpis,
1239 get_count_order(nvecs));
1243 *hwirq = dev->event_map.lpi_base + idx;
1244 set_bit(idx, dev->event_map.lpi_map);
1249 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1250 int nvec, msi_alloc_info_t *info)
1252 struct its_node *its;
1253 struct its_device *its_dev;
1254 struct msi_domain_info *msi_info;
1258 * We ignore "dev" entierely, and rely on the dev_id that has
1259 * been passed via the scratchpad. This limits this domain's
1260 * usefulness to upper layers that definitely know that they
1261 * are built on top of the ITS.
1263 dev_id = info->scratchpad[0].ul;
1265 msi_info = msi_get_domain_info(domain);
1266 its = msi_info->data;
1268 its_dev = its_find_device(its, dev_id);
1271 * We already have seen this ID, probably through
1272 * another alias (PCI bridge of some sort). No need to
1273 * create the device.
1275 pr_debug("Reusing ITT for devID %x\n", dev_id);
1279 its_dev = its_create_device(its, dev_id, nvec);
1283 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1285 info->scratchpad[0].ptr = its_dev;
1289 static struct msi_domain_ops its_msi_domain_ops = {
1290 .msi_prepare = its_msi_prepare,
1293 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1295 irq_hw_number_t hwirq)
1297 struct irq_fwspec fwspec;
1299 if (irq_domain_get_of_node(domain->parent)) {
1300 fwspec.fwnode = domain->parent->fwnode;
1301 fwspec.param_count = 3;
1302 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1303 fwspec.param[1] = hwirq;
1304 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1309 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1312 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1313 unsigned int nr_irqs, void *args)
1315 msi_alloc_info_t *info = args;
1316 struct its_device *its_dev = info->scratchpad[0].ptr;
1317 irq_hw_number_t hwirq;
1321 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
1325 for (i = 0; i < nr_irqs; i++) {
1326 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
1330 irq_domain_set_hwirq_and_chip(domain, virq + i,
1331 hwirq + i, &its_irq_chip, its_dev);
1332 pr_debug("ID:%d pID:%d vID:%d\n",
1333 (int)(hwirq + i - its_dev->event_map.lpi_base),
1334 (int)(hwirq + i), virq + i);
1340 static void its_irq_domain_activate(struct irq_domain *domain,
1343 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1344 u32 event = its_get_event_id(d);
1345 const struct cpumask *cpu_mask = cpu_online_mask;
1347 /* get the cpu_mask of local node */
1348 if (its_dev->its->numa_node >= 0)
1349 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1351 /* Bind the LPI to the first possible CPU */
1352 its_dev->event_map.col_map[event] = cpumask_first(cpu_mask);
1354 /* Map the GIC IRQ and event to the device */
1355 its_send_mapvi(its_dev, d->hwirq, event);
1358 static void its_irq_domain_deactivate(struct irq_domain *domain,
1361 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1362 u32 event = its_get_event_id(d);
1364 /* Stop the delivery of interrupts */
1365 its_send_discard(its_dev, event);
1368 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1369 unsigned int nr_irqs)
1371 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1372 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1375 bitmap_release_region(its_dev->event_map.lpi_map,
1376 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
1377 get_count_order(nr_irqs));
1379 for (i = 0; i < nr_irqs; i++) {
1380 struct irq_data *data = irq_domain_get_irq_data(domain,
1382 /* Nuke the entry in the domain */
1383 irq_domain_reset_irq_data(data);
1386 /* If all interrupts have been freed, start mopping the floor */
1387 if (bitmap_empty(its_dev->event_map.lpi_map,
1388 its_dev->event_map.nr_lpis)) {
1389 its_lpi_free(&its_dev->event_map);
1391 /* Unmap device/itt */
1392 its_send_mapd(its_dev, 0);
1393 its_free_device(its_dev);
1396 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1399 static const struct irq_domain_ops its_domain_ops = {
1400 .alloc = its_irq_domain_alloc,
1401 .free = its_irq_domain_free,
1402 .activate = its_irq_domain_activate,
1403 .deactivate = its_irq_domain_deactivate,
1406 static int its_force_quiescent(void __iomem *base)
1408 u32 count = 1000000; /* 1s */
1411 val = readl_relaxed(base + GITS_CTLR);
1412 if (val & GITS_CTLR_QUIESCENT)
1415 /* Disable the generation of all interrupts to this ITS */
1416 val &= ~GITS_CTLR_ENABLE;
1417 writel_relaxed(val, base + GITS_CTLR);
1419 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1421 val = readl_relaxed(base + GITS_CTLR);
1422 if (val & GITS_CTLR_QUIESCENT)
1434 static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1436 struct its_node *its = data;
1438 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1441 static void __maybe_unused its_enable_quirk_cavium_23144(void *data)
1443 struct its_node *its = data;
1445 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
1448 static const struct gic_quirk its_quirks[] = {
1449 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1451 .desc = "ITS: Cavium errata 22375, 24313",
1452 .iidr = 0xa100034c, /* ThunderX pass 1.x */
1454 .init = its_enable_quirk_cavium_22375,
1457 #ifdef CONFIG_CAVIUM_ERRATUM_23144
1459 .desc = "ITS: Cavium erratum 23144",
1460 .iidr = 0xa100034c, /* ThunderX pass 1.x */
1462 .init = its_enable_quirk_cavium_23144,
1469 static void its_enable_quirks(struct its_node *its)
1471 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1473 gic_enable_quirks(iidr, its_quirks, its);
1476 static int its_probe(struct device_node *node, struct irq_domain *parent)
1478 struct resource res;
1479 struct its_node *its;
1480 void __iomem *its_base;
1481 struct irq_domain *inner_domain;
1486 err = of_address_to_resource(node, 0, &res);
1488 pr_warn("%s: no regs?\n", node->full_name);
1492 its_base = ioremap(res.start, resource_size(&res));
1494 pr_warn("%s: unable to map registers\n", node->full_name);
1498 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1499 if (val != 0x30 && val != 0x40) {
1500 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1505 err = its_force_quiescent(its_base);
1507 pr_warn("%s: failed to quiesce, giving up\n",
1512 pr_info("ITS: %s\n", node->full_name);
1514 its = kzalloc(sizeof(*its), GFP_KERNEL);
1520 raw_spin_lock_init(&its->lock);
1521 INIT_LIST_HEAD(&its->entry);
1522 INIT_LIST_HEAD(&its->its_device_list);
1523 its->base = its_base;
1524 its->phys_base = res.start;
1525 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1526 its->numa_node = of_node_to_nid(node);
1528 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1529 if (!its->cmd_base) {
1533 its->cmd_write = its->cmd_base;
1535 its_enable_quirks(its);
1537 err = its_alloc_tables(node->full_name, its);
1541 err = its_alloc_collections(its);
1543 goto out_free_tables;
1545 baser = (virt_to_phys(its->cmd_base) |
1547 GITS_CBASER_InnerShareable |
1548 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1551 writeq_relaxed(baser, its->base + GITS_CBASER);
1552 tmp = readq_relaxed(its->base + GITS_CBASER);
1554 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1555 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1557 * The HW reports non-shareable, we must
1558 * remove the cacheability attributes as
1561 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1562 GITS_CBASER_CACHEABILITY_MASK);
1563 baser |= GITS_CBASER_nC;
1564 writeq_relaxed(baser, its->base + GITS_CBASER);
1566 pr_info("ITS: using cache flushing for cmd queue\n");
1567 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1570 writeq_relaxed(0, its->base + GITS_CWRITER);
1571 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1573 if (of_property_read_bool(node, "msi-controller")) {
1574 struct msi_domain_info *info;
1576 info = kzalloc(sizeof(*info), GFP_KERNEL);
1579 goto out_free_tables;
1582 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1583 if (!inner_domain) {
1586 goto out_free_tables;
1589 inner_domain->parent = parent;
1590 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1591 info->ops = &its_msi_domain_ops;
1593 inner_domain->host_data = info;
1596 spin_lock(&its_lock);
1597 list_add(&its->entry, &its_nodes);
1598 spin_unlock(&its_lock);
1603 its_free_tables(its);
1605 kfree(its->cmd_base);
1610 pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1614 static bool gic_rdists_supports_plpis(void)
1616 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1619 int its_cpu_init(void)
1621 if (!list_empty(&its_nodes)) {
1622 if (!gic_rdists_supports_plpis()) {
1623 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1626 its_cpu_init_lpis();
1627 its_cpu_init_collection();
1633 static struct of_device_id its_device_id[] = {
1634 { .compatible = "arm,gic-v3-its", },
1638 int its_init(struct device_node *node, struct rdists *rdists,
1639 struct irq_domain *parent_domain)
1641 struct device_node *np;
1643 for (np = of_find_matching_node(node, its_device_id); np;
1644 np = of_find_matching_node(np, its_device_id)) {
1645 its_probe(np, parent_domain);
1648 if (list_empty(&its_nodes)) {
1649 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1653 gic_rdists = rdists;
1654 gic_root_node = node;
1656 its_alloc_lpi_tables();
1657 its_lpi_init(rdists->id_bits);