2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/acpi.h>
19 #include <linux/acpi_iort.h>
20 #include <linux/bitmap.h>
21 #include <linux/cpu.h>
22 #include <linux/delay.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/list.h>
27 #include <linux/list_sort.h>
28 #include <linux/log2.h>
30 #include <linux/msi.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_pci.h>
35 #include <linux/of_platform.h>
36 #include <linux/percpu.h>
37 #include <linux/slab.h>
38 #include <linux/syscore_ops.h>
40 #include <linux/irqchip.h>
41 #include <linux/irqchip/arm-gic-v3.h>
42 #include <linux/irqchip/arm-gic-v4.h>
44 #include <asm/cputype.h>
45 #include <asm/exception.h>
47 #include "irq-gic-common.h"
49 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
50 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
51 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
53 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
55 static u32 lpi_id_bits;
58 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
59 * deal with (one configuration byte per interrupt). PENDBASE has to
60 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
62 #define LPI_NRBITS lpi_id_bits
63 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
64 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
66 #define LPI_PROP_DEFAULT_PRIO 0xa0
69 * Collection structure - just an ID, and a redistributor address to
70 * ping. We use one per CPU as a bag of interrupts assigned to this
73 struct its_collection {
79 * The ITS_BASER structure - contains memory information, cached
80 * value of BASER register configuration and ITS page size.
92 * The ITS structure - contains most of the infrastructure, with the
93 * top-level MSI domain, the command queue, the collections, and the
94 * list of devices writing to it.
96 * dev_alloc_lock has to be taken for device allocations, while the
97 * spinlock must be taken to parse data structures such as the device
102 struct mutex dev_alloc_lock;
103 struct list_head entry;
105 phys_addr_t phys_base;
106 struct its_cmd_block *cmd_base;
107 struct its_cmd_block *cmd_write;
108 struct its_baser tables[GITS_BASER_NR_REGS];
109 struct its_collection *collections;
110 struct fwnode_handle *fwnode_handle;
111 u64 (*get_msi_base)(struct its_device *its_dev);
114 struct list_head its_device_list;
116 unsigned long list_nr;
120 unsigned int msi_domain_flags;
121 u32 pre_its_base; /* for Socionext Synquacer */
123 int vlpi_redist_offset;
126 #define ITS_ITT_ALIGN SZ_256
128 /* The maximum number of VPEID bits supported by VLPI commands */
129 #define ITS_MAX_VPEID_BITS (16)
130 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
132 /* Convert page order to size in bytes */
133 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
135 struct event_lpi_map {
136 unsigned long *lpi_map;
138 irq_hw_number_t lpi_base;
140 struct mutex vlpi_lock;
142 struct its_vlpi_map *vlpi_maps;
147 * The ITS view of a device - belongs to an ITS, owns an interrupt
148 * translation table, and a list of interrupts. If it some of its
149 * LPIs are injected into a guest (GICv4), the event_map.vm field
150 * indicates which one.
153 struct list_head entry;
154 struct its_node *its;
155 struct event_lpi_map event_map;
164 struct its_device *dev;
165 struct its_vpe **vpes;
169 static LIST_HEAD(its_nodes);
170 static DEFINE_RAW_SPINLOCK(its_lock);
171 static struct rdists *gic_rdists;
172 static struct irq_domain *its_parent;
174 static unsigned long its_list_map;
175 static u16 vmovp_seq_num;
176 static DEFINE_RAW_SPINLOCK(vmovp_lock);
178 static DEFINE_IDA(its_vpeid_ida);
180 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
181 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
182 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
184 static u16 get_its_list(struct its_vm *vm)
186 struct its_node *its;
187 unsigned long its_list = 0;
189 list_for_each_entry(its, &its_nodes, entry) {
193 if (vm->vlpi_count[its->list_nr])
194 __set_bit(its->list_nr, &its_list);
197 return (u16)its_list;
200 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
203 struct its_node *its = its_dev->its;
205 return its->collections + its_dev->event_map.col_map[event];
208 static struct its_collection *valid_col(struct its_collection *col)
210 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
216 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
218 if (valid_col(its->collections + vpe->col_idx))
225 * ITS command descriptors - parameters to be encoded in a command
228 struct its_cmd_desc {
231 struct its_device *dev;
236 struct its_device *dev;
241 struct its_device *dev;
246 struct its_device *dev;
251 struct its_collection *col;
256 struct its_device *dev;
262 struct its_device *dev;
263 struct its_collection *col;
268 struct its_device *dev;
273 struct its_collection *col;
282 struct its_collection *col;
288 struct its_device *dev;
296 struct its_device *dev;
303 struct its_collection *col;
311 * The ITS command block, which is what the ITS actually parses.
313 struct its_cmd_block {
317 #define ITS_CMD_QUEUE_SZ SZ_64K
318 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
320 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
321 struct its_cmd_block *,
322 struct its_cmd_desc *);
324 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
325 struct its_cmd_block *,
326 struct its_cmd_desc *);
328 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
330 u64 mask = GENMASK_ULL(h, l);
332 *raw_cmd |= (val << l) & mask;
335 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
337 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
340 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
342 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
345 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
347 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
350 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
352 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
355 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
357 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
360 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
362 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
365 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
367 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
370 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
372 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
375 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
377 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
380 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
382 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
385 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
387 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
390 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
392 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
395 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
397 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
400 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
402 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
405 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
407 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
410 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
412 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
415 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
417 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
420 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
422 /* Let's fixup BE commands */
423 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
424 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
425 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
426 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
429 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
430 struct its_cmd_block *cmd,
431 struct its_cmd_desc *desc)
433 unsigned long itt_addr;
434 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
436 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
437 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
439 its_encode_cmd(cmd, GITS_CMD_MAPD);
440 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
441 its_encode_size(cmd, size - 1);
442 its_encode_itt(cmd, itt_addr);
443 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
450 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
451 struct its_cmd_block *cmd,
452 struct its_cmd_desc *desc)
454 its_encode_cmd(cmd, GITS_CMD_MAPC);
455 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
456 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
457 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
461 return desc->its_mapc_cmd.col;
464 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
465 struct its_cmd_block *cmd,
466 struct its_cmd_desc *desc)
468 struct its_collection *col;
470 col = dev_event_to_col(desc->its_mapti_cmd.dev,
471 desc->its_mapti_cmd.event_id);
473 its_encode_cmd(cmd, GITS_CMD_MAPTI);
474 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
475 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
476 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
477 its_encode_collection(cmd, col->col_id);
481 return valid_col(col);
484 static struct its_collection *its_build_movi_cmd(struct its_node *its,
485 struct its_cmd_block *cmd,
486 struct its_cmd_desc *desc)
488 struct its_collection *col;
490 col = dev_event_to_col(desc->its_movi_cmd.dev,
491 desc->its_movi_cmd.event_id);
493 its_encode_cmd(cmd, GITS_CMD_MOVI);
494 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
495 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
496 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
500 return valid_col(col);
503 static struct its_collection *its_build_discard_cmd(struct its_node *its,
504 struct its_cmd_block *cmd,
505 struct its_cmd_desc *desc)
507 struct its_collection *col;
509 col = dev_event_to_col(desc->its_discard_cmd.dev,
510 desc->its_discard_cmd.event_id);
512 its_encode_cmd(cmd, GITS_CMD_DISCARD);
513 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
514 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
518 return valid_col(col);
521 static struct its_collection *its_build_inv_cmd(struct its_node *its,
522 struct its_cmd_block *cmd,
523 struct its_cmd_desc *desc)
525 struct its_collection *col;
527 col = dev_event_to_col(desc->its_inv_cmd.dev,
528 desc->its_inv_cmd.event_id);
530 its_encode_cmd(cmd, GITS_CMD_INV);
531 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
532 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
536 return valid_col(col);
539 static struct its_collection *its_build_int_cmd(struct its_node *its,
540 struct its_cmd_block *cmd,
541 struct its_cmd_desc *desc)
543 struct its_collection *col;
545 col = dev_event_to_col(desc->its_int_cmd.dev,
546 desc->its_int_cmd.event_id);
548 its_encode_cmd(cmd, GITS_CMD_INT);
549 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
550 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
554 return valid_col(col);
557 static struct its_collection *its_build_clear_cmd(struct its_node *its,
558 struct its_cmd_block *cmd,
559 struct its_cmd_desc *desc)
561 struct its_collection *col;
563 col = dev_event_to_col(desc->its_clear_cmd.dev,
564 desc->its_clear_cmd.event_id);
566 its_encode_cmd(cmd, GITS_CMD_CLEAR);
567 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
568 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
572 return valid_col(col);
575 static struct its_collection *its_build_invall_cmd(struct its_node *its,
576 struct its_cmd_block *cmd,
577 struct its_cmd_desc *desc)
579 its_encode_cmd(cmd, GITS_CMD_INVALL);
580 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
584 return desc->its_invall_cmd.col;
587 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
588 struct its_cmd_block *cmd,
589 struct its_cmd_desc *desc)
591 its_encode_cmd(cmd, GITS_CMD_VINVALL);
592 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
596 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
599 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
600 struct its_cmd_block *cmd,
601 struct its_cmd_desc *desc)
603 unsigned long vpt_addr;
606 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
607 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
609 its_encode_cmd(cmd, GITS_CMD_VMAPP);
610 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
611 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
612 its_encode_target(cmd, target);
613 its_encode_vpt_addr(cmd, vpt_addr);
614 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
618 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
621 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
622 struct its_cmd_block *cmd,
623 struct its_cmd_desc *desc)
627 if (desc->its_vmapti_cmd.db_enabled)
628 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
632 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
633 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
634 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
635 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
636 its_encode_db_phys_id(cmd, db);
637 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
641 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
644 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
645 struct its_cmd_block *cmd,
646 struct its_cmd_desc *desc)
650 if (desc->its_vmovi_cmd.db_enabled)
651 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
655 its_encode_cmd(cmd, GITS_CMD_VMOVI);
656 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
657 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
658 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
659 its_encode_db_phys_id(cmd, db);
660 its_encode_db_valid(cmd, true);
664 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
667 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
668 struct its_cmd_block *cmd,
669 struct its_cmd_desc *desc)
673 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
674 its_encode_cmd(cmd, GITS_CMD_VMOVP);
675 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
676 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
677 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
678 its_encode_target(cmd, target);
682 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
685 static u64 its_cmd_ptr_to_offset(struct its_node *its,
686 struct its_cmd_block *ptr)
688 return (ptr - its->cmd_base) * sizeof(*ptr);
691 static int its_queue_full(struct its_node *its)
696 widx = its->cmd_write - its->cmd_base;
697 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
699 /* This is incredibly unlikely to happen, unless the ITS locks up. */
700 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
706 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
708 struct its_cmd_block *cmd;
709 u32 count = 1000000; /* 1s! */
711 while (its_queue_full(its)) {
714 pr_err_ratelimited("ITS queue not draining\n");
721 cmd = its->cmd_write++;
723 /* Handle queue wrapping */
724 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
725 its->cmd_write = its->cmd_base;
736 static struct its_cmd_block *its_post_commands(struct its_node *its)
738 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
740 writel_relaxed(wr, its->base + GITS_CWRITER);
742 return its->cmd_write;
745 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
748 * Make sure the commands written to memory are observable by
751 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
752 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
757 static int its_wait_for_range_completion(struct its_node *its,
759 struct its_cmd_block *to)
761 u64 rd_idx, to_idx, linear_idx;
762 u32 count = 1000000; /* 1s! */
764 /* Linearize to_idx if the command set has wrapped around */
765 to_idx = its_cmd_ptr_to_offset(its, to);
766 if (to_idx < prev_idx)
767 to_idx += ITS_CMD_QUEUE_SZ;
769 linear_idx = prev_idx;
774 rd_idx = readl_relaxed(its->base + GITS_CREADR);
777 * Compute the read pointer progress, taking the
778 * potential wrap-around into account.
780 delta = rd_idx - prev_idx;
781 if (rd_idx < prev_idx)
782 delta += ITS_CMD_QUEUE_SZ;
785 if (linear_idx >= to_idx)
790 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
802 /* Warning, macro hell follows */
803 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
804 void name(struct its_node *its, \
806 struct its_cmd_desc *desc) \
808 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
809 synctype *sync_obj; \
810 unsigned long flags; \
813 raw_spin_lock_irqsave(&its->lock, flags); \
815 cmd = its_allocate_entry(its); \
816 if (!cmd) { /* We're soooooo screewed... */ \
817 raw_spin_unlock_irqrestore(&its->lock, flags); \
820 sync_obj = builder(its, cmd, desc); \
821 its_flush_cmd(its, cmd); \
824 sync_cmd = its_allocate_entry(its); \
828 buildfn(its, sync_cmd, sync_obj); \
829 its_flush_cmd(its, sync_cmd); \
833 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
834 next_cmd = its_post_commands(its); \
835 raw_spin_unlock_irqrestore(&its->lock, flags); \
837 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
838 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
841 static void its_build_sync_cmd(struct its_node *its,
842 struct its_cmd_block *sync_cmd,
843 struct its_collection *sync_col)
845 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
846 its_encode_target(sync_cmd, sync_col->target_address);
848 its_fixup_cmd(sync_cmd);
851 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
852 struct its_collection, its_build_sync_cmd)
854 static void its_build_vsync_cmd(struct its_node *its,
855 struct its_cmd_block *sync_cmd,
856 struct its_vpe *sync_vpe)
858 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
859 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
861 its_fixup_cmd(sync_cmd);
864 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
865 struct its_vpe, its_build_vsync_cmd)
867 static void its_send_int(struct its_device *dev, u32 event_id)
869 struct its_cmd_desc desc;
871 desc.its_int_cmd.dev = dev;
872 desc.its_int_cmd.event_id = event_id;
874 its_send_single_command(dev->its, its_build_int_cmd, &desc);
877 static void its_send_clear(struct its_device *dev, u32 event_id)
879 struct its_cmd_desc desc;
881 desc.its_clear_cmd.dev = dev;
882 desc.its_clear_cmd.event_id = event_id;
884 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
887 static void its_send_inv(struct its_device *dev, u32 event_id)
889 struct its_cmd_desc desc;
891 desc.its_inv_cmd.dev = dev;
892 desc.its_inv_cmd.event_id = event_id;
894 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
897 static void its_send_mapd(struct its_device *dev, int valid)
899 struct its_cmd_desc desc;
901 desc.its_mapd_cmd.dev = dev;
902 desc.its_mapd_cmd.valid = !!valid;
904 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
907 static void its_send_mapc(struct its_node *its, struct its_collection *col,
910 struct its_cmd_desc desc;
912 desc.its_mapc_cmd.col = col;
913 desc.its_mapc_cmd.valid = !!valid;
915 its_send_single_command(its, its_build_mapc_cmd, &desc);
918 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
920 struct its_cmd_desc desc;
922 desc.its_mapti_cmd.dev = dev;
923 desc.its_mapti_cmd.phys_id = irq_id;
924 desc.its_mapti_cmd.event_id = id;
926 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
929 static void its_send_movi(struct its_device *dev,
930 struct its_collection *col, u32 id)
932 struct its_cmd_desc desc;
934 desc.its_movi_cmd.dev = dev;
935 desc.its_movi_cmd.col = col;
936 desc.its_movi_cmd.event_id = id;
938 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
941 static void its_send_discard(struct its_device *dev, u32 id)
943 struct its_cmd_desc desc;
945 desc.its_discard_cmd.dev = dev;
946 desc.its_discard_cmd.event_id = id;
948 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
951 static void its_send_invall(struct its_node *its, struct its_collection *col)
953 struct its_cmd_desc desc;
955 desc.its_invall_cmd.col = col;
957 its_send_single_command(its, its_build_invall_cmd, &desc);
960 static void its_send_vmapti(struct its_device *dev, u32 id)
962 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
963 struct its_cmd_desc desc;
965 desc.its_vmapti_cmd.vpe = map->vpe;
966 desc.its_vmapti_cmd.dev = dev;
967 desc.its_vmapti_cmd.virt_id = map->vintid;
968 desc.its_vmapti_cmd.event_id = id;
969 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
971 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
974 static void its_send_vmovi(struct its_device *dev, u32 id)
976 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
977 struct its_cmd_desc desc;
979 desc.its_vmovi_cmd.vpe = map->vpe;
980 desc.its_vmovi_cmd.dev = dev;
981 desc.its_vmovi_cmd.event_id = id;
982 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
984 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
987 static void its_send_vmapp(struct its_node *its,
988 struct its_vpe *vpe, bool valid)
990 struct its_cmd_desc desc;
992 desc.its_vmapp_cmd.vpe = vpe;
993 desc.its_vmapp_cmd.valid = valid;
994 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
996 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
999 static void its_send_vmovp(struct its_vpe *vpe)
1001 struct its_cmd_desc desc = {};
1002 struct its_node *its;
1003 unsigned long flags;
1004 int col_id = vpe->col_idx;
1006 desc.its_vmovp_cmd.vpe = vpe;
1008 if (!its_list_map) {
1009 its = list_first_entry(&its_nodes, struct its_node, entry);
1010 desc.its_vmovp_cmd.col = &its->collections[col_id];
1011 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1016 * Yet another marvel of the architecture. If using the
1017 * its_list "feature", we need to make sure that all ITSs
1018 * receive all VMOVP commands in the same order. The only way
1019 * to guarantee this is to make vmovp a serialization point.
1023 raw_spin_lock_irqsave(&vmovp_lock, flags);
1025 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1026 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1029 list_for_each_entry(its, &its_nodes, entry) {
1033 if (!vpe->its_vm->vlpi_count[its->list_nr])
1036 desc.its_vmovp_cmd.col = &its->collections[col_id];
1037 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1040 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1043 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1045 struct its_cmd_desc desc;
1047 desc.its_vinvall_cmd.vpe = vpe;
1048 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1052 * irqchip functions - assumes MSI, mostly.
1055 static inline u32 its_get_event_id(struct irq_data *d)
1057 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1058 return d->hwirq - its_dev->event_map.lpi_base;
1061 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1063 irq_hw_number_t hwirq;
1064 struct page *prop_page;
1067 if (irqd_is_forwarded_to_vcpu(d)) {
1068 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1069 u32 event = its_get_event_id(d);
1070 struct its_vlpi_map *map;
1072 prop_page = its_dev->event_map.vm->vprop_page;
1073 map = &its_dev->event_map.vlpi_maps[event];
1074 hwirq = map->vintid;
1076 /* Remember the updated property */
1077 map->properties &= ~clr;
1078 map->properties |= set | LPI_PROP_GROUP1;
1080 prop_page = gic_rdists->prop_page;
1084 cfg = page_address(prop_page) + hwirq - 8192;
1086 *cfg |= set | LPI_PROP_GROUP1;
1089 * Make the above write visible to the redistributors.
1090 * And yes, we're flushing exactly: One. Single. Byte.
1093 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1094 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1099 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1101 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1103 lpi_write_config(d, clr, set);
1104 its_send_inv(its_dev, its_get_event_id(d));
1107 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1109 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1110 u32 event = its_get_event_id(d);
1112 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1115 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1118 * More fun with the architecture:
1120 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1121 * value or to 1023, depending on the enable bit. But that
1122 * would be issueing a mapping for an /existing/ DevID+EventID
1123 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1124 * to the /same/ vPE, using this opportunity to adjust the
1125 * doorbell. Mouahahahaha. We loves it, Precious.
1127 its_send_vmovi(its_dev, event);
1130 static void its_mask_irq(struct irq_data *d)
1132 if (irqd_is_forwarded_to_vcpu(d))
1133 its_vlpi_set_doorbell(d, false);
1135 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1138 static void its_unmask_irq(struct irq_data *d)
1140 if (irqd_is_forwarded_to_vcpu(d))
1141 its_vlpi_set_doorbell(d, true);
1143 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1146 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1150 const struct cpumask *cpu_mask = cpu_online_mask;
1151 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1152 struct its_collection *target_col;
1153 u32 id = its_get_event_id(d);
1155 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1156 if (irqd_is_forwarded_to_vcpu(d))
1159 /* lpi cannot be routed to a redistributor that is on a foreign node */
1160 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1161 if (its_dev->its->numa_node >= 0) {
1162 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1163 if (!cpumask_intersects(mask_val, cpu_mask))
1168 cpu = cpumask_any_and(mask_val, cpu_mask);
1170 if (cpu >= nr_cpu_ids)
1173 /* don't set the affinity when the target cpu is same as current one */
1174 if (cpu != its_dev->event_map.col_map[id]) {
1175 target_col = &its_dev->its->collections[cpu];
1176 its_send_movi(its_dev, target_col, id);
1177 its_dev->event_map.col_map[id] = cpu;
1178 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1181 return IRQ_SET_MASK_OK_DONE;
1184 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1186 struct its_node *its = its_dev->its;
1188 return its->phys_base + GITS_TRANSLATER;
1191 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1193 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1194 struct its_node *its;
1198 addr = its->get_msi_base(its_dev);
1200 msg->address_lo = lower_32_bits(addr);
1201 msg->address_hi = upper_32_bits(addr);
1202 msg->data = its_get_event_id(d);
1204 iommu_dma_map_msi_msg(d->irq, msg);
1207 static int its_irq_set_irqchip_state(struct irq_data *d,
1208 enum irqchip_irq_state which,
1211 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1212 u32 event = its_get_event_id(d);
1214 if (which != IRQCHIP_STATE_PENDING)
1218 its_send_int(its_dev, event);
1220 its_send_clear(its_dev, event);
1225 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1227 unsigned long flags;
1229 /* Not using the ITS list? Everything is always mapped. */
1233 raw_spin_lock_irqsave(&vmovp_lock, flags);
1236 * If the VM wasn't mapped yet, iterate over the vpes and get
1239 vm->vlpi_count[its->list_nr]++;
1241 if (vm->vlpi_count[its->list_nr] == 1) {
1244 for (i = 0; i < vm->nr_vpes; i++) {
1245 struct its_vpe *vpe = vm->vpes[i];
1246 struct irq_data *d = irq_get_irq_data(vpe->irq);
1248 /* Map the VPE to the first possible CPU */
1249 vpe->col_idx = cpumask_first(cpu_online_mask);
1250 its_send_vmapp(its, vpe, true);
1251 its_send_vinvall(its, vpe);
1252 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1256 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1259 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1261 unsigned long flags;
1263 /* Not using the ITS list? Everything is always mapped. */
1267 raw_spin_lock_irqsave(&vmovp_lock, flags);
1269 if (!--vm->vlpi_count[its->list_nr]) {
1272 for (i = 0; i < vm->nr_vpes; i++)
1273 its_send_vmapp(its, vm->vpes[i], false);
1276 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1279 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1281 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1282 u32 event = its_get_event_id(d);
1288 mutex_lock(&its_dev->event_map.vlpi_lock);
1290 if (!its_dev->event_map.vm) {
1291 struct its_vlpi_map *maps;
1293 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1300 its_dev->event_map.vm = info->map->vm;
1301 its_dev->event_map.vlpi_maps = maps;
1302 } else if (its_dev->event_map.vm != info->map->vm) {
1307 /* Get our private copy of the mapping information */
1308 its_dev->event_map.vlpi_maps[event] = *info->map;
1310 if (irqd_is_forwarded_to_vcpu(d)) {
1311 /* Already mapped, move it around */
1312 its_send_vmovi(its_dev, event);
1314 /* Ensure all the VPEs are mapped on this ITS */
1315 its_map_vm(its_dev->its, info->map->vm);
1318 * Flag the interrupt as forwarded so that we can
1319 * start poking the virtual property table.
1321 irqd_set_forwarded_to_vcpu(d);
1323 /* Write out the property to the prop table */
1324 lpi_write_config(d, 0xff, info->map->properties);
1326 /* Drop the physical mapping */
1327 its_send_discard(its_dev, event);
1329 /* and install the virtual one */
1330 its_send_vmapti(its_dev, event);
1332 /* Increment the number of VLPIs */
1333 its_dev->event_map.nr_vlpis++;
1337 mutex_unlock(&its_dev->event_map.vlpi_lock);
1341 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1343 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1344 u32 event = its_get_event_id(d);
1347 mutex_lock(&its_dev->event_map.vlpi_lock);
1349 if (!its_dev->event_map.vm ||
1350 !its_dev->event_map.vlpi_maps[event].vm) {
1355 /* Copy our mapping information to the incoming request */
1356 *info->map = its_dev->event_map.vlpi_maps[event];
1359 mutex_unlock(&its_dev->event_map.vlpi_lock);
1363 static int its_vlpi_unmap(struct irq_data *d)
1365 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1366 u32 event = its_get_event_id(d);
1369 mutex_lock(&its_dev->event_map.vlpi_lock);
1371 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1376 /* Drop the virtual mapping */
1377 its_send_discard(its_dev, event);
1379 /* and restore the physical one */
1380 irqd_clr_forwarded_to_vcpu(d);
1381 its_send_mapti(its_dev, d->hwirq, event);
1382 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1386 /* Potentially unmap the VM from this ITS */
1387 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1390 * Drop the refcount and make the device available again if
1391 * this was the last VLPI.
1393 if (!--its_dev->event_map.nr_vlpis) {
1394 its_dev->event_map.vm = NULL;
1395 kfree(its_dev->event_map.vlpi_maps);
1399 mutex_unlock(&its_dev->event_map.vlpi_lock);
1403 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1405 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1407 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1410 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1411 lpi_update_config(d, 0xff, info->config);
1413 lpi_write_config(d, 0xff, info->config);
1414 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1419 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1421 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1422 struct its_cmd_info *info = vcpu_info;
1425 if (!its_dev->its->is_v4)
1428 /* Unmap request? */
1430 return its_vlpi_unmap(d);
1432 switch (info->cmd_type) {
1434 return its_vlpi_map(d, info);
1437 return its_vlpi_get(d, info);
1439 case PROP_UPDATE_VLPI:
1440 case PROP_UPDATE_AND_INV_VLPI:
1441 return its_vlpi_prop_update(d, info);
1448 static struct irq_chip its_irq_chip = {
1450 .irq_mask = its_mask_irq,
1451 .irq_unmask = its_unmask_irq,
1452 .irq_eoi = irq_chip_eoi_parent,
1453 .irq_set_affinity = its_set_affinity,
1454 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1455 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1456 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1461 * How we allocate LPIs:
1463 * lpi_range_list contains ranges of LPIs that are to available to
1464 * allocate from. To allocate LPIs, just pick the first range that
1465 * fits the required allocation, and reduce it by the required
1466 * amount. Once empty, remove the range from the list.
1468 * To free a range of LPIs, add a free range to the list, sort it and
1469 * merge the result if the new range happens to be adjacent to an
1470 * already free block.
1472 * The consequence of the above is that allocation is cost is low, but
1473 * freeing is expensive. We assumes that freeing rarely occurs.
1475 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1477 static DEFINE_MUTEX(lpi_range_lock);
1478 static LIST_HEAD(lpi_range_list);
1481 struct list_head entry;
1486 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1488 struct lpi_range *range;
1490 range = kzalloc(sizeof(*range), GFP_KERNEL);
1492 INIT_LIST_HEAD(&range->entry);
1493 range->base_id = base;
1500 static int lpi_range_cmp(void *priv, struct list_head *a, struct list_head *b)
1502 struct lpi_range *ra, *rb;
1504 ra = container_of(a, struct lpi_range, entry);
1505 rb = container_of(b, struct lpi_range, entry);
1507 return ra->base_id - rb->base_id;
1510 static void merge_lpi_ranges(void)
1512 struct lpi_range *range, *tmp;
1514 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1515 if (!list_is_last(&range->entry, &lpi_range_list) &&
1516 (tmp->base_id == (range->base_id + range->span))) {
1517 tmp->base_id = range->base_id;
1518 tmp->span += range->span;
1519 list_del(&range->entry);
1525 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1527 struct lpi_range *range, *tmp;
1530 mutex_lock(&lpi_range_lock);
1532 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1533 if (range->span >= nr_lpis) {
1534 *base = range->base_id;
1535 range->base_id += nr_lpis;
1536 range->span -= nr_lpis;
1538 if (range->span == 0) {
1539 list_del(&range->entry);
1548 mutex_unlock(&lpi_range_lock);
1550 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1554 static int free_lpi_range(u32 base, u32 nr_lpis)
1556 struct lpi_range *new;
1559 mutex_lock(&lpi_range_lock);
1561 new = mk_lpi_range(base, nr_lpis);
1567 list_add(&new->entry, &lpi_range_list);
1568 list_sort(NULL, &lpi_range_list, lpi_range_cmp);
1571 mutex_unlock(&lpi_range_lock);
1575 static int __init its_lpi_init(u32 id_bits)
1577 u32 lpis = (1UL << id_bits) - 8192;
1581 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1583 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1585 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1590 * Initializing the allocator is just the same as freeing the
1591 * full range of LPIs.
1593 err = free_lpi_range(8192, lpis);
1594 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1598 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1600 unsigned long *bitmap = NULL;
1604 err = alloc_lpi_range(nr_irqs, base);
1609 } while (nr_irqs > 0);
1617 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1625 *base = *nr_ids = 0;
1630 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1632 WARN_ON(free_lpi_range(base, nr_ids));
1636 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1638 struct page *prop_page;
1640 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1644 /* Priority 0xa0, Group-1, disabled */
1645 memset(page_address(prop_page),
1646 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
1649 /* Make sure the GIC will observe the written configuration */
1650 gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ);
1655 static void its_free_prop_table(struct page *prop_page)
1657 free_pages((unsigned long)page_address(prop_page),
1658 get_order(LPI_PROPBASE_SZ));
1661 static int __init its_alloc_lpi_tables(void)
1665 lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1666 ITS_MAX_LPI_NRBITS);
1667 gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
1668 if (!gic_rdists->prop_page) {
1669 pr_err("Failed to allocate PROPBASE\n");
1673 paddr = page_to_phys(gic_rdists->prop_page);
1674 pr_info("GIC: using LPI property table @%pa\n", &paddr);
1676 return its_lpi_init(lpi_id_bits);
1679 static const char *its_base_type_string[] = {
1680 [GITS_BASER_TYPE_DEVICE] = "Devices",
1681 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1682 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1683 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1684 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1685 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1686 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1689 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1691 u32 idx = baser - its->tables;
1693 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1696 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1699 u32 idx = baser - its->tables;
1701 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1702 baser->val = its_read_baser(its, baser);
1705 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1706 u64 cache, u64 shr, u32 psz, u32 order,
1709 u64 val = its_read_baser(its, baser);
1710 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1711 u64 type = GITS_BASER_TYPE(val);
1712 u64 baser_phys, tmp;
1717 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1718 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1719 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1720 &its->phys_base, its_base_type_string[type],
1721 alloc_pages, GITS_BASER_PAGES_MAX);
1722 alloc_pages = GITS_BASER_PAGES_MAX;
1723 order = get_order(GITS_BASER_PAGES_MAX * psz);
1726 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
1730 baser_phys = virt_to_phys(base);
1732 /* Check if the physical address of the memory is above 48bits */
1733 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1735 /* 52bit PA is supported only when PageSize=64K */
1736 if (psz != SZ_64K) {
1737 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1738 free_pages((unsigned long)base, order);
1742 /* Convert 52bit PA to 48bit field */
1743 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1748 (type << GITS_BASER_TYPE_SHIFT) |
1749 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1750 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1755 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1759 val |= GITS_BASER_PAGE_SIZE_4K;
1762 val |= GITS_BASER_PAGE_SIZE_16K;
1765 val |= GITS_BASER_PAGE_SIZE_64K;
1769 its_write_baser(its, baser, val);
1772 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1774 * Shareability didn't stick. Just use
1775 * whatever the read reported, which is likely
1776 * to be the only thing this redistributor
1777 * supports. If that's zero, make it
1778 * non-cacheable as well.
1780 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1782 cache = GITS_BASER_nC;
1783 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1788 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1790 * Page size didn't stick. Let's try a smaller
1791 * size and retry. If we reach 4K, then
1792 * something is horribly wrong...
1794 free_pages((unsigned long)base, order);
1800 goto retry_alloc_baser;
1803 goto retry_alloc_baser;
1808 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1809 &its->phys_base, its_base_type_string[type],
1811 free_pages((unsigned long)base, order);
1815 baser->order = order;
1818 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1820 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1821 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1822 its_base_type_string[type],
1823 (unsigned long)virt_to_phys(base),
1824 indirect ? "indirect" : "flat", (int)esz,
1825 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1830 static bool its_parse_indirect_baser(struct its_node *its,
1831 struct its_baser *baser,
1832 u32 psz, u32 *order, u32 ids)
1834 u64 tmp = its_read_baser(its, baser);
1835 u64 type = GITS_BASER_TYPE(tmp);
1836 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1837 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1838 u32 new_order = *order;
1839 bool indirect = false;
1841 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1842 if ((esz << ids) > (psz * 2)) {
1844 * Find out whether hw supports a single or two-level table by
1845 * table by reading bit at offset '62' after writing '1' to it.
1847 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1848 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1852 * The size of the lvl2 table is equal to ITS page size
1853 * which is 'psz'. For computing lvl1 table size,
1854 * subtract ID bits that sparse lvl2 table from 'ids'
1855 * which is reported by ITS hardware times lvl1 table
1858 ids -= ilog2(psz / (int)esz);
1859 esz = GITS_LVL1_ENTRY_SIZE;
1864 * Allocate as many entries as required to fit the
1865 * range of device IDs that the ITS can grok... The ID
1866 * space being incredibly sparse, this results in a
1867 * massive waste of memory if two-level device table
1868 * feature is not supported by hardware.
1870 new_order = max_t(u32, get_order(esz << ids), new_order);
1871 if (new_order >= MAX_ORDER) {
1872 new_order = MAX_ORDER - 1;
1873 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1874 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1875 &its->phys_base, its_base_type_string[type],
1876 its->device_ids, ids);
1884 static void its_free_tables(struct its_node *its)
1888 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1889 if (its->tables[i].base) {
1890 free_pages((unsigned long)its->tables[i].base,
1891 its->tables[i].order);
1892 its->tables[i].base = NULL;
1897 static int its_alloc_tables(struct its_node *its)
1899 u64 shr = GITS_BASER_InnerShareable;
1900 u64 cache = GITS_BASER_RaWaWb;
1904 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1905 /* erratum 24313: ignore memory access type */
1906 cache = GITS_BASER_nCnB;
1908 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1909 struct its_baser *baser = its->tables + i;
1910 u64 val = its_read_baser(its, baser);
1911 u64 type = GITS_BASER_TYPE(val);
1912 u32 order = get_order(psz);
1913 bool indirect = false;
1916 case GITS_BASER_TYPE_NONE:
1919 case GITS_BASER_TYPE_DEVICE:
1920 indirect = its_parse_indirect_baser(its, baser,
1925 case GITS_BASER_TYPE_VCPU:
1926 indirect = its_parse_indirect_baser(its, baser,
1928 ITS_MAX_VPEID_BITS);
1932 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1934 its_free_tables(its);
1938 /* Update settings which will be used for next BASERn */
1940 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1941 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1947 static int its_alloc_collections(struct its_node *its)
1951 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
1953 if (!its->collections)
1956 for (i = 0; i < nr_cpu_ids; i++)
1957 its->collections[i].target_address = ~0ULL;
1962 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1964 struct page *pend_page;
1966 * The pending pages have to be at least 64kB aligned,
1967 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1969 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
1970 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1974 /* Make sure the GIC will observe the zero-ed page */
1975 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
1980 static void its_free_pending_table(struct page *pt)
1982 free_pages((unsigned long)page_address(pt),
1983 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1986 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
1988 u32 count = 1000000; /* 1s! */
1992 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
1993 val &= ~GICR_VPENDBASER_Valid;
1994 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
1997 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
1998 clean = !(val & GICR_VPENDBASER_Dirty);
2004 } while (!clean && count);
2009 static void its_cpu_init_lpis(void)
2011 void __iomem *rbase = gic_data_rdist_rd_base();
2012 struct page *pend_page;
2015 /* If we didn't allocate the pending table yet, do it now */
2016 pend_page = gic_data_rdist()->pend_page;
2020 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2022 pr_err("Failed to allocate PENDBASE for CPU%d\n",
2023 smp_processor_id());
2027 paddr = page_to_phys(pend_page);
2028 pr_info("CPU%d: using LPI pending table @%pa\n",
2029 smp_processor_id(), &paddr);
2030 gic_data_rdist()->pend_page = pend_page;
2034 val = (page_to_phys(gic_rdists->prop_page) |
2035 GICR_PROPBASER_InnerShareable |
2036 GICR_PROPBASER_RaWaWb |
2037 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2039 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2040 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2042 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2043 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2045 * The HW reports non-shareable, we must
2046 * remove the cacheability attributes as
2049 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2050 GICR_PROPBASER_CACHEABILITY_MASK);
2051 val |= GICR_PROPBASER_nC;
2052 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2054 pr_info_once("GIC: using cache flushing for LPI property table\n");
2055 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2059 val = (page_to_phys(pend_page) |
2060 GICR_PENDBASER_InnerShareable |
2061 GICR_PENDBASER_RaWaWb);
2063 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2064 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2066 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2068 * The HW reports non-shareable, we must remove the
2069 * cacheability attributes as well.
2071 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2072 GICR_PENDBASER_CACHEABILITY_MASK);
2073 val |= GICR_PENDBASER_nC;
2074 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2078 val = readl_relaxed(rbase + GICR_CTLR);
2079 val |= GICR_CTLR_ENABLE_LPIS;
2080 writel_relaxed(val, rbase + GICR_CTLR);
2082 if (gic_rdists->has_vlpis) {
2083 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2086 * It's possible for CPU to receive VLPIs before it is
2087 * sheduled as a vPE, especially for the first CPU, and the
2088 * VLPI with INTID larger than 2^(IDbits+1) will be considered
2089 * as out of range and dropped by GIC.
2090 * So we initialize IDbits to known value to avoid VLPI drop.
2092 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2093 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2094 smp_processor_id(), val);
2095 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2098 * Also clear Valid bit of GICR_VPENDBASER, in case some
2099 * ancient programming gets left in and has possibility of
2100 * corrupting memory.
2102 val = its_clear_vpend_valid(vlpi_base);
2103 WARN_ON(val & GICR_VPENDBASER_Dirty);
2106 /* Make sure the GIC has seen the above */
2110 static void its_cpu_init_collection(struct its_node *its)
2112 int cpu = smp_processor_id();
2115 /* avoid cross node collections and its mapping */
2116 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2117 struct device_node *cpu_node;
2119 cpu_node = of_get_cpu_node(cpu, NULL);
2120 if (its->numa_node != NUMA_NO_NODE &&
2121 its->numa_node != of_node_to_nid(cpu_node))
2126 * We now have to bind each collection to its target
2129 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2131 * This ITS wants the physical address of the
2134 target = gic_data_rdist()->phys_base;
2136 /* This ITS wants a linear CPU number. */
2137 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2138 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2141 /* Perform collection mapping */
2142 its->collections[cpu].target_address = target;
2143 its->collections[cpu].col_id = cpu;
2145 its_send_mapc(its, &its->collections[cpu], 1);
2146 its_send_invall(its, &its->collections[cpu]);
2149 static void its_cpu_init_collections(void)
2151 struct its_node *its;
2153 raw_spin_lock(&its_lock);
2155 list_for_each_entry(its, &its_nodes, entry)
2156 its_cpu_init_collection(its);
2158 raw_spin_unlock(&its_lock);
2161 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2163 struct its_device *its_dev = NULL, *tmp;
2164 unsigned long flags;
2166 raw_spin_lock_irqsave(&its->lock, flags);
2168 list_for_each_entry(tmp, &its->its_device_list, entry) {
2169 if (tmp->device_id == dev_id) {
2175 raw_spin_unlock_irqrestore(&its->lock, flags);
2180 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2184 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2185 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2186 return &its->tables[i];
2192 static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
2198 /* Don't allow device id that exceeds single, flat table limit */
2199 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2200 if (!(baser->val & GITS_BASER_INDIRECT))
2201 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2203 /* Compute 1st level table index & check if that exceeds table limit */
2204 idx = id >> ilog2(baser->psz / esz);
2205 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2208 table = baser->base;
2210 /* Allocate memory for 2nd level table */
2212 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
2216 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2217 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2218 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2220 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2222 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2223 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2224 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2226 /* Ensure updated table contents are visible to ITS hardware */
2233 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2235 struct its_baser *baser;
2237 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2239 /* Don't allow device id that exceeds ITS hardware limit */
2241 return (ilog2(dev_id) < its->device_ids);
2243 return its_alloc_table_entry(baser, dev_id);
2246 static bool its_alloc_vpe_table(u32 vpe_id)
2248 struct its_node *its;
2251 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2252 * could try and only do it on ITSs corresponding to devices
2253 * that have interrupts targeted at this VPE, but the
2254 * complexity becomes crazy (and you have tons of memory
2257 list_for_each_entry(its, &its_nodes, entry) {
2258 struct its_baser *baser;
2263 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2267 if (!its_alloc_table_entry(baser, vpe_id))
2274 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2275 int nvecs, bool alloc_lpis)
2277 struct its_device *dev;
2278 unsigned long *lpi_map = NULL;
2279 unsigned long flags;
2280 u16 *col_map = NULL;
2287 if (!its_alloc_device_table(its, dev_id))
2290 if (WARN_ON(!is_power_of_2(nvecs)))
2291 nvecs = roundup_pow_of_two(nvecs);
2293 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2295 * Even if the device wants a single LPI, the ITT must be
2296 * sized as a power of two (and you need at least one bit...).
2298 nr_ites = max(2, nvecs);
2299 sz = nr_ites * its->ite_size;
2300 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2301 itt = kzalloc(sz, GFP_KERNEL);
2303 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2305 col_map = kcalloc(nr_lpis, sizeof(*col_map),
2308 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2313 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2321 gic_flush_dcache_to_poc(itt, sz);
2325 dev->nr_ites = nr_ites;
2326 dev->event_map.lpi_map = lpi_map;
2327 dev->event_map.col_map = col_map;
2328 dev->event_map.lpi_base = lpi_base;
2329 dev->event_map.nr_lpis = nr_lpis;
2330 mutex_init(&dev->event_map.vlpi_lock);
2331 dev->device_id = dev_id;
2332 INIT_LIST_HEAD(&dev->entry);
2334 raw_spin_lock_irqsave(&its->lock, flags);
2335 list_add(&dev->entry, &its->its_device_list);
2336 raw_spin_unlock_irqrestore(&its->lock, flags);
2338 /* Map device to its ITT */
2339 its_send_mapd(dev, 1);
2344 static void its_free_device(struct its_device *its_dev)
2346 unsigned long flags;
2348 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2349 list_del(&its_dev->entry);
2350 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2351 kfree(its_dev->itt);
2355 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2359 idx = bitmap_find_free_region(dev->event_map.lpi_map,
2360 dev->event_map.nr_lpis,
2361 get_count_order(nvecs));
2365 *hwirq = dev->event_map.lpi_base + idx;
2366 set_bit(idx, dev->event_map.lpi_map);
2371 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2372 int nvec, msi_alloc_info_t *info)
2374 struct its_node *its;
2375 struct its_device *its_dev;
2376 struct msi_domain_info *msi_info;
2381 * We ignore "dev" entierely, and rely on the dev_id that has
2382 * been passed via the scratchpad. This limits this domain's
2383 * usefulness to upper layers that definitely know that they
2384 * are built on top of the ITS.
2386 dev_id = info->scratchpad[0].ul;
2388 msi_info = msi_get_domain_info(domain);
2389 its = msi_info->data;
2391 if (!gic_rdists->has_direct_lpi &&
2393 vpe_proxy.dev->its == its &&
2394 dev_id == vpe_proxy.dev->device_id) {
2395 /* Bad luck. Get yourself a better implementation */
2396 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2401 mutex_lock(&its->dev_alloc_lock);
2402 its_dev = its_find_device(its, dev_id);
2405 * We already have seen this ID, probably through
2406 * another alias (PCI bridge of some sort). No need to
2407 * create the device.
2409 its_dev->shared = true;
2410 pr_debug("Reusing ITT for devID %x\n", dev_id);
2414 its_dev = its_create_device(its, dev_id, nvec, true);
2420 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2422 mutex_unlock(&its->dev_alloc_lock);
2423 info->scratchpad[0].ptr = its_dev;
2427 static struct msi_domain_ops its_msi_domain_ops = {
2428 .msi_prepare = its_msi_prepare,
2431 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2433 irq_hw_number_t hwirq)
2435 struct irq_fwspec fwspec;
2437 if (irq_domain_get_of_node(domain->parent)) {
2438 fwspec.fwnode = domain->parent->fwnode;
2439 fwspec.param_count = 3;
2440 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2441 fwspec.param[1] = hwirq;
2442 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2443 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2444 fwspec.fwnode = domain->parent->fwnode;
2445 fwspec.param_count = 2;
2446 fwspec.param[0] = hwirq;
2447 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2452 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2455 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2456 unsigned int nr_irqs, void *args)
2458 msi_alloc_info_t *info = args;
2459 struct its_device *its_dev = info->scratchpad[0].ptr;
2460 struct irq_data *irqd;
2461 irq_hw_number_t hwirq;
2465 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2469 for (i = 0; i < nr_irqs; i++) {
2470 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2474 irq_domain_set_hwirq_and_chip(domain, virq + i,
2475 hwirq + i, &its_irq_chip, its_dev);
2476 irqd = irq_get_irq_data(virq + i);
2477 irqd_set_single_target(irqd);
2478 irqd_set_affinity_on_activate(irqd);
2479 pr_debug("ID:%d pID:%d vID:%d\n",
2480 (int)(hwirq + i - its_dev->event_map.lpi_base),
2481 (int)(hwirq + i), virq + i);
2487 static int its_irq_domain_activate(struct irq_domain *domain,
2488 struct irq_data *d, bool reserve)
2490 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2491 u32 event = its_get_event_id(d);
2492 const struct cpumask *cpu_mask = cpu_online_mask;
2495 /* get the cpu_mask of local node */
2496 if (its_dev->its->numa_node >= 0)
2497 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2499 /* Bind the LPI to the first possible CPU */
2500 cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2501 if (cpu >= nr_cpu_ids) {
2502 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2505 cpu = cpumask_first(cpu_online_mask);
2508 its_dev->event_map.col_map[event] = cpu;
2509 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2511 /* Map the GIC IRQ and event to the device */
2512 its_send_mapti(its_dev, d->hwirq, event);
2516 static void its_irq_domain_deactivate(struct irq_domain *domain,
2519 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2520 u32 event = its_get_event_id(d);
2522 /* Stop the delivery of interrupts */
2523 its_send_discard(its_dev, event);
2526 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2527 unsigned int nr_irqs)
2529 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2530 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2531 struct its_node *its = its_dev->its;
2534 bitmap_release_region(its_dev->event_map.lpi_map,
2535 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
2536 get_count_order(nr_irqs));
2538 for (i = 0; i < nr_irqs; i++) {
2539 struct irq_data *data = irq_domain_get_irq_data(domain,
2541 /* Nuke the entry in the domain */
2542 irq_domain_reset_irq_data(data);
2545 mutex_lock(&its->dev_alloc_lock);
2548 * If all interrupts have been freed, start mopping the
2549 * floor. This is conditionned on the device not being shared.
2551 if (!its_dev->shared &&
2552 bitmap_empty(its_dev->event_map.lpi_map,
2553 its_dev->event_map.nr_lpis)) {
2554 its_lpi_free(its_dev->event_map.lpi_map,
2555 its_dev->event_map.lpi_base,
2556 its_dev->event_map.nr_lpis);
2557 kfree(its_dev->event_map.col_map);
2559 /* Unmap device/itt */
2560 its_send_mapd(its_dev, 0);
2561 its_free_device(its_dev);
2564 mutex_unlock(&its->dev_alloc_lock);
2566 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2569 static const struct irq_domain_ops its_domain_ops = {
2570 .alloc = its_irq_domain_alloc,
2571 .free = its_irq_domain_free,
2572 .activate = its_irq_domain_activate,
2573 .deactivate = its_irq_domain_deactivate,
2579 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2580 * likely), the only way to perform an invalidate is to use a fake
2581 * device to issue an INV command, implying that the LPI has first
2582 * been mapped to some event on that device. Since this is not exactly
2583 * cheap, we try to keep that mapping around as long as possible, and
2584 * only issue an UNMAP if we're short on available slots.
2586 * Broken by design(tm).
2588 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2590 /* Already unmapped? */
2591 if (vpe->vpe_proxy_event == -1)
2594 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2595 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2598 * We don't track empty slots at all, so let's move the
2599 * next_victim pointer if we can quickly reuse that slot
2600 * instead of nuking an existing entry. Not clear that this is
2601 * always a win though, and this might just generate a ripple
2602 * effect... Let's just hope VPEs don't migrate too often.
2604 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2605 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2607 vpe->vpe_proxy_event = -1;
2610 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2612 if (!gic_rdists->has_direct_lpi) {
2613 unsigned long flags;
2615 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2616 its_vpe_db_proxy_unmap_locked(vpe);
2617 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2621 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2623 /* Already mapped? */
2624 if (vpe->vpe_proxy_event != -1)
2627 /* This slot was already allocated. Kick the other VPE out. */
2628 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2629 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2631 /* Map the new VPE instead */
2632 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2633 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2634 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2636 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2637 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2640 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2642 unsigned long flags;
2643 struct its_collection *target_col;
2645 if (gic_rdists->has_direct_lpi) {
2646 void __iomem *rdbase;
2648 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2649 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2650 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2656 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2658 its_vpe_db_proxy_map_locked(vpe);
2660 target_col = &vpe_proxy.dev->its->collections[to];
2661 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2662 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2664 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2667 static int its_vpe_set_affinity(struct irq_data *d,
2668 const struct cpumask *mask_val,
2671 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2672 int cpu = cpumask_first(mask_val);
2675 * Changing affinity is mega expensive, so let's be as lazy as
2676 * we can and only do it if we really have to. Also, if mapped
2677 * into the proxy device, we need to move the doorbell
2678 * interrupt to its new location.
2680 if (vpe->col_idx != cpu) {
2681 int from = vpe->col_idx;
2684 its_send_vmovp(vpe);
2685 its_vpe_db_proxy_move(vpe, from, cpu);
2688 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2690 return IRQ_SET_MASK_OK_DONE;
2693 static void its_vpe_schedule(struct its_vpe *vpe)
2695 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2698 /* Schedule the VPE */
2699 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2700 GENMASK_ULL(51, 12);
2701 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2702 val |= GICR_VPROPBASER_RaWb;
2703 val |= GICR_VPROPBASER_InnerShareable;
2704 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2706 val = virt_to_phys(page_address(vpe->vpt_page)) &
2707 GENMASK_ULL(51, 16);
2708 val |= GICR_VPENDBASER_RaWaWb;
2709 val |= GICR_VPENDBASER_NonShareable;
2711 * There is no good way of finding out if the pending table is
2712 * empty as we can race against the doorbell interrupt very
2713 * easily. So in the end, vpe->pending_last is only an
2714 * indication that the vcpu has something pending, not one
2715 * that the pending table is empty. A good implementation
2716 * would be able to read its coarse map pretty quickly anyway,
2717 * making this a tolerable issue.
2719 val |= GICR_VPENDBASER_PendingLast;
2720 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2721 val |= GICR_VPENDBASER_Valid;
2722 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2725 static void its_vpe_deschedule(struct its_vpe *vpe)
2727 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2730 val = its_clear_vpend_valid(vlpi_base);
2732 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2733 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2735 vpe->pending_last = true;
2737 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2738 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2742 static void its_vpe_invall(struct its_vpe *vpe)
2744 struct its_node *its;
2746 list_for_each_entry(its, &its_nodes, entry) {
2750 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2754 * Sending a VINVALL to a single ITS is enough, as all
2755 * we need is to reach the redistributors.
2757 its_send_vinvall(its, vpe);
2762 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2764 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2765 struct its_cmd_info *info = vcpu_info;
2767 switch (info->cmd_type) {
2769 its_vpe_schedule(vpe);
2772 case DESCHEDULE_VPE:
2773 its_vpe_deschedule(vpe);
2777 its_vpe_invall(vpe);
2785 static void its_vpe_send_cmd(struct its_vpe *vpe,
2786 void (*cmd)(struct its_device *, u32))
2788 unsigned long flags;
2790 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2792 its_vpe_db_proxy_map_locked(vpe);
2793 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2795 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2798 static void its_vpe_send_inv(struct irq_data *d)
2800 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2802 if (gic_rdists->has_direct_lpi) {
2803 void __iomem *rdbase;
2805 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2806 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2807 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2810 its_vpe_send_cmd(vpe, its_send_inv);
2814 static void its_vpe_mask_irq(struct irq_data *d)
2817 * We need to unmask the LPI, which is described by the parent
2818 * irq_data. Instead of calling into the parent (which won't
2819 * exactly do the right thing, let's simply use the
2820 * parent_data pointer. Yes, I'm naughty.
2822 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2823 its_vpe_send_inv(d);
2826 static void its_vpe_unmask_irq(struct irq_data *d)
2828 /* Same hack as above... */
2829 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2830 its_vpe_send_inv(d);
2833 static int its_vpe_set_irqchip_state(struct irq_data *d,
2834 enum irqchip_irq_state which,
2837 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2839 if (which != IRQCHIP_STATE_PENDING)
2842 if (gic_rdists->has_direct_lpi) {
2843 void __iomem *rdbase;
2845 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2847 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2849 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2850 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2855 its_vpe_send_cmd(vpe, its_send_int);
2857 its_vpe_send_cmd(vpe, its_send_clear);
2863 static int its_vpe_retrigger(struct irq_data *d)
2865 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
2868 static struct irq_chip its_vpe_irq_chip = {
2869 .name = "GICv4-vpe",
2870 .irq_mask = its_vpe_mask_irq,
2871 .irq_unmask = its_vpe_unmask_irq,
2872 .irq_eoi = irq_chip_eoi_parent,
2873 .irq_set_affinity = its_vpe_set_affinity,
2874 .irq_retrigger = its_vpe_retrigger,
2875 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
2876 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
2879 static int its_vpe_id_alloc(void)
2881 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2884 static void its_vpe_id_free(u16 id)
2886 ida_simple_remove(&its_vpeid_ida, id);
2889 static int its_vpe_init(struct its_vpe *vpe)
2891 struct page *vpt_page;
2894 /* Allocate vpe_id */
2895 vpe_id = its_vpe_id_alloc();
2900 vpt_page = its_allocate_pending_table(GFP_KERNEL);
2902 its_vpe_id_free(vpe_id);
2906 if (!its_alloc_vpe_table(vpe_id)) {
2907 its_vpe_id_free(vpe_id);
2908 its_free_pending_table(vpt_page);
2912 vpe->vpe_id = vpe_id;
2913 vpe->vpt_page = vpt_page;
2914 vpe->vpe_proxy_event = -1;
2919 static void its_vpe_teardown(struct its_vpe *vpe)
2921 its_vpe_db_proxy_unmap(vpe);
2922 its_vpe_id_free(vpe->vpe_id);
2923 its_free_pending_table(vpe->vpt_page);
2926 static void its_vpe_irq_domain_free(struct irq_domain *domain,
2928 unsigned int nr_irqs)
2930 struct its_vm *vm = domain->host_data;
2933 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2935 for (i = 0; i < nr_irqs; i++) {
2936 struct irq_data *data = irq_domain_get_irq_data(domain,
2938 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
2940 BUG_ON(vm != vpe->its_vm);
2942 clear_bit(data->hwirq, vm->db_bitmap);
2943 its_vpe_teardown(vpe);
2944 irq_domain_reset_irq_data(data);
2947 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
2948 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
2949 its_free_prop_table(vm->vprop_page);
2953 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2954 unsigned int nr_irqs, void *args)
2956 struct its_vm *vm = args;
2957 unsigned long *bitmap;
2958 struct page *vprop_page;
2959 int base, nr_ids, i, err = 0;
2963 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
2967 if (nr_ids < nr_irqs) {
2968 its_lpi_free(bitmap, base, nr_ids);
2972 vprop_page = its_allocate_prop_table(GFP_KERNEL);
2974 its_lpi_free(bitmap, base, nr_ids);
2978 vm->db_bitmap = bitmap;
2979 vm->db_lpi_base = base;
2980 vm->nr_db_lpis = nr_ids;
2981 vm->vprop_page = vprop_page;
2983 for (i = 0; i < nr_irqs; i++) {
2984 vm->vpes[i]->vpe_db_lpi = base + i;
2985 err = its_vpe_init(vm->vpes[i]);
2988 err = its_irq_gic_domain_alloc(domain, virq + i,
2989 vm->vpes[i]->vpe_db_lpi);
2992 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
2993 &its_vpe_irq_chip, vm->vpes[i]);
2999 its_vpe_irq_domain_free(domain, virq, i);
3001 its_lpi_free(bitmap, base, nr_ids);
3002 its_free_prop_table(vprop_page);
3008 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3009 struct irq_data *d, bool reserve)
3011 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3012 struct its_node *its;
3014 /* If we use the list map, we issue VMAPP on demand... */
3018 /* Map the VPE to the first possible CPU */
3019 vpe->col_idx = cpumask_first(cpu_online_mask);
3021 list_for_each_entry(its, &its_nodes, entry) {
3025 its_send_vmapp(its, vpe, true);
3026 its_send_vinvall(its, vpe);
3029 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3034 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3037 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3038 struct its_node *its;
3041 * If we use the list map, we unmap the VPE once no VLPIs are
3042 * associated with the VM.
3047 list_for_each_entry(its, &its_nodes, entry) {
3051 its_send_vmapp(its, vpe, false);
3055 static const struct irq_domain_ops its_vpe_domain_ops = {
3056 .alloc = its_vpe_irq_domain_alloc,
3057 .free = its_vpe_irq_domain_free,
3058 .activate = its_vpe_irq_domain_activate,
3059 .deactivate = its_vpe_irq_domain_deactivate,
3062 static int its_force_quiescent(void __iomem *base)
3064 u32 count = 1000000; /* 1s */
3067 val = readl_relaxed(base + GITS_CTLR);
3069 * GIC architecture specification requires the ITS to be both
3070 * disabled and quiescent for writes to GITS_BASER<n> or
3071 * GITS_CBASER to not have UNPREDICTABLE results.
3073 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3076 /* Disable the generation of all interrupts to this ITS */
3077 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3078 writel_relaxed(val, base + GITS_CTLR);
3080 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3082 val = readl_relaxed(base + GITS_CTLR);
3083 if (val & GITS_CTLR_QUIESCENT)
3095 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3097 struct its_node *its = data;
3099 /* erratum 22375: only alloc 8MB table size */
3100 its->device_ids = 0x14; /* 20 bits, 8MB */
3101 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3106 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3108 struct its_node *its = data;
3110 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3115 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3117 struct its_node *its = data;
3119 /* On QDF2400, the size of the ITE is 16Bytes */
3125 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3127 struct its_node *its = its_dev->its;
3130 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3131 * which maps 32-bit writes targeted at a separate window of
3132 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3133 * with device ID taken from bits [device_id_bits + 1:2] of
3134 * the window offset.
3136 return its->pre_its_base + (its_dev->device_id << 2);
3139 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3141 struct its_node *its = data;
3142 u32 pre_its_window[2];
3145 if (!fwnode_property_read_u32_array(its->fwnode_handle,
3146 "socionext,synquacer-pre-its",
3148 ARRAY_SIZE(pre_its_window))) {
3150 its->pre_its_base = pre_its_window[0];
3151 its->get_msi_base = its_irq_get_msi_base_pre_its;
3153 ids = ilog2(pre_its_window[1]) - 2;
3154 if (its->device_ids > ids)
3155 its->device_ids = ids;
3157 /* the pre-ITS breaks isolation, so disable MSI remapping */
3158 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3164 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3166 struct its_node *its = data;
3169 * Hip07 insists on using the wrong address for the VLPI
3170 * page. Trick it into doing the right thing...
3172 its->vlpi_redist_offset = SZ_128K;
3176 static const struct gic_quirk its_quirks[] = {
3177 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3179 .desc = "ITS: Cavium errata 22375, 24313",
3180 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3182 .init = its_enable_quirk_cavium_22375,
3185 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3187 .desc = "ITS: Cavium erratum 23144",
3188 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3190 .init = its_enable_quirk_cavium_23144,
3193 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3195 .desc = "ITS: QDF2400 erratum 0065",
3196 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
3198 .init = its_enable_quirk_qdf2400_e0065,
3201 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3204 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3205 * implementation, but with a 'pre-ITS' added that requires
3206 * special handling in software.
3208 .desc = "ITS: Socionext Synquacer pre-ITS",
3211 .init = its_enable_quirk_socionext_synquacer,
3214 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3216 .desc = "ITS: Hip07 erratum 161600802",
3219 .init = its_enable_quirk_hip07_161600802,
3226 static void its_enable_quirks(struct its_node *its)
3228 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3230 gic_enable_quirks(iidr, its_quirks, its);
3233 static int its_save_disable(void)
3235 struct its_node *its;
3238 raw_spin_lock(&its_lock);
3239 list_for_each_entry(its, &its_nodes, entry) {
3243 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3244 err = its_force_quiescent(base);
3246 pr_err("ITS@%pa: failed to quiesce: %d\n",
3247 &its->phys_base, err);
3248 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3252 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3257 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3261 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3264 raw_spin_unlock(&its_lock);
3269 static void its_restore_enable(void)
3271 struct its_node *its;
3274 raw_spin_lock(&its_lock);
3275 list_for_each_entry(its, &its_nodes, entry) {
3282 * Make sure that the ITS is disabled. If it fails to quiesce,
3283 * don't restore it since writing to CBASER or BASER<n>
3284 * registers is undefined according to the GIC v3 ITS
3287 * Firmware resuming with the ITS enabled is terminally broken.
3289 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
3290 ret = its_force_quiescent(base);
3292 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3293 &its->phys_base, ret);
3297 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3300 * Writing CBASER resets CREADR to 0, so make CWRITER and
3301 * cmd_write line up with it.
3303 its->cmd_write = its->cmd_base;
3304 gits_write_cwriter(0, base + GITS_CWRITER);
3306 /* Restore GITS_BASER from the value cache. */
3307 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3308 struct its_baser *baser = &its->tables[i];
3310 if (!(baser->val & GITS_BASER_VALID))
3313 its_write_baser(its, baser, baser->val);
3315 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3318 * Reinit the collection if it's stored in the ITS. This is
3319 * indicated by the col_id being less than the HCC field.
3320 * CID < HCC as specified in the GIC v3 Documentation.
3322 if (its->collections[smp_processor_id()].col_id <
3323 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3324 its_cpu_init_collection(its);
3326 raw_spin_unlock(&its_lock);
3329 static struct syscore_ops its_syscore_ops = {
3330 .suspend = its_save_disable,
3331 .resume = its_restore_enable,
3334 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3336 struct irq_domain *inner_domain;
3337 struct msi_domain_info *info;
3339 info = kzalloc(sizeof(*info), GFP_KERNEL);
3343 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3344 if (!inner_domain) {
3349 inner_domain->parent = its_parent;
3350 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3351 inner_domain->flags |= its->msi_domain_flags;
3352 info->ops = &its_msi_domain_ops;
3354 inner_domain->host_data = info;
3359 static int its_init_vpe_domain(void)
3361 struct its_node *its;
3365 if (gic_rdists->has_direct_lpi) {
3366 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3370 /* Any ITS will do, even if not v4 */
3371 its = list_first_entry(&its_nodes, struct its_node, entry);
3373 entries = roundup_pow_of_two(nr_cpu_ids);
3374 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3376 if (!vpe_proxy.vpes) {
3377 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3381 /* Use the last possible DevID */
3382 devid = GENMASK(its->device_ids - 1, 0);
3383 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3384 if (!vpe_proxy.dev) {
3385 kfree(vpe_proxy.vpes);
3386 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3390 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3392 raw_spin_lock_init(&vpe_proxy.lock);
3393 vpe_proxy.next_victim = 0;
3394 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3395 devid, vpe_proxy.dev->nr_ites);
3400 static int __init its_compute_its_list_map(struct resource *res,
3401 void __iomem *its_base)
3407 * This is assumed to be done early enough that we're
3408 * guaranteed to be single-threaded, hence no
3409 * locking. Should this change, we should address
3412 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3413 if (its_number >= GICv4_ITS_LIST_MAX) {
3414 pr_err("ITS@%pa: No ITSList entry available!\n",
3419 ctlr = readl_relaxed(its_base + GITS_CTLR);
3420 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3421 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3422 writel_relaxed(ctlr, its_base + GITS_CTLR);
3423 ctlr = readl_relaxed(its_base + GITS_CTLR);
3424 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3425 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3426 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3429 if (test_and_set_bit(its_number, &its_list_map)) {
3430 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3431 &res->start, its_number);
3438 static int __init its_probe_one(struct resource *res,
3439 struct fwnode_handle *handle, int numa_node)
3441 struct its_node *its;
3442 void __iomem *its_base;
3444 u64 baser, tmp, typer;
3447 its_base = ioremap(res->start, resource_size(res));
3449 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3453 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3454 if (val != 0x30 && val != 0x40) {
3455 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3460 err = its_force_quiescent(its_base);
3462 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3466 pr_info("ITS %pR\n", res);
3468 its = kzalloc(sizeof(*its), GFP_KERNEL);
3474 raw_spin_lock_init(&its->lock);
3475 mutex_init(&its->dev_alloc_lock);
3476 INIT_LIST_HEAD(&its->entry);
3477 INIT_LIST_HEAD(&its->its_device_list);
3478 typer = gic_read_typer(its_base + GITS_TYPER);
3479 its->base = its_base;
3480 its->phys_base = res->start;
3481 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3482 its->device_ids = GITS_TYPER_DEVBITS(typer);
3483 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3485 if (!(typer & GITS_TYPER_VMOVP)) {
3486 err = its_compute_its_list_map(res, its_base);
3492 pr_info("ITS@%pa: Using ITS number %d\n",
3495 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3499 its->numa_node = numa_node;
3501 its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
3502 get_order(ITS_CMD_QUEUE_SZ));
3503 if (!its->cmd_base) {
3507 its->cmd_write = its->cmd_base;
3508 its->fwnode_handle = handle;
3509 its->get_msi_base = its_irq_get_msi_base;
3510 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3512 its_enable_quirks(its);
3514 err = its_alloc_tables(its);
3518 err = its_alloc_collections(its);
3520 goto out_free_tables;
3522 baser = (virt_to_phys(its->cmd_base) |
3523 GITS_CBASER_RaWaWb |
3524 GITS_CBASER_InnerShareable |
3525 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3528 gits_write_cbaser(baser, its->base + GITS_CBASER);
3529 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3531 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3532 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3534 * The HW reports non-shareable, we must
3535 * remove the cacheability attributes as
3538 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3539 GITS_CBASER_CACHEABILITY_MASK);
3540 baser |= GITS_CBASER_nC;
3541 gits_write_cbaser(baser, its->base + GITS_CBASER);
3543 pr_info("ITS: using cache flushing for cmd queue\n");
3544 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3547 gits_write_cwriter(0, its->base + GITS_CWRITER);
3548 ctlr = readl_relaxed(its->base + GITS_CTLR);
3549 ctlr |= GITS_CTLR_ENABLE;
3551 ctlr |= GITS_CTLR_ImDe;
3552 writel_relaxed(ctlr, its->base + GITS_CTLR);
3554 err = its_init_domain(handle, its);
3556 goto out_free_tables;
3558 raw_spin_lock(&its_lock);
3559 list_add(&its->entry, &its_nodes);
3560 raw_spin_unlock(&its_lock);
3565 its_free_tables(its);
3567 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3572 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3576 static bool gic_rdists_supports_plpis(void)
3578 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3581 static int redist_disable_lpis(void)
3583 void __iomem *rbase = gic_data_rdist_rd_base();
3584 u64 timeout = USEC_PER_SEC;
3588 * If coming via a CPU hotplug event, we don't need to disable
3589 * LPIs before trying to re-enable them. They are already
3590 * configured and all is well in the world. Detect this case
3591 * by checking the allocation of the pending table for the
3594 if (gic_data_rdist()->pend_page)
3597 if (!gic_rdists_supports_plpis()) {
3598 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3602 val = readl_relaxed(rbase + GICR_CTLR);
3603 if (!(val & GICR_CTLR_ENABLE_LPIS))
3606 pr_warn("CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3607 smp_processor_id());
3608 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3611 val &= ~GICR_CTLR_ENABLE_LPIS;
3612 writel_relaxed(val, rbase + GICR_CTLR);
3614 /* Make sure any change to GICR_CTLR is observable by the GIC */
3618 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3619 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3620 * Error out if we time out waiting for RWP to clear.
3622 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3624 pr_err("CPU%d: Timeout while disabling LPIs\n",
3625 smp_processor_id());
3633 * After it has been written to 1, it is IMPLEMENTATION
3634 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3635 * cleared to 0. Error out if clearing the bit failed.
3637 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3638 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3645 int its_cpu_init(void)
3647 if (!list_empty(&its_nodes)) {
3650 ret = redist_disable_lpis();
3654 its_cpu_init_lpis();
3655 its_cpu_init_collections();
3661 static const struct of_device_id its_device_id[] = {
3662 { .compatible = "arm,gic-v3-its", },
3666 static int __init its_of_probe(struct device_node *node)
3668 struct device_node *np;
3669 struct resource res;
3671 for (np = of_find_matching_node(node, its_device_id); np;
3672 np = of_find_matching_node(np, its_device_id)) {
3673 if (!of_device_is_available(np))
3675 if (!of_property_read_bool(np, "msi-controller")) {
3676 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3681 if (of_address_to_resource(np, 0, &res)) {
3682 pr_warn("%pOF: no regs?\n", np);
3686 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3693 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3695 #ifdef CONFIG_ACPI_NUMA
3696 struct its_srat_map {
3703 static struct its_srat_map *its_srat_maps __initdata;
3704 static int its_in_srat __initdata;
3706 static int __init acpi_get_its_numa_node(u32 its_id)
3710 for (i = 0; i < its_in_srat; i++) {
3711 if (its_id == its_srat_maps[i].its_id)
3712 return its_srat_maps[i].numa_node;
3714 return NUMA_NO_NODE;
3717 static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header,
3718 const unsigned long end)
3723 static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header,
3724 const unsigned long end)
3727 struct acpi_srat_gic_its_affinity *its_affinity;
3729 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3733 if (its_affinity->header.length < sizeof(*its_affinity)) {
3734 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3735 its_affinity->header.length);
3739 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3741 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3742 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3746 its_srat_maps[its_in_srat].numa_node = node;
3747 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3749 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3750 its_affinity->proximity_domain, its_affinity->its_id, node);
3755 static void __init acpi_table_parse_srat_its(void)
3759 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3760 sizeof(struct acpi_table_srat),
3761 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3762 gic_acpi_match_srat_its, 0);
3766 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3768 if (!its_srat_maps) {
3769 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3773 acpi_table_parse_entries(ACPI_SIG_SRAT,
3774 sizeof(struct acpi_table_srat),
3775 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3776 gic_acpi_parse_srat_its, 0);
3779 /* free the its_srat_maps after ITS probing */
3780 static void __init acpi_its_srat_maps_free(void)
3782 kfree(its_srat_maps);
3785 static void __init acpi_table_parse_srat_its(void) { }
3786 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3787 static void __init acpi_its_srat_maps_free(void) { }
3790 static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
3791 const unsigned long end)
3793 struct acpi_madt_generic_translator *its_entry;
3794 struct fwnode_handle *dom_handle;
3795 struct resource res;
3798 its_entry = (struct acpi_madt_generic_translator *)header;
3799 memset(&res, 0, sizeof(res));
3800 res.start = its_entry->base_address;
3801 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3802 res.flags = IORESOURCE_MEM;
3804 dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
3806 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3811 err = iort_register_domain_token(its_entry->translation_id, res.start,
3814 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3815 &res.start, its_entry->translation_id);
3819 err = its_probe_one(&res, dom_handle,
3820 acpi_get_its_numa_node(its_entry->translation_id));
3824 iort_deregister_domain_token(its_entry->translation_id);
3826 irq_domain_free_fwnode(dom_handle);
3830 static void __init its_acpi_probe(void)
3832 acpi_table_parse_srat_its();
3833 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3834 gic_acpi_parse_madt_its, 0);
3835 acpi_its_srat_maps_free();
3838 static void __init its_acpi_probe(void) { }
3841 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3842 struct irq_domain *parent_domain)
3844 struct device_node *of_node;
3845 struct its_node *its;
3846 bool has_v4 = false;
3849 its_parent = parent_domain;
3850 of_node = to_of_node(handle);
3852 its_of_probe(of_node);
3856 if (list_empty(&its_nodes)) {
3857 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3861 gic_rdists = rdists;
3862 err = its_alloc_lpi_tables();
3866 list_for_each_entry(its, &its_nodes, entry)
3867 has_v4 |= its->is_v4;
3869 if (has_v4 & rdists->has_vlpis) {
3870 if (its_init_vpe_domain() ||
3871 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3872 rdists->has_vlpis = false;
3873 pr_err("ITS: Disabling GICv4 support\n");
3877 register_syscore_ops(&its_syscore_ops);