1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 #include <linux/interrupt.h>
9 #include <linux/irqchip/arm-gic.h>
11 #include "irq-gic-common.h"
13 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
15 static const struct gic_kvm_info *gic_kvm_info;
17 const struct gic_kvm_info *gic_get_kvm_info(void)
22 void gic_set_kvm_info(const struct gic_kvm_info *info)
24 BUG_ON(gic_kvm_info != NULL);
28 void gic_enable_of_quirks(const struct device_node *np,
29 const struct gic_quirk *quirks, void *data)
31 for (; quirks->desc; quirks++) {
32 if (!quirks->compatible && !quirks->property)
34 if (quirks->compatible &&
35 !of_device_is_compatible(np, quirks->compatible))
37 if (quirks->property &&
38 !of_property_read_bool(np, quirks->property))
40 if (quirks->init(data))
41 pr_info("GIC: enabling workaround for %s\n",
46 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
49 for (; quirks->desc; quirks++) {
50 if (quirks->compatible || quirks->property)
52 if (quirks->iidr != (quirks->mask & iidr))
54 if (quirks->init(data))
55 pr_info("GIC: enabling workaround for %s\n",
60 int gic_configure_irq(unsigned int irq, unsigned int type,
61 void __iomem *base, void (*sync_access)(void))
63 u32 confmask = 0x2 << ((irq % 16) * 2);
64 u32 confoff = (irq / 16) * 4;
70 * Read current configuration register, and insert the config
71 * for "irq", depending on "type".
73 raw_spin_lock_irqsave(&irq_controller_lock, flags);
74 val = oldval = readl_relaxed(base + confoff);
75 if (type & IRQ_TYPE_LEVEL_MASK)
77 else if (type & IRQ_TYPE_EDGE_BOTH)
80 /* If the current configuration is the same, then we are done */
82 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
87 * Write back the new configuration, and possibly re-enable
88 * the interrupt. If we fail to write a new configuration for
89 * an SPI then WARN and return an error. If we fail to write the
90 * configuration for a PPI this is most likely because the GIC
91 * does not allow us to set the configuration or we are in a
92 * non-secure mode, and hence it may not be catastrophic.
94 writel_relaxed(val, base + confoff);
95 if (readl_relaxed(base + confoff) != val)
98 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
106 void gic_dist_config(void __iomem *base, int gic_irqs,
107 void (*sync_access)(void))
112 * Set all global interrupts to be level triggered, active low.
114 for (i = 32; i < gic_irqs; i += 16)
115 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
116 base + GIC_DIST_CONFIG + i / 4);
119 * Set priority on all global interrupts.
121 for (i = 32; i < gic_irqs; i += 4)
122 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
125 * Deactivate and disable all SPIs. Leave the PPI and SGIs
126 * alone as they are in the redistributor registers on GICv3.
128 for (i = 32; i < gic_irqs; i += 32) {
129 writel_relaxed(GICD_INT_EN_CLR_X32,
130 base + GIC_DIST_ACTIVE_CLEAR + i / 8);
131 writel_relaxed(GICD_INT_EN_CLR_X32,
132 base + GIC_DIST_ENABLE_CLEAR + i / 8);
139 void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
144 * Deal with the banked PPI and SGI interrupts - disable all
145 * private interrupts. Make sure everything is deactivated.
147 for (i = 0; i < nr; i += 32) {
148 writel_relaxed(GICD_INT_EN_CLR_X32,
149 base + GIC_DIST_ACTIVE_CLEAR + i / 8);
150 writel_relaxed(GICD_INT_EN_CLR_X32,
151 base + GIC_DIST_ENABLE_CLEAR + i / 8);
155 * Set priority on PPI and SGI interrupts
157 for (i = 0; i < nr; i += 4)
158 writel_relaxed(GICD_INT_DEF_PRI_X4,
159 base + GIC_DIST_PRI + i * 4 / 4);