1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
5 * Copyright (C) 2014-2024 Broadcom
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/irqchip.h>
24 #include <linux/irqchip/chained_irq.h>
26 struct brcmstb_intc_init_params {
27 irq_flow_handler_t handler;
35 /* Register offsets in the L2 latched interrupt controller */
36 static const struct brcmstb_intc_init_params l2_edge_intc_init = {
37 .handler = handle_edge_irq,
40 .cpu_mask_status = 0x0c,
42 .cpu_mask_clear = 0x14
45 /* Register offsets in the L2 level interrupt controller */
46 static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
47 .handler = handle_level_irq,
49 .cpu_clear = -1, /* Register not present */
50 .cpu_mask_status = 0x04,
52 .cpu_mask_clear = 0x0C
55 /* L2 intc private data structure */
56 struct brcmstb_l2_intc_data {
57 struct irq_domain *domain;
58 struct irq_chip_generic *gc;
62 u32 saved_mask; /* for suspend/resume */
66 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
69 * Chip has separate enable/disable registers instead of a single mask
70 * register and pending interrupt is acknowledged by setting a bit.
72 * Note: This function is generic and could easily be added to the
73 * generic irqchip implementation if there ever becomes a will to do so.
74 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
76 * e.g.: https://patchwork.kernel.org/patch/9831047/
78 static void brcmstb_l2_mask_and_ack(struct irq_data *d)
80 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
81 struct irq_chip_type *ct = irq_data_get_chip_type(d);
85 irq_reg_writel(gc, mask, ct->regs.disable);
86 *ct->mask_cache &= ~mask;
87 irq_reg_writel(gc, mask, ct->regs.ack);
91 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
93 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
94 struct irq_chip *chip = irq_desc_get_chip(desc);
98 chained_irq_enter(chip, desc);
100 status = irq_reg_readl(b->gc, b->status_offset) &
101 ~(irq_reg_readl(b->gc, b->mask_offset));
104 raw_spin_lock(&desc->lock);
105 handle_bad_irq(desc);
106 raw_spin_unlock(&desc->lock);
111 irq = ffs(status) - 1;
112 status &= ~(1 << irq);
113 generic_handle_irq(irq_linear_revmap(b->domain, irq));
116 /* Don't ack parent before all device writes are done */
119 chained_irq_exit(chip, desc);
122 static void brcmstb_l2_intc_suspend(struct irq_data *d)
124 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
125 struct irq_chip_type *ct = irq_data_get_chip_type(d);
126 struct brcmstb_l2_intc_data *b = gc->private;
129 irq_gc_lock_irqsave(gc, flags);
130 /* Save the current mask */
131 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
134 /* Program the wakeup mask */
135 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
136 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
138 irq_gc_unlock_irqrestore(gc, flags);
141 static void brcmstb_l2_intc_resume(struct irq_data *d)
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
145 struct brcmstb_l2_intc_data *b = gc->private;
148 irq_gc_lock_irqsave(gc, flags);
149 if (ct->chip.irq_ack) {
150 /* Clear unmasked non-wakeup interrupts */
151 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
155 /* Restore the saved mask */
156 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
157 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
158 irq_gc_unlock_irqrestore(gc, flags);
161 static int __init brcmstb_l2_intc_of_init(struct device_node *np,
162 struct device_node *parent,
163 const struct brcmstb_intc_init_params
166 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
167 unsigned int set = 0;
168 struct brcmstb_l2_intc_data *data;
169 struct irq_chip_type *ct;
175 data = kzalloc(sizeof(*data), GFP_KERNEL);
179 base = of_iomap(np, 0);
181 pr_err("failed to remap intc L2 registers\n");
186 /* Disable all interrupts by default */
187 writel(0xffffffff, base + init_params->cpu_mask_set);
189 /* Wakeup interrupts may be retained from S5 (cold boot) */
190 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
191 if (!data->can_wake && (init_params->cpu_clear >= 0))
192 writel(0xffffffff, base + init_params->cpu_clear);
194 parent_irq = irq_of_parse_and_map(np, 0);
196 pr_err("failed to find parent interrupt\n");
201 data->domain = irq_domain_add_linear(np, 32,
202 &irq_generic_chip_ops, NULL);
208 /* MIPS chips strapped for BE will automagically configure the
209 * peripheral registers for CPU-native byte order.
212 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
213 flags |= IRQ_GC_BE_IO;
215 if (init_params->handler == handle_level_irq)
218 /* Allocate a single Generic IRQ chip for this node */
219 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
220 np->full_name, init_params->handler, clr, set, flags);
222 pr_err("failed to allocate generic irq chip\n");
223 goto out_free_domain;
226 /* Set the IRQ chaining logic */
227 irq_set_chained_handler_and_data(parent_irq,
228 brcmstb_l2_intc_irq_handle, data);
230 data->gc = irq_get_domain_generic_chip(data->domain, 0);
231 data->gc->reg_base = base;
232 data->gc->private = data;
233 data->status_offset = init_params->cpu_status;
234 data->mask_offset = init_params->cpu_mask_status;
236 ct = data->gc->chip_types;
238 if (init_params->cpu_clear >= 0) {
239 ct->regs.ack = init_params->cpu_clear;
240 ct->chip.irq_ack = irq_gc_ack_set_bit;
241 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
243 /* No Ack - but still slightly more efficient to define this */
244 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
247 ct->chip.irq_mask = irq_gc_mask_disable_reg;
248 ct->regs.disable = init_params->cpu_mask_set;
249 ct->regs.mask = init_params->cpu_mask_status;
251 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
252 ct->regs.enable = init_params->cpu_mask_clear;
254 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
255 ct->chip.irq_resume = brcmstb_l2_intc_resume;
256 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
258 if (data->can_wake) {
259 /* This IRQ chip can wake the system, set all child interrupts
260 * in wake_enabled mask
262 data->gc->wake_enabled = 0xffffffff;
263 ct->chip.irq_set_wake = irq_gc_set_wake;
264 enable_irq_wake(parent_irq);
267 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
272 irq_domain_remove(data->domain);
280 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
281 struct device_node *parent)
283 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
285 IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
286 IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
287 brcmstb_l2_edge_intc_of_init);
288 IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc",
289 brcmstb_l2_edge_intc_of_init);
291 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
292 struct device_node *parent)
294 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
296 IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
297 brcmstb_l2_lvl_intc_of_init);