drivers/irqchip/irq-bcm6345-l1.c

   1 /*
   2  * Broadcom BCM6345 style Level 1 interrupt controller driver
   3  *
   4  * Copyright (C) 2014 Broadcom Corporation
   5  * Copyright 2015 Simon Arlott
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This is based on the BCM7038 (which supports SMP) but with a single
  12  * enable register instead of separate mask/set/clear registers.
  13  *
  14  * The BCM3380 has a similar mask/status register layout, but each pair
  15  * of words is at separate locations (and SMP is not supported).
  16  *
  17  * ENABLE/STATUS words are packed next to each other for each CPU:
  18  *
  19  * BCM6368:
  20  *   0x1000_0020: CPU0_W0_ENABLE
  21  *   0x1000_0024: CPU0_W1_ENABLE
  22  *   0x1000_0028: CPU0_W0_STATUS                IRQs 31-63
  23  *   0x1000_002c: CPU0_W1_STATUS                IRQs 0-31
  24  *   0x1000_0030: CPU1_W0_ENABLE
  25  *   0x1000_0034: CPU1_W1_ENABLE
  26  *   0x1000_0038: CPU1_W0_STATUS                IRQs 31-63
  27  *   0x1000_003c: CPU1_W1_STATUS                IRQs 0-31
  28  *
  29  * BCM63168:
  30  *   0x1000_0020: CPU0_W0_ENABLE
  31  *   0x1000_0024: CPU0_W1_ENABLE
  32  *   0x1000_0028: CPU0_W2_ENABLE
  33  *   0x1000_002c: CPU0_W3_ENABLE
  34  *   0x1000_0030: CPU0_W0_STATUS        IRQs 96-127
  35  *   0x1000_0034: CPU0_W1_STATUS        IRQs 64-95
  36  *   0x1000_0038: CPU0_W2_STATUS        IRQs 32-63
  37  *   0x1000_003c: CPU0_W3_STATUS        IRQs 0-31
  38  *   0x1000_0040: CPU1_W0_ENABLE
  39  *   0x1000_0044: CPU1_W1_ENABLE
  40  *   0x1000_0048: CPU1_W2_ENABLE
  41  *   0x1000_004c: CPU1_W3_ENABLE
  42  *   0x1000_0050: CPU1_W0_STATUS        IRQs 96-127
  43  *   0x1000_0054: CPU1_W1_STATUS        IRQs 64-95
  44  *   0x1000_0058: CPU1_W2_STATUS        IRQs 32-63
  45  *   0x1000_005c: CPU1_W3_STATUS        IRQs 0-31
  46  *
  47  * IRQs are numbered in CPU native endian order
  48  * (which is big-endian in these examples)
  49  */
  50
  51 #define pr_fmt(fmt)     KBUILD_MODNAME  ": " fmt
  52
  53 #include <linux/bitops.h>
  54 #include <linux/cpumask.h>
  55 #include <linux/kernel.h>
  56 #include <linux/init.h>
  57 #include <linux/interrupt.h>
  58 #include <linux/io.h>
  59 #include <linux/ioport.h>
  60 #include <linux/irq.h>
  61 #include <linux/irqdomain.h>
  62 #include <linux/module.h>
  63 #include <linux/of.h>
  64 #include <linux/of_irq.h>
  65 #include <linux/of_address.h>
  66 #include <linux/of_platform.h>
  67 #include <linux/platform_device.h>
  68 #include <linux/slab.h>
  69 #include <linux/smp.h>
  70 #include <linux/types.h>
  71 #include <linux/irqchip.h>
  72 #include <linux/irqchip/chained_irq.h>
  73
  74 #define IRQS_PER_WORD           32
  75 #define REG_BYTES_PER_IRQ_WORD  (sizeof(u32) * 2)
  76
  77 struct bcm6345_l1_cpu;
  78
  79 struct bcm6345_l1_chip {
  80         raw_spinlock_t          lock;
  81         unsigned int            n_words;
  82         struct irq_domain       *domain;
  83         struct cpumask          cpumask;
  84         struct bcm6345_l1_cpu   *cpus[NR_CPUS];
  85 };
  86
  87 struct bcm6345_l1_cpu {
  88         struct bcm6345_l1_chip  *intc;
  89         void __iomem            *map_base;
  90         unsigned int            parent_irq;
  91         u32                     enable_cache[];
  92 };
  93
  94 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
  95                                            unsigned int word)
  96 {
  97 #ifdef __BIG_ENDIAN
  98         return (1 * intc->n_words - word - 1) * sizeof(u32);
  99 #else
 100         return (0 * intc->n_words + word) * sizeof(u32);
 101 #endif
 102 }
 103
 104 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
 105                                       unsigned int word)
 106 {
 107 #ifdef __BIG_ENDIAN
 108         return (2 * intc->n_words - word - 1) * sizeof(u32);
 109 #else
 110         return (1 * intc->n_words + word) * sizeof(u32);
 111 #endif
 112 }
 113
 114 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
 115                                         struct irq_data *d)
 116 {
 117         return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
 118 }
 119
 120 static void bcm6345_l1_irq_handle(struct irq_desc *desc)
 121 {
 122         struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc);
 123         struct bcm6345_l1_chip *intc = cpu->intc;
 124         struct irq_chip *chip = irq_desc_get_chip(desc);
 125         unsigned int idx;
 126
 127         chained_irq_enter(chip, desc);
 128
 129         for (idx = 0; idx < intc->n_words; idx++) {
 130                 int base = idx * IRQS_PER_WORD;
 131                 unsigned long pending;
 132                 irq_hw_number_t hwirq;
 133                 unsigned int irq;
 134
 135                 pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
 136                 pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
 137
 138                 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
 139                         irq = irq_linear_revmap(intc->domain, base + hwirq);
 140                         if (irq)
 141                                 generic_handle_irq(irq);
 142                         else
 143                                 spurious_interrupt();
 144                 }
 145         }
 146
 147         chained_irq_exit(chip, desc);
 148 }
 149
 150 static inline void __bcm6345_l1_unmask(struct irq_data *d)
 151 {
 152         struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 153         u32 word = d->hwirq / IRQS_PER_WORD;
 154         u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
 155         unsigned int cpu_idx = cpu_for_irq(intc, d);
 156
 157         intc->cpus[cpu_idx]->enable_cache[word] |= mask;
 158         __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
 159                 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
 160 }
 161
 162 static inline void __bcm6345_l1_mask(struct irq_data *d)
 163 {
 164         struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 165         u32 word = d->hwirq / IRQS_PER_WORD;
 166         u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
 167         unsigned int cpu_idx = cpu_for_irq(intc, d);
 168
 169         intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
 170         __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
 171                 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
 172 }
 173
 174 static void bcm6345_l1_unmask(struct irq_data *d)
 175 {
 176         struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 177         unsigned long flags;
 178
 179         raw_spin_lock_irqsave(&intc->lock, flags);
 180         __bcm6345_l1_unmask(d);
 181         raw_spin_unlock_irqrestore(&intc->lock, flags);
 182 }
 183
 184 static void bcm6345_l1_mask(struct irq_data *d)
 185 {
 186         struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 187         unsigned long flags;
 188
 189         raw_spin_lock_irqsave(&intc->lock, flags);
 190         __bcm6345_l1_mask(d);
 191         raw_spin_unlock_irqrestore(&intc->lock, flags);
 192 }
 193
 194 static int bcm6345_l1_set_affinity(struct irq_data *d,
 195                                    const struct cpumask *dest,
 196                                    bool force)
 197 {
 198         struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 199         u32 word = d->hwirq / IRQS_PER_WORD;
 200         u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
 201         unsigned int old_cpu = cpu_for_irq(intc, d);
 202         unsigned int new_cpu;
 203         struct cpumask valid;
 204         unsigned long flags;
 205         bool enabled;
 206
 207         if (!cpumask_and(&valid, &intc->cpumask, dest))
 208                 return -EINVAL;
 209
 210         new_cpu = cpumask_any_and(&valid, cpu_online_mask);
 211         if (new_cpu >= nr_cpu_ids)
 212                 return -EINVAL;
 213
 214         dest = cpumask_of(new_cpu);
 215
 216         raw_spin_lock_irqsave(&intc->lock, flags);
 217         if (old_cpu != new_cpu) {
 218                 enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
 219                 if (enabled)
 220                         __bcm6345_l1_mask(d);
 221                 cpumask_copy(irq_data_get_affinity_mask(d), dest);
 222                 if (enabled)
 223                         __bcm6345_l1_unmask(d);
 224         } else {
 225                 cpumask_copy(irq_data_get_affinity_mask(d), dest);
 226         }
 227         raw_spin_unlock_irqrestore(&intc->lock, flags);
 228
 229         irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
 230
 231         return IRQ_SET_MASK_OK_NOCOPY;
 232 }
 233
 234 static int __init bcm6345_l1_init_one(struct device_node *dn,
 235                                       unsigned int idx,
 236                                       struct bcm6345_l1_chip *intc)
 237 {
 238         struct resource res;
 239         resource_size_t sz;
 240         struct bcm6345_l1_cpu *cpu;
 241         unsigned int i, n_words;
 242
 243         if (of_address_to_resource(dn, idx, &res))
 244                 return -EINVAL;
 245         sz = resource_size(&res);
 246         n_words = sz / REG_BYTES_PER_IRQ_WORD;
 247
 248         if (!intc->n_words)
 249                 intc->n_words = n_words;
 250         else if (intc->n_words != n_words)
 251                 return -EINVAL;
 252
 253         cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
 254                                         GFP_KERNEL);
 255         if (!cpu)
 256                 return -ENOMEM;
 257
 258         cpu->intc = intc;
 259         cpu->map_base = ioremap(res.start, sz);
 260         if (!cpu->map_base)
 261                 return -ENOMEM;
 262
 263         for (i = 0; i < n_words; i++) {
 264                 cpu->enable_cache[i] = 0;
 265                 __raw_writel(0, cpu->map_base + reg_enable(intc, i));
 266         }
 267
 268         cpu->parent_irq = irq_of_parse_and_map(dn, idx);
 269         if (!cpu->parent_irq) {
 270                 pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
 271                 return -EINVAL;
 272         }
 273         irq_set_chained_handler_and_data(cpu->parent_irq,
 274                                                 bcm6345_l1_irq_handle, cpu);
 275
 276         return 0;
 277 }
 278
 279 static struct irq_chip bcm6345_l1_irq_chip = {
 280         .name                   = "bcm6345-l1",
 281         .irq_mask               = bcm6345_l1_mask,
 282         .irq_unmask             = bcm6345_l1_unmask,
 283         .irq_set_affinity       = bcm6345_l1_set_affinity,
 284 };
 285
 286 static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
 287                           irq_hw_number_t hw_irq)
 288 {
 289         irq_set_chip_and_handler(virq,
 290                 &bcm6345_l1_irq_chip, handle_percpu_irq);
 291         irq_set_chip_data(virq, d->host_data);
 292         irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 293         return 0;
 294 }
 295
 296 static const struct irq_domain_ops bcm6345_l1_domain_ops = {
 297         .xlate                  = irq_domain_xlate_onecell,
 298         .map                    = bcm6345_l1_map,
 299 };
 300
 301 static int __init bcm6345_l1_of_init(struct device_node *dn,
 302                               struct device_node *parent)
 303 {
 304         struct bcm6345_l1_chip *intc;
 305         unsigned int idx;
 306         int ret;
 307
 308         intc = kzalloc(sizeof(*intc), GFP_KERNEL);
 309         if (!intc)
 310                 return -ENOMEM;
 311
 312         for_each_possible_cpu(idx) {
 313                 ret = bcm6345_l1_init_one(dn, idx, intc);
 314                 if (ret)
 315                         pr_err("failed to init intc L1 for cpu %d: %d\n",
 316                                 idx, ret);
 317                 else
 318                         cpumask_set_cpu(idx, &intc->cpumask);
 319         }
 320
 321         if (!cpumask_weight(&intc->cpumask)) {
 322                 ret = -ENODEV;
 323                 goto out_free;
 324         }
 325
 326         raw_spin_lock_init(&intc->lock);
 327
 328         intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
 329                                              &bcm6345_l1_domain_ops,
 330                                              intc);
 331         if (!intc->domain) {
 332                 ret = -ENOMEM;
 333                 goto out_unmap;
 334         }
 335
 336         pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
 337                         IRQS_PER_WORD * intc->n_words);
 338         for_each_cpu(idx, &intc->cpumask) {
 339                 struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
 340
 341                 pr_info("  CPU%u at MMIO 0x%p (irq = %d)\n", idx,
 342                                 cpu->map_base, cpu->parent_irq);
 343         }
 344
 345         return 0;
 346
 347 out_unmap:
 348         for_each_possible_cpu(idx) {
 349                 struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
 350
 351                 if (cpu) {
 352                         if (cpu->map_base)
 353                                 iounmap(cpu->map_base);
 354                         kfree(cpu);
 355                 }
 356         }
 357 out_free:
 358         kfree(intc);
 359         return ret;
 360 }
 361
 362 IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);