1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM6345 style Level 1 interrupt controller driver
5 * Copyright (C) 2014 Broadcom Corporation
6 * Copyright 2015 Simon Arlott
8 * This is based on the BCM7038 (which supports SMP) but with a single
9 * enable register instead of separate mask/set/clear registers.
11 * The BCM3380 has a similar mask/status register layout, but each pair
12 * of words is at separate locations (and SMP is not supported).
14 * ENABLE/STATUS words are packed next to each other for each CPU:
17 * 0x1000_0020: CPU0_W0_ENABLE
18 * 0x1000_0024: CPU0_W1_ENABLE
19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
21 * 0x1000_0030: CPU1_W0_ENABLE
22 * 0x1000_0034: CPU1_W1_ENABLE
23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
27 * 0x1000_0020: CPU0_W0_ENABLE
28 * 0x1000_0024: CPU0_W1_ENABLE
29 * 0x1000_0028: CPU0_W2_ENABLE
30 * 0x1000_002c: CPU0_W3_ENABLE
31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
35 * 0x1000_0040: CPU1_W0_ENABLE
36 * 0x1000_0044: CPU1_W1_ENABLE
37 * 0x1000_0048: CPU1_W2_ENABLE
38 * 0x1000_004c: CPU1_W3_ENABLE
39 * 0x1000_0050: CPU1_W0_STATUS IRQs 96-127
40 * 0x1000_0054: CPU1_W1_STATUS IRQs 64-95
41 * 0x1000_0058: CPU1_W2_STATUS IRQs 32-63
42 * 0x1000_005c: CPU1_W3_STATUS IRQs 0-31
44 * IRQs are numbered in CPU native endian order
45 * (which is big-endian in these examples)
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/bitops.h>
51 #include <linux/cpumask.h>
52 #include <linux/kernel.h>
53 #include <linux/init.h>
54 #include <linux/interrupt.h>
56 #include <linux/ioport.h>
57 #include <linux/irq.h>
58 #include <linux/irqdomain.h>
59 #include <linux/module.h>
61 #include <linux/of_irq.h>
62 #include <linux/of_address.h>
63 #include <linux/of_platform.h>
64 #include <linux/platform_device.h>
65 #include <linux/slab.h>
66 #include <linux/smp.h>
67 #include <linux/types.h>
68 #include <linux/irqchip.h>
69 #include <linux/irqchip/chained_irq.h>
71 #define IRQS_PER_WORD 32
72 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2)
74 struct bcm6345_l1_cpu;
76 struct bcm6345_l1_chip {
79 struct irq_domain *domain;
80 struct cpumask cpumask;
81 struct bcm6345_l1_cpu *cpus[NR_CPUS];
84 struct bcm6345_l1_cpu {
85 struct bcm6345_l1_chip *intc;
86 void __iomem *map_base;
87 unsigned int parent_irq;
91 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
95 return (1 * intc->n_words - word - 1) * sizeof(u32);
97 return (0 * intc->n_words + word) * sizeof(u32);
101 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
105 return (2 * intc->n_words - word - 1) * sizeof(u32);
107 return (1 * intc->n_words + word) * sizeof(u32);
111 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
114 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
117 static void bcm6345_l1_irq_handle(struct irq_desc *desc)
119 struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc);
120 struct bcm6345_l1_chip *intc = cpu->intc;
121 struct irq_chip *chip = irq_desc_get_chip(desc);
124 chained_irq_enter(chip, desc);
126 for (idx = 0; idx < intc->n_words; idx++) {
127 int base = idx * IRQS_PER_WORD;
128 unsigned long pending;
129 irq_hw_number_t hwirq;
132 pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
133 pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
135 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
136 irq = irq_linear_revmap(intc->domain, base + hwirq);
138 generic_handle_irq(irq);
140 spurious_interrupt();
144 chained_irq_exit(chip, desc);
147 static inline void __bcm6345_l1_unmask(struct irq_data *d)
149 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
150 u32 word = d->hwirq / IRQS_PER_WORD;
151 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
152 unsigned int cpu_idx = cpu_for_irq(intc, d);
154 intc->cpus[cpu_idx]->enable_cache[word] |= mask;
155 __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
156 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
159 static inline void __bcm6345_l1_mask(struct irq_data *d)
161 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
162 u32 word = d->hwirq / IRQS_PER_WORD;
163 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
164 unsigned int cpu_idx = cpu_for_irq(intc, d);
166 intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
167 __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
168 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
171 static void bcm6345_l1_unmask(struct irq_data *d)
173 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
176 raw_spin_lock_irqsave(&intc->lock, flags);
177 __bcm6345_l1_unmask(d);
178 raw_spin_unlock_irqrestore(&intc->lock, flags);
181 static void bcm6345_l1_mask(struct irq_data *d)
183 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
186 raw_spin_lock_irqsave(&intc->lock, flags);
187 __bcm6345_l1_mask(d);
188 raw_spin_unlock_irqrestore(&intc->lock, flags);
191 static int bcm6345_l1_set_affinity(struct irq_data *d,
192 const struct cpumask *dest,
195 struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
196 u32 word = d->hwirq / IRQS_PER_WORD;
197 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
198 unsigned int old_cpu = cpu_for_irq(intc, d);
199 unsigned int new_cpu;
200 struct cpumask valid;
204 if (!cpumask_and(&valid, &intc->cpumask, dest))
207 new_cpu = cpumask_any_and(&valid, cpu_online_mask);
208 if (new_cpu >= nr_cpu_ids)
211 dest = cpumask_of(new_cpu);
213 raw_spin_lock_irqsave(&intc->lock, flags);
214 if (old_cpu != new_cpu) {
215 enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
217 __bcm6345_l1_mask(d);
218 cpumask_copy(irq_data_get_affinity_mask(d), dest);
220 __bcm6345_l1_unmask(d);
222 cpumask_copy(irq_data_get_affinity_mask(d), dest);
224 raw_spin_unlock_irqrestore(&intc->lock, flags);
226 irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
228 return IRQ_SET_MASK_OK_NOCOPY;
231 static int __init bcm6345_l1_init_one(struct device_node *dn,
233 struct bcm6345_l1_chip *intc)
237 struct bcm6345_l1_cpu *cpu;
238 unsigned int i, n_words;
240 if (of_address_to_resource(dn, idx, &res))
242 sz = resource_size(&res);
243 n_words = sz / REG_BYTES_PER_IRQ_WORD;
246 intc->n_words = n_words;
247 else if (intc->n_words != n_words)
250 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
256 cpu->map_base = ioremap(res.start, sz);
260 for (i = 0; i < n_words; i++) {
261 cpu->enable_cache[i] = 0;
262 __raw_writel(0, cpu->map_base + reg_enable(intc, i));
265 cpu->parent_irq = irq_of_parse_and_map(dn, idx);
266 if (!cpu->parent_irq) {
267 pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
270 irq_set_chained_handler_and_data(cpu->parent_irq,
271 bcm6345_l1_irq_handle, cpu);
276 static struct irq_chip bcm6345_l1_irq_chip = {
277 .name = "bcm6345-l1",
278 .irq_mask = bcm6345_l1_mask,
279 .irq_unmask = bcm6345_l1_unmask,
280 .irq_set_affinity = bcm6345_l1_set_affinity,
283 static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
284 irq_hw_number_t hw_irq)
286 irq_set_chip_and_handler(virq,
287 &bcm6345_l1_irq_chip, handle_percpu_irq);
288 irq_set_chip_data(virq, d->host_data);
289 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
293 static const struct irq_domain_ops bcm6345_l1_domain_ops = {
294 .xlate = irq_domain_xlate_onecell,
295 .map = bcm6345_l1_map,
298 static int __init bcm6345_l1_of_init(struct device_node *dn,
299 struct device_node *parent)
301 struct bcm6345_l1_chip *intc;
305 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
309 for_each_possible_cpu(idx) {
310 ret = bcm6345_l1_init_one(dn, idx, intc);
312 pr_err("failed to init intc L1 for cpu %d: %d\n",
315 cpumask_set_cpu(idx, &intc->cpumask);
318 if (!cpumask_weight(&intc->cpumask)) {
323 raw_spin_lock_init(&intc->lock);
325 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
326 &bcm6345_l1_domain_ops,
333 pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
334 IRQS_PER_WORD * intc->n_words);
335 for_each_cpu(idx, &intc->cpumask) {
336 struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
338 pr_info(" CPU%u at MMIO 0x%p (irq = %d)\n", idx,
339 cpu->map_base, cpu->parent_irq);
345 for_each_possible_cpu(idx) {
346 struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
350 iounmap(cpu->map_base);
359 IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);