2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/cpu.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/irqdomain.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/msi.h>
32 #include <asm/mach/arch.h>
33 #include <asm/exception.h>
34 #include <asm/smp_plat.h>
35 #include <asm/mach/irq.h>
37 /* Interrupt Controller Registers Map */
38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
41 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
43 #define ARMADA_370_XP_INT_CONTROL (0x00)
44 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
45 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
46 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
47 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
48 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
50 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
51 #define ARMADA_375_PPI_CAUSE (0x10)
53 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
54 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
55 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
57 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
59 #define IPI_DOORBELL_START (0)
60 #define IPI_DOORBELL_END (8)
61 #define IPI_DOORBELL_MASK 0xFF
62 #define PCI_MSI_DOORBELL_START (16)
63 #define PCI_MSI_DOORBELL_NR (16)
64 #define PCI_MSI_DOORBELL_END (32)
65 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
67 static void __iomem *per_cpu_int_base;
68 static void __iomem *main_int_base;
69 static struct irq_domain *armada_370_xp_mpic_domain;
70 static u32 doorbell_mask_reg;
71 static int parent_irq;
73 static struct irq_domain *armada_370_xp_msi_domain;
74 static struct irq_domain *armada_370_xp_msi_inner_domain;
75 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
76 static DEFINE_MUTEX(msi_used_lock);
77 static phys_addr_t msi_doorbell_addr;
80 static inline bool is_percpu_irq(irq_hw_number_t irq)
82 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
90 * For shared global interrupts, mask/unmask global enable bit
91 * For CPU interrupts, mask/unmask the calling CPU's bit
93 static void armada_370_xp_irq_mask(struct irq_data *d)
95 irq_hw_number_t hwirq = irqd_to_hwirq(d);
97 if (!is_percpu_irq(hwirq))
98 writel(hwirq, main_int_base +
99 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
101 writel(hwirq, per_cpu_int_base +
102 ARMADA_370_XP_INT_SET_MASK_OFFS);
105 static void armada_370_xp_irq_unmask(struct irq_data *d)
107 irq_hw_number_t hwirq = irqd_to_hwirq(d);
109 if (!is_percpu_irq(hwirq))
110 writel(hwirq, main_int_base +
111 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
113 writel(hwirq, per_cpu_int_base +
114 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
117 #ifdef CONFIG_PCI_MSI
119 static struct irq_chip armada_370_xp_msi_irq_chip = {
121 .irq_mask = pci_msi_mask_irq,
122 .irq_unmask = pci_msi_unmask_irq,
125 static struct msi_domain_info armada_370_xp_msi_domain_info = {
126 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
127 MSI_FLAG_MULTI_PCI_MSI),
128 .chip = &armada_370_xp_msi_irq_chip,
131 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
133 msg->address_lo = lower_32_bits(msi_doorbell_addr);
134 msg->address_hi = upper_32_bits(msi_doorbell_addr);
135 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
138 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
139 const struct cpumask *mask, bool force)
144 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
146 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
147 .irq_set_affinity = armada_370_xp_msi_set_affinity,
150 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
151 unsigned int nr_irqs, void *args)
155 mutex_lock(&msi_used_lock);
156 hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR,
157 order_base_2(nr_irqs));
158 mutex_unlock(&msi_used_lock);
163 for (i = 0; i < nr_irqs; i++) {
164 irq_domain_set_info(domain, virq + i, hwirq + i,
165 &armada_370_xp_msi_bottom_irq_chip,
166 domain->host_data, handle_simple_irq,
173 static void armada_370_xp_msi_free(struct irq_domain *domain,
174 unsigned int virq, unsigned int nr_irqs)
176 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
178 mutex_lock(&msi_used_lock);
179 bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));
180 mutex_unlock(&msi_used_lock);
183 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
184 .alloc = armada_370_xp_msi_alloc,
185 .free = armada_370_xp_msi_free,
188 static int armada_370_xp_msi_init(struct device_node *node,
189 phys_addr_t main_int_phys_base)
193 msi_doorbell_addr = main_int_phys_base +
194 ARMADA_370_XP_SW_TRIG_INT_OFFS;
196 armada_370_xp_msi_inner_domain =
197 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
198 &armada_370_xp_msi_domain_ops, NULL);
199 if (!armada_370_xp_msi_inner_domain)
202 armada_370_xp_msi_domain =
203 pci_msi_create_irq_domain(of_node_to_fwnode(node),
204 &armada_370_xp_msi_domain_info,
205 armada_370_xp_msi_inner_domain);
206 if (!armada_370_xp_msi_domain) {
207 irq_domain_remove(armada_370_xp_msi_inner_domain);
211 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
212 | PCI_MSI_DOORBELL_MASK;
214 writel(reg, per_cpu_int_base +
215 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
217 /* Unmask IPI interrupt */
218 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
223 static inline int armada_370_xp_msi_init(struct device_node *node,
224 phys_addr_t main_int_phys_base)
231 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
233 static int armada_xp_set_affinity(struct irq_data *d,
234 const struct cpumask *mask_val, bool force)
236 irq_hw_number_t hwirq = irqd_to_hwirq(d);
237 unsigned long reg, mask;
240 /* Select a single core from the affinity mask which is online */
241 cpu = cpumask_any_and(mask_val, cpu_online_mask);
242 mask = 1UL << cpu_logical_map(cpu);
244 raw_spin_lock(&irq_controller_lock);
245 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
246 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
247 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
248 raw_spin_unlock(&irq_controller_lock);
250 return IRQ_SET_MASK_OK;
254 static struct irq_chip armada_370_xp_irq_chip = {
256 .irq_mask = armada_370_xp_irq_mask,
257 .irq_mask_ack = armada_370_xp_irq_mask,
258 .irq_unmask = armada_370_xp_irq_unmask,
260 .irq_set_affinity = armada_xp_set_affinity,
262 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
265 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
266 unsigned int virq, irq_hw_number_t hw)
268 armada_370_xp_irq_mask(irq_get_irq_data(virq));
269 if (!is_percpu_irq(hw))
270 writel(hw, per_cpu_int_base +
271 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
273 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
274 irq_set_status_flags(virq, IRQ_LEVEL);
276 if (is_percpu_irq(hw)) {
277 irq_set_percpu_devid(virq);
278 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
279 handle_percpu_devid_irq);
282 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
286 irq_clear_status_flags(virq, IRQ_NOAUTOEN);
291 static void armada_xp_mpic_smp_cpu_init(void)
296 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
297 nr_irqs = (control >> 2) & 0x3ff;
299 for (i = 0; i < nr_irqs; i++)
300 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
302 /* Clear pending IPIs */
303 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
305 /* Enable first 8 IPIs */
306 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
307 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
309 /* Unmask IPI interrupt */
310 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
313 static void armada_xp_mpic_perf_init(void)
315 unsigned long cpuid = cpu_logical_map(smp_processor_id());
317 /* Enable Performance Counter Overflow interrupts */
318 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
319 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
323 static void armada_mpic_send_doorbell(const struct cpumask *mask,
327 unsigned long map = 0;
329 /* Convert our logical CPU mask into a physical one. */
330 for_each_cpu(cpu, mask)
331 map |= 1 << cpu_logical_map(cpu);
334 * Ensure that stores to Normal memory are visible to the
335 * other CPUs before issuing the IPI.
340 writel((map << 8) | irq, main_int_base +
341 ARMADA_370_XP_SW_TRIG_INT_OFFS);
344 static int armada_xp_mpic_starting_cpu(unsigned int cpu)
346 armada_xp_mpic_perf_init();
347 armada_xp_mpic_smp_cpu_init();
351 static int mpic_cascaded_starting_cpu(unsigned int cpu)
353 armada_xp_mpic_perf_init();
354 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
359 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
360 .map = armada_370_xp_mpic_irq_map,
361 .xlate = irq_domain_xlate_onecell,
364 #ifdef CONFIG_PCI_MSI
365 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
369 msimask = readl_relaxed(per_cpu_int_base +
370 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
371 & PCI_MSI_DOORBELL_MASK;
373 writel(~msimask, per_cpu_int_base +
374 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
376 for (msinr = PCI_MSI_DOORBELL_START;
377 msinr < PCI_MSI_DOORBELL_END; msinr++) {
380 if (!(msimask & BIT(msinr)))
384 irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
385 msinr - PCI_MSI_DOORBELL_START);
386 generic_handle_irq(irq);
388 irq = msinr - PCI_MSI_DOORBELL_START;
389 handle_domain_irq(armada_370_xp_msi_inner_domain,
395 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
398 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
400 struct irq_chip *chip = irq_desc_get_chip(desc);
401 unsigned long irqmap, irqn, irqsrc, cpuid;
402 unsigned int cascade_irq;
404 chained_irq_enter(chip, desc);
406 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
407 cpuid = cpu_logical_map(smp_processor_id());
409 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
410 irqsrc = readl_relaxed(main_int_base +
411 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
413 /* Check if the interrupt is not masked on current CPU.
414 * Test IRQ (0-1) and FIQ (8-9) mask bits.
416 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
420 armada_370_xp_handle_msi_irq(NULL, true);
424 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
425 generic_handle_irq(cascade_irq);
428 chained_irq_exit(chip, desc);
431 static void __exception_irq_entry
432 armada_370_xp_handle_irq(struct pt_regs *regs)
437 irqstat = readl_relaxed(per_cpu_int_base +
438 ARMADA_370_XP_CPU_INTACK_OFFS);
439 irqnr = irqstat & 0x3FF;
445 handle_domain_irq(armada_370_xp_mpic_domain,
452 armada_370_xp_handle_msi_irq(regs, false);
459 ipimask = readl_relaxed(per_cpu_int_base +
460 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
463 writel(~ipimask, per_cpu_int_base +
464 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
466 /* Handle all pending doorbells */
467 for (ipinr = IPI_DOORBELL_START;
468 ipinr < IPI_DOORBELL_END; ipinr++) {
469 if (ipimask & (0x1 << ipinr))
470 handle_IPI(ipinr, regs);
479 static int armada_370_xp_mpic_suspend(void)
481 doorbell_mask_reg = readl(per_cpu_int_base +
482 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
486 static void armada_370_xp_mpic_resume(void)
491 /* Re-enable interrupts */
492 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
493 for (irq = 0; irq < nirqs; irq++) {
494 struct irq_data *data;
497 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
501 if (!is_percpu_irq(irq))
502 writel(irq, per_cpu_int_base +
503 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
505 writel(irq, main_int_base +
506 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
508 data = irq_get_irq_data(virq);
509 if (!irqd_irq_disabled(data))
510 armada_370_xp_irq_unmask(data);
513 /* Reconfigure doorbells for IPIs and MSIs */
514 writel(doorbell_mask_reg,
515 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
516 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
517 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
518 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
519 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
522 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
523 .suspend = armada_370_xp_mpic_suspend,
524 .resume = armada_370_xp_mpic_resume,
527 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
528 struct device_node *parent)
530 struct resource main_int_res, per_cpu_int_res;
534 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
535 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
537 BUG_ON(!request_mem_region(main_int_res.start,
538 resource_size(&main_int_res),
540 BUG_ON(!request_mem_region(per_cpu_int_res.start,
541 resource_size(&per_cpu_int_res),
544 main_int_base = ioremap(main_int_res.start,
545 resource_size(&main_int_res));
546 BUG_ON(!main_int_base);
548 per_cpu_int_base = ioremap(per_cpu_int_res.start,
549 resource_size(&per_cpu_int_res));
550 BUG_ON(!per_cpu_int_base);
552 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
553 nr_irqs = (control >> 2) & 0x3ff;
555 for (i = 0; i < nr_irqs; i++)
556 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
558 armada_370_xp_mpic_domain =
559 irq_domain_add_linear(node, nr_irqs,
560 &armada_370_xp_mpic_irq_ops, NULL);
561 BUG_ON(!armada_370_xp_mpic_domain);
562 armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED;
564 /* Setup for the boot CPU */
565 armada_xp_mpic_perf_init();
566 armada_xp_mpic_smp_cpu_init();
568 armada_370_xp_msi_init(node, main_int_res.start);
570 parent_irq = irq_of_parse_and_map(node, 0);
571 if (parent_irq <= 0) {
572 irq_set_default_host(armada_370_xp_mpic_domain);
573 set_handle_irq(armada_370_xp_handle_irq);
575 set_smp_cross_call(armada_mpic_send_doorbell);
576 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
577 "AP_IRQ_ARMADA_XP_STARTING",
578 armada_xp_mpic_starting_cpu, NULL);
582 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING,
583 "AP_IRQ_ARMADA_CASC_STARTING",
584 mpic_cascaded_starting_cpu, NULL);
586 irq_set_chained_handler(parent_irq,
587 armada_370_xp_mpic_handle_cascade_irq);
590 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
595 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);