drivers/irqchip/irq-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370 and Armada XP SoC IRQ handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/irqchip/chained_irq.h>
  23 #include <linux/cpu.h>
  24 #include <linux/io.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_pci.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/slab.h>
  30 #include <linux/syscore_ops.h>
  31 #include <linux/msi.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/exception.h>
  34 #include <asm/smp_plat.h>
  35 #include <asm/mach/irq.h>
  36
  37 /* Interrupt Controller Registers Map */
  38 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
  39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
  40 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS      (0x54)
  41 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)       (1 << cpu)
  42
  43 #define ARMADA_370_XP_INT_CONTROL               (0x00)
  44 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
  45 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
  46 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)       (0x100 + irq*4)
  47 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK       0xF
  48 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)   ((BIT(0) | BIT(8)) << cpuid)
  49
  50 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
  51 #define ARMADA_375_PPI_CAUSE                    (0x10)
  52
  53 #define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
  54 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
  55 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
  56
  57 #define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
  58
  59 #define IPI_DOORBELL_START                      (0)
  60 #define IPI_DOORBELL_END                        (8)
  61 #define IPI_DOORBELL_MASK                       0xFF
  62 #define PCI_MSI_DOORBELL_START                  (16)
  63 #define PCI_MSI_DOORBELL_NR                     (16)
  64 #define PCI_MSI_DOORBELL_END                    (32)
  65 #define PCI_MSI_DOORBELL_MASK                   0xFFFF0000
  66
  67 static void __iomem *per_cpu_int_base;
  68 static void __iomem *main_int_base;
  69 static struct irq_domain *armada_370_xp_mpic_domain;
  70 static u32 doorbell_mask_reg;
  71 static int parent_irq;
  72 #ifdef CONFIG_PCI_MSI
  73 static struct irq_domain *armada_370_xp_msi_domain;
  74 static struct irq_domain *armada_370_xp_msi_inner_domain;
  75 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
  76 static DEFINE_MUTEX(msi_used_lock);
  77 static phys_addr_t msi_doorbell_addr;
  78 #endif
  79
  80 static inline bool is_percpu_irq(irq_hw_number_t irq)
  81 {
  82         if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
  83                 return true;
  84
  85         return false;
  86 }
  87
  88 /*
  89  * In SMP mode:
  90  * For shared global interrupts, mask/unmask global enable bit
  91  * For CPU interrupts, mask/unmask the calling CPU's bit
  92  */
  93 static void armada_370_xp_irq_mask(struct irq_data *d)
  94 {
  95         irq_hw_number_t hwirq = irqd_to_hwirq(d);
  96
  97         if (!is_percpu_irq(hwirq))
  98                 writel(hwirq, main_int_base +
  99                                 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
 100         else
 101                 writel(hwirq, per_cpu_int_base +
 102                                 ARMADA_370_XP_INT_SET_MASK_OFFS);
 103 }
 104
 105 static void armada_370_xp_irq_unmask(struct irq_data *d)
 106 {
 107         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 108
 109         if (!is_percpu_irq(hwirq))
 110                 writel(hwirq, main_int_base +
 111                                 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 112         else
 113                 writel(hwirq, per_cpu_int_base +
 114                                 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 115 }
 116
 117 #ifdef CONFIG_PCI_MSI
 118
 119 static struct irq_chip armada_370_xp_msi_irq_chip = {
 120         .name = "MPIC MSI",
 121         .irq_mask = pci_msi_mask_irq,
 122         .irq_unmask = pci_msi_unmask_irq,
 123 };
 124
 125 static struct msi_domain_info armada_370_xp_msi_domain_info = {
 126         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 127                    MSI_FLAG_MULTI_PCI_MSI),
 128         .chip   = &armada_370_xp_msi_irq_chip,
 129 };
 130
 131 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 132 {
 133         msg->address_lo = lower_32_bits(msi_doorbell_addr);
 134         msg->address_hi = upper_32_bits(msi_doorbell_addr);
 135         msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
 136 }
 137
 138 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
 139                                           const struct cpumask *mask, bool force)
 140 {
 141          return -EINVAL;
 142 }
 143
 144 static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
 145         .name                   = "MPIC MSI",
 146         .irq_compose_msi_msg    = armada_370_xp_compose_msi_msg,
 147         .irq_set_affinity       = armada_370_xp_msi_set_affinity,
 148 };
 149
 150 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 151                                    unsigned int nr_irqs, void *args)
 152 {
 153         int hwirq, i;
 154
 155         mutex_lock(&msi_used_lock);
 156         hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR,
 157                                         order_base_2(nr_irqs));
 158         mutex_unlock(&msi_used_lock);
 159
 160         if (hwirq < 0)
 161                 return -ENOSPC;
 162
 163         for (i = 0; i < nr_irqs; i++) {
 164                 irq_domain_set_info(domain, virq + i, hwirq + i,
 165                                     &armada_370_xp_msi_bottom_irq_chip,
 166                                     domain->host_data, handle_simple_irq,
 167                                     NULL, NULL);
 168         }
 169
 170         return 0;
 171 }
 172
 173 static void armada_370_xp_msi_free(struct irq_domain *domain,
 174                                    unsigned int virq, unsigned int nr_irqs)
 175 {
 176         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 177
 178         mutex_lock(&msi_used_lock);
 179         bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));
 180         mutex_unlock(&msi_used_lock);
 181 }
 182
 183 static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
 184         .alloc  = armada_370_xp_msi_alloc,
 185         .free   = armada_370_xp_msi_free,
 186 };
 187
 188 static int armada_370_xp_msi_init(struct device_node *node,
 189                                   phys_addr_t main_int_phys_base)
 190 {
 191         u32 reg;
 192
 193         msi_doorbell_addr = main_int_phys_base +
 194                 ARMADA_370_XP_SW_TRIG_INT_OFFS;
 195
 196         armada_370_xp_msi_inner_domain =
 197                 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
 198                                       &armada_370_xp_msi_domain_ops, NULL);
 199         if (!armada_370_xp_msi_inner_domain)
 200                 return -ENOMEM;
 201
 202         armada_370_xp_msi_domain =
 203                 pci_msi_create_irq_domain(of_node_to_fwnode(node),
 204                                           &armada_370_xp_msi_domain_info,
 205                                           armada_370_xp_msi_inner_domain);
 206         if (!armada_370_xp_msi_domain) {
 207                 irq_domain_remove(armada_370_xp_msi_inner_domain);
 208                 return -ENOMEM;
 209         }
 210
 211         reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
 212                 | PCI_MSI_DOORBELL_MASK;
 213
 214         writel(reg, per_cpu_int_base +
 215                ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 216
 217         /* Unmask IPI interrupt */
 218         writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 219
 220         return 0;
 221 }
 222 #else
 223 static inline int armada_370_xp_msi_init(struct device_node *node,
 224                                          phys_addr_t main_int_phys_base)
 225 {
 226         return 0;
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_SMP
 231 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 232
 233 static int armada_xp_set_affinity(struct irq_data *d,
 234                                   const struct cpumask *mask_val, bool force)
 235 {
 236         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 237         unsigned long reg, mask;
 238         int cpu;
 239
 240         /* Select a single core from the affinity mask which is online */
 241         cpu = cpumask_any_and(mask_val, cpu_online_mask);
 242         mask = 1UL << cpu_logical_map(cpu);
 243
 244         raw_spin_lock(&irq_controller_lock);
 245         reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 246         reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
 247         writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
 248         raw_spin_unlock(&irq_controller_lock);
 249
 250         return IRQ_SET_MASK_OK;
 251 }
 252 #endif
 253
 254 static struct irq_chip armada_370_xp_irq_chip = {
 255         .name           = "MPIC",
 256         .irq_mask       = armada_370_xp_irq_mask,
 257         .irq_mask_ack   = armada_370_xp_irq_mask,
 258         .irq_unmask     = armada_370_xp_irq_unmask,
 259 #ifdef CONFIG_SMP
 260         .irq_set_affinity = armada_xp_set_affinity,
 261 #endif
 262         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
 263 };
 264
 265 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 266                                       unsigned int virq, irq_hw_number_t hw)
 267 {
 268         armada_370_xp_irq_mask(irq_get_irq_data(virq));
 269         if (!is_percpu_irq(hw))
 270                 writel(hw, per_cpu_int_base +
 271                         ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 272         else
 273                 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 274         irq_set_status_flags(virq, IRQ_LEVEL);
 275
 276         if (is_percpu_irq(hw)) {
 277                 irq_set_percpu_devid(virq);
 278                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 279                                         handle_percpu_devid_irq);
 280
 281         } else {
 282                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
 283                                         handle_level_irq);
 284         }
 285         irq_set_probe(virq);
 286         irq_clear_status_flags(virq, IRQ_NOAUTOEN);
 287
 288         return 0;
 289 }
 290
 291 static void armada_xp_mpic_smp_cpu_init(void)
 292 {
 293         u32 control;
 294         int nr_irqs, i;
 295
 296         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 297         nr_irqs = (control >> 2) & 0x3ff;
 298
 299         for (i = 0; i < nr_irqs; i++)
 300                 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
 301
 302         /* Clear pending IPIs */
 303         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 304
 305         /* Enable first 8 IPIs */
 306         writel(IPI_DOORBELL_MASK, per_cpu_int_base +
 307                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 308
 309         /* Unmask IPI interrupt */
 310         writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 311 }
 312
 313 static void armada_xp_mpic_perf_init(void)
 314 {
 315         unsigned long cpuid;
 316
 317         /*
 318          * This Performance Counter Overflow interrupt is specific for
 319          * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
 320          */
 321         if (!of_machine_is_compatible("marvell,armada-370-xp"))
 322                 return;
 323
 324         cpuid = cpu_logical_map(smp_processor_id());
 325
 326         /* Enable Performance Counter Overflow interrupts */
 327         writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
 328                per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
 329 }
 330
 331 #ifdef CONFIG_SMP
 332 static void armada_mpic_send_doorbell(const struct cpumask *mask,
 333                                       unsigned int irq)
 334 {
 335         int cpu;
 336         unsigned long map = 0;
 337
 338         /* Convert our logical CPU mask into a physical one. */
 339         for_each_cpu(cpu, mask)
 340                 map |= 1 << cpu_logical_map(cpu);
 341
 342         /*
 343          * Ensure that stores to Normal memory are visible to the
 344          * other CPUs before issuing the IPI.
 345          */
 346         dsb();
 347
 348         /* submit softirq */
 349         writel((map << 8) | irq, main_int_base +
 350                 ARMADA_370_XP_SW_TRIG_INT_OFFS);
 351 }
 352
 353 static int armada_xp_mpic_starting_cpu(unsigned int cpu)
 354 {
 355         armada_xp_mpic_perf_init();
 356         armada_xp_mpic_smp_cpu_init();
 357         return 0;
 358 }
 359
 360 static int mpic_cascaded_starting_cpu(unsigned int cpu)
 361 {
 362         armada_xp_mpic_perf_init();
 363         enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
 364         return 0;
 365 }
 366 #endif
 367
 368 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 369         .map = armada_370_xp_mpic_irq_map,
 370         .xlate = irq_domain_xlate_onecell,
 371 };
 372
 373 #ifdef CONFIG_PCI_MSI
 374 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 375 {
 376         u32 msimask, msinr;
 377
 378         msimask = readl_relaxed(per_cpu_int_base +
 379                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 380                 & PCI_MSI_DOORBELL_MASK;
 381
 382         writel(~msimask, per_cpu_int_base +
 383                ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 384
 385         for (msinr = PCI_MSI_DOORBELL_START;
 386              msinr < PCI_MSI_DOORBELL_END; msinr++) {
 387                 int irq;
 388
 389                 if (!(msimask & BIT(msinr)))
 390                         continue;
 391
 392                 if (is_chained) {
 393                         irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
 394                                                msinr - PCI_MSI_DOORBELL_START);
 395                         generic_handle_irq(irq);
 396                 } else {
 397                         irq = msinr - PCI_MSI_DOORBELL_START;
 398                         handle_domain_irq(armada_370_xp_msi_inner_domain,
 399                                           irq, regs);
 400                 }
 401         }
 402 }
 403 #else
 404 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
 405 #endif
 406
 407 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
 408 {
 409         struct irq_chip *chip = irq_desc_get_chip(desc);
 410         unsigned long irqmap, irqn, irqsrc, cpuid;
 411         unsigned int cascade_irq;
 412
 413         chained_irq_enter(chip, desc);
 414
 415         irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
 416         cpuid = cpu_logical_map(smp_processor_id());
 417
 418         for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
 419                 irqsrc = readl_relaxed(main_int_base +
 420                                        ARMADA_370_XP_INT_SOURCE_CTL(irqn));
 421
 422                 /* Check if the interrupt is not masked on current CPU.
 423                  * Test IRQ (0-1) and FIQ (8-9) mask bits.
 424                  */
 425                 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
 426                         continue;
 427
 428                 if (irqn == 1) {
 429                         armada_370_xp_handle_msi_irq(NULL, true);
 430                         continue;
 431                 }
 432
 433                 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
 434                 generic_handle_irq(cascade_irq);
 435         }
 436
 437         chained_irq_exit(chip, desc);
 438 }
 439
 440 static void __exception_irq_entry
 441 armada_370_xp_handle_irq(struct pt_regs *regs)
 442 {
 443         u32 irqstat, irqnr;
 444
 445         do {
 446                 irqstat = readl_relaxed(per_cpu_int_base +
 447                                         ARMADA_370_XP_CPU_INTACK_OFFS);
 448                 irqnr = irqstat & 0x3FF;
 449
 450                 if (irqnr > 1022)
 451                         break;
 452
 453                 if (irqnr > 1) {
 454                         handle_domain_irq(armada_370_xp_mpic_domain,
 455                                           irqnr, regs);
 456                         continue;
 457                 }
 458
 459                 /* MSI handling */
 460                 if (irqnr == 1)
 461                         armada_370_xp_handle_msi_irq(regs, false);
 462
 463 #ifdef CONFIG_SMP
 464                 /* IPI Handling */
 465                 if (irqnr == 0) {
 466                         u32 ipimask, ipinr;
 467
 468                         ipimask = readl_relaxed(per_cpu_int_base +
 469                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 470                                 & IPI_DOORBELL_MASK;
 471
 472                         writel(~ipimask, per_cpu_int_base +
 473                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 474
 475                         /* Handle all pending doorbells */
 476                         for (ipinr = IPI_DOORBELL_START;
 477                              ipinr < IPI_DOORBELL_END; ipinr++) {
 478                                 if (ipimask & (0x1 << ipinr))
 479                                         handle_IPI(ipinr, regs);
 480                         }
 481                         continue;
 482                 }
 483 #endif
 484
 485         } while (1);
 486 }
 487
 488 static int armada_370_xp_mpic_suspend(void)
 489 {
 490         doorbell_mask_reg = readl(per_cpu_int_base +
 491                                   ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 492         return 0;
 493 }
 494
 495 static void armada_370_xp_mpic_resume(void)
 496 {
 497         int nirqs;
 498         irq_hw_number_t irq;
 499
 500         /* Re-enable interrupts */
 501         nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
 502         for (irq = 0; irq < nirqs; irq++) {
 503                 struct irq_data *data;
 504                 int virq;
 505
 506                 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
 507                 if (virq == 0)
 508                         continue;
 509
 510                 if (!is_percpu_irq(irq))
 511                         writel(irq, per_cpu_int_base +
 512                                ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 513                 else
 514                         writel(irq, main_int_base +
 515                                ARMADA_370_XP_INT_SET_ENABLE_OFFS);
 516
 517                 data = irq_get_irq_data(virq);
 518                 if (!irqd_irq_disabled(data))
 519                         armada_370_xp_irq_unmask(data);
 520         }
 521
 522         /* Reconfigure doorbells for IPIs and MSIs */
 523         writel(doorbell_mask_reg,
 524                per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 525         if (doorbell_mask_reg & IPI_DOORBELL_MASK)
 526                 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 527         if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
 528                 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 529 }
 530
 531 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
 532         .suspend        = armada_370_xp_mpic_suspend,
 533         .resume         = armada_370_xp_mpic_resume,
 534 };
 535
 536 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 537                                              struct device_node *parent)
 538 {
 539         struct resource main_int_res, per_cpu_int_res;
 540         int nr_irqs, i;
 541         u32 control;
 542
 543         BUG_ON(of_address_to_resource(node, 0, &main_int_res));
 544         BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
 545
 546         BUG_ON(!request_mem_region(main_int_res.start,
 547                                    resource_size(&main_int_res),
 548                                    node->full_name));
 549         BUG_ON(!request_mem_region(per_cpu_int_res.start,
 550                                    resource_size(&per_cpu_int_res),
 551                                    node->full_name));
 552
 553         main_int_base = ioremap(main_int_res.start,
 554                                 resource_size(&main_int_res));
 555         BUG_ON(!main_int_base);
 556
 557         per_cpu_int_base = ioremap(per_cpu_int_res.start,
 558                                    resource_size(&per_cpu_int_res));
 559         BUG_ON(!per_cpu_int_base);
 560
 561         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 562         nr_irqs = (control >> 2) & 0x3ff;
 563
 564         for (i = 0; i < nr_irqs; i++)
 565                 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
 566
 567         armada_370_xp_mpic_domain =
 568                 irq_domain_add_linear(node, nr_irqs,
 569                                 &armada_370_xp_mpic_irq_ops, NULL);
 570         BUG_ON(!armada_370_xp_mpic_domain);
 571         armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED;
 572
 573         /* Setup for the boot CPU */
 574         armada_xp_mpic_perf_init();
 575         armada_xp_mpic_smp_cpu_init();
 576
 577         armada_370_xp_msi_init(node, main_int_res.start);
 578
 579         parent_irq = irq_of_parse_and_map(node, 0);
 580         if (parent_irq <= 0) {
 581                 irq_set_default_host(armada_370_xp_mpic_domain);
 582                 set_handle_irq(armada_370_xp_handle_irq);
 583 #ifdef CONFIG_SMP
 584                 set_smp_cross_call(armada_mpic_send_doorbell);
 585                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
 586                                           "AP_IRQ_ARMADA_XP_STARTING",
 587                                           armada_xp_mpic_starting_cpu, NULL);
 588 #endif
 589         } else {
 590 #ifdef CONFIG_SMP
 591                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING,
 592                                           "AP_IRQ_ARMADA_CASC_STARTING",
 593                                           mpic_cascaded_starting_cpu, NULL);
 594 #endif
 595                 irq_set_chained_handler(parent_irq,
 596                                         armada_370_xp_mpic_handle_cascade_irq);
 597         }
 598
 599         register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
 600
 601         return 0;
 602 }
 603
 604 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);