2 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/bitops.h>
10 #include <linux/debugfs.h>
11 #include <linux/err.h>
12 #include <linux/iommu.h>
13 #include <linux/kernel.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <soc/tegra/ahb.h>
20 #include <soc/tegra/mc.h>
27 const struct tegra_smmu_soc *soc;
29 unsigned long pfn_mask;
30 unsigned long tlb_mask;
35 struct list_head list;
37 struct dentry *debugfs;
40 struct tegra_smmu_as {
41 struct iommu_domain domain;
42 struct tegra_smmu *smmu;
43 unsigned int use_count;
52 static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
54 return container_of(dom, struct tegra_smmu_as, domain);
57 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
60 writel(value, smmu->regs + offset);
63 static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
65 return readl(smmu->regs + offset);
68 #define SMMU_CONFIG 0x010
69 #define SMMU_CONFIG_ENABLE (1 << 0)
71 #define SMMU_TLB_CONFIG 0x14
72 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
73 #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
74 #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \
75 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
77 #define SMMU_PTC_CONFIG 0x18
78 #define SMMU_PTC_CONFIG_ENABLE (1 << 29)
79 #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
80 #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
82 #define SMMU_PTB_ASID 0x01c
83 #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
85 #define SMMU_PTB_DATA 0x020
86 #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
88 #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
90 #define SMMU_TLB_FLUSH 0x030
91 #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
92 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
93 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
94 #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
95 SMMU_TLB_FLUSH_VA_MATCH_SECTION)
96 #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
97 SMMU_TLB_FLUSH_VA_MATCH_GROUP)
98 #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
100 #define SMMU_PTC_FLUSH 0x034
101 #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
102 #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
104 #define SMMU_PTC_FLUSH_HI 0x9b8
105 #define SMMU_PTC_FLUSH_HI_MASK 0x3
107 /* per-SWGROUP SMMU_*_ASID register */
108 #define SMMU_ASID_ENABLE (1 << 31)
109 #define SMMU_ASID_MASK 0x7f
110 #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
112 /* page table definitions */
113 #define SMMU_NUM_PDE 1024
114 #define SMMU_NUM_PTE 1024
116 #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
117 #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
119 #define SMMU_PDE_SHIFT 22
120 #define SMMU_PTE_SHIFT 12
122 #define SMMU_PD_READABLE (1 << 31)
123 #define SMMU_PD_WRITABLE (1 << 30)
124 #define SMMU_PD_NONSECURE (1 << 29)
126 #define SMMU_PDE_READABLE (1 << 31)
127 #define SMMU_PDE_WRITABLE (1 << 30)
128 #define SMMU_PDE_NONSECURE (1 << 29)
129 #define SMMU_PDE_NEXT (1 << 28)
131 #define SMMU_PTE_READABLE (1 << 31)
132 #define SMMU_PTE_WRITABLE (1 << 30)
133 #define SMMU_PTE_NONSECURE (1 << 29)
135 #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
137 #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
140 static unsigned int iova_pd_index(unsigned long iova)
142 return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1);
145 static unsigned int iova_pt_index(unsigned long iova)
147 return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1);
150 static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
153 return (addr & smmu->pfn_mask) == addr;
156 static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde)
158 return (dma_addr_t)(pde & smmu->pfn_mask) << 12;
161 static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
163 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
166 static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma,
167 unsigned long offset)
171 offset &= ~(smmu->mc->soc->atom_size - 1);
173 if (smmu->mc->soc->num_address_bits > 32) {
174 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
175 value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
179 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
182 value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
183 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
186 static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
188 smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
191 static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
196 if (smmu->soc->num_asids == 4)
197 value = (asid & 0x3) << 29;
199 value = (asid & 0x7f) << 24;
201 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
202 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
205 static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
211 if (smmu->soc->num_asids == 4)
212 value = (asid & 0x3) << 29;
214 value = (asid & 0x7f) << 24;
216 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
217 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
220 static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
226 if (smmu->soc->num_asids == 4)
227 value = (asid & 0x3) << 29;
229 value = (asid & 0x7f) << 24;
231 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
232 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
235 static inline void smmu_flush(struct tegra_smmu *smmu)
237 smmu_readl(smmu, SMMU_CONFIG);
240 static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
244 mutex_lock(&smmu->lock);
246 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
247 if (id >= smmu->soc->num_asids) {
248 mutex_unlock(&smmu->lock);
252 set_bit(id, smmu->asids);
255 mutex_unlock(&smmu->lock);
259 static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
261 mutex_lock(&smmu->lock);
262 clear_bit(id, smmu->asids);
263 mutex_unlock(&smmu->lock);
266 static bool tegra_smmu_capable(enum iommu_cap cap)
271 static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
273 struct tegra_smmu_as *as;
275 if (type != IOMMU_DOMAIN_UNMANAGED)
278 as = kzalloc(sizeof(*as), GFP_KERNEL);
282 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
284 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
290 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL);
297 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL);
306 as->domain.geometry.aperture_start = 0;
307 as->domain.geometry.aperture_end = 0xffffffff;
308 as->domain.geometry.force_aperture = true;
313 static void tegra_smmu_domain_free(struct iommu_domain *domain)
315 struct tegra_smmu_as *as = to_smmu_as(domain);
317 /* TODO: free page directory and page tables */
322 static const struct tegra_smmu_swgroup *
323 tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
325 const struct tegra_smmu_swgroup *group = NULL;
328 for (i = 0; i < smmu->soc->num_swgroups; i++) {
329 if (smmu->soc->swgroups[i].swgroup == swgroup) {
330 group = &smmu->soc->swgroups[i];
338 static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
341 const struct tegra_smmu_swgroup *group;
345 for (i = 0; i < smmu->soc->num_clients; i++) {
346 const struct tegra_mc_client *client = &smmu->soc->clients[i];
348 if (client->swgroup != swgroup)
351 value = smmu_readl(smmu, client->smmu.reg);
352 value |= BIT(client->smmu.bit);
353 smmu_writel(smmu, value, client->smmu.reg);
356 group = tegra_smmu_find_swgroup(smmu, swgroup);
358 value = smmu_readl(smmu, group->reg);
359 value &= ~SMMU_ASID_MASK;
360 value |= SMMU_ASID_VALUE(asid);
361 value |= SMMU_ASID_ENABLE;
362 smmu_writel(smmu, value, group->reg);
366 static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
369 const struct tegra_smmu_swgroup *group;
373 group = tegra_smmu_find_swgroup(smmu, swgroup);
375 value = smmu_readl(smmu, group->reg);
376 value &= ~SMMU_ASID_MASK;
377 value |= SMMU_ASID_VALUE(asid);
378 value &= ~SMMU_ASID_ENABLE;
379 smmu_writel(smmu, value, group->reg);
382 for (i = 0; i < smmu->soc->num_clients; i++) {
383 const struct tegra_mc_client *client = &smmu->soc->clients[i];
385 if (client->swgroup != swgroup)
388 value = smmu_readl(smmu, client->smmu.reg);
389 value &= ~BIT(client->smmu.bit);
390 smmu_writel(smmu, value, client->smmu.reg);
394 static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
395 struct tegra_smmu_as *as)
400 if (as->use_count > 0) {
405 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
407 if (dma_mapping_error(smmu->dev, as->pd_dma))
410 /* We can't handle 64-bit DMA addresses */
411 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
416 err = tegra_smmu_alloc_asid(smmu, &as->id);
420 smmu_flush_ptc(smmu, as->pd_dma, 0);
421 smmu_flush_tlb_asid(smmu, as->id);
423 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
424 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
425 smmu_writel(smmu, value, SMMU_PTB_DATA);
434 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
438 static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
439 struct tegra_smmu_as *as)
441 if (--as->use_count > 0)
444 tegra_smmu_free_asid(smmu, as->id);
446 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
451 static int tegra_smmu_attach_dev(struct iommu_domain *domain,
454 struct tegra_smmu *smmu = dev->archdata.iommu;
455 struct tegra_smmu_as *as = to_smmu_as(domain);
456 struct device_node *np = dev->of_node;
457 struct of_phandle_args args;
458 unsigned int index = 0;
461 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
463 unsigned int swgroup = args.args[0];
465 if (args.np != smmu->dev->of_node) {
466 of_node_put(args.np);
470 of_node_put(args.np);
472 err = tegra_smmu_as_prepare(smmu, as);
476 tegra_smmu_enable(smmu, swgroup, as->id);
486 static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
488 struct tegra_smmu_as *as = to_smmu_as(domain);
489 struct device_node *np = dev->of_node;
490 struct tegra_smmu *smmu = as->smmu;
491 struct of_phandle_args args;
492 unsigned int index = 0;
494 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
496 unsigned int swgroup = args.args[0];
498 if (args.np != smmu->dev->of_node) {
499 of_node_put(args.np);
503 of_node_put(args.np);
505 tegra_smmu_disable(smmu, swgroup, as->id);
506 tegra_smmu_as_unprepare(smmu, as);
511 static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova,
514 unsigned int pd_index = iova_pd_index(iova);
515 struct tegra_smmu *smmu = as->smmu;
516 u32 *pd = page_address(as->pd);
517 unsigned long offset = pd_index * sizeof(*pd);
519 /* Set the page directory entry first */
520 pd[pd_index] = value;
522 /* The flush the page directory entry from caches */
523 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
524 sizeof(*pd), DMA_TO_DEVICE);
526 /* And flush the iommu */
527 smmu_flush_ptc(smmu, as->pd_dma, offset);
528 smmu_flush_tlb_section(smmu, as->id, iova);
532 static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova)
534 u32 *pt = page_address(pt_page);
536 return pt + iova_pt_index(iova);
539 static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
542 unsigned int pd_index = iova_pd_index(iova);
543 struct tegra_smmu *smmu = as->smmu;
544 struct page *pt_page;
547 pt_page = as->pts[pd_index];
551 pd = page_address(as->pd);
552 *dmap = smmu_pde_to_dma(smmu, pd[pd_index]);
554 return tegra_smmu_pte_offset(pt_page, iova);
557 static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
560 unsigned int pde = iova_pd_index(iova);
561 struct tegra_smmu *smmu = as->smmu;
567 page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
571 dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT,
573 if (dma_mapping_error(smmu->dev, dma)) {
578 if (!smmu_dma_addr_valid(smmu, dma)) {
579 dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT,
587 tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR |
592 u32 *pd = page_address(as->pd);
594 *dmap = smmu_pde_to_dma(smmu, pd[pde]);
597 return tegra_smmu_pte_offset(as->pts[pde], iova);
600 static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova)
602 unsigned int pd_index = iova_pd_index(iova);
604 as->count[pd_index]++;
607 static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
609 unsigned int pde = iova_pd_index(iova);
610 struct page *page = as->pts[pde];
613 * When no entries in this page table are used anymore, return the
614 * memory page to the system.
616 if (--as->count[pde] == 0) {
617 struct tegra_smmu *smmu = as->smmu;
618 u32 *pd = page_address(as->pd);
619 dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]);
621 tegra_smmu_set_pde(as, iova, 0);
623 dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE);
629 static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
630 u32 *pte, dma_addr_t pte_dma, u32 val)
632 struct tegra_smmu *smmu = as->smmu;
633 unsigned long offset = offset_in_page(pte);
637 dma_sync_single_range_for_device(smmu->dev, pte_dma, offset,
639 smmu_flush_ptc(smmu, pte_dma, offset);
640 smmu_flush_tlb_group(smmu, as->id, iova);
644 static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
645 phys_addr_t paddr, size_t size, int prot)
647 struct tegra_smmu_as *as = to_smmu_as(domain);
651 pte = as_get_pte(as, iova, &pte_dma);
655 /* If we aren't overwriting a pre-existing entry, increment use */
657 tegra_smmu_pte_get_use(as, iova);
659 tegra_smmu_set_pte(as, iova, pte, pte_dma,
660 __phys_to_pfn(paddr) | SMMU_PTE_ATTR);
665 static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
668 struct tegra_smmu_as *as = to_smmu_as(domain);
672 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
676 tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
677 tegra_smmu_pte_put_use(as, iova);
682 static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
685 struct tegra_smmu_as *as = to_smmu_as(domain);
690 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
694 pfn = *pte & as->smmu->pfn_mask;
696 return PFN_PHYS(pfn);
699 static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
701 struct platform_device *pdev;
704 pdev = of_find_device_by_node(np);
708 mc = platform_get_drvdata(pdev);
715 static int tegra_smmu_add_device(struct device *dev)
717 struct device_node *np = dev->of_node;
718 struct of_phandle_args args;
719 unsigned int index = 0;
721 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
723 struct tegra_smmu *smmu;
725 smmu = tegra_smmu_find(args.np);
728 * Only a single IOMMU master interface is currently
729 * supported by the Linux kernel, so abort after the
732 dev->archdata.iommu = smmu;
742 static void tegra_smmu_remove_device(struct device *dev)
744 dev->archdata.iommu = NULL;
747 static const struct iommu_ops tegra_smmu_ops = {
748 .capable = tegra_smmu_capable,
749 .domain_alloc = tegra_smmu_domain_alloc,
750 .domain_free = tegra_smmu_domain_free,
751 .attach_dev = tegra_smmu_attach_dev,
752 .detach_dev = tegra_smmu_detach_dev,
753 .add_device = tegra_smmu_add_device,
754 .remove_device = tegra_smmu_remove_device,
755 .map = tegra_smmu_map,
756 .unmap = tegra_smmu_unmap,
757 .map_sg = default_iommu_map_sg,
758 .iova_to_phys = tegra_smmu_iova_to_phys,
760 .pgsize_bitmap = SZ_4K,
763 static void tegra_smmu_ahb_enable(void)
765 static const struct of_device_id ahb_match[] = {
766 { .compatible = "nvidia,tegra30-ahb", },
769 struct device_node *ahb;
771 ahb = of_find_matching_node(NULL, ahb_match);
773 tegra_ahb_enable_smmu(ahb);
778 static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
780 struct tegra_smmu *smmu = s->private;
784 seq_printf(s, "swgroup enabled ASID\n");
785 seq_printf(s, "------------------------\n");
787 for (i = 0; i < smmu->soc->num_swgroups; i++) {
788 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
792 value = smmu_readl(smmu, group->reg);
794 if (value & SMMU_ASID_ENABLE)
799 asid = value & SMMU_ASID_MASK;
801 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
808 static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file)
810 return single_open(file, tegra_smmu_swgroups_show, inode->i_private);
813 static const struct file_operations tegra_smmu_swgroups_fops = {
814 .open = tegra_smmu_swgroups_open,
817 .release = single_release,
820 static int tegra_smmu_clients_show(struct seq_file *s, void *data)
822 struct tegra_smmu *smmu = s->private;
826 seq_printf(s, "client enabled\n");
827 seq_printf(s, "--------------------\n");
829 for (i = 0; i < smmu->soc->num_clients; i++) {
830 const struct tegra_mc_client *client = &smmu->soc->clients[i];
833 value = smmu_readl(smmu, client->smmu.reg);
835 if (value & BIT(client->smmu.bit))
840 seq_printf(s, "%-12s %s\n", client->name, status);
846 static int tegra_smmu_clients_open(struct inode *inode, struct file *file)
848 return single_open(file, tegra_smmu_clients_show, inode->i_private);
851 static const struct file_operations tegra_smmu_clients_fops = {
852 .open = tegra_smmu_clients_open,
855 .release = single_release,
858 static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
860 smmu->debugfs = debugfs_create_dir("smmu", NULL);
864 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
865 &tegra_smmu_swgroups_fops);
866 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
867 &tegra_smmu_clients_fops);
870 static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
872 debugfs_remove_recursive(smmu->debugfs);
875 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
876 const struct tegra_smmu_soc *soc,
879 struct tegra_smmu *smmu;
884 /* This can happen on Tegra20 which doesn't have an SMMU */
888 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
890 return ERR_PTR(-ENOMEM);
893 * This is a bit of a hack. Ideally we'd want to simply return this
894 * value. However the IOMMU registration process will attempt to add
895 * all devices to the IOMMU when bus_set_iommu() is called. In order
896 * not to rely on global variables to track the IOMMU instance, we
897 * set it here so that it can be looked up from the .add_device()
898 * callback via the IOMMU device's .drvdata field.
902 size = BITS_TO_LONGS(soc->num_asids) * sizeof(long);
904 smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL);
906 return ERR_PTR(-ENOMEM);
908 mutex_init(&smmu->lock);
910 smmu->regs = mc->regs;
915 smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
916 dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
917 mc->soc->num_address_bits, smmu->pfn_mask);
918 smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1;
919 dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
922 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
924 if (soc->supports_request_limit)
925 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
927 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
929 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
930 SMMU_TLB_CONFIG_ACTIVE_LINES(smmu);
932 if (soc->supports_round_robin_arbitration)
933 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
935 smmu_writel(smmu, value, SMMU_TLB_CONFIG);
937 smmu_flush_ptc_all(smmu);
938 smmu_flush_tlb(smmu);
939 smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
942 tegra_smmu_ahb_enable();
944 err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
948 if (IS_ENABLED(CONFIG_DEBUG_FS))
949 tegra_smmu_debugfs_init(smmu);
954 void tegra_smmu_remove(struct tegra_smmu *smmu)
956 if (IS_ENABLED(CONFIG_DEBUG_FS))
957 tegra_smmu_debugfs_exit(smmu);