2 * IOMMU API for GART in Tegra20
4 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #define pr_fmt(fmt) "%s(): " fmt, __func__
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
28 #include <linux/list.h>
29 #include <linux/device.h>
31 #include <linux/iommu.h>
34 #include <asm/cacheflush.h>
36 /* bitmap of the page sizes currently supported */
37 #define GART_IOMMU_PGSIZES (SZ_4K)
39 #define GART_REG_BASE 0x24
40 #define GART_CONFIG (0x24 - GART_REG_BASE)
41 #define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
42 #define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
43 #define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
45 #define GART_PAGE_SHIFT 12
46 #define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
47 #define GART_PAGE_MASK \
48 (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
52 struct list_head list;
58 u32 page_count; /* total remappable size */
59 dma_addr_t iovmm_base; /* offset to vmm_area */
60 spinlock_t pte_lock; /* for pagetable */
61 struct list_head client;
62 spinlock_t client_lock; /* for client list */
65 struct iommu_device iommu; /* IOMMU Core handle */
69 struct iommu_domain domain; /* generic domain handle */
70 struct gart_device *gart; /* link to gart device */
73 static struct gart_device *gart_handle; /* unique for a system */
75 static bool gart_debug;
77 #define GART_PTE(_pfn) \
78 (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
80 static struct gart_domain *to_gart_domain(struct iommu_domain *dom)
82 return container_of(dom, struct gart_domain, domain);
86 * Any interaction between any block on PPSB and a block on APB or AHB
87 * must have these read-back to ensure the APB/AHB bus transaction is
88 * complete before initiating activity on the PPSB block.
90 #define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG))
92 #define for_each_gart_pte(gart, iova) \
93 for (iova = gart->iovmm_base; \
94 iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
95 iova += GART_PAGE_SIZE)
97 static inline void gart_set_pte(struct gart_device *gart,
98 unsigned long offs, u32 pte)
100 writel(offs, gart->regs + GART_ENTRY_ADDR);
101 writel(pte, gart->regs + GART_ENTRY_DATA);
103 dev_dbg(gart->dev, "%s %08lx:%08x\n",
104 pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
107 static inline unsigned long gart_read_pte(struct gart_device *gart,
112 writel(offs, gart->regs + GART_ENTRY_ADDR);
113 pte = readl(gart->regs + GART_ENTRY_DATA);
118 static void do_gart_setup(struct gart_device *gart, const u32 *data)
122 for_each_gart_pte(gart, iova)
123 gart_set_pte(gart, iova, data ? *(data++) : 0);
125 writel(1, gart->regs + GART_CONFIG);
126 FLUSH_GART_REGS(gart);
130 static void gart_dump_table(struct gart_device *gart)
135 spin_lock_irqsave(&gart->pte_lock, flags);
136 for_each_gart_pte(gart, iova) {
139 pte = gart_read_pte(gart, iova);
141 dev_dbg(gart->dev, "%s %08lx:%08lx\n",
142 (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
143 iova, pte & GART_PAGE_MASK);
145 spin_unlock_irqrestore(&gart->pte_lock, flags);
148 static inline void gart_dump_table(struct gart_device *gart)
153 static inline bool gart_iova_range_valid(struct gart_device *gart,
154 unsigned long iova, size_t bytes)
156 unsigned long iova_start, iova_end, gart_start, gart_end;
159 iova_end = iova_start + bytes - 1;
160 gart_start = gart->iovmm_base;
161 gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
163 if (iova_start < gart_start)
165 if (iova_end > gart_end)
170 static int gart_iommu_attach_dev(struct iommu_domain *domain,
173 struct gart_domain *gart_domain = to_gart_domain(domain);
174 struct gart_device *gart = gart_domain->gart;
175 struct gart_client *client, *c;
178 client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL);
183 spin_lock(&gart->client_lock);
184 list_for_each_entry(c, &gart->client, list) {
187 "%s is already attached\n", dev_name(dev));
192 list_add(&client->list, &gart->client);
193 spin_unlock(&gart->client_lock);
194 dev_dbg(gart->dev, "Attached %s\n", dev_name(dev));
198 devm_kfree(gart->dev, client);
199 spin_unlock(&gart->client_lock);
203 static void gart_iommu_detach_dev(struct iommu_domain *domain,
206 struct gart_domain *gart_domain = to_gart_domain(domain);
207 struct gart_device *gart = gart_domain->gart;
208 struct gart_client *c;
210 spin_lock(&gart->client_lock);
212 list_for_each_entry(c, &gart->client, list) {
215 devm_kfree(gart->dev, c);
216 dev_dbg(gart->dev, "Detached %s\n", dev_name(dev));
220 dev_err(gart->dev, "Couldn't find\n");
222 spin_unlock(&gart->client_lock);
225 static struct iommu_domain *gart_iommu_domain_alloc(unsigned type)
227 struct gart_domain *gart_domain;
228 struct gart_device *gart;
230 if (type != IOMMU_DOMAIN_UNMANAGED)
237 gart_domain = kzalloc(sizeof(*gart_domain), GFP_KERNEL);
241 gart_domain->gart = gart;
242 gart_domain->domain.geometry.aperture_start = gart->iovmm_base;
243 gart_domain->domain.geometry.aperture_end = gart->iovmm_base +
244 gart->page_count * GART_PAGE_SIZE - 1;
245 gart_domain->domain.geometry.force_aperture = true;
247 return &gart_domain->domain;
250 static void gart_iommu_domain_free(struct iommu_domain *domain)
252 struct gart_domain *gart_domain = to_gart_domain(domain);
253 struct gart_device *gart = gart_domain->gart;
256 spin_lock(&gart->client_lock);
257 if (!list_empty(&gart->client)) {
258 struct gart_client *c;
260 list_for_each_entry(c, &gart->client, list)
261 gart_iommu_detach_dev(domain, c->dev);
263 spin_unlock(&gart->client_lock);
269 static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
270 phys_addr_t pa, size_t bytes, int prot)
272 struct gart_domain *gart_domain = to_gart_domain(domain);
273 struct gart_device *gart = gart_domain->gart;
278 if (!gart_iova_range_valid(gart, iova, bytes))
281 spin_lock_irqsave(&gart->pte_lock, flags);
282 pfn = __phys_to_pfn(pa);
283 if (!pfn_valid(pfn)) {
284 dev_err(gart->dev, "Invalid page: %pa\n", &pa);
285 spin_unlock_irqrestore(&gart->pte_lock, flags);
289 pte = gart_read_pte(gart, iova);
290 if (pte & GART_ENTRY_PHYS_ADDR_VALID) {
291 spin_unlock_irqrestore(&gart->pte_lock, flags);
292 dev_err(gart->dev, "Page entry is in-use\n");
296 gart_set_pte(gart, iova, GART_PTE(pfn));
297 FLUSH_GART_REGS(gart);
298 spin_unlock_irqrestore(&gart->pte_lock, flags);
302 static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
305 struct gart_domain *gart_domain = to_gart_domain(domain);
306 struct gart_device *gart = gart_domain->gart;
309 if (!gart_iova_range_valid(gart, iova, bytes))
312 spin_lock_irqsave(&gart->pte_lock, flags);
313 gart_set_pte(gart, iova, 0);
314 FLUSH_GART_REGS(gart);
315 spin_unlock_irqrestore(&gart->pte_lock, flags);
319 static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
322 struct gart_domain *gart_domain = to_gart_domain(domain);
323 struct gart_device *gart = gart_domain->gart;
328 if (!gart_iova_range_valid(gart, iova, 0))
331 spin_lock_irqsave(&gart->pte_lock, flags);
332 pte = gart_read_pte(gart, iova);
333 spin_unlock_irqrestore(&gart->pte_lock, flags);
335 pa = (pte & GART_PAGE_MASK);
336 if (!pfn_valid(__phys_to_pfn(pa))) {
337 dev_err(gart->dev, "No entry for %08llx:%pa\n",
338 (unsigned long long)iova, &pa);
339 gart_dump_table(gart);
345 static bool gart_iommu_capable(enum iommu_cap cap)
350 static int gart_iommu_add_device(struct device *dev)
352 struct iommu_group *group = iommu_group_get_for_dev(dev);
355 return PTR_ERR(group);
357 iommu_group_put(group);
359 iommu_device_link(&gart_handle->iommu, dev);
364 static void gart_iommu_remove_device(struct device *dev)
366 iommu_group_remove_device(dev);
367 iommu_device_unlink(&gart_handle->iommu, dev);
370 static const struct iommu_ops gart_iommu_ops = {
371 .capable = gart_iommu_capable,
372 .domain_alloc = gart_iommu_domain_alloc,
373 .domain_free = gart_iommu_domain_free,
374 .attach_dev = gart_iommu_attach_dev,
375 .detach_dev = gart_iommu_detach_dev,
376 .add_device = gart_iommu_add_device,
377 .remove_device = gart_iommu_remove_device,
378 .device_group = generic_device_group,
379 .map = gart_iommu_map,
380 .unmap = gart_iommu_unmap,
381 .iova_to_phys = gart_iommu_iova_to_phys,
382 .pgsize_bitmap = GART_IOMMU_PGSIZES,
385 static int tegra_gart_suspend(struct device *dev)
387 struct gart_device *gart = dev_get_drvdata(dev);
389 u32 *data = gart->savedata;
392 spin_lock_irqsave(&gart->pte_lock, flags);
393 for_each_gart_pte(gart, iova)
394 *(data++) = gart_read_pte(gart, iova);
395 spin_unlock_irqrestore(&gart->pte_lock, flags);
399 static int tegra_gart_resume(struct device *dev)
401 struct gart_device *gart = dev_get_drvdata(dev);
404 spin_lock_irqsave(&gart->pte_lock, flags);
405 do_gart_setup(gart, gart->savedata);
406 spin_unlock_irqrestore(&gart->pte_lock, flags);
410 static int tegra_gart_probe(struct platform_device *pdev)
412 struct gart_device *gart;
413 struct resource *res, *res_remap;
414 void __iomem *gart_regs;
415 struct device *dev = &pdev->dev;
421 BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
423 /* the GART memory aperture is required */
424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425 res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
426 if (!res || !res_remap) {
427 dev_err(dev, "GART memory aperture expected\n");
431 gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL);
433 dev_err(dev, "failed to allocate gart_device\n");
437 gart_regs = devm_ioremap(dev, res->start, resource_size(res));
439 dev_err(dev, "failed to remap GART registers\n");
443 ret = iommu_device_sysfs_add(&gart->iommu, &pdev->dev, NULL,
444 dev_name(&pdev->dev));
446 dev_err(dev, "Failed to register IOMMU in sysfs\n");
450 iommu_device_set_ops(&gart->iommu, &gart_iommu_ops);
452 ret = iommu_device_register(&gart->iommu);
454 dev_err(dev, "Failed to register IOMMU\n");
455 iommu_device_sysfs_remove(&gart->iommu);
459 gart->dev = &pdev->dev;
460 spin_lock_init(&gart->pte_lock);
461 spin_lock_init(&gart->client_lock);
462 INIT_LIST_HEAD(&gart->client);
463 gart->regs = gart_regs;
464 gart->iovmm_base = (dma_addr_t)res_remap->start;
465 gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
467 gart->savedata = vmalloc(array_size(sizeof(u32), gart->page_count));
468 if (!gart->savedata) {
469 dev_err(dev, "failed to allocate context save area\n");
473 platform_set_drvdata(pdev, gart);
474 do_gart_setup(gart, NULL);
481 static int tegra_gart_remove(struct platform_device *pdev)
483 struct gart_device *gart = platform_get_drvdata(pdev);
485 iommu_device_unregister(&gart->iommu);
486 iommu_device_sysfs_remove(&gart->iommu);
488 writel(0, gart->regs + GART_CONFIG);
490 vfree(gart->savedata);
495 static const struct dev_pm_ops tegra_gart_pm_ops = {
496 .suspend = tegra_gart_suspend,
497 .resume = tegra_gart_resume,
500 static const struct of_device_id tegra_gart_of_match[] = {
501 { .compatible = "nvidia,tegra20-gart", },
504 MODULE_DEVICE_TABLE(of, tegra_gart_of_match);
506 static struct platform_driver tegra_gart_driver = {
507 .probe = tegra_gart_probe,
508 .remove = tegra_gart_remove,
510 .name = "tegra-gart",
511 .pm = &tegra_gart_pm_ops,
512 .of_match_table = tegra_gart_of_match,
516 static int tegra_gart_init(void)
518 return platform_driver_register(&tegra_gart_driver);
521 static void __exit tegra_gart_exit(void)
523 platform_driver_unregister(&tegra_gart_driver);
526 subsys_initcall(tegra_gart_init);
527 module_exit(tegra_gart_exit);
528 module_param(gart_debug, bool, 0644);
530 MODULE_PARM_DESC(gart_debug, "Enable GART debugging");
531 MODULE_DESCRIPTION("IOMMU API for GART in Tegra20");
532 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
533 MODULE_ALIAS("platform:tegra-gart");
534 MODULE_LICENSE("GPL v2");