2 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2013 ARM Limited
17 * Copyright (C) 2017 Red Hat
20 #include <linux/atomic.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/iommu.h>
30 #include <linux/iopoll.h>
31 #include <linux/kconfig.h>
32 #include <linux/module.h>
33 #include <linux/mutex.h>
35 #include <linux/of_address.h>
36 #include <linux/of_device.h>
37 #include <linux/of_iommu.h>
38 #include <linux/platform_device.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/qcom_scm.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
45 #include "io-pgtable.h"
46 #include "arm-smmu-regs.h"
48 #define SMMU_INTR_SEL_NS 0x2000
50 struct qcom_iommu_ctx;
52 struct qcom_iommu_dev {
53 /* IOMMU core code handle */
54 struct iommu_device iommu;
56 struct clk *iface_clk;
58 void __iomem *local_base;
61 struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */
64 struct qcom_iommu_ctx {
68 u8 asid; /* asid and ctx bank # are 1:1 */
69 struct iommu_domain *domain;
72 struct qcom_iommu_domain {
73 struct io_pgtable_ops *pgtbl_ops;
74 spinlock_t pgtbl_lock;
75 struct mutex init_mutex; /* Protects iommu pointer */
76 struct iommu_domain domain;
77 struct qcom_iommu_dev *iommu;
80 static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
82 return container_of(dom, struct qcom_iommu_domain, domain);
85 static const struct iommu_ops qcom_iommu_ops;
87 static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec)
89 if (!fwspec || fwspec->ops != &qcom_iommu_ops)
91 return fwspec->iommu_priv;
94 static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid)
96 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
99 return qcom_iommu->ctxs[asid - 1];
103 iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
105 writel_relaxed(val, ctx->base + reg);
109 iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
111 writeq_relaxed(val, ctx->base + reg);
115 iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
117 return readl_relaxed(ctx->base + reg);
121 iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
123 return readq_relaxed(ctx->base + reg);
126 static void qcom_iommu_tlb_sync(void *cookie)
128 struct iommu_fwspec *fwspec = cookie;
131 for (i = 0; i < fwspec->num_ids; i++) {
132 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
133 unsigned int val, ret;
135 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
137 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
138 (val & 0x1) == 0, 0, 5000000);
140 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
144 static void qcom_iommu_tlb_inv_context(void *cookie)
146 struct iommu_fwspec *fwspec = cookie;
149 for (i = 0; i < fwspec->num_ids; i++) {
150 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
151 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
154 qcom_iommu_tlb_sync(cookie);
157 static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
158 size_t granule, bool leaf, void *cookie)
160 struct iommu_fwspec *fwspec = cookie;
163 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
165 for (i = 0; i < fwspec->num_ids; i++) {
166 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
172 iommu_writel(ctx, reg, iova);
174 } while (s -= granule);
178 static const struct iommu_gather_ops qcom_gather_ops = {
179 .tlb_flush_all = qcom_iommu_tlb_inv_context,
180 .tlb_add_flush = qcom_iommu_tlb_inv_range_nosync,
181 .tlb_sync = qcom_iommu_tlb_sync,
184 static irqreturn_t qcom_iommu_fault(int irq, void *dev)
186 struct qcom_iommu_ctx *ctx = dev;
190 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
192 if (!(fsr & FSR_FAULT))
195 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
196 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
198 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
199 dev_err_ratelimited(ctx->dev,
200 "Unhandled context fault: fsr=0x%x, "
201 "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
202 fsr, iova, fsynr, ctx->asid);
205 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
206 iommu_writel(ctx, ARM_SMMU_CB_RESUME, RESUME_TERMINATE);
211 static int qcom_iommu_init_domain(struct iommu_domain *domain,
212 struct qcom_iommu_dev *qcom_iommu,
213 struct iommu_fwspec *fwspec)
215 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
216 struct io_pgtable_ops *pgtbl_ops;
217 struct io_pgtable_cfg pgtbl_cfg;
221 mutex_lock(&qcom_domain->init_mutex);
222 if (qcom_domain->iommu)
225 pgtbl_cfg = (struct io_pgtable_cfg) {
226 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
229 .tlb = &qcom_gather_ops,
230 .iommu_dev = qcom_iommu->dev,
233 qcom_domain->iommu = qcom_iommu;
234 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec);
236 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
238 goto out_clear_iommu;
241 /* Update the domain's page sizes to reflect the page table format */
242 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
243 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
244 domain->geometry.force_aperture = true;
246 for (i = 0; i < fwspec->num_ids; i++) {
247 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
249 if (!ctx->secure_init) {
250 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
252 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
253 goto out_clear_iommu;
255 ctx->secure_init = true;
259 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
260 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
261 ((u64)ctx->asid << TTBRn_ASID_SHIFT));
262 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1,
263 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
264 ((u64)ctx->asid << TTBRn_ASID_SHIFT));
267 iommu_writel(ctx, ARM_SMMU_CB_TTBCR2,
268 (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
269 TTBCR2_SEP_UPSTREAM);
270 iommu_writel(ctx, ARM_SMMU_CB_TTBCR,
271 pgtbl_cfg.arm_lpae_s1_cfg.tcr);
273 /* MAIRs (stage-1 only) */
274 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
275 pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
276 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
277 pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);
280 reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
281 SCTLR_M | SCTLR_S1_ASIDPNE | SCTLR_CFCFG;
283 if (IS_ENABLED(CONFIG_BIG_ENDIAN))
286 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
288 ctx->domain = domain;
291 mutex_unlock(&qcom_domain->init_mutex);
293 /* Publish page table ops for map/unmap */
294 qcom_domain->pgtbl_ops = pgtbl_ops;
299 qcom_domain->iommu = NULL;
301 mutex_unlock(&qcom_domain->init_mutex);
305 static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
307 struct qcom_iommu_domain *qcom_domain;
309 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
312 * Allocate the domain and initialise some of its data structures.
313 * We can't really do anything meaningful until we've added a
316 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
320 if (type == IOMMU_DOMAIN_DMA &&
321 iommu_get_dma_cookie(&qcom_domain->domain)) {
326 mutex_init(&qcom_domain->init_mutex);
327 spin_lock_init(&qcom_domain->pgtbl_lock);
329 return &qcom_domain->domain;
332 static void qcom_iommu_domain_free(struct iommu_domain *domain)
334 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
336 iommu_put_dma_cookie(domain);
338 if (qcom_domain->iommu) {
340 * NOTE: unmap can be called after client device is powered
341 * off, for example, with GPUs or anything involving dma-buf.
342 * So we cannot rely on the device_link. Make sure the IOMMU
343 * is on to avoid unclocked accesses in the TLB inv path:
345 pm_runtime_get_sync(qcom_domain->iommu->dev);
346 free_io_pgtable_ops(qcom_domain->pgtbl_ops);
347 pm_runtime_put_sync(qcom_domain->iommu->dev);
353 static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
355 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
356 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
360 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
364 /* Ensure that the domain is finalized */
365 pm_runtime_get_sync(qcom_iommu->dev);
366 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev->iommu_fwspec);
367 pm_runtime_put_sync(qcom_iommu->dev);
372 * Sanity check the domain. We don't support domains across
375 if (qcom_domain->iommu != qcom_iommu) {
376 dev_err(dev, "cannot attach to IOMMU %s while already "
377 "attached to domain on IOMMU %s\n",
378 dev_name(qcom_domain->iommu->dev),
379 dev_name(qcom_iommu->dev));
386 static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
388 struct iommu_fwspec *fwspec = dev->iommu_fwspec;
389 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
390 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
393 if (WARN_ON(!qcom_domain->iommu))
396 pm_runtime_get_sync(qcom_iommu->dev);
397 for (i = 0; i < fwspec->num_ids; i++) {
398 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
400 /* Disable the context bank: */
401 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
405 pm_runtime_put_sync(qcom_iommu->dev);
408 static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
409 phys_addr_t paddr, size_t size, int prot)
413 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
414 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
419 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
420 ret = ops->map(ops, iova, paddr, size, prot);
421 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
425 static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
430 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
431 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
436 /* NOTE: unmap can be called after client device is powered off,
437 * for example, with GPUs or anything involving dma-buf. So we
438 * cannot rely on the device_link. Make sure the IOMMU is on to
439 * avoid unclocked accesses in the TLB inv path:
441 pm_runtime_get_sync(qcom_domain->iommu->dev);
442 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
443 ret = ops->unmap(ops, iova, size);
444 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
445 pm_runtime_put_sync(qcom_domain->iommu->dev);
450 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain)
452 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
453 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
454 struct io_pgtable, ops);
455 if (!qcom_domain->pgtbl_ops)
458 pm_runtime_get_sync(qcom_domain->iommu->dev);
459 qcom_iommu_tlb_sync(pgtable->cookie);
460 pm_runtime_put_sync(qcom_domain->iommu->dev);
463 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
468 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
469 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
474 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
475 ret = ops->iova_to_phys(ops, iova);
476 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
481 static bool qcom_iommu_capable(enum iommu_cap cap)
484 case IOMMU_CAP_CACHE_COHERENCY:
486 * Return true here as the SMMU can always send out coherent
490 case IOMMU_CAP_NOEXEC:
497 static int qcom_iommu_add_device(struct device *dev)
499 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
500 struct iommu_group *group;
501 struct device_link *link;
507 * Establish the link between iommu and master, so that the
508 * iommu gets runtime enabled/disabled as per the master's
511 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
513 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
514 dev_name(qcom_iommu->dev), dev_name(dev));
518 group = iommu_group_get_for_dev(dev);
519 if (IS_ERR_OR_NULL(group))
520 return PTR_ERR_OR_ZERO(group);
522 iommu_group_put(group);
523 iommu_device_link(&qcom_iommu->iommu, dev);
528 static void qcom_iommu_remove_device(struct device *dev)
530 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
535 iommu_device_unlink(&qcom_iommu->iommu, dev);
536 iommu_group_remove_device(dev);
537 iommu_fwspec_free(dev);
540 static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
542 struct qcom_iommu_dev *qcom_iommu;
543 struct platform_device *iommu_pdev;
544 unsigned asid = args->args[0];
546 if (args->args_count != 1) {
547 dev_err(dev, "incorrect number of iommu params found for %s "
548 "(found %d, expected 1)\n",
549 args->np->full_name, args->args_count);
553 iommu_pdev = of_find_device_by_node(args->np);
554 if (WARN_ON(!iommu_pdev))
557 qcom_iommu = platform_get_drvdata(iommu_pdev);
559 /* make sure the asid specified in dt is valid, so we don't have
560 * to sanity check this elsewhere, since 'asid - 1' is used to
561 * index into qcom_iommu->ctxs:
563 if (WARN_ON(asid < 1) ||
564 WARN_ON(asid > qcom_iommu->num_ctxs))
567 if (!dev->iommu_fwspec->iommu_priv) {
568 dev->iommu_fwspec->iommu_priv = qcom_iommu;
570 /* make sure devices iommus dt node isn't referring to
571 * multiple different iommu devices. Multiple context
572 * banks are ok, but multiple devices are not:
574 if (WARN_ON(qcom_iommu != dev->iommu_fwspec->iommu_priv))
578 return iommu_fwspec_add_ids(dev, &asid, 1);
581 static const struct iommu_ops qcom_iommu_ops = {
582 .capable = qcom_iommu_capable,
583 .domain_alloc = qcom_iommu_domain_alloc,
584 .domain_free = qcom_iommu_domain_free,
585 .attach_dev = qcom_iommu_attach_dev,
586 .detach_dev = qcom_iommu_detach_dev,
587 .map = qcom_iommu_map,
588 .unmap = qcom_iommu_unmap,
589 .flush_iotlb_all = qcom_iommu_iotlb_sync,
590 .iotlb_sync = qcom_iommu_iotlb_sync,
591 .iova_to_phys = qcom_iommu_iova_to_phys,
592 .add_device = qcom_iommu_add_device,
593 .remove_device = qcom_iommu_remove_device,
594 .device_group = generic_device_group,
595 .of_xlate = qcom_iommu_of_xlate,
596 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
599 static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu)
603 ret = clk_prepare_enable(qcom_iommu->iface_clk);
605 dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n");
609 ret = clk_prepare_enable(qcom_iommu->bus_clk);
611 dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n");
612 clk_disable_unprepare(qcom_iommu->iface_clk);
619 static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
621 clk_disable_unprepare(qcom_iommu->bus_clk);
622 clk_disable_unprepare(qcom_iommu->iface_clk);
625 static int qcom_iommu_sec_ptbl_init(struct device *dev)
628 unsigned int spare = 0;
632 static bool allocated = false;
638 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
640 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
645 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
647 attrs = DMA_ATTR_NO_KERNEL_MAPPING;
649 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
651 dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
656 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
658 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
666 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
670 static int get_asid(const struct device_node *np)
674 /* read the "reg" property directly to get the relative address
675 * of the context bank, and calculate the asid from that:
677 if (of_property_read_u32_index(np, "reg", 0, ®))
680 return reg / 0x1000; /* context banks are 0x1000 apart */
683 static int qcom_iommu_ctx_probe(struct platform_device *pdev)
685 struct qcom_iommu_ctx *ctx;
686 struct device *dev = &pdev->dev;
687 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
688 struct resource *res;
691 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
696 platform_set_drvdata(pdev, ctx);
698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 ctx->base = devm_ioremap_resource(dev, res);
700 if (IS_ERR(ctx->base))
701 return PTR_ERR(ctx->base);
703 irq = platform_get_irq(pdev, 0);
705 dev_err(dev, "failed to get irq\n");
709 /* clear IRQs before registering fault handler, just in case the
710 * boot-loader left us a surprise:
712 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
714 ret = devm_request_irq(dev, irq,
720 dev_err(dev, "failed to request IRQ %u\n", irq);
724 ret = get_asid(dev->of_node);
726 dev_err(dev, "missing reg property\n");
732 dev_dbg(dev, "found asid %u\n", ctx->asid);
734 qcom_iommu->ctxs[ctx->asid - 1] = ctx;
739 static int qcom_iommu_ctx_remove(struct platform_device *pdev)
741 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
742 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
744 platform_set_drvdata(pdev, NULL);
746 qcom_iommu->ctxs[ctx->asid - 1] = NULL;
751 static const struct of_device_id ctx_of_match[] = {
752 { .compatible = "qcom,msm-iommu-v1-ns" },
753 { .compatible = "qcom,msm-iommu-v1-sec" },
757 static struct platform_driver qcom_iommu_ctx_driver = {
759 .name = "qcom-iommu-ctx",
760 .of_match_table = of_match_ptr(ctx_of_match),
762 .probe = qcom_iommu_ctx_probe,
763 .remove = qcom_iommu_ctx_remove,
766 static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
768 struct device_node *child;
770 for_each_child_of_node(qcom_iommu->dev->of_node, child) {
771 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) {
780 static int qcom_iommu_device_probe(struct platform_device *pdev)
782 struct device_node *child;
783 struct qcom_iommu_dev *qcom_iommu;
784 struct device *dev = &pdev->dev;
785 struct resource *res;
786 int ret, sz, max_asid = 0;
788 /* find the max asid (which is 1:1 to ctx bank idx), so we know how
789 * many child ctx devices we have:
791 for_each_child_of_node(dev->of_node, child)
792 max_asid = max(max_asid, get_asid(child));
794 sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0]));
796 qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL);
799 qcom_iommu->num_ctxs = max_asid;
800 qcom_iommu->dev = dev;
802 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
804 qcom_iommu->local_base = devm_ioremap_resource(dev, res);
805 if (IS_ERR(qcom_iommu->local_base))
806 return PTR_ERR(qcom_iommu->local_base);
809 qcom_iommu->iface_clk = devm_clk_get(dev, "iface");
810 if (IS_ERR(qcom_iommu->iface_clk)) {
811 dev_err(dev, "failed to get iface clock\n");
812 return PTR_ERR(qcom_iommu->iface_clk);
815 qcom_iommu->bus_clk = devm_clk_get(dev, "bus");
816 if (IS_ERR(qcom_iommu->bus_clk)) {
817 dev_err(dev, "failed to get bus clock\n");
818 return PTR_ERR(qcom_iommu->bus_clk);
821 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
822 &qcom_iommu->sec_id)) {
823 dev_err(dev, "missing qcom,iommu-secure-id property\n");
827 if (qcom_iommu_has_secure_context(qcom_iommu)) {
828 ret = qcom_iommu_sec_ptbl_init(dev);
830 dev_err(dev, "cannot init secure pg table(%d)\n", ret);
835 platform_set_drvdata(pdev, qcom_iommu);
837 pm_runtime_enable(dev);
839 /* register context bank devices, which are child nodes: */
840 ret = devm_of_platform_populate(dev);
842 dev_err(dev, "Failed to populate iommu contexts\n");
846 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
849 dev_err(dev, "Failed to register iommu in sysfs\n");
853 iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops);
854 iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode);
856 ret = iommu_device_register(&qcom_iommu->iommu);
858 dev_err(dev, "Failed to register iommu\n");
862 bus_set_iommu(&platform_bus_type, &qcom_iommu_ops);
864 if (qcom_iommu->local_base) {
865 pm_runtime_get_sync(dev);
866 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
867 pm_runtime_put_sync(dev);
873 static int qcom_iommu_device_remove(struct platform_device *pdev)
875 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
877 bus_set_iommu(&platform_bus_type, NULL);
879 pm_runtime_force_suspend(&pdev->dev);
880 platform_set_drvdata(pdev, NULL);
881 iommu_device_sysfs_remove(&qcom_iommu->iommu);
882 iommu_device_unregister(&qcom_iommu->iommu);
887 static int __maybe_unused qcom_iommu_resume(struct device *dev)
889 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
891 return qcom_iommu_enable_clocks(qcom_iommu);
894 static int __maybe_unused qcom_iommu_suspend(struct device *dev)
896 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
898 qcom_iommu_disable_clocks(qcom_iommu);
903 static const struct dev_pm_ops qcom_iommu_pm_ops = {
904 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
905 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
906 pm_runtime_force_resume)
909 static const struct of_device_id qcom_iommu_of_match[] = {
910 { .compatible = "qcom,msm-iommu-v1" },
913 MODULE_DEVICE_TABLE(of, qcom_iommu_of_match);
915 static struct platform_driver qcom_iommu_driver = {
917 .name = "qcom-iommu",
918 .of_match_table = of_match_ptr(qcom_iommu_of_match),
919 .pm = &qcom_iommu_pm_ops,
921 .probe = qcom_iommu_device_probe,
922 .remove = qcom_iommu_device_remove,
925 static int __init qcom_iommu_init(void)
929 ret = platform_driver_register(&qcom_iommu_ctx_driver);
933 ret = platform_driver_register(&qcom_iommu_driver);
935 platform_driver_unregister(&qcom_iommu_ctx_driver);
940 static void __exit qcom_iommu_exit(void)
942 platform_driver_unregister(&qcom_iommu_driver);
943 platform_driver_unregister(&qcom_iommu_ctx_driver);
946 module_init(qcom_iommu_init);
947 module_exit(qcom_iommu_exit);
949 MODULE_DESCRIPTION("IOMMU API for QCOM IOMMU v1 implementations");
950 MODULE_LICENSE("GPL v2");