drivers/iommu/mtk_iommu.c

   1 /*
   2  * Copyright (c) 2015-2016 MediaTek Inc.
   3  * Author: Yong Wu <yong.wu@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <linux/bootmem.h>
  15 #include <linux/bug.h>
  16 #include <linux/clk.h>
  17 #include <linux/component.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-iommu.h>
  20 #include <linux/err.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/iommu.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/list.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_iommu.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/slab.h>
  32 #include <linux/spinlock.h>
  33 #include <asm/barrier.h>
  34 #include <soc/mediatek/smi.h>
  35
  36 #include "mtk_iommu.h"
  37
  38 #define REG_MMU_PT_BASE_ADDR                    0x000
  39
  40 #define REG_MMU_INVALIDATE                      0x020
  41 #define F_ALL_INVLD                             0x2
  42 #define F_MMU_INV_RANGE                         0x1
  43
  44 #define REG_MMU_INVLD_START_A                   0x024
  45 #define REG_MMU_INVLD_END_A                     0x028
  46
  47 #define REG_MMU_INV_SEL                         0x038
  48 #define F_INVLD_EN0                             BIT(0)
  49 #define F_INVLD_EN1                             BIT(1)
  50
  51 #define REG_MMU_STANDARD_AXI_MODE               0x048
  52 #define REG_MMU_DCM_DIS                         0x050
  53
  54 #define REG_MMU_CTRL_REG                        0x110
  55 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  56 #define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
  57         ((data)->m4u_plat == M4U_MT2712 ? 4 : 5)
  58 /* It's named by F_MMU_TF_PROT_SEL in mt2712. */
  59 #define F_MMU_TF_PROTECT_SEL(prot, data) \
  60         (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
  61
  62 #define REG_MMU_IVRP_PADDR                      0x114
  63
  64 #define REG_MMU_VLD_PA_RNG                      0x118
  65 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  66
  67 #define REG_MMU_INT_CONTROL0                    0x120
  68 #define F_L2_MULIT_HIT_EN                       BIT(0)
  69 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  70 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  71 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  72 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  73 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  74 #define F_INT_CLR_BIT                           BIT(12)
  75
  76 #define REG_MMU_INT_MAIN_CONTROL                0x124
  77 #define F_INT_TRANSLATION_FAULT                 BIT(0)
  78 #define F_INT_MAIN_MULTI_HIT_FAULT              BIT(1)
  79 #define F_INT_INVALID_PA_FAULT                  BIT(2)
  80 #define F_INT_ENTRY_REPLACEMENT_FAULT           BIT(3)
  81 #define F_INT_TLB_MISS_FAULT                    BIT(4)
  82 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       BIT(5)
  83 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    BIT(6)
  84
  85 #define REG_MMU_CPE_DONE                        0x12C
  86
  87 #define REG_MMU_FAULT_ST1                       0x134
  88
  89 #define REG_MMU_FAULT_VA                        0x13c
  90 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
  91 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
  92
  93 #define REG_MMU_INVLD_PA                        0x140
  94 #define REG_MMU_INT_ID                          0x150
  95 #define F_MMU0_INT_ID_LARB_ID(a)                (((a) >> 7) & 0x7)
  96 #define F_MMU0_INT_ID_PORT_ID(a)                (((a) >> 2) & 0x1f)
  97
  98 #define MTK_PROTECT_PA_ALIGN                    128
  99
 100 /*
 101  * Get the local arbiter ID and the portid within the larb arbiter
 102  * from mtk_m4u_id which is defined by MTK_M4U_ID.
 103  */
 104 #define MTK_M4U_TO_LARB(id)             (((id) >> 5) & 0xf)
 105 #define MTK_M4U_TO_PORT(id)             ((id) & 0x1f)
 106
 107 struct mtk_iommu_domain {
 108         spinlock_t                      pgtlock; /* lock for page table */
 109
 110         struct io_pgtable_cfg           cfg;
 111         struct io_pgtable_ops           *iop;
 112
 113         struct iommu_domain             domain;
 114 };
 115
 116 static struct iommu_ops mtk_iommu_ops;
 117
 118 /*
 119  * In M4U 4GB mode, the physical address is remapped as below:
 120  *
 121  * CPU Physical address:
 122  * ====================
 123  *
 124  * 0      1G       2G     3G       4G     5G
 125  * |---A---|---B---|---C---|---D---|---E---|
 126  * +--I/O--+------------Memory-------------+
 127  *
 128  * IOMMU output physical address:
 129  *  =============================
 130  *
 131  *                                 4G      5G     6G      7G      8G
 132  *                                 |---E---|---B---|---C---|---D---|
 133  *                                 +------------Memory-------------+
 134  *
 135  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 136  * bit32 of the CPU physical address always is needed to set, and for Region
 137  * 'E', the CPU physical address keep as is.
 138  * Additionally, The iommu consumers always use the CPU phyiscal address.
 139  */
 140 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x40000000
 141
 142 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 143
 144 #define for_each_m4u(data)      list_for_each_entry(data, &m4ulist, list)
 145
 146 /*
 147  * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
 148  * for the performance.
 149  *
 150  * Here always return the mtk_iommu_data of the first probed M4U where the
 151  * iommu domain information is recorded.
 152  */
 153 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
 154 {
 155         struct mtk_iommu_data *data;
 156
 157         for_each_m4u(data)
 158                 return data;
 159
 160         return NULL;
 161 }
 162
 163 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 164 {
 165         return container_of(dom, struct mtk_iommu_domain, domain);
 166 }
 167
 168 static void mtk_iommu_tlb_flush_all(void *cookie)
 169 {
 170         struct mtk_iommu_data *data = cookie;
 171
 172         for_each_m4u(data) {
 173                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 174                                data->base + REG_MMU_INV_SEL);
 175                 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 176                 wmb(); /* Make sure the tlb flush all done */
 177         }
 178 }
 179
 180 static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
 181                                            size_t granule, bool leaf,
 182                                            void *cookie)
 183 {
 184         struct mtk_iommu_data *data = cookie;
 185
 186         for_each_m4u(data) {
 187                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 188                                data->base + REG_MMU_INV_SEL);
 189
 190                 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
 191                 writel_relaxed(iova + size - 1,
 192                                data->base + REG_MMU_INVLD_END_A);
 193                 writel_relaxed(F_MMU_INV_RANGE,
 194                                data->base + REG_MMU_INVALIDATE);
 195                 data->tlb_flush_active = true;
 196         }
 197 }
 198
 199 static void mtk_iommu_tlb_sync(void *cookie)
 200 {
 201         struct mtk_iommu_data *data = cookie;
 202         int ret;
 203         u32 tmp;
 204
 205         for_each_m4u(data) {
 206                 /* Avoid timing out if there's nothing to wait for */
 207                 if (!data->tlb_flush_active)
 208                         return;
 209
 210                 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
 211                                                 tmp, tmp != 0, 10, 100000);
 212                 if (ret) {
 213                         dev_warn(data->dev,
 214                                  "Partial TLB flush timed out, falling back to full flush\n");
 215                         mtk_iommu_tlb_flush_all(cookie);
 216                 }
 217                 /* Clear the CPE status */
 218                 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 219                 data->tlb_flush_active = false;
 220         }
 221 }
 222
 223 static const struct iommu_gather_ops mtk_iommu_gather_ops = {
 224         .tlb_flush_all = mtk_iommu_tlb_flush_all,
 225         .tlb_add_flush = mtk_iommu_tlb_add_flush_nosync,
 226         .tlb_sync = mtk_iommu_tlb_sync,
 227 };
 228
 229 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 230 {
 231         struct mtk_iommu_data *data = dev_id;
 232         struct mtk_iommu_domain *dom = data->m4u_dom;
 233         u32 int_state, regval, fault_iova, fault_pa;
 234         unsigned int fault_larb, fault_port;
 235         bool layer, write;
 236
 237         /* Read error info from registers */
 238         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
 239         fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
 240         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 241         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 242         fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
 243         regval = readl_relaxed(data->base + REG_MMU_INT_ID);
 244         fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
 245         fault_port = F_MMU0_INT_ID_PORT_ID(regval);
 246
 247         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 248                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 249                 dev_err_ratelimited(
 250                         data->dev,
 251                         "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
 252                         int_state, fault_iova, fault_pa, fault_larb, fault_port,
 253                         layer, write ? "write" : "read");
 254         }
 255
 256         /* Interrupt clear */
 257         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
 258         regval |= F_INT_CLR_BIT;
 259         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 260
 261         mtk_iommu_tlb_flush_all(data);
 262
 263         return IRQ_HANDLED;
 264 }
 265
 266 static void mtk_iommu_config(struct mtk_iommu_data *data,
 267                              struct device *dev, bool enable)
 268 {
 269         struct mtk_smi_larb_iommu    *larb_mmu;
 270         unsigned int                 larbid, portid;
 271         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
 272         int i;
 273
 274         for (i = 0; i < fwspec->num_ids; ++i) {
 275                 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
 276                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 277                 larb_mmu = &data->smi_imu.larb_imu[larbid];
 278
 279                 dev_dbg(dev, "%s iommu port: %d\n",
 280                         enable ? "enable" : "disable", portid);
 281
 282                 if (enable)
 283                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 284                 else
 285                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 286         }
 287 }
 288
 289 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
 290 {
 291         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 292
 293         spin_lock_init(&dom->pgtlock);
 294
 295         dom->cfg = (struct io_pgtable_cfg) {
 296                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 297                         IO_PGTABLE_QUIRK_NO_PERMS |
 298                         IO_PGTABLE_QUIRK_TLBI_ON_MAP,
 299                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 300                 .ias = 32,
 301                 .oas = 32,
 302                 .tlb = &mtk_iommu_gather_ops,
 303                 .iommu_dev = data->dev,
 304         };
 305
 306         if (data->enable_4GB)
 307                 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB;
 308
 309         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 310         if (!dom->iop) {
 311                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 312                 return -EINVAL;
 313         }
 314
 315         /* Update our support page sizes bitmap */
 316         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 317         return 0;
 318 }
 319
 320 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 321 {
 322         struct mtk_iommu_domain *dom;
 323
 324         if (type != IOMMU_DOMAIN_DMA)
 325                 return NULL;
 326
 327         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 328         if (!dom)
 329                 return NULL;
 330
 331         if (iommu_get_dma_cookie(&dom->domain))
 332                 goto  free_dom;
 333
 334         if (mtk_iommu_domain_finalise(dom))
 335                 goto  put_dma_cookie;
 336
 337         dom->domain.geometry.aperture_start = 0;
 338         dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
 339         dom->domain.geometry.force_aperture = true;
 340
 341         return &dom->domain;
 342
 343 put_dma_cookie:
 344         iommu_put_dma_cookie(&dom->domain);
 345 free_dom:
 346         kfree(dom);
 347         return NULL;
 348 }
 349
 350 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 351 {
 352         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 353
 354         free_io_pgtable_ops(dom->iop);
 355         iommu_put_dma_cookie(domain);
 356         kfree(to_mtk_domain(domain));
 357 }
 358
 359 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 360                                    struct device *dev)
 361 {
 362         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 363         struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
 364
 365         if (!data)
 366                 return -ENODEV;
 367
 368         /* Update the pgtable base address register of the M4U HW */
 369         if (!data->m4u_dom) {
 370                 data->m4u_dom = dom;
 371                 writel(dom->cfg.arm_v7s_cfg.ttbr[0],
 372                        data->base + REG_MMU_PT_BASE_ADDR);
 373         }
 374
 375         mtk_iommu_config(data, dev, true);
 376         return 0;
 377 }
 378
 379 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 380                                     struct device *dev)
 381 {
 382         struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
 383
 384         if (!data)
 385                 return;
 386
 387         mtk_iommu_config(data, dev, false);
 388 }
 389
 390 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 391                          phys_addr_t paddr, size_t size, int prot)
 392 {
 393         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 394         unsigned long flags;
 395         int ret;
 396
 397         spin_lock_irqsave(&dom->pgtlock, flags);
 398         ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32),
 399                             size, prot);
 400         spin_unlock_irqrestore(&dom->pgtlock, flags);
 401
 402         return ret;
 403 }
 404
 405 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 406                               unsigned long iova, size_t size)
 407 {
 408         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 409         unsigned long flags;
 410         size_t unmapsz;
 411
 412         spin_lock_irqsave(&dom->pgtlock, flags);
 413         unmapsz = dom->iop->unmap(dom->iop, iova, size);
 414         spin_unlock_irqrestore(&dom->pgtlock, flags);
 415
 416         return unmapsz;
 417 }
 418
 419 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 420                                           dma_addr_t iova)
 421 {
 422         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 423         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 424         unsigned long flags;
 425         phys_addr_t pa;
 426
 427         spin_lock_irqsave(&dom->pgtlock, flags);
 428         pa = dom->iop->iova_to_phys(dom->iop, iova);
 429         spin_unlock_irqrestore(&dom->pgtlock, flags);
 430
 431         if (data->enable_4GB && pa < MTK_IOMMU_4GB_MODE_REMAP_BASE)
 432                 pa |= BIT_ULL(32);
 433
 434         return pa;
 435 }
 436
 437 static int mtk_iommu_add_device(struct device *dev)
 438 {
 439         struct mtk_iommu_data *data;
 440         struct iommu_group *group;
 441
 442         if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops)
 443                 return -ENODEV; /* Not a iommu client device */
 444
 445         data = dev->iommu_fwspec->iommu_priv;
 446         iommu_device_link(&data->iommu, dev);
 447
 448         group = iommu_group_get_for_dev(dev);
 449         if (IS_ERR(group))
 450                 return PTR_ERR(group);
 451
 452         iommu_group_put(group);
 453         return 0;
 454 }
 455
 456 static void mtk_iommu_remove_device(struct device *dev)
 457 {
 458         struct mtk_iommu_data *data;
 459
 460         if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops)
 461                 return;
 462
 463         data = dev->iommu_fwspec->iommu_priv;
 464         iommu_device_unlink(&data->iommu, dev);
 465
 466         iommu_group_remove_device(dev);
 467         iommu_fwspec_free(dev);
 468 }
 469
 470 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 471 {
 472         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 473
 474         if (!data)
 475                 return ERR_PTR(-ENODEV);
 476
 477         /* All the client devices are in the same m4u iommu-group */
 478         if (!data->m4u_group) {
 479                 data->m4u_group = iommu_group_alloc();
 480                 if (IS_ERR(data->m4u_group))
 481                         dev_err(dev, "Failed to allocate M4U IOMMU group\n");
 482         } else {
 483                 iommu_group_ref_get(data->m4u_group);
 484         }
 485         return data->m4u_group;
 486 }
 487
 488 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 489 {
 490         struct platform_device *m4updev;
 491
 492         if (args->args_count != 1) {
 493                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 494                         args->args_count);
 495                 return -EINVAL;
 496         }
 497
 498         if (!dev->iommu_fwspec->iommu_priv) {
 499                 /* Get the m4u device */
 500                 m4updev = of_find_device_by_node(args->np);
 501                 if (WARN_ON(!m4updev))
 502                         return -EINVAL;
 503
 504                 dev->iommu_fwspec->iommu_priv = platform_get_drvdata(m4updev);
 505         }
 506
 507         return iommu_fwspec_add_ids(dev, args->args, 1);
 508 }
 509
 510 static struct iommu_ops mtk_iommu_ops = {
 511         .domain_alloc   = mtk_iommu_domain_alloc,
 512         .domain_free    = mtk_iommu_domain_free,
 513         .attach_dev     = mtk_iommu_attach_device,
 514         .detach_dev     = mtk_iommu_detach_device,
 515         .map            = mtk_iommu_map,
 516         .unmap          = mtk_iommu_unmap,
 517         .map_sg         = default_iommu_map_sg,
 518         .iova_to_phys   = mtk_iommu_iova_to_phys,
 519         .add_device     = mtk_iommu_add_device,
 520         .remove_device  = mtk_iommu_remove_device,
 521         .device_group   = mtk_iommu_device_group,
 522         .of_xlate       = mtk_iommu_of_xlate,
 523         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
 524 };
 525
 526 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 527 {
 528         u32 regval;
 529         int ret;
 530
 531         ret = clk_prepare_enable(data->bclk);
 532         if (ret) {
 533                 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
 534                 return ret;
 535         }
 536
 537         regval = F_MMU_TF_PROTECT_SEL(2, data);
 538         if (data->m4u_plat == M4U_MT8173)
 539                 regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
 540         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 541
 542         regval = F_L2_MULIT_HIT_EN |
 543                 F_TABLE_WALK_FAULT_INT_EN |
 544                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
 545                 F_MISS_FIFO_OVERFLOW_INT_EN |
 546                 F_PREFETCH_FIFO_ERR_INT_EN |
 547                 F_MISS_FIFO_ERR_INT_EN;
 548         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 549
 550         regval = F_INT_TRANSLATION_FAULT |
 551                 F_INT_MAIN_MULTI_HIT_FAULT |
 552                 F_INT_INVALID_PA_FAULT |
 553                 F_INT_ENTRY_REPLACEMENT_FAULT |
 554                 F_INT_TLB_MISS_FAULT |
 555                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
 556                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
 557         writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
 558
 559         if (data->m4u_plat == M4U_MT8173)
 560                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
 561         else
 562                 regval = lower_32_bits(data->protect_base) |
 563                          upper_32_bits(data->protect_base);
 564         writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
 565
 566         if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
 567                 /*
 568                  * If 4GB mode is enabled, the validate PA range is from
 569                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
 570                  */
 571                 regval = F_MMU_VLD_PA_RNG(7, 4);
 572                 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
 573         }
 574         writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 575
 576         /* It's MISC control register whose default value is ok except mt8173.*/
 577         if (data->m4u_plat == M4U_MT8173)
 578                 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
 579
 580         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 581                              dev_name(data->dev), (void *)data)) {
 582                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 583                 clk_disable_unprepare(data->bclk);
 584                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 585                 return -ENODEV;
 586         }
 587
 588         return 0;
 589 }
 590
 591 static const struct component_master_ops mtk_iommu_com_ops = {
 592         .bind           = mtk_iommu_bind,
 593         .unbind         = mtk_iommu_unbind,
 594 };
 595
 596 static int mtk_iommu_probe(struct platform_device *pdev)
 597 {
 598         struct mtk_iommu_data   *data;
 599         struct device           *dev = &pdev->dev;
 600         struct resource         *res;
 601         resource_size_t         ioaddr;
 602         struct component_match  *match = NULL;
 603         void                    *protect;
 604         int                     i, larb_nr, ret;
 605
 606         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 607         if (!data)
 608                 return -ENOMEM;
 609         data->dev = dev;
 610         data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);
 611
 612         /* Protect memory. HW will access here while translation fault.*/
 613         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
 614         if (!protect)
 615                 return -ENOMEM;
 616         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 617
 618         /* Whether the current dram is over 4GB */
 619         data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
 620
 621         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 622         data->base = devm_ioremap_resource(dev, res);
 623         if (IS_ERR(data->base))
 624                 return PTR_ERR(data->base);
 625         ioaddr = res->start;
 626
 627         data->irq = platform_get_irq(pdev, 0);
 628         if (data->irq < 0)
 629                 return data->irq;
 630
 631         data->bclk = devm_clk_get(dev, "bclk");
 632         if (IS_ERR(data->bclk))
 633                 return PTR_ERR(data->bclk);
 634
 635         larb_nr = of_count_phandle_with_args(dev->of_node,
 636                                              "mediatek,larbs", NULL);
 637         if (larb_nr < 0)
 638                 return larb_nr;
 639         data->smi_imu.larb_nr = larb_nr;
 640
 641         for (i = 0; i < larb_nr; i++) {
 642                 struct device_node *larbnode;
 643                 struct platform_device *plarbdev;
 644                 u32 id;
 645
 646                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
 647                 if (!larbnode)
 648                         return -EINVAL;
 649
 650                 if (!of_device_is_available(larbnode))
 651                         continue;
 652
 653                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
 654                 if (ret)/* The id is consecutive if there is no this property */
 655                         id = i;
 656
 657                 plarbdev = of_find_device_by_node(larbnode);
 658                 if (!plarbdev)
 659                         return -EPROBE_DEFER;
 660                 data->smi_imu.larb_imu[id].dev = &plarbdev->dev;
 661
 662                 component_match_add_release(dev, &match, release_of,
 663                                             compare_of, larbnode);
 664         }
 665
 666         platform_set_drvdata(pdev, data);
 667
 668         ret = mtk_iommu_hw_init(data);
 669         if (ret)
 670                 return ret;
 671
 672         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
 673                                      "mtk-iommu.%pa", &ioaddr);
 674         if (ret)
 675                 return ret;
 676
 677         iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
 678         iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode);
 679
 680         ret = iommu_device_register(&data->iommu);
 681         if (ret)
 682                 return ret;
 683
 684         list_add_tail(&data->list, &m4ulist);
 685
 686         if (!iommu_present(&platform_bus_type))
 687                 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
 688
 689         return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
 690 }
 691
 692 static int mtk_iommu_remove(struct platform_device *pdev)
 693 {
 694         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
 695
 696         iommu_device_sysfs_remove(&data->iommu);
 697         iommu_device_unregister(&data->iommu);
 698
 699         list_del(&data->list);
 700
 701         clk_disable_unprepare(data->bclk);
 702         devm_free_irq(&pdev->dev, data->irq, data);
 703         component_master_del(&pdev->dev, &mtk_iommu_com_ops);
 704         return 0;
 705 }
 706
 707 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 708 {
 709         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 710         struct mtk_iommu_suspend_reg *reg = &data->reg;
 711         void __iomem *base = data->base;
 712
 713         reg->standard_axi_mode = readl_relaxed(base +
 714                                                REG_MMU_STANDARD_AXI_MODE);
 715         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
 716         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
 717         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 718         reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
 719         reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
 720         clk_disable_unprepare(data->bclk);
 721         return 0;
 722 }
 723
 724 static int __maybe_unused mtk_iommu_resume(struct device *dev)
 725 {
 726         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 727         struct mtk_iommu_suspend_reg *reg = &data->reg;
 728         void __iomem *base = data->base;
 729         int ret;
 730
 731         ret = clk_prepare_enable(data->bclk);
 732         if (ret) {
 733                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 734                 return ret;
 735         }
 736         writel_relaxed(reg->standard_axi_mode,
 737                        base + REG_MMU_STANDARD_AXI_MODE);
 738         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
 739         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
 740         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
 741         writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
 742         writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
 743         if (data->m4u_dom)
 744                 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
 745                        base + REG_MMU_PT_BASE_ADDR);
 746         return 0;
 747 }
 748
 749 static const struct dev_pm_ops mtk_iommu_pm_ops = {
 750         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
 751 };
 752
 753 static const struct of_device_id mtk_iommu_of_ids[] = {
 754         { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},
 755         { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},
 756         {}
 757 };
 758
 759 static struct platform_driver mtk_iommu_driver = {
 760         .probe  = mtk_iommu_probe,
 761         .remove = mtk_iommu_remove,
 762         .driver = {
 763                 .name = "mtk-iommu",
 764                 .of_match_table = of_match_ptr(mtk_iommu_of_ids),
 765                 .pm = &mtk_iommu_pm_ops,
 766         }
 767 };
 768
 769 static int __init mtk_iommu_init(void)
 770 {
 771         int ret;
 772
 773         ret = platform_driver_register(&mtk_iommu_driver);
 774         if (ret != 0)
 775                 pr_err("Failed to register MTK IOMMU driver\n");
 776
 777         return ret;
 778 }
 779
 780 subsys_initcall(mtk_iommu_init)