1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic ARM page table allocator.
5 * Copyright (C) 2014 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
12 #include <linux/atomic.h>
13 #include <linux/bitops.h>
14 #include <linux/io-pgtable.h>
15 #include <linux/kernel.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 #include <linux/types.h>
19 #include <linux/dma-mapping.h>
21 #include <asm/barrier.h>
23 #define ARM_LPAE_MAX_ADDR_BITS 52
24 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
25 #define ARM_LPAE_MAX_LEVELS 4
27 /* Struct accessors */
28 #define io_pgtable_to_data(x) \
29 container_of((x), struct arm_lpae_io_pgtable, iop)
31 #define io_pgtable_ops_to_data(x) \
32 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
35 * For consistency with the architecture, we always consider
36 * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
38 #define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
41 * Calculate the right shift amount to get to the portion describing level l
42 * in a virtual address mapped by the pagetable in d.
44 #define ARM_LPAE_LVL_SHIFT(l,d) \
45 ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
46 * (d)->bits_per_level) + (d)->pg_shift)
48 #define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift)
50 #define ARM_LPAE_PAGES_PER_PGD(d) \
51 DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d))
54 * Calculate the index at level l used to map virtual address a using the
57 #define ARM_LPAE_PGD_IDX(l,d) \
58 ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
60 #define ARM_LPAE_LVL_IDX(a,l,d) \
61 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
62 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
64 /* Calculate the block/page mapping size at level l for pagetable in d. */
65 #define ARM_LPAE_BLOCK_SIZE(l,d) \
66 (1ULL << (ilog2(sizeof(arm_lpae_iopte)) + \
67 ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
70 #define ARM_LPAE_PTE_TYPE_SHIFT 0
71 #define ARM_LPAE_PTE_TYPE_MASK 0x3
73 #define ARM_LPAE_PTE_TYPE_BLOCK 1
74 #define ARM_LPAE_PTE_TYPE_TABLE 3
75 #define ARM_LPAE_PTE_TYPE_PAGE 3
77 #define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
79 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
80 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
81 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
82 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
83 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
84 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
85 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
86 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
88 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
89 /* Ignore the contiguous bit for block splitting */
90 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
91 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
92 ARM_LPAE_PTE_ATTR_HI_MASK)
93 /* Software bit for solving coherency races */
94 #define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
97 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
98 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
99 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
100 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
103 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
104 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
105 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
106 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
107 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
108 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
111 #define ARM_32_LPAE_TCR_EAE (1 << 31)
112 #define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
114 #define ARM_LPAE_TCR_EPD1 (1 << 23)
116 #define ARM_LPAE_TCR_TG0_4K (0 << 14)
117 #define ARM_LPAE_TCR_TG0_64K (1 << 14)
118 #define ARM_LPAE_TCR_TG0_16K (2 << 14)
120 #define ARM_LPAE_TCR_SH0_SHIFT 12
121 #define ARM_LPAE_TCR_SH0_MASK 0x3
122 #define ARM_LPAE_TCR_SH_NS 0
123 #define ARM_LPAE_TCR_SH_OS 2
124 #define ARM_LPAE_TCR_SH_IS 3
126 #define ARM_LPAE_TCR_ORGN0_SHIFT 10
127 #define ARM_LPAE_TCR_IRGN0_SHIFT 8
128 #define ARM_LPAE_TCR_RGN_MASK 0x3
129 #define ARM_LPAE_TCR_RGN_NC 0
130 #define ARM_LPAE_TCR_RGN_WBWA 1
131 #define ARM_LPAE_TCR_RGN_WT 2
132 #define ARM_LPAE_TCR_RGN_WB 3
134 #define ARM_LPAE_TCR_SL0_SHIFT 6
135 #define ARM_LPAE_TCR_SL0_MASK 0x3
137 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
138 #define ARM_LPAE_TCR_SZ_MASK 0xf
140 #define ARM_LPAE_TCR_PS_SHIFT 16
141 #define ARM_LPAE_TCR_PS_MASK 0x7
143 #define ARM_LPAE_TCR_IPS_SHIFT 32
144 #define ARM_LPAE_TCR_IPS_MASK 0x7
146 #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
147 #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
148 #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
149 #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
150 #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
151 #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
152 #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
154 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
155 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
156 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
157 #define ARM_LPAE_MAIR_ATTR_NC 0x44
158 #define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4
159 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
160 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
161 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
162 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
163 #define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3
165 #define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
166 #define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
167 #define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
169 #define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL
170 #define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
172 /* IOPTE accessors */
173 #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
175 #define iopte_type(pte,l) \
176 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
178 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
180 struct arm_lpae_io_pgtable {
181 struct io_pgtable iop;
185 unsigned long pg_shift;
186 unsigned long bits_per_level;
191 typedef u64 arm_lpae_iopte;
193 static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl,
194 enum io_pgtable_fmt fmt)
196 if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE)
197 return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_PAGE;
199 return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_BLOCK;
202 static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
203 struct arm_lpae_io_pgtable *data)
205 arm_lpae_iopte pte = paddr;
207 /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
208 return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
211 static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
212 struct arm_lpae_io_pgtable *data)
214 u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
216 if (data->pg_shift < 16)
219 /* Rotate the packed high-order bits back to the top */
220 return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
223 static bool selftest_running = false;
225 static dma_addr_t __arm_lpae_dma_addr(void *pages)
227 return (dma_addr_t)virt_to_phys(pages);
230 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
231 struct io_pgtable_cfg *cfg)
233 struct device *dev = cfg->iommu_dev;
234 int order = get_order(size);
239 VM_BUG_ON((gfp & __GFP_HIGHMEM));
240 p = alloc_pages_node(dev ? dev_to_node(dev) : NUMA_NO_NODE,
241 gfp | __GFP_ZERO, order);
245 pages = page_address(p);
246 if (!cfg->coherent_walk) {
247 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
248 if (dma_mapping_error(dev, dma))
251 * We depend on the IOMMU being able to work with any physical
252 * address directly, so if the DMA layer suggests otherwise by
253 * translating or truncating them, that bodes very badly...
255 if (dma != virt_to_phys(pages))
262 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
263 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
265 __free_pages(p, order);
269 static void __arm_lpae_free_pages(void *pages, size_t size,
270 struct io_pgtable_cfg *cfg)
272 if (!cfg->coherent_walk)
273 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
274 size, DMA_TO_DEVICE);
275 free_pages((unsigned long)pages, get_order(size));
278 static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep,
279 struct io_pgtable_cfg *cfg)
281 dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
282 sizeof(*ptep), DMA_TO_DEVICE);
285 static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
286 struct io_pgtable_cfg *cfg)
290 if (!cfg->coherent_walk)
291 __arm_lpae_sync_pte(ptep, cfg);
294 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
295 struct iommu_iotlb_gather *gather,
296 unsigned long iova, size_t size, int lvl,
297 arm_lpae_iopte *ptep);
299 static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
300 phys_addr_t paddr, arm_lpae_iopte prot,
301 int lvl, arm_lpae_iopte *ptep)
303 arm_lpae_iopte pte = prot;
305 if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
306 pte |= ARM_LPAE_PTE_NS;
308 if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1)
309 pte |= ARM_LPAE_PTE_TYPE_PAGE;
311 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
313 if (data->iop.fmt != ARM_MALI_LPAE)
314 pte |= ARM_LPAE_PTE_AF;
315 pte |= ARM_LPAE_PTE_SH_IS;
316 pte |= paddr_to_iopte(paddr, data);
318 __arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
321 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
322 unsigned long iova, phys_addr_t paddr,
323 arm_lpae_iopte prot, int lvl,
324 arm_lpae_iopte *ptep)
326 arm_lpae_iopte pte = *ptep;
328 if (iopte_leaf(pte, lvl, data->iop.fmt)) {
329 /* We require an unmap first */
330 WARN_ON(!selftest_running);
332 } else if (iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
334 * We need to unmap and free the old table before
335 * overwriting it with a block entry.
337 arm_lpae_iopte *tblp;
338 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
340 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
341 if (__arm_lpae_unmap(data, NULL, iova, sz, lvl, tblp) != sz) {
347 __arm_lpae_init_pte(data, paddr, prot, lvl, ptep);
351 static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
352 arm_lpae_iopte *ptep,
354 struct arm_lpae_io_pgtable *data)
356 arm_lpae_iopte old, new;
357 struct io_pgtable_cfg *cfg = &data->iop.cfg;
359 new = paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE;
360 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
361 new |= ARM_LPAE_PTE_NSTABLE;
364 * Ensure the table itself is visible before its PTE can be.
365 * Whilst we could get away with cmpxchg64_release below, this
366 * doesn't have any ordering semantics when !CONFIG_SMP.
370 old = cmpxchg64_relaxed(ptep, curr, new);
372 if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC))
375 /* Even if it's not ours, there's no point waiting; just kick it */
376 __arm_lpae_sync_pte(ptep, cfg);
378 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
383 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
384 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
385 int lvl, arm_lpae_iopte *ptep)
387 arm_lpae_iopte *cptep, pte;
388 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
389 size_t tblsz = ARM_LPAE_GRANULE(data);
390 struct io_pgtable_cfg *cfg = &data->iop.cfg;
392 /* Find our entry at the current level */
393 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
395 /* If we can install a leaf entry at this level, then do so */
396 if (size == block_size && (size & cfg->pgsize_bitmap))
397 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
399 /* We can't allocate tables at the final level */
400 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
403 /* Grab a pointer to the next level */
404 pte = READ_ONCE(*ptep);
406 cptep = __arm_lpae_alloc_pages(tblsz, GFP_ATOMIC, cfg);
410 pte = arm_lpae_install_table(cptep, ptep, 0, data);
412 __arm_lpae_free_pages(cptep, tblsz, cfg);
413 } else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) {
414 __arm_lpae_sync_pte(ptep, cfg);
417 if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) {
418 cptep = iopte_deref(pte, data);
420 /* We require an unmap first */
421 WARN_ON(!selftest_running);
426 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
429 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
434 if (data->iop.fmt == ARM_64_LPAE_S1 ||
435 data->iop.fmt == ARM_32_LPAE_S1) {
436 pte = ARM_LPAE_PTE_nG;
437 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
438 pte |= ARM_LPAE_PTE_AP_RDONLY;
439 if (!(prot & IOMMU_PRIV))
440 pte |= ARM_LPAE_PTE_AP_UNPRIV;
442 pte = ARM_LPAE_PTE_HAP_FAULT;
443 if (prot & IOMMU_READ)
444 pte |= ARM_LPAE_PTE_HAP_READ;
445 if (prot & IOMMU_WRITE)
446 pte |= ARM_LPAE_PTE_HAP_WRITE;
450 * Note that this logic is structured to accommodate Mali LPAE
451 * having stage-1-like attributes but stage-2-like permissions.
453 if (data->iop.fmt == ARM_64_LPAE_S2 ||
454 data->iop.fmt == ARM_32_LPAE_S2) {
455 if (prot & IOMMU_MMIO)
456 pte |= ARM_LPAE_PTE_MEMATTR_DEV;
457 else if (prot & IOMMU_CACHE)
458 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
460 pte |= ARM_LPAE_PTE_MEMATTR_NC;
462 if (prot & IOMMU_MMIO)
463 pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
464 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
465 else if (prot & IOMMU_CACHE)
466 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
467 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
468 else if (prot & IOMMU_QCOM_SYS_CACHE)
469 pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
470 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
473 if (prot & IOMMU_NOEXEC)
474 pte |= ARM_LPAE_PTE_XN;
479 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
480 phys_addr_t paddr, size_t size, int iommu_prot)
482 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
483 arm_lpae_iopte *ptep = data->pgd;
484 int ret, lvl = ARM_LPAE_START_LVL(data);
487 /* If no access, then nothing to do */
488 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
491 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
492 paddr >= (1ULL << data->iop.cfg.oas)))
495 prot = arm_lpae_prot_to_pte(data, iommu_prot);
496 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
498 * Synchronise all PTE updates for the new mapping before there's
499 * a chance for anything to kick off a table walk for the new iova.
506 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
507 arm_lpae_iopte *ptep)
509 arm_lpae_iopte *start, *end;
510 unsigned long table_size;
512 if (lvl == ARM_LPAE_START_LVL(data))
513 table_size = data->pgd_size;
515 table_size = ARM_LPAE_GRANULE(data);
519 /* Only leaf entries at the last level */
520 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
523 end = (void *)ptep + table_size;
525 while (ptep != end) {
526 arm_lpae_iopte pte = *ptep++;
528 if (!pte || iopte_leaf(pte, lvl, data->iop.fmt))
531 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
534 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
537 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
539 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
541 __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
545 static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
546 struct iommu_iotlb_gather *gather,
547 unsigned long iova, size_t size,
548 arm_lpae_iopte blk_pte, int lvl,
549 arm_lpae_iopte *ptep)
551 struct io_pgtable_cfg *cfg = &data->iop.cfg;
552 arm_lpae_iopte pte, *tablep;
553 phys_addr_t blk_paddr;
554 size_t tablesz = ARM_LPAE_GRANULE(data);
555 size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
556 int i, unmap_idx = -1;
558 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
561 tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);
563 return 0; /* Bytes unmapped */
565 if (size == split_sz)
566 unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
568 blk_paddr = iopte_to_paddr(blk_pte, data);
569 pte = iopte_prot(blk_pte);
571 for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
576 __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]);
579 pte = arm_lpae_install_table(tablep, ptep, blk_pte, data);
580 if (pte != blk_pte) {
581 __arm_lpae_free_pages(tablep, tablesz, cfg);
583 * We may race against someone unmapping another part of this
584 * block, but anything else is invalid. We can't misinterpret
585 * a page entry here since we're never at the last level.
587 if (iopte_type(pte, lvl - 1) != ARM_LPAE_PTE_TYPE_TABLE)
590 tablep = iopte_deref(pte, data);
591 } else if (unmap_idx >= 0) {
592 io_pgtable_tlb_add_page(&data->iop, gather, iova, size);
596 return __arm_lpae_unmap(data, gather, iova, size, lvl, tablep);
599 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
600 struct iommu_iotlb_gather *gather,
601 unsigned long iova, size_t size, int lvl,
602 arm_lpae_iopte *ptep)
605 struct io_pgtable *iop = &data->iop;
607 /* Something went horribly wrong and we ran out of page table */
608 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
611 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
612 pte = READ_ONCE(*ptep);
616 /* If the size matches this level, we're in the right place */
617 if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
618 __arm_lpae_set_pte(ptep, 0, &iop->cfg);
620 if (!iopte_leaf(pte, lvl, iop->fmt)) {
621 /* Also flush any partial walks */
622 io_pgtable_tlb_flush_walk(iop, iova, size,
623 ARM_LPAE_GRANULE(data));
624 ptep = iopte_deref(pte, data);
625 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
626 } else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
628 * Order the PTE update against queueing the IOVA, to
629 * guarantee that a flush callback from a different CPU
630 * has observed it before the TLBIALL can be issued.
634 io_pgtable_tlb_add_page(iop, gather, iova, size);
638 } else if (iopte_leaf(pte, lvl, iop->fmt)) {
640 * Insert a table at the next level to map the old region,
641 * minus the part we want to unmap
643 return arm_lpae_split_blk_unmap(data, gather, iova, size, pte,
647 /* Keep on walkin' */
648 ptep = iopte_deref(pte, data);
649 return __arm_lpae_unmap(data, gather, iova, size, lvl + 1, ptep);
652 static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
653 size_t size, struct iommu_iotlb_gather *gather)
655 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
656 arm_lpae_iopte *ptep = data->pgd;
657 int lvl = ARM_LPAE_START_LVL(data);
659 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
662 return __arm_lpae_unmap(data, gather, iova, size, lvl, ptep);
665 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
668 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
669 arm_lpae_iopte pte, *ptep = data->pgd;
670 int lvl = ARM_LPAE_START_LVL(data);
673 /* Valid IOPTE pointer? */
677 /* Grab the IOPTE we're interested in */
678 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
679 pte = READ_ONCE(*ptep);
686 if (iopte_leaf(pte, lvl, data->iop.fmt))
687 goto found_translation;
689 /* Take it to the next level */
690 ptep = iopte_deref(pte, data);
691 } while (++lvl < ARM_LPAE_MAX_LEVELS);
693 /* Ran out of page tables to walk */
697 iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
698 return iopte_to_paddr(pte, data) | iova;
701 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
703 unsigned long granule, page_sizes;
704 unsigned int max_addr_bits = 48;
707 * We need to restrict the supported page sizes to match the
708 * translation regime for a particular granule. Aim to match
709 * the CPU page size if possible, otherwise prefer smaller sizes.
710 * While we're at it, restrict the block sizes to match the
713 if (cfg->pgsize_bitmap & PAGE_SIZE)
715 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
716 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
717 else if (cfg->pgsize_bitmap & PAGE_MASK)
718 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
724 page_sizes = (SZ_4K | SZ_2M | SZ_1G);
727 page_sizes = (SZ_16K | SZ_32M);
731 page_sizes = (SZ_64K | SZ_512M);
733 page_sizes |= 1ULL << 42; /* 4TB */
739 cfg->pgsize_bitmap &= page_sizes;
740 cfg->ias = min(cfg->ias, max_addr_bits);
741 cfg->oas = min(cfg->oas, max_addr_bits);
744 static struct arm_lpae_io_pgtable *
745 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
747 unsigned long va_bits, pgd_bits;
748 struct arm_lpae_io_pgtable *data;
750 arm_lpae_restrict_pgsizes(cfg);
752 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
755 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
758 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
761 if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) {
762 dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n");
766 data = kmalloc(sizeof(*data), GFP_KERNEL);
770 data->pg_shift = __ffs(cfg->pgsize_bitmap);
771 data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
773 va_bits = cfg->ias - data->pg_shift;
774 data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
776 /* Calculate the actual size of our pgd (without concatenation) */
777 pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
778 data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
780 data->iop.ops = (struct io_pgtable_ops) {
782 .unmap = arm_lpae_unmap,
783 .iova_to_phys = arm_lpae_iova_to_phys,
789 static struct io_pgtable *
790 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
793 struct arm_lpae_io_pgtable *data;
795 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
796 IO_PGTABLE_QUIRK_NON_STRICT))
799 data = arm_lpae_alloc_pgtable(cfg);
804 if (cfg->coherent_walk) {
805 reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
806 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
807 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
809 reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |
810 (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |
811 (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);
814 switch (ARM_LPAE_GRANULE(data)) {
816 reg |= ARM_LPAE_TCR_TG0_4K;
819 reg |= ARM_LPAE_TCR_TG0_16K;
822 reg |= ARM_LPAE_TCR_TG0_64K;
828 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
831 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
834 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
837 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
840 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
843 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
846 reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_IPS_SHIFT);
852 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
854 /* Disable speculative walks through TTBR1 */
855 reg |= ARM_LPAE_TCR_EPD1;
856 cfg->arm_lpae_s1_cfg.tcr = reg;
859 reg = (ARM_LPAE_MAIR_ATTR_NC
860 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
861 (ARM_LPAE_MAIR_ATTR_WBRWA
862 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
863 (ARM_LPAE_MAIR_ATTR_DEVICE
864 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) |
865 (ARM_LPAE_MAIR_ATTR_INC_OWBRWA
866 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));
868 cfg->arm_lpae_s1_cfg.mair[0] = reg;
869 cfg->arm_lpae_s1_cfg.mair[1] = 0;
871 /* Looking good; allocate a pgd */
872 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
876 /* Ensure the empty pgd is visible before any actual TTBR write */
880 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
881 cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
889 static struct io_pgtable *
890 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
893 struct arm_lpae_io_pgtable *data;
895 /* The NS quirk doesn't apply at stage 2 */
896 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT))
899 data = arm_lpae_alloc_pgtable(cfg);
904 * Concatenate PGDs at level 1 if possible in order to reduce
905 * the depth of the stage-2 walk.
907 if (data->levels == ARM_LPAE_MAX_LEVELS) {
908 unsigned long pgd_pages;
910 pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
911 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
912 data->pgd_size = pgd_pages << data->pg_shift;
918 reg = ARM_64_LPAE_S2_TCR_RES1 |
919 (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
920 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
921 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
923 sl = ARM_LPAE_START_LVL(data);
925 switch (ARM_LPAE_GRANULE(data)) {
927 reg |= ARM_LPAE_TCR_TG0_4K;
928 sl++; /* SL0 format is different for 4K granule size */
931 reg |= ARM_LPAE_TCR_TG0_16K;
934 reg |= ARM_LPAE_TCR_TG0_64K;
940 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
943 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
946 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
949 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
952 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
955 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
958 reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT);
964 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
965 reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
966 cfg->arm_lpae_s2_cfg.vtcr = reg;
968 /* Allocate pgd pages */
969 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
973 /* Ensure the empty pgd is visible before any actual TTBR write */
977 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
985 static struct io_pgtable *
986 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
988 struct io_pgtable *iop;
990 if (cfg->ias > 32 || cfg->oas > 40)
993 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
994 iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
996 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
997 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
1003 static struct io_pgtable *
1004 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
1006 struct io_pgtable *iop;
1008 if (cfg->ias > 40 || cfg->oas > 40)
1011 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1012 iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
1014 cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
1019 static struct io_pgtable *
1020 arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
1022 struct arm_lpae_io_pgtable *data;
1024 /* No quirks for Mali (hopefully) */
1028 if (cfg->ias > 48 || cfg->oas > 40)
1031 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1033 data = arm_lpae_alloc_pgtable(cfg);
1037 /* Mali seems to need a full 4-level table regardless of IAS */
1038 if (data->levels < ARM_LPAE_MAX_LEVELS) {
1039 data->levels = ARM_LPAE_MAX_LEVELS;
1040 data->pgd_size = sizeof(arm_lpae_iopte);
1043 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
1044 * best we can do is mimic the out-of-tree driver and hope that the
1045 * "implementation-defined caching policy" is good enough. Similarly,
1046 * we'll use it for the sake of a valid attribute for our 'device'
1047 * index, although callers should never request that in practice.
1049 cfg->arm_mali_lpae_cfg.memattr =
1050 (ARM_MALI_LPAE_MEMATTR_IMP_DEF
1051 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
1052 (ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
1053 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
1054 (ARM_MALI_LPAE_MEMATTR_IMP_DEF
1055 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
1057 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
1061 /* Ensure the empty pgd is visible before TRANSTAB can be written */
1064 cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
1065 ARM_MALI_LPAE_TTBR_READ_INNER |
1066 ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
1074 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
1075 .alloc = arm_64_lpae_alloc_pgtable_s1,
1076 .free = arm_lpae_free_pgtable,
1079 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
1080 .alloc = arm_64_lpae_alloc_pgtable_s2,
1081 .free = arm_lpae_free_pgtable,
1084 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
1085 .alloc = arm_32_lpae_alloc_pgtable_s1,
1086 .free = arm_lpae_free_pgtable,
1089 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
1090 .alloc = arm_32_lpae_alloc_pgtable_s2,
1091 .free = arm_lpae_free_pgtable,
1094 struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = {
1095 .alloc = arm_mali_lpae_alloc_pgtable,
1096 .free = arm_lpae_free_pgtable,
1099 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
1101 static struct io_pgtable_cfg *cfg_cookie;
1103 static void dummy_tlb_flush_all(void *cookie)
1105 WARN_ON(cookie != cfg_cookie);
1108 static void dummy_tlb_flush(unsigned long iova, size_t size, size_t granule,
1111 WARN_ON(cookie != cfg_cookie);
1112 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
1115 static void dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
1116 unsigned long iova, size_t granule, void *cookie)
1118 dummy_tlb_flush(iova, granule, granule, cookie);
1121 static const struct iommu_flush_ops dummy_tlb_ops __initconst = {
1122 .tlb_flush_all = dummy_tlb_flush_all,
1123 .tlb_flush_walk = dummy_tlb_flush,
1124 .tlb_flush_leaf = dummy_tlb_flush,
1125 .tlb_add_page = dummy_tlb_add_page,
1128 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
1130 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
1131 struct io_pgtable_cfg *cfg = &data->iop.cfg;
1133 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
1134 cfg->pgsize_bitmap, cfg->ias);
1135 pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
1136 data->levels, data->pgd_size, data->pg_shift,
1137 data->bits_per_level, data->pgd);
1140 #define __FAIL(ops, i) ({ \
1141 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
1142 arm_lpae_dump_ops(ops); \
1143 selftest_running = false; \
1147 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
1149 static const enum io_pgtable_fmt fmts[] = {
1157 struct io_pgtable_ops *ops;
1159 selftest_running = true;
1161 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
1163 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
1165 pr_err("selftest: failed to allocate io pgtable ops\n");
1170 * Initial sanity checks.
1171 * Empty page tables shouldn't provide any translations.
1173 if (ops->iova_to_phys(ops, 42))
1174 return __FAIL(ops, i);
1176 if (ops->iova_to_phys(ops, SZ_1G + 42))
1177 return __FAIL(ops, i);
1179 if (ops->iova_to_phys(ops, SZ_2G + 42))
1180 return __FAIL(ops, i);
1183 * Distinct mappings of different granule sizes.
1186 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1189 if (ops->map(ops, iova, iova, size, IOMMU_READ |
1193 return __FAIL(ops, i);
1195 /* Overlapping mappings */
1196 if (!ops->map(ops, iova, iova + size, size,
1197 IOMMU_READ | IOMMU_NOEXEC))
1198 return __FAIL(ops, i);
1200 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1201 return __FAIL(ops, i);
1207 size = 1UL << __ffs(cfg->pgsize_bitmap);
1208 if (ops->unmap(ops, SZ_1G + size, size, NULL) != size)
1209 return __FAIL(ops, i);
1211 /* Remap of partial unmap */
1212 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
1213 return __FAIL(ops, i);
1215 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1216 return __FAIL(ops, i);
1220 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1223 if (ops->unmap(ops, iova, size, NULL) != size)
1224 return __FAIL(ops, i);
1226 if (ops->iova_to_phys(ops, iova + 42))
1227 return __FAIL(ops, i);
1229 /* Remap full block */
1230 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
1231 return __FAIL(ops, i);
1233 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1234 return __FAIL(ops, i);
1239 free_io_pgtable_ops(ops);
1242 selftest_running = false;
1246 static int __init arm_lpae_do_selftests(void)
1248 static const unsigned long pgsize[] = {
1249 SZ_4K | SZ_2M | SZ_1G,
1254 static const unsigned int ias[] = {
1255 32, 36, 40, 42, 44, 48,
1258 int i, j, pass = 0, fail = 0;
1259 struct io_pgtable_cfg cfg = {
1260 .tlb = &dummy_tlb_ops,
1262 .coherent_walk = true,
1265 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1266 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1267 cfg.pgsize_bitmap = pgsize[i];
1269 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1271 if (arm_lpae_run_tests(&cfg))
1278 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1279 return fail ? -EFAULT : 0;
1281 subsys_initcall(arm_lpae_do_selftests);