2 * CPU-agnostic ARM page table allocator.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2014 ARM Limited
18 * Author: Will Deacon <will.deacon@arm.com>
21 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
23 #include <linux/atomic.h>
24 #include <linux/bitops.h>
25 #include <linux/iommu.h>
26 #include <linux/kernel.h>
27 #include <linux/sizes.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
30 #include <linux/dma-mapping.h>
32 #include <asm/barrier.h>
34 #include "io-pgtable.h"
36 #define ARM_LPAE_MAX_ADDR_BITS 52
37 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
38 #define ARM_LPAE_MAX_LEVELS 4
40 /* Struct accessors */
41 #define io_pgtable_to_data(x) \
42 container_of((x), struct arm_lpae_io_pgtable, iop)
44 #define io_pgtable_ops_to_data(x) \
45 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
48 * For consistency with the architecture, we always consider
49 * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
51 #define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
54 * Calculate the right shift amount to get to the portion describing level l
55 * in a virtual address mapped by the pagetable in d.
57 #define ARM_LPAE_LVL_SHIFT(l,d) \
58 ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
59 * (d)->bits_per_level) + (d)->pg_shift)
61 #define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift)
63 #define ARM_LPAE_PAGES_PER_PGD(d) \
64 DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d))
67 * Calculate the index at level l used to map virtual address a using the
70 #define ARM_LPAE_PGD_IDX(l,d) \
71 ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
73 #define ARM_LPAE_LVL_IDX(a,l,d) \
74 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
75 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
77 /* Calculate the block/page mapping size at level l for pagetable in d. */
78 #define ARM_LPAE_BLOCK_SIZE(l,d) \
79 (1ULL << (ilog2(sizeof(arm_lpae_iopte)) + \
80 ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
83 #define ARM_LPAE_PTE_TYPE_SHIFT 0
84 #define ARM_LPAE_PTE_TYPE_MASK 0x3
86 #define ARM_LPAE_PTE_TYPE_BLOCK 1
87 #define ARM_LPAE_PTE_TYPE_TABLE 3
88 #define ARM_LPAE_PTE_TYPE_PAGE 3
90 #define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
92 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
93 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
94 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
95 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
96 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
97 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
98 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
99 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
101 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
102 /* Ignore the contiguous bit for block splitting */
103 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
104 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
105 ARM_LPAE_PTE_ATTR_HI_MASK)
106 /* Software bit for solving coherency races */
107 #define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
110 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
111 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
112 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
113 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
116 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
117 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
118 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
119 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
120 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
121 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
124 #define ARM_32_LPAE_TCR_EAE (1 << 31)
125 #define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
127 #define ARM_LPAE_TCR_EPD1 (1 << 23)
129 #define ARM_LPAE_TCR_TG0_4K (0 << 14)
130 #define ARM_LPAE_TCR_TG0_64K (1 << 14)
131 #define ARM_LPAE_TCR_TG0_16K (2 << 14)
133 #define ARM_LPAE_TCR_SH0_SHIFT 12
134 #define ARM_LPAE_TCR_SH0_MASK 0x3
135 #define ARM_LPAE_TCR_SH_NS 0
136 #define ARM_LPAE_TCR_SH_OS 2
137 #define ARM_LPAE_TCR_SH_IS 3
139 #define ARM_LPAE_TCR_ORGN0_SHIFT 10
140 #define ARM_LPAE_TCR_IRGN0_SHIFT 8
141 #define ARM_LPAE_TCR_RGN_MASK 0x3
142 #define ARM_LPAE_TCR_RGN_NC 0
143 #define ARM_LPAE_TCR_RGN_WBWA 1
144 #define ARM_LPAE_TCR_RGN_WT 2
145 #define ARM_LPAE_TCR_RGN_WB 3
147 #define ARM_LPAE_TCR_SL0_SHIFT 6
148 #define ARM_LPAE_TCR_SL0_MASK 0x3
150 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
151 #define ARM_LPAE_TCR_SZ_MASK 0xf
153 #define ARM_LPAE_TCR_PS_SHIFT 16
154 #define ARM_LPAE_TCR_PS_MASK 0x7
156 #define ARM_LPAE_TCR_IPS_SHIFT 32
157 #define ARM_LPAE_TCR_IPS_MASK 0x7
159 #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
160 #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
161 #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
162 #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
163 #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
164 #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
165 #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
167 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
168 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
169 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
170 #define ARM_LPAE_MAIR_ATTR_NC 0x44
171 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
172 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
173 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
174 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
176 /* IOPTE accessors */
177 #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
179 #define iopte_type(pte,l) \
180 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
182 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
184 #define iopte_leaf(pte,l) \
185 (l == (ARM_LPAE_MAX_LEVELS - 1) ? \
186 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
187 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
189 struct arm_lpae_io_pgtable {
190 struct io_pgtable iop;
194 unsigned long pg_shift;
195 unsigned long bits_per_level;
200 typedef u64 arm_lpae_iopte;
202 static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
203 struct arm_lpae_io_pgtable *data)
205 arm_lpae_iopte pte = paddr;
207 /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
208 return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
211 static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
212 struct arm_lpae_io_pgtable *data)
214 u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
216 if (data->pg_shift < 16)
219 /* Rotate the packed high-order bits back to the top */
220 return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
223 static bool selftest_running = false;
225 static dma_addr_t __arm_lpae_dma_addr(void *pages)
227 return (dma_addr_t)virt_to_phys(pages);
230 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
231 struct io_pgtable_cfg *cfg)
233 struct device *dev = cfg->iommu_dev;
234 int order = get_order(size);
239 VM_BUG_ON((gfp & __GFP_HIGHMEM));
240 p = alloc_pages_node(dev ? dev_to_node(dev) : NUMA_NO_NODE,
241 gfp | __GFP_ZERO, order);
245 pages = page_address(p);
246 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA)) {
247 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
248 if (dma_mapping_error(dev, dma))
251 * We depend on the IOMMU being able to work with any physical
252 * address directly, so if the DMA layer suggests otherwise by
253 * translating or truncating them, that bodes very badly...
255 if (dma != virt_to_phys(pages))
262 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
263 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
265 __free_pages(p, order);
269 static void __arm_lpae_free_pages(void *pages, size_t size,
270 struct io_pgtable_cfg *cfg)
272 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
273 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
274 size, DMA_TO_DEVICE);
275 free_pages((unsigned long)pages, get_order(size));
278 static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep,
279 struct io_pgtable_cfg *cfg)
281 dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
282 sizeof(*ptep), DMA_TO_DEVICE);
285 static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
286 struct io_pgtable_cfg *cfg)
290 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
291 __arm_lpae_sync_pte(ptep, cfg);
294 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
295 unsigned long iova, size_t size, int lvl,
296 arm_lpae_iopte *ptep);
298 static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
299 phys_addr_t paddr, arm_lpae_iopte prot,
300 int lvl, arm_lpae_iopte *ptep)
302 arm_lpae_iopte pte = prot;
304 if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
305 pte |= ARM_LPAE_PTE_NS;
307 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
308 pte |= ARM_LPAE_PTE_TYPE_PAGE;
310 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
312 pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
313 pte |= paddr_to_iopte(paddr, data);
315 __arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
318 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
319 unsigned long iova, phys_addr_t paddr,
320 arm_lpae_iopte prot, int lvl,
321 arm_lpae_iopte *ptep)
323 arm_lpae_iopte pte = *ptep;
325 if (iopte_leaf(pte, lvl)) {
326 /* We require an unmap first */
327 WARN_ON(!selftest_running);
329 } else if (iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
331 * We need to unmap and free the old table before
332 * overwriting it with a block entry.
334 arm_lpae_iopte *tblp;
335 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
337 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
338 if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz))
342 __arm_lpae_init_pte(data, paddr, prot, lvl, ptep);
346 static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
347 arm_lpae_iopte *ptep,
349 struct arm_lpae_io_pgtable *data)
351 arm_lpae_iopte old, new;
352 struct io_pgtable_cfg *cfg = &data->iop.cfg;
354 new = paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE;
355 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
356 new |= ARM_LPAE_PTE_NSTABLE;
359 * Ensure the table itself is visible before its PTE can be.
360 * Whilst we could get away with cmpxchg64_release below, this
361 * doesn't have any ordering semantics when !CONFIG_SMP.
365 old = cmpxchg64_relaxed(ptep, curr, new);
367 if ((cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) ||
368 (old & ARM_LPAE_PTE_SW_SYNC))
371 /* Even if it's not ours, there's no point waiting; just kick it */
372 __arm_lpae_sync_pte(ptep, cfg);
374 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
379 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
380 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
381 int lvl, arm_lpae_iopte *ptep)
383 arm_lpae_iopte *cptep, pte;
384 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
385 size_t tblsz = ARM_LPAE_GRANULE(data);
386 struct io_pgtable_cfg *cfg = &data->iop.cfg;
388 /* Find our entry at the current level */
389 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
391 /* If we can install a leaf entry at this level, then do so */
392 if (size == block_size && (size & cfg->pgsize_bitmap))
393 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
395 /* We can't allocate tables at the final level */
396 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
399 /* Grab a pointer to the next level */
400 pte = READ_ONCE(*ptep);
402 cptep = __arm_lpae_alloc_pages(tblsz, GFP_ATOMIC, cfg);
406 pte = arm_lpae_install_table(cptep, ptep, 0, data);
408 __arm_lpae_free_pages(cptep, tblsz, cfg);
409 } else if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) &&
410 !(pte & ARM_LPAE_PTE_SW_SYNC)) {
411 __arm_lpae_sync_pte(ptep, cfg);
414 if (pte && !iopte_leaf(pte, lvl)) {
415 cptep = iopte_deref(pte, data);
417 /* We require an unmap first */
418 WARN_ON(!selftest_running);
423 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
426 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
431 if (data->iop.fmt == ARM_64_LPAE_S1 ||
432 data->iop.fmt == ARM_32_LPAE_S1) {
433 pte = ARM_LPAE_PTE_nG;
435 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
436 pte |= ARM_LPAE_PTE_AP_RDONLY;
438 if (!(prot & IOMMU_PRIV))
439 pte |= ARM_LPAE_PTE_AP_UNPRIV;
441 if (prot & IOMMU_MMIO)
442 pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
443 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
444 else if (prot & IOMMU_CACHE)
445 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
446 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
448 pte = ARM_LPAE_PTE_HAP_FAULT;
449 if (prot & IOMMU_READ)
450 pte |= ARM_LPAE_PTE_HAP_READ;
451 if (prot & IOMMU_WRITE)
452 pte |= ARM_LPAE_PTE_HAP_WRITE;
453 if (prot & IOMMU_MMIO)
454 pte |= ARM_LPAE_PTE_MEMATTR_DEV;
455 else if (prot & IOMMU_CACHE)
456 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
458 pte |= ARM_LPAE_PTE_MEMATTR_NC;
461 if (prot & IOMMU_NOEXEC)
462 pte |= ARM_LPAE_PTE_XN;
467 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
468 phys_addr_t paddr, size_t size, int iommu_prot)
470 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
471 arm_lpae_iopte *ptep = data->pgd;
472 int ret, lvl = ARM_LPAE_START_LVL(data);
475 /* If no access, then nothing to do */
476 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
479 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
480 paddr >= (1ULL << data->iop.cfg.oas)))
483 prot = arm_lpae_prot_to_pte(data, iommu_prot);
484 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
486 * Synchronise all PTE updates for the new mapping before there's
487 * a chance for anything to kick off a table walk for the new iova.
494 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
495 arm_lpae_iopte *ptep)
497 arm_lpae_iopte *start, *end;
498 unsigned long table_size;
500 if (lvl == ARM_LPAE_START_LVL(data))
501 table_size = data->pgd_size;
503 table_size = ARM_LPAE_GRANULE(data);
507 /* Only leaf entries at the last level */
508 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
511 end = (void *)ptep + table_size;
513 while (ptep != end) {
514 arm_lpae_iopte pte = *ptep++;
516 if (!pte || iopte_leaf(pte, lvl))
519 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
522 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
525 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
527 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
529 __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
533 static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
534 unsigned long iova, size_t size,
535 arm_lpae_iopte blk_pte, int lvl,
536 arm_lpae_iopte *ptep)
538 struct io_pgtable_cfg *cfg = &data->iop.cfg;
539 arm_lpae_iopte pte, *tablep;
540 phys_addr_t blk_paddr;
541 size_t tablesz = ARM_LPAE_GRANULE(data);
542 size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
543 int i, unmap_idx = -1;
545 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
548 tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);
550 return 0; /* Bytes unmapped */
552 if (size == split_sz)
553 unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
555 blk_paddr = iopte_to_paddr(blk_pte, data);
556 pte = iopte_prot(blk_pte);
558 for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
563 __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]);
566 pte = arm_lpae_install_table(tablep, ptep, blk_pte, data);
567 if (pte != blk_pte) {
568 __arm_lpae_free_pages(tablep, tablesz, cfg);
570 * We may race against someone unmapping another part of this
571 * block, but anything else is invalid. We can't misinterpret
572 * a page entry here since we're never at the last level.
574 if (iopte_type(pte, lvl - 1) != ARM_LPAE_PTE_TYPE_TABLE)
577 tablep = iopte_deref(pte, data);
578 } else if (unmap_idx >= 0) {
579 io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true);
583 return __arm_lpae_unmap(data, iova, size, lvl, tablep);
586 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
587 unsigned long iova, size_t size, int lvl,
588 arm_lpae_iopte *ptep)
591 struct io_pgtable *iop = &data->iop;
593 /* Something went horribly wrong and we ran out of page table */
594 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
597 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
598 pte = READ_ONCE(*ptep);
602 /* If the size matches this level, we're in the right place */
603 if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
604 __arm_lpae_set_pte(ptep, 0, &iop->cfg);
606 if (!iopte_leaf(pte, lvl)) {
607 /* Also flush any partial walks */
608 io_pgtable_tlb_add_flush(iop, iova, size,
609 ARM_LPAE_GRANULE(data), false);
610 io_pgtable_tlb_sync(iop);
611 ptep = iopte_deref(pte, data);
612 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
614 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
618 } else if (iopte_leaf(pte, lvl)) {
620 * Insert a table at the next level to map the old region,
621 * minus the part we want to unmap
623 return arm_lpae_split_blk_unmap(data, iova, size, pte,
627 /* Keep on walkin' */
628 ptep = iopte_deref(pte, data);
629 return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
632 static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
635 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
636 arm_lpae_iopte *ptep = data->pgd;
637 int lvl = ARM_LPAE_START_LVL(data);
639 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
642 return __arm_lpae_unmap(data, iova, size, lvl, ptep);
645 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
648 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
649 arm_lpae_iopte pte, *ptep = data->pgd;
650 int lvl = ARM_LPAE_START_LVL(data);
653 /* Valid IOPTE pointer? */
657 /* Grab the IOPTE we're interested in */
658 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
659 pte = READ_ONCE(*ptep);
666 if (iopte_leaf(pte,lvl))
667 goto found_translation;
669 /* Take it to the next level */
670 ptep = iopte_deref(pte, data);
671 } while (++lvl < ARM_LPAE_MAX_LEVELS);
673 /* Ran out of page tables to walk */
677 iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
678 return iopte_to_paddr(pte, data) | iova;
681 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
683 unsigned long granule, page_sizes;
684 unsigned int max_addr_bits = 48;
687 * We need to restrict the supported page sizes to match the
688 * translation regime for a particular granule. Aim to match
689 * the CPU page size if possible, otherwise prefer smaller sizes.
690 * While we're at it, restrict the block sizes to match the
693 if (cfg->pgsize_bitmap & PAGE_SIZE)
695 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
696 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
697 else if (cfg->pgsize_bitmap & PAGE_MASK)
698 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
704 page_sizes = (SZ_4K | SZ_2M | SZ_1G);
707 page_sizes = (SZ_16K | SZ_32M);
711 page_sizes = (SZ_64K | SZ_512M);
713 page_sizes |= 1ULL << 42; /* 4TB */
719 cfg->pgsize_bitmap &= page_sizes;
720 cfg->ias = min(cfg->ias, max_addr_bits);
721 cfg->oas = min(cfg->oas, max_addr_bits);
724 static struct arm_lpae_io_pgtable *
725 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
727 unsigned long va_bits, pgd_bits;
728 struct arm_lpae_io_pgtable *data;
730 arm_lpae_restrict_pgsizes(cfg);
732 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
735 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
738 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
741 if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) {
742 dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n");
746 data = kmalloc(sizeof(*data), GFP_KERNEL);
750 data->pg_shift = __ffs(cfg->pgsize_bitmap);
751 data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
753 va_bits = cfg->ias - data->pg_shift;
754 data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
756 /* Calculate the actual size of our pgd (without concatenation) */
757 pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
758 data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
760 data->iop.ops = (struct io_pgtable_ops) {
762 .unmap = arm_lpae_unmap,
763 .iova_to_phys = arm_lpae_iova_to_phys,
769 static struct io_pgtable *
770 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
773 struct arm_lpae_io_pgtable *data;
775 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA))
778 data = arm_lpae_alloc_pgtable(cfg);
783 reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
784 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
785 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
787 switch (ARM_LPAE_GRANULE(data)) {
789 reg |= ARM_LPAE_TCR_TG0_4K;
792 reg |= ARM_LPAE_TCR_TG0_16K;
795 reg |= ARM_LPAE_TCR_TG0_64K;
801 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
804 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
807 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
810 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
813 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
816 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
819 reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_IPS_SHIFT);
825 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
827 /* Disable speculative walks through TTBR1 */
828 reg |= ARM_LPAE_TCR_EPD1;
829 cfg->arm_lpae_s1_cfg.tcr = reg;
832 reg = (ARM_LPAE_MAIR_ATTR_NC
833 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
834 (ARM_LPAE_MAIR_ATTR_WBRWA
835 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
836 (ARM_LPAE_MAIR_ATTR_DEVICE
837 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
839 cfg->arm_lpae_s1_cfg.mair[0] = reg;
840 cfg->arm_lpae_s1_cfg.mair[1] = 0;
842 /* Looking good; allocate a pgd */
843 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
847 /* Ensure the empty pgd is visible before any actual TTBR write */
851 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
852 cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
860 static struct io_pgtable *
861 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
864 struct arm_lpae_io_pgtable *data;
866 /* The NS quirk doesn't apply at stage 2 */
867 if (cfg->quirks & ~IO_PGTABLE_QUIRK_NO_DMA)
870 data = arm_lpae_alloc_pgtable(cfg);
875 * Concatenate PGDs at level 1 if possible in order to reduce
876 * the depth of the stage-2 walk.
878 if (data->levels == ARM_LPAE_MAX_LEVELS) {
879 unsigned long pgd_pages;
881 pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
882 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
883 data->pgd_size = pgd_pages << data->pg_shift;
889 reg = ARM_64_LPAE_S2_TCR_RES1 |
890 (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
891 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
892 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
894 sl = ARM_LPAE_START_LVL(data);
896 switch (ARM_LPAE_GRANULE(data)) {
898 reg |= ARM_LPAE_TCR_TG0_4K;
899 sl++; /* SL0 format is different for 4K granule size */
902 reg |= ARM_LPAE_TCR_TG0_16K;
905 reg |= ARM_LPAE_TCR_TG0_64K;
911 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
914 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
917 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
920 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
923 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
926 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
929 reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT);
935 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
936 reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
937 cfg->arm_lpae_s2_cfg.vtcr = reg;
939 /* Allocate pgd pages */
940 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
944 /* Ensure the empty pgd is visible before any actual TTBR write */
948 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
956 static struct io_pgtable *
957 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
959 struct io_pgtable *iop;
961 if (cfg->ias > 32 || cfg->oas > 40)
964 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
965 iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
967 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
968 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
974 static struct io_pgtable *
975 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
977 struct io_pgtable *iop;
979 if (cfg->ias > 40 || cfg->oas > 40)
982 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
983 iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
985 cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
990 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
991 .alloc = arm_64_lpae_alloc_pgtable_s1,
992 .free = arm_lpae_free_pgtable,
995 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
996 .alloc = arm_64_lpae_alloc_pgtable_s2,
997 .free = arm_lpae_free_pgtable,
1000 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
1001 .alloc = arm_32_lpae_alloc_pgtable_s1,
1002 .free = arm_lpae_free_pgtable,
1005 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
1006 .alloc = arm_32_lpae_alloc_pgtable_s2,
1007 .free = arm_lpae_free_pgtable,
1010 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
1012 static struct io_pgtable_cfg *cfg_cookie;
1014 static void dummy_tlb_flush_all(void *cookie)
1016 WARN_ON(cookie != cfg_cookie);
1019 static void dummy_tlb_add_flush(unsigned long iova, size_t size,
1020 size_t granule, bool leaf, void *cookie)
1022 WARN_ON(cookie != cfg_cookie);
1023 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
1026 static void dummy_tlb_sync(void *cookie)
1028 WARN_ON(cookie != cfg_cookie);
1031 static const struct iommu_gather_ops dummy_tlb_ops __initconst = {
1032 .tlb_flush_all = dummy_tlb_flush_all,
1033 .tlb_add_flush = dummy_tlb_add_flush,
1034 .tlb_sync = dummy_tlb_sync,
1037 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
1039 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
1040 struct io_pgtable_cfg *cfg = &data->iop.cfg;
1042 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
1043 cfg->pgsize_bitmap, cfg->ias);
1044 pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
1045 data->levels, data->pgd_size, data->pg_shift,
1046 data->bits_per_level, data->pgd);
1049 #define __FAIL(ops, i) ({ \
1050 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
1051 arm_lpae_dump_ops(ops); \
1052 selftest_running = false; \
1056 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
1058 static const enum io_pgtable_fmt fmts[] = {
1066 struct io_pgtable_ops *ops;
1068 selftest_running = true;
1070 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
1072 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
1074 pr_err("selftest: failed to allocate io pgtable ops\n");
1079 * Initial sanity checks.
1080 * Empty page tables shouldn't provide any translations.
1082 if (ops->iova_to_phys(ops, 42))
1083 return __FAIL(ops, i);
1085 if (ops->iova_to_phys(ops, SZ_1G + 42))
1086 return __FAIL(ops, i);
1088 if (ops->iova_to_phys(ops, SZ_2G + 42))
1089 return __FAIL(ops, i);
1092 * Distinct mappings of different granule sizes.
1095 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1098 if (ops->map(ops, iova, iova, size, IOMMU_READ |
1102 return __FAIL(ops, i);
1104 /* Overlapping mappings */
1105 if (!ops->map(ops, iova, iova + size, size,
1106 IOMMU_READ | IOMMU_NOEXEC))
1107 return __FAIL(ops, i);
1109 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1110 return __FAIL(ops, i);
1116 size = 1UL << __ffs(cfg->pgsize_bitmap);
1117 if (ops->unmap(ops, SZ_1G + size, size) != size)
1118 return __FAIL(ops, i);
1120 /* Remap of partial unmap */
1121 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
1122 return __FAIL(ops, i);
1124 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1125 return __FAIL(ops, i);
1129 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1132 if (ops->unmap(ops, iova, size) != size)
1133 return __FAIL(ops, i);
1135 if (ops->iova_to_phys(ops, iova + 42))
1136 return __FAIL(ops, i);
1138 /* Remap full block */
1139 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
1140 return __FAIL(ops, i);
1142 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1143 return __FAIL(ops, i);
1148 free_io_pgtable_ops(ops);
1151 selftest_running = false;
1155 static int __init arm_lpae_do_selftests(void)
1157 static const unsigned long pgsize[] = {
1158 SZ_4K | SZ_2M | SZ_1G,
1163 static const unsigned int ias[] = {
1164 32, 36, 40, 42, 44, 48,
1167 int i, j, pass = 0, fail = 0;
1168 struct io_pgtable_cfg cfg = {
1169 .tlb = &dummy_tlb_ops,
1171 .quirks = IO_PGTABLE_QUIRK_NO_DMA,
1174 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1175 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1176 cfg.pgsize_bitmap = pgsize[i];
1178 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1180 if (arm_lpae_run_tests(&cfg))
1187 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1188 return fail ? -EFAULT : 0;
1190 subsys_initcall(arm_lpae_do_selftests);