2 * CPU-agnostic ARM page table allocator.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2014 ARM Limited
18 * Author: Will Deacon <will.deacon@arm.com>
21 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
23 #include <linux/atomic.h>
24 #include <linux/iommu.h>
25 #include <linux/kernel.h>
26 #include <linux/sizes.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
29 #include <linux/dma-mapping.h>
31 #include <asm/barrier.h>
33 #include "io-pgtable.h"
35 #define ARM_LPAE_MAX_ADDR_BITS 48
36 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
37 #define ARM_LPAE_MAX_LEVELS 4
39 /* Struct accessors */
40 #define io_pgtable_to_data(x) \
41 container_of((x), struct arm_lpae_io_pgtable, iop)
43 #define io_pgtable_ops_to_data(x) \
44 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
47 * For consistency with the architecture, we always consider
48 * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
50 #define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
53 * Calculate the right shift amount to get to the portion describing level l
54 * in a virtual address mapped by the pagetable in d.
56 #define ARM_LPAE_LVL_SHIFT(l,d) \
57 ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
58 * (d)->bits_per_level) + (d)->pg_shift)
60 #define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift)
62 #define ARM_LPAE_PAGES_PER_PGD(d) \
63 DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d))
66 * Calculate the index at level l used to map virtual address a using the
69 #define ARM_LPAE_PGD_IDX(l,d) \
70 ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
72 #define ARM_LPAE_LVL_IDX(a,l,d) \
73 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
74 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
76 /* Calculate the block/page mapping size at level l for pagetable in d. */
77 #define ARM_LPAE_BLOCK_SIZE(l,d) \
78 (1ULL << (ilog2(sizeof(arm_lpae_iopte)) + \
79 ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
82 #define ARM_LPAE_PTE_TYPE_SHIFT 0
83 #define ARM_LPAE_PTE_TYPE_MASK 0x3
85 #define ARM_LPAE_PTE_TYPE_BLOCK 1
86 #define ARM_LPAE_PTE_TYPE_TABLE 3
87 #define ARM_LPAE_PTE_TYPE_PAGE 3
89 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
90 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
91 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
92 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
93 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
94 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
95 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
96 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
98 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
99 /* Ignore the contiguous bit for block splitting */
100 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
101 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
102 ARM_LPAE_PTE_ATTR_HI_MASK)
103 /* Software bit for solving coherency races */
104 #define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
107 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
108 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
109 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
110 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
113 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
114 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
115 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
116 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
117 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
118 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
121 #define ARM_32_LPAE_TCR_EAE (1 << 31)
122 #define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
124 #define ARM_LPAE_TCR_EPD1 (1 << 23)
126 #define ARM_LPAE_TCR_TG0_4K (0 << 14)
127 #define ARM_LPAE_TCR_TG0_64K (1 << 14)
128 #define ARM_LPAE_TCR_TG0_16K (2 << 14)
130 #define ARM_LPAE_TCR_SH0_SHIFT 12
131 #define ARM_LPAE_TCR_SH0_MASK 0x3
132 #define ARM_LPAE_TCR_SH_NS 0
133 #define ARM_LPAE_TCR_SH_OS 2
134 #define ARM_LPAE_TCR_SH_IS 3
136 #define ARM_LPAE_TCR_ORGN0_SHIFT 10
137 #define ARM_LPAE_TCR_IRGN0_SHIFT 8
138 #define ARM_LPAE_TCR_RGN_MASK 0x3
139 #define ARM_LPAE_TCR_RGN_NC 0
140 #define ARM_LPAE_TCR_RGN_WBWA 1
141 #define ARM_LPAE_TCR_RGN_WT 2
142 #define ARM_LPAE_TCR_RGN_WB 3
144 #define ARM_LPAE_TCR_SL0_SHIFT 6
145 #define ARM_LPAE_TCR_SL0_MASK 0x3
147 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
148 #define ARM_LPAE_TCR_SZ_MASK 0xf
150 #define ARM_LPAE_TCR_PS_SHIFT 16
151 #define ARM_LPAE_TCR_PS_MASK 0x7
153 #define ARM_LPAE_TCR_IPS_SHIFT 32
154 #define ARM_LPAE_TCR_IPS_MASK 0x7
156 #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
157 #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
158 #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
159 #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
160 #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
161 #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
163 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
164 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
165 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
166 #define ARM_LPAE_MAIR_ATTR_NC 0x44
167 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
168 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
169 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
170 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
172 /* IOPTE accessors */
173 #define iopte_deref(pte,d) \
174 (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \
175 & ~(ARM_LPAE_GRANULE(d) - 1ULL)))
177 #define iopte_type(pte,l) \
178 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
180 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
182 #define iopte_leaf(pte,l) \
183 (l == (ARM_LPAE_MAX_LEVELS - 1) ? \
184 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
185 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
187 #define iopte_to_pfn(pte,d) \
188 (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift)
190 #define pfn_to_iopte(pfn,d) \
191 (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1))
193 struct arm_lpae_io_pgtable {
194 struct io_pgtable iop;
198 unsigned long pg_shift;
199 unsigned long bits_per_level;
204 typedef u64 arm_lpae_iopte;
206 static bool selftest_running = false;
208 static dma_addr_t __arm_lpae_dma_addr(void *pages)
210 return (dma_addr_t)virt_to_phys(pages);
213 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
214 struct io_pgtable_cfg *cfg)
216 struct device *dev = cfg->iommu_dev;
218 void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO);
223 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA)) {
224 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
225 if (dma_mapping_error(dev, dma))
228 * We depend on the IOMMU being able to work with any physical
229 * address directly, so if the DMA layer suggests otherwise by
230 * translating or truncating them, that bodes very badly...
232 if (dma != virt_to_phys(pages))
239 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
240 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
242 free_pages_exact(pages, size);
246 static void __arm_lpae_free_pages(void *pages, size_t size,
247 struct io_pgtable_cfg *cfg)
249 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
250 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
251 size, DMA_TO_DEVICE);
252 free_pages_exact(pages, size);
255 static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep,
256 struct io_pgtable_cfg *cfg)
258 dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
259 sizeof(*ptep), DMA_TO_DEVICE);
262 static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
263 struct io_pgtable_cfg *cfg)
267 if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
268 __arm_lpae_sync_pte(ptep, cfg);
271 static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
272 unsigned long iova, size_t size, int lvl,
273 arm_lpae_iopte *ptep);
275 static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
276 phys_addr_t paddr, arm_lpae_iopte prot,
277 int lvl, arm_lpae_iopte *ptep)
279 arm_lpae_iopte pte = prot;
281 if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
282 pte |= ARM_LPAE_PTE_NS;
284 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
285 pte |= ARM_LPAE_PTE_TYPE_PAGE;
287 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
289 pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
290 pte |= pfn_to_iopte(paddr >> data->pg_shift, data);
292 __arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
295 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
296 unsigned long iova, phys_addr_t paddr,
297 arm_lpae_iopte prot, int lvl,
298 arm_lpae_iopte *ptep)
300 arm_lpae_iopte pte = *ptep;
302 if (iopte_leaf(pte, lvl)) {
303 /* We require an unmap first */
304 WARN_ON(!selftest_running);
306 } else if (iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
308 * We need to unmap and free the old table before
309 * overwriting it with a block entry.
311 arm_lpae_iopte *tblp;
312 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
314 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
315 if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz))
319 __arm_lpae_init_pte(data, paddr, prot, lvl, ptep);
323 static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
324 arm_lpae_iopte *ptep,
326 struct io_pgtable_cfg *cfg)
328 arm_lpae_iopte old, new;
330 new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE;
331 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
332 new |= ARM_LPAE_PTE_NSTABLE;
335 * Ensure the table itself is visible before its PTE can be.
336 * Whilst we could get away with cmpxchg64_release below, this
337 * doesn't have any ordering semantics when !CONFIG_SMP.
341 old = cmpxchg64_relaxed(ptep, curr, new);
343 if ((cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) ||
344 (old & ARM_LPAE_PTE_SW_SYNC))
347 /* Even if it's not ours, there's no point waiting; just kick it */
348 __arm_lpae_sync_pte(ptep, cfg);
350 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
355 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
356 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
357 int lvl, arm_lpae_iopte *ptep)
359 arm_lpae_iopte *cptep, pte;
360 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
361 size_t tblsz = ARM_LPAE_GRANULE(data);
362 struct io_pgtable_cfg *cfg = &data->iop.cfg;
364 /* Find our entry at the current level */
365 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
367 /* If we can install a leaf entry at this level, then do so */
368 if (size == block_size && (size & cfg->pgsize_bitmap))
369 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
371 /* We can't allocate tables at the final level */
372 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
375 /* Grab a pointer to the next level */
376 pte = READ_ONCE(*ptep);
378 cptep = __arm_lpae_alloc_pages(tblsz, GFP_ATOMIC, cfg);
382 pte = arm_lpae_install_table(cptep, ptep, 0, cfg);
384 __arm_lpae_free_pages(cptep, tblsz, cfg);
385 } else if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) &&
386 !(pte & ARM_LPAE_PTE_SW_SYNC)) {
387 __arm_lpae_sync_pte(ptep, cfg);
390 if (pte && !iopte_leaf(pte, lvl)) {
391 cptep = iopte_deref(pte, data);
393 /* We require an unmap first */
394 WARN_ON(!selftest_running);
399 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
402 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
407 if (data->iop.fmt == ARM_64_LPAE_S1 ||
408 data->iop.fmt == ARM_32_LPAE_S1) {
409 pte = ARM_LPAE_PTE_nG;
411 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
412 pte |= ARM_LPAE_PTE_AP_RDONLY;
414 if (!(prot & IOMMU_PRIV))
415 pte |= ARM_LPAE_PTE_AP_UNPRIV;
417 if (prot & IOMMU_MMIO)
418 pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
419 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
420 else if (prot & IOMMU_CACHE)
421 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
422 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
424 pte = ARM_LPAE_PTE_HAP_FAULT;
425 if (prot & IOMMU_READ)
426 pte |= ARM_LPAE_PTE_HAP_READ;
427 if (prot & IOMMU_WRITE)
428 pte |= ARM_LPAE_PTE_HAP_WRITE;
429 if (prot & IOMMU_MMIO)
430 pte |= ARM_LPAE_PTE_MEMATTR_DEV;
431 else if (prot & IOMMU_CACHE)
432 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
434 pte |= ARM_LPAE_PTE_MEMATTR_NC;
437 if (prot & IOMMU_NOEXEC)
438 pte |= ARM_LPAE_PTE_XN;
443 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
444 phys_addr_t paddr, size_t size, int iommu_prot)
446 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
447 arm_lpae_iopte *ptep = data->pgd;
448 int ret, lvl = ARM_LPAE_START_LVL(data);
451 /* If no access, then nothing to do */
452 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
455 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
456 paddr >= (1ULL << data->iop.cfg.oas)))
459 prot = arm_lpae_prot_to_pte(data, iommu_prot);
460 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
462 * Synchronise all PTE updates for the new mapping before there's
463 * a chance for anything to kick off a table walk for the new iova.
470 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
471 arm_lpae_iopte *ptep)
473 arm_lpae_iopte *start, *end;
474 unsigned long table_size;
476 if (lvl == ARM_LPAE_START_LVL(data))
477 table_size = data->pgd_size;
479 table_size = ARM_LPAE_GRANULE(data);
483 /* Only leaf entries at the last level */
484 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
487 end = (void *)ptep + table_size;
489 while (ptep != end) {
490 arm_lpae_iopte pte = *ptep++;
492 if (!pte || iopte_leaf(pte, lvl))
495 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
498 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
501 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
503 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
505 __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
509 static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
510 unsigned long iova, size_t size,
511 arm_lpae_iopte blk_pte, int lvl,
512 arm_lpae_iopte *ptep)
514 struct io_pgtable_cfg *cfg = &data->iop.cfg;
515 arm_lpae_iopte pte, *tablep;
516 phys_addr_t blk_paddr;
517 size_t tablesz = ARM_LPAE_GRANULE(data);
518 size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
519 int i, unmap_idx = -1;
521 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
524 tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);
526 return 0; /* Bytes unmapped */
528 if (size == split_sz)
529 unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
531 blk_paddr = iopte_to_pfn(blk_pte, data) << data->pg_shift;
532 pte = iopte_prot(blk_pte);
534 for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
539 __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]);
542 pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg);
543 if (pte != blk_pte) {
544 __arm_lpae_free_pages(tablep, tablesz, cfg);
546 * We may race against someone unmapping another part of this
547 * block, but anything else is invalid. We can't misinterpret
548 * a page entry here since we're never at the last level.
550 if (iopte_type(pte, lvl - 1) != ARM_LPAE_PTE_TYPE_TABLE)
553 tablep = iopte_deref(pte, data);
554 } else if (unmap_idx >= 0) {
555 io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true);
559 return __arm_lpae_unmap(data, iova, size, lvl, tablep);
562 static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
563 unsigned long iova, size_t size, int lvl,
564 arm_lpae_iopte *ptep)
567 struct io_pgtable *iop = &data->iop;
569 /* Something went horribly wrong and we ran out of page table */
570 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
573 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
574 pte = READ_ONCE(*ptep);
578 /* If the size matches this level, we're in the right place */
579 if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
580 __arm_lpae_set_pte(ptep, 0, &iop->cfg);
582 if (!iopte_leaf(pte, lvl)) {
583 /* Also flush any partial walks */
584 io_pgtable_tlb_add_flush(iop, iova, size,
585 ARM_LPAE_GRANULE(data), false);
586 io_pgtable_tlb_sync(iop);
587 ptep = iopte_deref(pte, data);
588 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
590 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
594 } else if (iopte_leaf(pte, lvl)) {
596 * Insert a table at the next level to map the old region,
597 * minus the part we want to unmap
599 return arm_lpae_split_blk_unmap(data, iova, size, pte,
603 /* Keep on walkin' */
604 ptep = iopte_deref(pte, data);
605 return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
608 static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
612 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
613 arm_lpae_iopte *ptep = data->pgd;
614 int lvl = ARM_LPAE_START_LVL(data);
616 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
619 unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep);
621 io_pgtable_tlb_sync(&data->iop);
626 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
629 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
630 arm_lpae_iopte pte, *ptep = data->pgd;
631 int lvl = ARM_LPAE_START_LVL(data);
634 /* Valid IOPTE pointer? */
638 /* Grab the IOPTE we're interested in */
639 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
640 pte = READ_ONCE(*ptep);
647 if (iopte_leaf(pte,lvl))
648 goto found_translation;
650 /* Take it to the next level */
651 ptep = iopte_deref(pte, data);
652 } while (++lvl < ARM_LPAE_MAX_LEVELS);
654 /* Ran out of page tables to walk */
658 iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
659 return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova;
662 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
664 unsigned long granule;
667 * We need to restrict the supported page sizes to match the
668 * translation regime for a particular granule. Aim to match
669 * the CPU page size if possible, otherwise prefer smaller sizes.
670 * While we're at it, restrict the block sizes to match the
673 if (cfg->pgsize_bitmap & PAGE_SIZE)
675 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
676 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
677 else if (cfg->pgsize_bitmap & PAGE_MASK)
678 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
684 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
687 cfg->pgsize_bitmap &= (SZ_16K | SZ_32M);
690 cfg->pgsize_bitmap &= (SZ_64K | SZ_512M);
693 cfg->pgsize_bitmap = 0;
697 static struct arm_lpae_io_pgtable *
698 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
700 unsigned long va_bits, pgd_bits;
701 struct arm_lpae_io_pgtable *data;
703 arm_lpae_restrict_pgsizes(cfg);
705 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
708 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
711 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
714 if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) {
715 dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n");
719 data = kmalloc(sizeof(*data), GFP_KERNEL);
723 data->pg_shift = __ffs(cfg->pgsize_bitmap);
724 data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
726 va_bits = cfg->ias - data->pg_shift;
727 data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
729 /* Calculate the actual size of our pgd (without concatenation) */
730 pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
731 data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
733 data->iop.ops = (struct io_pgtable_ops) {
735 .unmap = arm_lpae_unmap,
736 .iova_to_phys = arm_lpae_iova_to_phys,
742 static struct io_pgtable *
743 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
746 struct arm_lpae_io_pgtable *data;
748 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA))
751 data = arm_lpae_alloc_pgtable(cfg);
756 reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
757 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
758 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
760 switch (ARM_LPAE_GRANULE(data)) {
762 reg |= ARM_LPAE_TCR_TG0_4K;
765 reg |= ARM_LPAE_TCR_TG0_16K;
768 reg |= ARM_LPAE_TCR_TG0_64K;
774 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
777 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
780 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
783 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
786 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
789 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
795 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
797 /* Disable speculative walks through TTBR1 */
798 reg |= ARM_LPAE_TCR_EPD1;
799 cfg->arm_lpae_s1_cfg.tcr = reg;
802 reg = (ARM_LPAE_MAIR_ATTR_NC
803 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
804 (ARM_LPAE_MAIR_ATTR_WBRWA
805 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
806 (ARM_LPAE_MAIR_ATTR_DEVICE
807 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
809 cfg->arm_lpae_s1_cfg.mair[0] = reg;
810 cfg->arm_lpae_s1_cfg.mair[1] = 0;
812 /* Looking good; allocate a pgd */
813 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
817 /* Ensure the empty pgd is visible before any actual TTBR write */
821 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
822 cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
830 static struct io_pgtable *
831 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
834 struct arm_lpae_io_pgtable *data;
836 /* The NS quirk doesn't apply at stage 2 */
837 if (cfg->quirks & ~IO_PGTABLE_QUIRK_NO_DMA)
840 data = arm_lpae_alloc_pgtable(cfg);
845 * Concatenate PGDs at level 1 if possible in order to reduce
846 * the depth of the stage-2 walk.
848 if (data->levels == ARM_LPAE_MAX_LEVELS) {
849 unsigned long pgd_pages;
851 pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
852 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
853 data->pgd_size = pgd_pages << data->pg_shift;
859 reg = ARM_64_LPAE_S2_TCR_RES1 |
860 (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
861 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
862 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
864 sl = ARM_LPAE_START_LVL(data);
866 switch (ARM_LPAE_GRANULE(data)) {
868 reg |= ARM_LPAE_TCR_TG0_4K;
869 sl++; /* SL0 format is different for 4K granule size */
872 reg |= ARM_LPAE_TCR_TG0_16K;
875 reg |= ARM_LPAE_TCR_TG0_64K;
881 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
884 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
887 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
890 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
893 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
896 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
902 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
903 reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
904 cfg->arm_lpae_s2_cfg.vtcr = reg;
906 /* Allocate pgd pages */
907 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
911 /* Ensure the empty pgd is visible before any actual TTBR write */
915 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
923 static struct io_pgtable *
924 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
926 struct io_pgtable *iop;
928 if (cfg->ias > 32 || cfg->oas > 40)
931 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
932 iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
934 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
935 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
941 static struct io_pgtable *
942 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
944 struct io_pgtable *iop;
946 if (cfg->ias > 40 || cfg->oas > 40)
949 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
950 iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
952 cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
957 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
958 .alloc = arm_64_lpae_alloc_pgtable_s1,
959 .free = arm_lpae_free_pgtable,
962 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
963 .alloc = arm_64_lpae_alloc_pgtable_s2,
964 .free = arm_lpae_free_pgtable,
967 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
968 .alloc = arm_32_lpae_alloc_pgtable_s1,
969 .free = arm_lpae_free_pgtable,
972 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
973 .alloc = arm_32_lpae_alloc_pgtable_s2,
974 .free = arm_lpae_free_pgtable,
977 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
979 static struct io_pgtable_cfg *cfg_cookie;
981 static void dummy_tlb_flush_all(void *cookie)
983 WARN_ON(cookie != cfg_cookie);
986 static void dummy_tlb_add_flush(unsigned long iova, size_t size,
987 size_t granule, bool leaf, void *cookie)
989 WARN_ON(cookie != cfg_cookie);
990 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
993 static void dummy_tlb_sync(void *cookie)
995 WARN_ON(cookie != cfg_cookie);
998 static const struct iommu_gather_ops dummy_tlb_ops __initconst = {
999 .tlb_flush_all = dummy_tlb_flush_all,
1000 .tlb_add_flush = dummy_tlb_add_flush,
1001 .tlb_sync = dummy_tlb_sync,
1004 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
1006 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
1007 struct io_pgtable_cfg *cfg = &data->iop.cfg;
1009 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
1010 cfg->pgsize_bitmap, cfg->ias);
1011 pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
1012 data->levels, data->pgd_size, data->pg_shift,
1013 data->bits_per_level, data->pgd);
1016 #define __FAIL(ops, i) ({ \
1017 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
1018 arm_lpae_dump_ops(ops); \
1019 selftest_running = false; \
1023 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
1025 static const enum io_pgtable_fmt fmts[] = {
1033 struct io_pgtable_ops *ops;
1035 selftest_running = true;
1037 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
1039 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
1041 pr_err("selftest: failed to allocate io pgtable ops\n");
1046 * Initial sanity checks.
1047 * Empty page tables shouldn't provide any translations.
1049 if (ops->iova_to_phys(ops, 42))
1050 return __FAIL(ops, i);
1052 if (ops->iova_to_phys(ops, SZ_1G + 42))
1053 return __FAIL(ops, i);
1055 if (ops->iova_to_phys(ops, SZ_2G + 42))
1056 return __FAIL(ops, i);
1059 * Distinct mappings of different granule sizes.
1062 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1065 if (ops->map(ops, iova, iova, size, IOMMU_READ |
1069 return __FAIL(ops, i);
1071 /* Overlapping mappings */
1072 if (!ops->map(ops, iova, iova + size, size,
1073 IOMMU_READ | IOMMU_NOEXEC))
1074 return __FAIL(ops, i);
1076 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1077 return __FAIL(ops, i);
1083 size = 1UL << __ffs(cfg->pgsize_bitmap);
1084 if (ops->unmap(ops, SZ_1G + size, size) != size)
1085 return __FAIL(ops, i);
1087 /* Remap of partial unmap */
1088 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
1089 return __FAIL(ops, i);
1091 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1092 return __FAIL(ops, i);
1096 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
1097 while (j != BITS_PER_LONG) {
1100 if (ops->unmap(ops, iova, size) != size)
1101 return __FAIL(ops, i);
1103 if (ops->iova_to_phys(ops, iova + 42))
1104 return __FAIL(ops, i);
1106 /* Remap full block */
1107 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
1108 return __FAIL(ops, i);
1110 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1111 return __FAIL(ops, i);
1115 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
1118 free_io_pgtable_ops(ops);
1121 selftest_running = false;
1125 static int __init arm_lpae_do_selftests(void)
1127 static const unsigned long pgsize[] = {
1128 SZ_4K | SZ_2M | SZ_1G,
1133 static const unsigned int ias[] = {
1134 32, 36, 40, 42, 44, 48,
1137 int i, j, pass = 0, fail = 0;
1138 struct io_pgtable_cfg cfg = {
1139 .tlb = &dummy_tlb_ops,
1141 .quirks = IO_PGTABLE_QUIRK_NO_DMA,
1144 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1145 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1146 cfg.pgsize_bitmap = pgsize[i];
1148 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1150 if (arm_lpae_run_tests(&cfg))
1157 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1158 return fail ? -EFAULT : 0;
1160 subsys_initcall(arm_lpae_do_selftests);