2 * CPU-agnostic ARM page table allocator.
4 * ARMv7 Short-descriptor format, supporting
5 * - Basic memory attributes
6 * - Simplified access permissions (AP[2:1] model)
7 * - Backwards-compatible TEX remap
8 * - Large pages/supersections (if indicated by the caller)
11 * - Legacy access permissions (AP[2:0] model)
13 * Almost certainly never supporting:
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program. If not, see <http://www.gnu.org/licenses/>.
29 * Copyright (C) 2014-2015 ARM Limited
30 * Copyright (c) 2014-2015 MediaTek Inc.
33 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
35 #include <linux/dma-mapping.h>
36 #include <linux/gfp.h>
37 #include <linux/iommu.h>
38 #include <linux/kernel.h>
39 #include <linux/kmemleak.h>
40 #include <linux/sizes.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
44 #include <asm/barrier.h>
46 #include "io-pgtable.h"
48 /* Struct accessors */
49 #define io_pgtable_to_data(x) \
50 container_of((x), struct arm_v7s_io_pgtable, iop)
52 #define io_pgtable_ops_to_data(x) \
53 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
56 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
57 * and 12 bits in a page. With some carefully-chosen coefficients we can
58 * hide the ugly inconsistencies behind these macros and at least let the
59 * rest of the code pretend to be somewhat sane.
61 #define ARM_V7S_ADDR_BITS 32
62 #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
63 #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
64 #define ARM_V7S_TABLE_SHIFT 10
66 #define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
67 #define ARM_V7S_TABLE_SIZE(lvl) \
68 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
70 #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
71 #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
72 #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
73 #define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
74 #define ARM_V7S_LVL_IDX(addr, lvl) ({ \
76 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
80 * Large page/supersection entries are effectively a block of 16 page/section
81 * entries, along the lines of the LPAE contiguous hint, but all with the
82 * same output address. For want of a better common name we'll call them
83 * "contiguous" versions of their respective page/section entries here, but
84 * noting the distinction (WRT to TLB maintenance) that they represent *one*
85 * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
87 #define ARM_V7S_CONT_PAGES 16
89 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
90 #define ARM_V7S_PTE_TYPE_TABLE 0x1
91 #define ARM_V7S_PTE_TYPE_PAGE 0x2
92 #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
94 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
95 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE))
98 #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
99 #define ARM_V7S_ATTR_B BIT(2)
100 #define ARM_V7S_ATTR_C BIT(3)
101 #define ARM_V7S_ATTR_NS_TABLE BIT(3)
102 #define ARM_V7S_ATTR_NS_SECTION BIT(19)
104 #define ARM_V7S_CONT_SECTION BIT(18)
105 #define ARM_V7S_CONT_PAGE_XN_SHIFT 15
108 * The attribute bits are consistently ordered*, but occupy bits [17:10] of
109 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
110 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
112 #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
114 #define ARM_V7S_ATTR_MASK 0xff
115 #define ARM_V7S_ATTR_AP0 BIT(0)
116 #define ARM_V7S_ATTR_AP1 BIT(1)
117 #define ARM_V7S_ATTR_AP2 BIT(5)
118 #define ARM_V7S_ATTR_S BIT(6)
119 #define ARM_V7S_ATTR_NG BIT(7)
120 #define ARM_V7S_TEX_SHIFT 2
121 #define ARM_V7S_TEX_MASK 0x7
122 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
124 #define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
126 /* *well, except for TEX on level 2 large pages, of course :( */
127 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
128 #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
130 /* Simplified access permissions */
131 #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
132 #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
133 #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
136 #define ARM_V7S_RGN_NC 0
137 #define ARM_V7S_RGN_WBWA 1
138 #define ARM_V7S_RGN_WT 2
139 #define ARM_V7S_RGN_WB 3
141 #define ARM_V7S_PRRR_TYPE_DEVICE 1
142 #define ARM_V7S_PRRR_TYPE_NORMAL 2
143 #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
144 #define ARM_V7S_PRRR_DS0 BIT(16)
145 #define ARM_V7S_PRRR_DS1 BIT(17)
146 #define ARM_V7S_PRRR_NS0 BIT(18)
147 #define ARM_V7S_PRRR_NS1 BIT(19)
148 #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
150 #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
151 #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
153 #define ARM_V7S_TTBR_S BIT(1)
154 #define ARM_V7S_TTBR_NOS BIT(5)
155 #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
156 #define ARM_V7S_TTBR_IRGN_ATTR(attr) \
157 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
159 #define ARM_V7S_TCR_PD1 BIT(5)
161 typedef u32 arm_v7s_iopte;
163 static bool selftest_running;
165 struct arm_v7s_io_pgtable {
166 struct io_pgtable iop;
169 struct kmem_cache *l2_tables;
172 static dma_addr_t __arm_v7s_dma_addr(void *pages)
174 return (dma_addr_t)virt_to_phys(pages);
177 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
179 if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
180 pte &= ARM_V7S_TABLE_MASK;
182 pte &= ARM_V7S_LVL_MASK(lvl);
183 return phys_to_virt(pte);
186 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
187 struct arm_v7s_io_pgtable *data)
189 struct device *dev = data->iop.cfg.iommu_dev;
191 size_t size = ARM_V7S_TABLE_SIZE(lvl);
195 table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size));
197 table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA);
198 if (table && !selftest_running) {
199 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
200 if (dma_mapping_error(dev, dma))
203 * We depend on the IOMMU being able to work with any physical
204 * address directly, so if the DMA layer suggests otherwise by
205 * translating or truncating them, that bodes very badly...
207 if (dma != virt_to_phys(table))
211 kmemleak_ignore(table);
215 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
216 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
219 free_pages((unsigned long)table, get_order(size));
221 kmem_cache_free(data->l2_tables, table);
225 static void __arm_v7s_free_table(void *table, int lvl,
226 struct arm_v7s_io_pgtable *data)
228 struct device *dev = data->iop.cfg.iommu_dev;
229 size_t size = ARM_V7S_TABLE_SIZE(lvl);
231 if (!selftest_running)
232 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
235 free_pages((unsigned long)table, get_order(size));
237 kmem_cache_free(data->l2_tables, table);
240 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
241 struct io_pgtable_cfg *cfg)
243 if (selftest_running)
246 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
247 num_entries * sizeof(*ptep), DMA_TO_DEVICE);
249 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
250 int num_entries, struct io_pgtable_cfg *cfg)
254 for (i = 0; i < num_entries; i++)
257 __arm_v7s_pte_sync(ptep, num_entries, cfg);
260 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
261 struct io_pgtable_cfg *cfg)
263 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
264 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
266 if (!(prot & IOMMU_MMIO))
267 pte |= ARM_V7S_ATTR_TEX(1);
269 pte |= ARM_V7S_PTE_AF | ARM_V7S_PTE_AP_UNPRIV;
270 if (!(prot & IOMMU_WRITE))
271 pte |= ARM_V7S_PTE_AP_RDONLY;
273 pte <<= ARM_V7S_ATTR_SHIFT(lvl);
275 if ((prot & IOMMU_NOEXEC) && ap)
276 pte |= ARM_V7S_ATTR_XN(lvl);
277 if (prot & IOMMU_MMIO)
278 pte |= ARM_V7S_ATTR_B;
279 else if (prot & IOMMU_CACHE)
280 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
285 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
287 int prot = IOMMU_READ;
288 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
290 if (!(attr & ARM_V7S_PTE_AP_RDONLY))
292 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
294 else if (pte & ARM_V7S_ATTR_C)
296 if (pte & ARM_V7S_ATTR_XN(lvl))
297 prot |= IOMMU_NOEXEC;
302 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
305 pte |= ARM_V7S_CONT_SECTION;
306 } else if (lvl == 2) {
307 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
308 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
310 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
311 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
312 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
313 ARM_V7S_PTE_TYPE_CONT_PAGE;
318 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
321 pte &= ~ARM_V7S_CONT_SECTION;
322 } else if (lvl == 2) {
323 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
324 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
325 ARM_V7S_CONT_PAGE_TEX_SHIFT);
327 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
328 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
329 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
330 ARM_V7S_PTE_TYPE_PAGE;
335 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
337 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
338 return pte & ARM_V7S_CONT_SECTION;
340 return !(pte & ARM_V7S_PTE_TYPE_PAGE);
344 static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long,
345 size_t, int, arm_v7s_iopte *);
347 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
348 unsigned long iova, phys_addr_t paddr, int prot,
349 int lvl, int num_entries, arm_v7s_iopte *ptep)
351 struct io_pgtable_cfg *cfg = &data->iop.cfg;
352 arm_v7s_iopte pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
355 for (i = 0; i < num_entries; i++)
356 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
358 * We need to unmap and free the old table before
359 * overwriting it with a block entry.
362 size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
364 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
365 if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz,
366 sz, lvl, tblp) != sz))
368 } else if (ptep[i]) {
369 /* We require an unmap first */
370 WARN_ON(!selftest_running);
374 pte |= ARM_V7S_PTE_TYPE_PAGE;
375 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
376 pte |= ARM_V7S_ATTR_NS_SECTION;
378 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
379 pte |= ARM_V7S_ATTR_MTK_4GB;
382 pte = arm_v7s_pte_to_cont(pte, lvl);
384 pte |= paddr & ARM_V7S_LVL_MASK(lvl);
386 __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
390 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
391 phys_addr_t paddr, size_t size, int prot,
392 int lvl, arm_v7s_iopte *ptep)
394 struct io_pgtable_cfg *cfg = &data->iop.cfg;
395 arm_v7s_iopte pte, *cptep;
396 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
398 /* Find our entry at the current level */
399 ptep += ARM_V7S_LVL_IDX(iova, lvl);
401 /* If we can install a leaf entry at this level, then do so */
403 return arm_v7s_init_pte(data, iova, paddr, prot,
404 lvl, num_entries, ptep);
406 /* We can't allocate tables at the final level */
407 if (WARN_ON(lvl == 2))
410 /* Grab a pointer to the next level */
413 cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data);
417 pte = virt_to_phys(cptep) | ARM_V7S_PTE_TYPE_TABLE;
418 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
419 pte |= ARM_V7S_ATTR_NS_TABLE;
421 __arm_v7s_set_pte(ptep, pte, 1, cfg);
422 } else if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
423 cptep = iopte_deref(pte, lvl);
425 /* We require an unmap first */
426 WARN_ON(!selftest_running);
431 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep);
434 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
435 phys_addr_t paddr, size_t size, int prot)
437 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
438 struct io_pgtable *iop = &data->iop;
441 /* If no access, then nothing to do */
442 if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
445 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
447 * Synchronise all PTE updates for the new mapping before there's
448 * a chance for anything to kick off a table walk for the new iova.
450 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) {
451 io_pgtable_tlb_add_flush(iop, iova, size,
452 ARM_V7S_BLOCK_SIZE(2), false);
453 io_pgtable_tlb_sync(iop);
461 static void arm_v7s_free_pgtable(struct io_pgtable *iop)
463 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
466 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
467 arm_v7s_iopte pte = data->pgd[i];
469 if (ARM_V7S_PTE_IS_TABLE(pte, 1))
470 __arm_v7s_free_table(iopte_deref(pte, 1), 2, data);
472 __arm_v7s_free_table(data->pgd, 1, data);
473 kmem_cache_destroy(data->l2_tables);
477 static void arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
478 unsigned long iova, int idx, int lvl,
481 struct io_pgtable *iop = &data->iop;
483 size_t size = ARM_V7S_BLOCK_SIZE(lvl);
486 ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
487 pte = arm_v7s_cont_to_pte(*ptep, lvl);
488 for (i = 0; i < ARM_V7S_CONT_PAGES; i++) {
493 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
495 size *= ARM_V7S_CONT_PAGES;
496 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
497 io_pgtable_tlb_sync(iop);
500 static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
501 unsigned long iova, size_t size,
504 unsigned long blk_start, blk_end, blk_size;
505 phys_addr_t blk_paddr;
506 arm_v7s_iopte table = 0;
507 int prot = arm_v7s_pte_to_prot(*ptep, 1);
509 blk_size = ARM_V7S_BLOCK_SIZE(1);
510 blk_start = iova & ARM_V7S_LVL_MASK(1);
511 blk_end = blk_start + ARM_V7S_BLOCK_SIZE(1);
512 blk_paddr = *ptep & ARM_V7S_LVL_MASK(1);
514 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) {
515 arm_v7s_iopte *tablep;
518 if (blk_start == iova)
521 /* __arm_v7s_map expects a pointer to the start of the table */
522 tablep = &table - ARM_V7S_LVL_IDX(blk_start, 1);
523 if (__arm_v7s_map(data, blk_start, blk_paddr, size, prot, 1,
526 /* Free the table we allocated */
527 tablep = iopte_deref(table, 1);
528 __arm_v7s_free_table(tablep, 2, data);
530 return 0; /* Bytes unmapped */
534 __arm_v7s_set_pte(ptep, table, 1, &data->iop.cfg);
535 iova &= ~(blk_size - 1);
536 io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true);
540 static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
541 unsigned long iova, size_t size, int lvl,
544 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
545 struct io_pgtable *iop = &data->iop;
546 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
548 /* Something went horribly wrong and we ran out of page table */
549 if (WARN_ON(lvl > 2))
552 idx = ARM_V7S_LVL_IDX(iova, lvl);
555 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(ptep[i])))
558 } while (++i < num_entries);
561 * If we've hit a contiguous 'large page' entry at this level, it
562 * needs splitting first, unless we're unmapping the whole lot.
564 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl))
565 arm_v7s_split_cont(data, iova, idx, lvl, ptep);
567 /* If the size matches this level, we're in the right place */
569 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
571 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
573 for (i = 0; i < num_entries; i++) {
574 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
575 /* Also flush any partial walks */
576 io_pgtable_tlb_add_flush(iop, iova, blk_size,
577 ARM_V7S_BLOCK_SIZE(lvl + 1), false);
578 io_pgtable_tlb_sync(iop);
579 ptep = iopte_deref(pte[i], lvl);
580 __arm_v7s_free_table(ptep, lvl + 1, data);
582 io_pgtable_tlb_add_flush(iop, iova, blk_size,
588 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
590 * Insert a table at the next level to map the old region,
591 * minus the part we want to unmap
593 return arm_v7s_split_blk_unmap(data, iova, size, ptep);
596 /* Keep on walkin' */
597 ptep = iopte_deref(pte[0], lvl);
598 return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep);
601 static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
604 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
607 unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd);
609 io_pgtable_tlb_sync(&data->iop);
614 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
617 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
618 arm_v7s_iopte *ptep = data->pgd, pte;
623 pte = ptep[ARM_V7S_LVL_IDX(iova, ++lvl)];
624 ptep = iopte_deref(pte, lvl);
625 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
627 if (!ARM_V7S_PTE_IS_VALID(pte))
630 mask = ARM_V7S_LVL_MASK(lvl);
631 if (arm_v7s_pte_is_cont(pte, lvl))
632 mask *= ARM_V7S_CONT_PAGES;
633 return (pte & mask) | (iova & ~mask);
636 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
639 struct arm_v7s_io_pgtable *data;
642 if (upper_32_bits(PHYS_OFFSET))
645 if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS)
648 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
649 IO_PGTABLE_QUIRK_NO_PERMS |
650 IO_PGTABLE_QUIRK_TLBI_ON_MAP |
651 IO_PGTABLE_QUIRK_ARM_MTK_4GB))
654 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
655 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
656 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
659 data = kmalloc(sizeof(*data), GFP_KERNEL);
663 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
664 ARM_V7S_TABLE_SIZE(2),
665 ARM_V7S_TABLE_SIZE(2),
666 SLAB_CACHE_DMA, NULL);
667 if (!data->l2_tables)
670 data->iop.ops = (struct io_pgtable_ops) {
672 .unmap = arm_v7s_unmap,
673 .iova_to_phys = arm_v7s_iova_to_phys,
676 /* We have to do this early for __arm_v7s_alloc_table to work... */
677 data->iop.cfg = *cfg;
680 * Unless the IOMMU driver indicates supersection support by
681 * having SZ_16M set in the initial bitmap, they won't be used.
683 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
685 /* TCR: T0SZ=0, disable TTBR1 */
686 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1;
689 * TEX remap: the indices used map to the closest equivalent types
690 * under the non-TEX-remap interpretation of those attribute bits,
691 * excepting various implementation-defined aspects of shareability.
693 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
694 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
695 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
696 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
697 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
698 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
699 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
701 /* Looking good; allocate a pgd */
702 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
706 /* Ensure the empty pgd is visible before any actual TTBR write */
710 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |
711 ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |
712 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
713 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA);
714 cfg->arm_v7s_cfg.ttbr[1] = 0;
718 kmem_cache_destroy(data->l2_tables);
723 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
724 .alloc = arm_v7s_alloc_pgtable,
725 .free = arm_v7s_free_pgtable,
728 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
730 static struct io_pgtable_cfg *cfg_cookie;
732 static void dummy_tlb_flush_all(void *cookie)
734 WARN_ON(cookie != cfg_cookie);
737 static void dummy_tlb_add_flush(unsigned long iova, size_t size,
738 size_t granule, bool leaf, void *cookie)
740 WARN_ON(cookie != cfg_cookie);
741 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
744 static void dummy_tlb_sync(void *cookie)
746 WARN_ON(cookie != cfg_cookie);
749 static struct iommu_gather_ops dummy_tlb_ops = {
750 .tlb_flush_all = dummy_tlb_flush_all,
751 .tlb_add_flush = dummy_tlb_add_flush,
752 .tlb_sync = dummy_tlb_sync,
755 #define __FAIL(ops) ({ \
756 WARN(1, "selftest: test failed\n"); \
757 selftest_running = false; \
761 static int __init arm_v7s_do_selftests(void)
763 struct io_pgtable_ops *ops;
764 struct io_pgtable_cfg cfg = {
765 .tlb = &dummy_tlb_ops,
768 .quirks = IO_PGTABLE_QUIRK_ARM_NS,
769 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
771 unsigned int iova, size, iova_start;
772 unsigned int i, loopnr = 0;
774 selftest_running = true;
778 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
780 pr_err("selftest: failed to allocate io pgtable ops\n");
785 * Initial sanity checks.
786 * Empty page tables shouldn't provide any translations.
788 if (ops->iova_to_phys(ops, 42))
791 if (ops->iova_to_phys(ops, SZ_1G + 42))
794 if (ops->iova_to_phys(ops, SZ_2G + 42))
798 * Distinct mappings of different granule sizes.
801 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
802 while (i != BITS_PER_LONG) {
804 if (ops->map(ops, iova, iova, size, IOMMU_READ |
810 /* Overlapping mappings */
811 if (!ops->map(ops, iova, iova + size, size,
812 IOMMU_READ | IOMMU_NOEXEC))
815 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
820 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
826 size = 1UL << __ffs(cfg.pgsize_bitmap);
828 iova_start = i * SZ_16M;
829 if (ops->unmap(ops, iova_start + size, size) != size)
832 /* Remap of partial unmap */
833 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ))
836 if (ops->iova_to_phys(ops, iova_start + size + 42)
844 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
845 while (i != BITS_PER_LONG) {
848 if (ops->unmap(ops, iova, size) != size)
851 if (ops->iova_to_phys(ops, iova + 42))
854 /* Remap full block */
855 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
858 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
863 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
866 free_io_pgtable_ops(ops);
868 selftest_running = false;
870 pr_info("self test ok\n");
873 subsys_initcall(arm_v7s_do_selftests);