1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
20 #include <asm/irq_remapping.h>
21 #include <asm/pci-direct.h>
22 #include <asm/msidef.h>
24 #include "irq_remapping.h"
32 struct intel_iommu *iommu;
34 unsigned int bus; /* PCI bus number */
35 unsigned int devfn; /* PCI devfn number */
39 struct intel_iommu *iommu;
46 struct intel_iommu *iommu;
53 struct intel_ir_data {
54 struct irq_2_iommu irq_2_iommu;
55 struct irte irte_entry;
57 struct msi_msg msi_entry;
61 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
62 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
64 static int __read_mostly eim_mode;
65 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
66 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
73 * ->iommu->register_lock
75 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
76 * in single-threaded environment with interrupt disabled, so no need to tabke
77 * the dmar_global_lock.
79 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
80 static const struct irq_domain_ops intel_ir_domain_ops;
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
83 static int __init parse_ioapics_under_ir(void);
85 static bool ir_pre_enabled(struct intel_iommu *iommu)
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
95 static void init_ir_status(struct intel_iommu *iommu)
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
104 static int alloc_irte(struct intel_iommu *iommu,
105 struct irq_2_iommu *irq_iommu, u16 count)
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
112 if (!count || !irq_iommu)
116 count = __roundup_pow_of_two(count);
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 irq_iommu->mode = IRQ_REMAPPING;
139 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
148 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
154 return qi_submit_sync(&desc, iommu);
157 static int modify_irte(struct irq_2_iommu *irq_iommu,
158 struct irte *irte_modified)
160 struct intel_iommu *iommu;
168 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
170 iommu = irq_iommu->iommu;
172 index = irq_iommu->irte_index + irq_iommu->sub_handle;
173 irte = &iommu->ir_table->base[index];
175 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
176 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
179 ret = cmpxchg_double(&irte->low, &irte->high,
180 irte->low, irte->high,
181 irte_modified->low, irte_modified->high);
183 * We use cmpxchg16 to atomically update the 128-bit IRTE,
184 * and it cannot be updated by the hardware or other processors
185 * behind us, so the return value of cmpxchg16 should be the
186 * same as the old value.
192 set_64bit(&irte->low, irte_modified->low);
193 set_64bit(&irte->high, irte_modified->high);
195 __iommu_flush_cache(iommu, irte, sizeof(*irte));
197 rc = qi_flush_iec(iommu, index, 0);
199 /* Update iommu mode according to the IRTE mode */
200 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
201 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
206 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
210 for (i = 0; i < MAX_HPET_TBS; i++)
211 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
212 return ir_hpet[i].iommu;
216 static struct intel_iommu *map_ioapic_to_ir(int apic)
220 for (i = 0; i < MAX_IO_APICS; i++)
221 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
222 return ir_ioapic[i].iommu;
226 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
228 struct dmar_drhd_unit *drhd;
230 drhd = dmar_find_matched_drhd_unit(dev);
237 static int clear_entries(struct irq_2_iommu *irq_iommu)
239 struct irte *start, *entry, *end;
240 struct intel_iommu *iommu;
243 if (irq_iommu->sub_handle)
246 iommu = irq_iommu->iommu;
247 index = irq_iommu->irte_index;
249 start = iommu->ir_table->base + index;
250 end = start + (1 << irq_iommu->irte_mask);
252 for (entry = start; entry < end; entry++) {
253 set_64bit(&entry->low, 0);
254 set_64bit(&entry->high, 0);
256 bitmap_release_region(iommu->ir_table->bitmap, index,
257 irq_iommu->irte_mask);
259 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
263 * source validation type
265 #define SVT_NO_VERIFY 0x0 /* no verification is required */
266 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
267 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
270 * source-id qualifier
272 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
273 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
274 * the third least significant bit
276 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
277 * the second and third least significant bits
279 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
280 * the least three significant bits
284 * set SVT, SQ and SID fields of irte to verify
285 * source ids of interrupt requests
287 static void set_irte_sid(struct irte *irte, unsigned int svt,
288 unsigned int sq, unsigned int sid)
290 if (disable_sourceid_checking)
298 * Set an IRTE to match only the bus number. Interrupt requests that reference
299 * this IRTE must have a requester-id whose bus number is between or equal
300 * to the start_bus and end_bus arguments.
302 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
303 unsigned int end_bus)
305 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
306 (start_bus << 8) | end_bus);
309 static int set_ioapic_sid(struct irte *irte, int apic)
317 down_read(&dmar_global_lock);
318 for (i = 0; i < MAX_IO_APICS; i++) {
319 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
320 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
324 up_read(&dmar_global_lock);
327 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
331 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
336 static int set_hpet_sid(struct irte *irte, u8 id)
344 down_read(&dmar_global_lock);
345 for (i = 0; i < MAX_HPET_TBS; i++) {
346 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
347 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
351 up_read(&dmar_global_lock);
354 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
359 * Should really use SQ_ALL_16. Some platforms are broken.
360 * While we figure out the right quirks for these broken platforms, use
361 * SQ_13_IGNORE_3 for now.
363 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
368 struct set_msi_sid_data {
369 struct pci_dev *pdev;
375 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
377 struct set_msi_sid_data *data = opaque;
379 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
380 data->busmatch_count++;
389 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
391 struct set_msi_sid_data data;
397 data.busmatch_count = 0;
398 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
401 * DMA alias provides us with a PCI device and alias. The only case
402 * where the it will return an alias on a different bus than the
403 * device is the case of a PCIe-to-PCI bridge, where the alias is for
404 * the subordinate bus. In this case we can only verify the bus.
406 * If there are multiple aliases, all with the same bus number,
407 * then all we can do is verify the bus. This is typical in NTB
408 * hardware which use proxy IDs where the device will generate traffic
409 * from multiple devfn numbers on the same bus.
411 * If the alias device is on a different bus than our source device
412 * then we have a topology based alias, use it.
414 * Otherwise, the alias is for a device DMA quirk and we cannot
415 * assume that MSI uses the same requester ID. Therefore use the
418 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
419 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
421 else if (data.count >= 2 && data.busmatch_count == data.count)
422 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
423 else if (data.pdev->bus->number != dev->bus->number)
424 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
426 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
432 static int iommu_load_old_irte(struct intel_iommu *iommu)
434 struct irte *old_ir_table;
435 phys_addr_t irt_phys;
440 /* Check whether the old ir-table has the same size as ours */
441 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
442 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
443 != INTR_REMAP_TABLE_REG_SIZE)
446 irt_phys = irta & VTD_PAGE_MASK;
447 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
449 /* Map the old IR table */
450 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
455 memcpy(iommu->ir_table->base, old_ir_table, size);
457 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
460 * Now check the table for used entries and mark those as
461 * allocated in the bitmap
463 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
464 if (iommu->ir_table->base[i].present)
465 bitmap_set(iommu->ir_table->bitmap, i, 1);
468 memunmap(old_ir_table);
474 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
480 addr = virt_to_phys((void *)iommu->ir_table->base);
482 raw_spin_lock_irqsave(&iommu->register_lock, flags);
484 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
485 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
487 /* Set interrupt-remapping table pointer */
488 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
490 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
491 readl, (sts & DMA_GSTS_IRTPS), sts);
492 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
495 * Global invalidation of interrupt entry cache to make sure the
496 * hardware uses the new irq remapping table.
498 qi_global_iec(iommu);
501 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
506 raw_spin_lock_irqsave(&iommu->register_lock, flags);
508 /* Enable interrupt-remapping */
509 iommu->gcmd |= DMA_GCMD_IRE;
510 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
511 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
512 readl, (sts & DMA_GSTS_IRES), sts);
514 /* Block compatibility-format MSIs */
515 if (sts & DMA_GSTS_CFIS) {
516 iommu->gcmd &= ~DMA_GCMD_CFI;
517 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
518 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
519 readl, !(sts & DMA_GSTS_CFIS), sts);
523 * With CFI clear in the Global Command register, we should be
524 * protected from dangerous (i.e. compatibility) interrupts
525 * regardless of x2apic status. Check just to be sure.
527 if (sts & DMA_GSTS_CFIS)
529 "Compatibility-format IRQs enabled despite intr remapping;\n"
530 "you are vulnerable to IRQ injection.\n");
532 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
535 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
537 struct ir_table *ir_table;
538 struct fwnode_handle *fn;
539 unsigned long *bitmap;
545 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
549 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
550 INTR_REMAP_PAGE_ORDER);
552 pr_err("IR%d: failed to allocate pages of order %d\n",
553 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
557 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
558 if (bitmap == NULL) {
559 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
563 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
565 goto out_free_bitmap;
568 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
569 0, INTR_REMAP_TABLE_ENTRIES,
570 fn, &intel_ir_domain_ops,
572 if (!iommu->ir_domain) {
573 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
574 goto out_free_fwnode;
576 iommu->ir_msi_domain =
577 arch_create_remap_msi_irq_domain(iommu->ir_domain,
581 ir_table->base = page_address(pages);
582 ir_table->bitmap = bitmap;
583 iommu->ir_table = ir_table;
586 * If the queued invalidation is already initialized,
587 * shouldn't disable it.
591 * Clear previous faults.
593 dmar_fault(-1, iommu);
594 dmar_disable_qi(iommu);
596 if (dmar_enable_qi(iommu)) {
597 pr_err("Failed to enable queued invalidation\n");
598 goto out_free_ir_domain;
602 init_ir_status(iommu);
604 if (ir_pre_enabled(iommu)) {
605 if (!is_kdump_kernel()) {
606 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
608 clear_ir_pre_enabled(iommu);
609 iommu_disable_irq_remapping(iommu);
610 } else if (iommu_load_old_irte(iommu))
611 pr_err("Failed to copy IR table for %s from previous kernel\n",
614 pr_info("Copied IR table for %s from previous kernel\n",
618 iommu_set_irq_remapping(iommu, eim_mode);
623 if (iommu->ir_msi_domain)
624 irq_domain_remove(iommu->ir_msi_domain);
625 iommu->ir_msi_domain = NULL;
626 irq_domain_remove(iommu->ir_domain);
627 iommu->ir_domain = NULL;
629 irq_domain_free_fwnode(fn);
633 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
637 iommu->ir_table = NULL;
642 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
644 struct fwnode_handle *fn;
646 if (iommu && iommu->ir_table) {
647 if (iommu->ir_msi_domain) {
648 fn = iommu->ir_msi_domain->fwnode;
650 irq_domain_remove(iommu->ir_msi_domain);
651 irq_domain_free_fwnode(fn);
652 iommu->ir_msi_domain = NULL;
654 if (iommu->ir_domain) {
655 fn = iommu->ir_domain->fwnode;
657 irq_domain_remove(iommu->ir_domain);
658 irq_domain_free_fwnode(fn);
659 iommu->ir_domain = NULL;
661 free_pages((unsigned long)iommu->ir_table->base,
662 INTR_REMAP_PAGE_ORDER);
663 bitmap_free(iommu->ir_table->bitmap);
664 kfree(iommu->ir_table);
665 iommu->ir_table = NULL;
670 * Disable Interrupt Remapping.
672 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
677 if (!ecap_ir_support(iommu->ecap))
681 * global invalidation of interrupt entry cache before disabling
682 * interrupt-remapping.
684 qi_global_iec(iommu);
686 raw_spin_lock_irqsave(&iommu->register_lock, flags);
688 sts = readl(iommu->reg + DMAR_GSTS_REG);
689 if (!(sts & DMA_GSTS_IRES))
692 iommu->gcmd &= ~DMA_GCMD_IRE;
693 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
695 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
696 readl, !(sts & DMA_GSTS_IRES), sts);
699 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
702 static int __init dmar_x2apic_optout(void)
704 struct acpi_table_dmar *dmar;
705 dmar = (struct acpi_table_dmar *)dmar_tbl;
706 if (!dmar || no_x2apic_optout)
708 return dmar->flags & DMAR_X2APIC_OPT_OUT;
711 static void __init intel_cleanup_irq_remapping(void)
713 struct dmar_drhd_unit *drhd;
714 struct intel_iommu *iommu;
716 for_each_iommu(iommu, drhd) {
717 if (ecap_ir_support(iommu->ecap)) {
718 iommu_disable_irq_remapping(iommu);
719 intel_teardown_irq_remapping(iommu);
723 if (x2apic_supported())
724 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
727 static int __init intel_prepare_irq_remapping(void)
729 struct dmar_drhd_unit *drhd;
730 struct intel_iommu *iommu;
733 if (irq_remap_broken) {
734 pr_warn("This system BIOS has enabled interrupt remapping\n"
735 "on a chipset that contains an erratum making that\n"
736 "feature unstable. To maintain system stability\n"
737 "interrupt remapping is being disabled. Please\n"
738 "contact your BIOS vendor for an update\n");
739 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
743 if (dmar_table_init() < 0)
746 if (!dmar_ir_support())
749 if (parse_ioapics_under_ir()) {
750 pr_info("Not enabling interrupt remapping\n");
754 /* First make sure all IOMMUs support IRQ remapping */
755 for_each_iommu(iommu, drhd)
756 if (!ecap_ir_support(iommu->ecap))
759 /* Detect remapping mode: lapic or x2apic */
760 if (x2apic_supported()) {
761 eim = !dmar_x2apic_optout();
763 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
764 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
768 for_each_iommu(iommu, drhd) {
769 if (eim && !ecap_eim_support(iommu->ecap)) {
770 pr_info("%s does not support EIM\n", iommu->name);
777 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
779 /* Do the initializations early */
780 for_each_iommu(iommu, drhd) {
781 if (intel_setup_irq_remapping(iommu)) {
782 pr_err("Failed to setup irq remapping for %s\n",
791 intel_cleanup_irq_remapping();
796 * Set Posted-Interrupts capability.
798 static inline void set_irq_posting_cap(void)
800 struct dmar_drhd_unit *drhd;
801 struct intel_iommu *iommu;
803 if (!disable_irq_post) {
805 * If IRTE is in posted format, the 'pda' field goes across the
806 * 64-bit boundary, we need use cmpxchg16b to atomically update
807 * it. We only expose posted-interrupt when X86_FEATURE_CX16
808 * is supported. Actually, hardware platforms supporting PI
809 * should have X86_FEATURE_CX16 support, this has been confirmed
810 * with Intel hardware guys.
812 if (boot_cpu_has(X86_FEATURE_CX16))
813 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
815 for_each_iommu(iommu, drhd)
816 if (!cap_pi_support(iommu->cap)) {
817 intel_irq_remap_ops.capability &=
818 ~(1 << IRQ_POSTING_CAP);
824 static int __init intel_enable_irq_remapping(void)
826 struct dmar_drhd_unit *drhd;
827 struct intel_iommu *iommu;
831 * Setup Interrupt-remapping for all the DRHD's now.
833 for_each_iommu(iommu, drhd) {
834 if (!ir_pre_enabled(iommu))
835 iommu_enable_irq_remapping(iommu);
842 irq_remapping_enabled = 1;
844 set_irq_posting_cap();
846 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
848 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
851 intel_cleanup_irq_remapping();
855 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
856 struct intel_iommu *iommu,
857 struct acpi_dmar_hardware_unit *drhd)
859 struct acpi_dmar_pci_path *path;
861 int count, free = -1;
864 path = (struct acpi_dmar_pci_path *)(scope + 1);
865 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
866 / sizeof(struct acpi_dmar_pci_path);
868 while (--count > 0) {
870 * Access PCI directly due to the PCI
871 * subsystem isn't initialized yet.
873 bus = read_pci_config_byte(bus, path->device, path->function,
878 for (count = 0; count < MAX_HPET_TBS; count++) {
879 if (ir_hpet[count].iommu == iommu &&
880 ir_hpet[count].id == scope->enumeration_id)
882 else if (ir_hpet[count].iommu == NULL && free == -1)
886 pr_warn("Exceeded Max HPET blocks\n");
890 ir_hpet[free].iommu = iommu;
891 ir_hpet[free].id = scope->enumeration_id;
892 ir_hpet[free].bus = bus;
893 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
894 pr_info("HPET id %d under DRHD base 0x%Lx\n",
895 scope->enumeration_id, drhd->address);
900 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
901 struct intel_iommu *iommu,
902 struct acpi_dmar_hardware_unit *drhd)
904 struct acpi_dmar_pci_path *path;
906 int count, free = -1;
909 path = (struct acpi_dmar_pci_path *)(scope + 1);
910 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
911 / sizeof(struct acpi_dmar_pci_path);
913 while (--count > 0) {
915 * Access PCI directly due to the PCI
916 * subsystem isn't initialized yet.
918 bus = read_pci_config_byte(bus, path->device, path->function,
923 for (count = 0; count < MAX_IO_APICS; count++) {
924 if (ir_ioapic[count].iommu == iommu &&
925 ir_ioapic[count].id == scope->enumeration_id)
927 else if (ir_ioapic[count].iommu == NULL && free == -1)
931 pr_warn("Exceeded Max IO APICS\n");
935 ir_ioapic[free].bus = bus;
936 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
937 ir_ioapic[free].iommu = iommu;
938 ir_ioapic[free].id = scope->enumeration_id;
939 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
940 scope->enumeration_id, drhd->address, iommu->seq_id);
945 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
946 struct intel_iommu *iommu)
949 struct acpi_dmar_hardware_unit *drhd;
950 struct acpi_dmar_device_scope *scope;
953 drhd = (struct acpi_dmar_hardware_unit *)header;
954 start = (void *)(drhd + 1);
955 end = ((void *)drhd) + header->length;
957 while (start < end && ret == 0) {
959 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
960 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
961 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
962 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
963 start += scope->length;
969 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
973 for (i = 0; i < MAX_HPET_TBS; i++)
974 if (ir_hpet[i].iommu == iommu)
975 ir_hpet[i].iommu = NULL;
977 for (i = 0; i < MAX_IO_APICS; i++)
978 if (ir_ioapic[i].iommu == iommu)
979 ir_ioapic[i].iommu = NULL;
983 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
986 static int __init parse_ioapics_under_ir(void)
988 struct dmar_drhd_unit *drhd;
989 struct intel_iommu *iommu;
990 bool ir_supported = false;
993 for_each_iommu(iommu, drhd) {
996 if (!ecap_ir_support(iommu->ecap))
999 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
1003 ir_supported = true;
1009 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1010 int ioapic_id = mpc_ioapic_id(ioapic_idx);
1011 if (!map_ioapic_to_ir(ioapic_id)) {
1012 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1013 "interrupt remapping will be disabled\n",
1022 static int __init ir_dev_scope_init(void)
1026 if (!irq_remapping_enabled)
1029 down_write(&dmar_global_lock);
1030 ret = dmar_dev_scope_init();
1031 up_write(&dmar_global_lock);
1035 rootfs_initcall(ir_dev_scope_init);
1037 static void disable_irq_remapping(void)
1039 struct dmar_drhd_unit *drhd;
1040 struct intel_iommu *iommu = NULL;
1043 * Disable Interrupt-remapping for all the DRHD's now.
1045 for_each_iommu(iommu, drhd) {
1046 if (!ecap_ir_support(iommu->ecap))
1049 iommu_disable_irq_remapping(iommu);
1053 * Clear Posted-Interrupts capability.
1055 if (!disable_irq_post)
1056 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1059 static int reenable_irq_remapping(int eim)
1061 struct dmar_drhd_unit *drhd;
1063 struct intel_iommu *iommu = NULL;
1065 for_each_iommu(iommu, drhd)
1067 dmar_reenable_qi(iommu);
1070 * Setup Interrupt-remapping for all the DRHD's now.
1072 for_each_iommu(iommu, drhd) {
1073 if (!ecap_ir_support(iommu->ecap))
1076 /* Set up interrupt remapping for iommu.*/
1077 iommu_set_irq_remapping(iommu, eim);
1078 iommu_enable_irq_remapping(iommu);
1085 set_irq_posting_cap();
1091 * handle error condition gracefully here!
1096 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1098 memset(irte, 0, sizeof(*irte));
1101 irte->dst_mode = apic->irq_dest_mode;
1103 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1104 * actual level or edge trigger will be setup in the IO-APIC
1105 * RTE. This will help simplify level triggered irq migration.
1106 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1107 * irq migration in the presence of interrupt-remapping.
1109 irte->trigger_mode = 0;
1110 irte->dlvry_mode = apic->irq_delivery_mode;
1111 irte->vector = vector;
1112 irte->dest_id = IRTE_DEST(dest);
1113 irte->redir_hint = 1;
1116 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1118 struct intel_iommu *iommu = NULL;
1123 switch (info->type) {
1124 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1125 iommu = map_ioapic_to_ir(info->ioapic_id);
1127 case X86_IRQ_ALLOC_TYPE_HPET:
1128 iommu = map_hpet_to_ir(info->hpet_id);
1130 case X86_IRQ_ALLOC_TYPE_MSI:
1131 case X86_IRQ_ALLOC_TYPE_MSIX:
1132 iommu = map_dev_to_ir(info->msi_dev);
1139 return iommu ? iommu->ir_domain : NULL;
1142 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1144 struct intel_iommu *iommu;
1149 switch (info->type) {
1150 case X86_IRQ_ALLOC_TYPE_MSI:
1151 case X86_IRQ_ALLOC_TYPE_MSIX:
1152 iommu = map_dev_to_ir(info->msi_dev);
1154 return iommu->ir_msi_domain;
1163 struct irq_remap_ops intel_irq_remap_ops = {
1164 .prepare = intel_prepare_irq_remapping,
1165 .enable = intel_enable_irq_remapping,
1166 .disable = disable_irq_remapping,
1167 .reenable = reenable_irq_remapping,
1168 .enable_faulting = enable_drhd_fault_handling,
1169 .get_ir_irq_domain = intel_get_ir_irq_domain,
1170 .get_irq_domain = intel_get_irq_domain,
1173 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1175 struct intel_ir_data *ir_data = irqd->chip_data;
1176 struct irte *irte = &ir_data->irte_entry;
1177 struct irq_cfg *cfg = irqd_cfg(irqd);
1180 * Atomically updates the IRTE with the new destination, vector
1181 * and flushes the interrupt entry cache.
1183 irte->vector = cfg->vector;
1184 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1186 /* Update the hardware only if the interrupt is in remapped mode. */
1187 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1188 modify_irte(&ir_data->irq_2_iommu, irte);
1192 * Migrate the IO-APIC irq in the presence of intr-remapping.
1194 * For both level and edge triggered, irq migration is a simple atomic
1195 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1197 * For level triggered, we eliminate the io-apic RTE modification (with the
1198 * updated vector information), by using a virtual vector (io-apic pin number).
1199 * Real vector that is used for interrupting cpu will be coming from
1200 * the interrupt-remapping table entry.
1202 * As the migration is a simple atomic update of IRTE, the same mechanism
1203 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1206 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1209 struct irq_data *parent = data->parent_data;
1210 struct irq_cfg *cfg = irqd_cfg(data);
1213 ret = parent->chip->irq_set_affinity(parent, mask, force);
1214 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1217 intel_ir_reconfigure_irte(data, false);
1219 * After this point, all the interrupts will start arriving
1220 * at the new destination. So, time to cleanup the previous
1221 * vector allocation.
1223 send_cleanup_vector(cfg);
1225 return IRQ_SET_MASK_OK_DONE;
1228 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1229 struct msi_msg *msg)
1231 struct intel_ir_data *ir_data = irq_data->chip_data;
1233 *msg = ir_data->msi_entry;
1236 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1238 struct intel_ir_data *ir_data = data->chip_data;
1239 struct vcpu_data *vcpu_pi_info = info;
1241 /* stop posting interrupts, back to remapping mode */
1242 if (!vcpu_pi_info) {
1243 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1245 struct irte irte_pi;
1248 * We are not caching the posted interrupt entry. We
1249 * copy the data from the remapped entry and modify
1250 * the fields which are relevant for posted mode. The
1251 * cached remapped entry is used for switching back to
1254 memset(&irte_pi, 0, sizeof(irte_pi));
1255 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1257 /* Update the posted mode fields */
1259 irte_pi.p_urgent = 0;
1260 irte_pi.p_vector = vcpu_pi_info->vector;
1261 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1262 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1263 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1264 ~(-1UL << PDA_HIGH_BIT);
1266 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1272 static struct irq_chip intel_ir_chip = {
1274 .irq_ack = apic_ack_irq,
1275 .irq_set_affinity = intel_ir_set_affinity,
1276 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1277 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1280 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1281 struct irq_cfg *irq_cfg,
1282 struct irq_alloc_info *info,
1283 int index, int sub_handle)
1285 struct IR_IO_APIC_route_entry *entry;
1286 struct irte *irte = &data->irte_entry;
1287 struct msi_msg *msg = &data->msi_entry;
1289 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1290 switch (info->type) {
1291 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1292 /* Set source-id of interrupt request */
1293 set_ioapic_sid(irte, info->ioapic_id);
1294 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1295 info->ioapic_id, irte->present, irte->fpd,
1296 irte->dst_mode, irte->redir_hint,
1297 irte->trigger_mode, irte->dlvry_mode,
1298 irte->avail, irte->vector, irte->dest_id,
1299 irte->sid, irte->sq, irte->svt);
1301 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1302 info->ioapic_entry = NULL;
1303 memset(entry, 0, sizeof(*entry));
1304 entry->index2 = (index >> 15) & 0x1;
1307 entry->index = (index & 0x7fff);
1309 * IO-APIC RTE will be configured with virtual vector.
1310 * irq handler will do the explicit EOI to the io-apic.
1312 entry->vector = info->ioapic_pin;
1313 entry->mask = 0; /* enable IRQ */
1314 entry->trigger = info->ioapic_trigger;
1315 entry->polarity = info->ioapic_polarity;
1316 if (info->ioapic_trigger)
1317 entry->mask = 1; /* Mask level triggered irqs. */
1320 case X86_IRQ_ALLOC_TYPE_HPET:
1321 case X86_IRQ_ALLOC_TYPE_MSI:
1322 case X86_IRQ_ALLOC_TYPE_MSIX:
1323 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1324 set_hpet_sid(irte, info->hpet_id);
1326 set_msi_sid(irte, info->msi_dev);
1328 msg->address_hi = MSI_ADDR_BASE_HI;
1329 msg->data = sub_handle;
1330 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1332 MSI_ADDR_IR_INDEX1(index) |
1333 MSI_ADDR_IR_INDEX2(index);
1342 static void intel_free_irq_resources(struct irq_domain *domain,
1343 unsigned int virq, unsigned int nr_irqs)
1345 struct irq_data *irq_data;
1346 struct intel_ir_data *data;
1347 struct irq_2_iommu *irq_iommu;
1348 unsigned long flags;
1350 for (i = 0; i < nr_irqs; i++) {
1351 irq_data = irq_domain_get_irq_data(domain, virq + i);
1352 if (irq_data && irq_data->chip_data) {
1353 data = irq_data->chip_data;
1354 irq_iommu = &data->irq_2_iommu;
1355 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1356 clear_entries(irq_iommu);
1357 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1358 irq_domain_reset_irq_data(irq_data);
1364 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1365 unsigned int virq, unsigned int nr_irqs,
1368 struct intel_iommu *iommu = domain->host_data;
1369 struct irq_alloc_info *info = arg;
1370 struct intel_ir_data *data, *ird;
1371 struct irq_data *irq_data;
1372 struct irq_cfg *irq_cfg;
1375 if (!info || !iommu)
1377 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1378 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1382 * With IRQ remapping enabled, don't need contiguous CPU vectors
1383 * to support multiple MSI interrupts.
1385 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1386 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1388 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1393 data = kzalloc(sizeof(*data), GFP_KERNEL);
1395 goto out_free_parent;
1397 down_read(&dmar_global_lock);
1398 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1399 up_read(&dmar_global_lock);
1401 pr_warn("Failed to allocate IRTE\n");
1403 goto out_free_parent;
1406 for (i = 0; i < nr_irqs; i++) {
1407 irq_data = irq_domain_get_irq_data(domain, virq + i);
1408 irq_cfg = irqd_cfg(irq_data);
1409 if (!irq_data || !irq_cfg) {
1417 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1420 /* Initialize the common data */
1421 ird->irq_2_iommu = data->irq_2_iommu;
1422 ird->irq_2_iommu.sub_handle = i;
1427 irq_data->hwirq = (index << 16) + i;
1428 irq_data->chip_data = ird;
1429 irq_data->chip = &intel_ir_chip;
1430 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1431 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1436 intel_free_irq_resources(domain, virq, i);
1438 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1442 static void intel_irq_remapping_free(struct irq_domain *domain,
1443 unsigned int virq, unsigned int nr_irqs)
1445 intel_free_irq_resources(domain, virq, nr_irqs);
1446 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1449 static int intel_irq_remapping_activate(struct irq_domain *domain,
1450 struct irq_data *irq_data, bool reserve)
1452 intel_ir_reconfigure_irte(irq_data, true);
1456 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1457 struct irq_data *irq_data)
1459 struct intel_ir_data *data = irq_data->chip_data;
1462 memset(&entry, 0, sizeof(entry));
1463 modify_irte(&data->irq_2_iommu, &entry);
1466 static const struct irq_domain_ops intel_ir_domain_ops = {
1467 .alloc = intel_irq_remapping_alloc,
1468 .free = intel_irq_remapping_free,
1469 .activate = intel_irq_remapping_activate,
1470 .deactivate = intel_irq_remapping_deactivate,
1474 * Support of Interrupt Remapping Unit Hotplug
1476 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1479 int eim = x2apic_enabled();
1481 if (eim && !ecap_eim_support(iommu->ecap)) {
1482 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1483 iommu->reg_phys, iommu->ecap);
1487 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1488 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1493 /* TODO: check all IOAPICs are covered by IOMMU */
1495 /* Setup Interrupt-remapping now. */
1496 ret = intel_setup_irq_remapping(iommu);
1498 pr_err("Failed to setup irq remapping for %s\n",
1500 intel_teardown_irq_remapping(iommu);
1501 ir_remove_ioapic_hpet_scope(iommu);
1503 iommu_enable_irq_remapping(iommu);
1509 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1512 struct intel_iommu *iommu = dmaru->iommu;
1514 if (!irq_remapping_enabled)
1518 if (!ecap_ir_support(iommu->ecap))
1520 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1521 !cap_pi_support(iommu->cap))
1525 if (!iommu->ir_table)
1526 ret = dmar_ir_add(dmaru, iommu);
1528 if (iommu->ir_table) {
1529 if (!bitmap_empty(iommu->ir_table->bitmap,
1530 INTR_REMAP_TABLE_ENTRIES)) {
1533 iommu_disable_irq_remapping(iommu);
1534 intel_teardown_irq_remapping(iommu);
1535 ir_remove_ioapic_hpet_scope(iommu);