drivers/iommu/intel-svm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright © 2015 Intel Corporation.
   4  *
   5  * Authors: David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #include <linux/intel-iommu.h>
   9 #include <linux/mmu_notifier.h>
  10 #include <linux/sched.h>
  11 #include <linux/sched/mm.h>
  12 #include <linux/slab.h>
  13 #include <linux/intel-svm.h>
  14 #include <linux/rculist.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci-ats.h>
  17 #include <linux/dmar.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/mm_types.h>
  20 #include <asm/page.h>
  21
  22 #include "intel-pasid.h"
  23
  24 static irqreturn_t prq_event_thread(int irq, void *d);
  25
  26 int intel_svm_init(struct intel_iommu *iommu)
  27 {
  28         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
  29                         !cap_fl1gp_support(iommu->cap))
  30                 return -EINVAL;
  31
  32         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
  33                         !cap_5lp_support(iommu->cap))
  34                 return -EINVAL;
  35
  36         return 0;
  37 }
  38
  39 #define PRQ_ORDER 0
  40
  41 int intel_svm_enable_prq(struct intel_iommu *iommu)
  42 {
  43         struct page *pages;
  44         int irq, ret;
  45
  46         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
  47         if (!pages) {
  48                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
  49                         iommu->name);
  50                 return -ENOMEM;
  51         }
  52         iommu->prq = page_address(pages);
  53
  54         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
  55         if (irq <= 0) {
  56                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
  57                        iommu->name);
  58                 ret = -EINVAL;
  59         err:
  60                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  61                 iommu->prq = NULL;
  62                 return ret;
  63         }
  64         iommu->pr_irq = irq;
  65
  66         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
  67
  68         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
  69                                    iommu->prq_name, iommu);
  70         if (ret) {
  71                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
  72                        iommu->name);
  73                 dmar_free_hwirq(irq);
  74                 iommu->pr_irq = 0;
  75                 goto err;
  76         }
  77         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  78         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  79         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
  80
  81         return 0;
  82 }
  83
  84 int intel_svm_finish_prq(struct intel_iommu *iommu)
  85 {
  86         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  87         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  88         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
  89
  90         if (iommu->pr_irq) {
  91                 free_irq(iommu->pr_irq, iommu);
  92                 dmar_free_hwirq(iommu->pr_irq);
  93                 iommu->pr_irq = 0;
  94         }
  95
  96         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  97         iommu->prq = NULL;
  98
  99         return 0;
 100 }
 101
 102 static void __flush_svm_range_dev(struct intel_svm *svm,
 103                                   struct intel_svm_dev *sdev,
 104                                   unsigned long address,
 105                                   unsigned long pages, int ih)
 106 {
 107         struct qi_desc desc;
 108
 109         if (pages == -1) {
 110                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 111                         QI_EIOTLB_DID(sdev->did) |
 112                         QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
 113                         QI_EIOTLB_TYPE;
 114                 desc.qw1 = 0;
 115         } else {
 116                 int mask = ilog2(__roundup_pow_of_two(pages));
 117
 118                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 119                                 QI_EIOTLB_DID(sdev->did) |
 120                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
 121                                 QI_EIOTLB_TYPE;
 122                 desc.qw1 = QI_EIOTLB_ADDR(address) |
 123                                 QI_EIOTLB_IH(ih) |
 124                                 QI_EIOTLB_AM(mask);
 125         }
 126         desc.qw2 = 0;
 127         desc.qw3 = 0;
 128         qi_submit_sync(&desc, svm->iommu);
 129
 130         if (sdev->dev_iotlb) {
 131                 desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
 132                                 QI_DEV_EIOTLB_SID(sdev->sid) |
 133                                 QI_DEV_EIOTLB_QDEP(sdev->qdep) |
 134                                 QI_DEIOTLB_TYPE;
 135                 if (pages == -1) {
 136                         desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
 137                                         QI_DEV_EIOTLB_SIZE;
 138                 } else if (pages > 1) {
 139                         /* The least significant zero bit indicates the size. So,
 140                          * for example, an "address" value of 0x12345f000 will
 141                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 142                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 143                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 144
 145                         desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
 146                                         (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 147                 } else {
 148                         desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
 149                 }
 150                 desc.qw2 = 0;
 151                 desc.qw3 = 0;
 152                 qi_submit_sync(&desc, svm->iommu);
 153         }
 154 }
 155
 156 static void intel_flush_svm_range_dev(struct intel_svm *svm,
 157                                       struct intel_svm_dev *sdev,
 158                                       unsigned long address,
 159                                       unsigned long pages, int ih)
 160 {
 161         unsigned long shift = ilog2(__roundup_pow_of_two(pages));
 162         unsigned long align = (1ULL << (VTD_PAGE_SHIFT + shift));
 163         unsigned long start = ALIGN_DOWN(address, align);
 164         unsigned long end = ALIGN(address + (pages << VTD_PAGE_SHIFT), align);
 165
 166         while (start < end) {
 167                 __flush_svm_range_dev(svm, sdev, start, align >> VTD_PAGE_SHIFT, ih);
 168                 start += align;
 169         }
 170 }
 171
 172 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 173                                 unsigned long pages, int ih)
 174 {
 175         struct intel_svm_dev *sdev;
 176
 177         rcu_read_lock();
 178         list_for_each_entry_rcu(sdev, &svm->devs, list)
 179                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih);
 180         rcu_read_unlock();
 181 }
 182
 183 /* Pages have been freed at this point */
 184 static void intel_invalidate_range(struct mmu_notifier *mn,
 185                                    struct mm_struct *mm,
 186                                    unsigned long start, unsigned long end)
 187 {
 188         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 189
 190         intel_flush_svm_range(svm, start,
 191                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0);
 192 }
 193
 194 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 195 {
 196         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 197         struct intel_svm_dev *sdev;
 198
 199         /* This might end up being called from exit_mmap(), *before* the page
 200          * tables are cleared. And __mmu_notifier_release() will delete us from
 201          * the list of notifiers so that our invalidate_range() callback doesn't
 202          * get called when the page tables are cleared. So we need to protect
 203          * against hardware accessing those page tables.
 204          *
 205          * We do it by clearing the entry in the PASID table and then flushing
 206          * the IOTLB and the PASID table caches. This might upset hardware;
 207          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 208          * page) so that we end up taking a fault that the hardware really
 209          * *has* to handle gracefully without affecting other processes.
 210          */
 211         rcu_read_lock();
 212         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 213                 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
 214                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
 215         }
 216         rcu_read_unlock();
 217
 218 }
 219
 220 static const struct mmu_notifier_ops intel_mmuops = {
 221         .release = intel_mm_release,
 222         .invalidate_range = intel_invalidate_range,
 223 };
 224
 225 static DEFINE_MUTEX(pasid_mutex);
 226 static LIST_HEAD(global_svm_list);
 227
 228 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 229 {
 230         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 231         struct device_domain_info *info;
 232         struct intel_svm_dev *sdev;
 233         struct intel_svm *svm = NULL;
 234         struct mm_struct *mm = NULL;
 235         int pasid_max;
 236         int ret;
 237
 238         if (!iommu || dmar_disabled)
 239                 return -EINVAL;
 240
 241         if (dev_is_pci(dev)) {
 242                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 243                 if (pasid_max < 0)
 244                         return -EINVAL;
 245         } else
 246                 pasid_max = 1 << 20;
 247
 248         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 249                 if (!ecap_srs(iommu->ecap))
 250                         return -EINVAL;
 251         } else if (pasid) {
 252                 mm = get_task_mm(current);
 253                 BUG_ON(!mm);
 254         }
 255
 256         mutex_lock(&pasid_mutex);
 257         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 258                 struct intel_svm *t;
 259
 260                 list_for_each_entry(t, &global_svm_list, list) {
 261                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 262                                 continue;
 263
 264                         svm = t;
 265                         if (svm->pasid >= pasid_max) {
 266                                 dev_warn(dev,
 267                                          "Limited PASID width. Cannot use existing PASID %d\n",
 268                                          svm->pasid);
 269                                 ret = -ENOSPC;
 270                                 goto out;
 271                         }
 272
 273                         list_for_each_entry(sdev, &svm->devs, list) {
 274                                 if (dev == sdev->dev) {
 275                                         if (sdev->ops != ops) {
 276                                                 ret = -EBUSY;
 277                                                 goto out;
 278                                         }
 279                                         sdev->users++;
 280                                         goto success;
 281                                 }
 282                         }
 283
 284                         break;
 285                 }
 286         }
 287
 288         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 289         if (!sdev) {
 290                 ret = -ENOMEM;
 291                 goto out;
 292         }
 293         sdev->dev = dev;
 294
 295         ret = intel_iommu_enable_pasid(iommu, dev);
 296         if (ret || !pasid) {
 297                 /* If they don't actually want to assign a PASID, this is
 298                  * just an enabling check/preparation. */
 299                 kfree(sdev);
 300                 goto out;
 301         }
 302
 303         info = dev->archdata.iommu;
 304         if (!info || !info->pasid_supported) {
 305                 kfree(sdev);
 306                 goto out;
 307         }
 308
 309         sdev->did = FLPT_DEFAULT_DID;
 310         sdev->sid = PCI_DEVID(info->bus, info->devfn);
 311         if (info->ats_enabled) {
 312                 sdev->dev_iotlb = 1;
 313                 sdev->qdep = info->ats_qdep;
 314                 if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
 315                         sdev->qdep = 0;
 316         }
 317
 318         /* Finish the setup now we know we're keeping it */
 319         sdev->users = 1;
 320         sdev->ops = ops;
 321         init_rcu_head(&sdev->rcu);
 322
 323         if (!svm) {
 324                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 325                 if (!svm) {
 326                         ret = -ENOMEM;
 327                         kfree(sdev);
 328                         goto out;
 329                 }
 330                 svm->iommu = iommu;
 331
 332                 if (pasid_max > intel_pasid_max_id)
 333                         pasid_max = intel_pasid_max_id;
 334
 335                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 336                 ret = intel_pasid_alloc_id(svm,
 337                                            !!cap_caching_mode(iommu->cap),
 338                                            pasid_max, GFP_KERNEL);
 339                 if (ret < 0) {
 340                         kfree(svm);
 341                         kfree(sdev);
 342                         goto out;
 343                 }
 344                 svm->pasid = ret;
 345                 svm->notifier.ops = &intel_mmuops;
 346                 svm->mm = mm;
 347                 svm->flags = flags;
 348                 INIT_LIST_HEAD_RCU(&svm->devs);
 349                 INIT_LIST_HEAD(&svm->list);
 350                 ret = -ENOMEM;
 351                 if (mm) {
 352                         ret = mmu_notifier_register(&svm->notifier, mm);
 353                         if (ret) {
 354                                 intel_pasid_free_id(svm->pasid);
 355                                 kfree(svm);
 356                                 kfree(sdev);
 357                                 goto out;
 358                         }
 359                 }
 360
 361                 spin_lock(&iommu->lock);
 362                 ret = intel_pasid_setup_first_level(iommu, dev,
 363                                 mm ? mm->pgd : init_mm.pgd,
 364                                 svm->pasid, FLPT_DEFAULT_DID,
 365                                 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
 366                 spin_unlock(&iommu->lock);
 367                 if (ret) {
 368                         if (mm)
 369                                 mmu_notifier_unregister(&svm->notifier, mm);
 370                         intel_pasid_free_id(svm->pasid);
 371                         kfree(svm);
 372                         kfree(sdev);
 373                         goto out;
 374                 }
 375
 376                 list_add_tail(&svm->list, &global_svm_list);
 377         } else {
 378                 /*
 379                  * Binding a new device with existing PASID, need to setup
 380                  * the PASID entry.
 381                  */
 382                 spin_lock(&iommu->lock);
 383                 ret = intel_pasid_setup_first_level(iommu, dev,
 384                                                 mm ? mm->pgd : init_mm.pgd,
 385                                                 svm->pasid, FLPT_DEFAULT_DID,
 386                                                 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
 387                 spin_unlock(&iommu->lock);
 388                 if (ret) {
 389                         kfree(sdev);
 390                         goto out;
 391                 }
 392         }
 393         list_add_rcu(&sdev->list, &svm->devs);
 394
 395  success:
 396         *pasid = svm->pasid;
 397         ret = 0;
 398  out:
 399         mutex_unlock(&pasid_mutex);
 400         if (mm)
 401                 mmput(mm);
 402         return ret;
 403 }
 404 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 405
 406 int intel_svm_unbind_mm(struct device *dev, int pasid)
 407 {
 408         struct intel_svm_dev *sdev;
 409         struct intel_iommu *iommu;
 410         struct intel_svm *svm;
 411         int ret = -EINVAL;
 412
 413         mutex_lock(&pasid_mutex);
 414         iommu = intel_svm_device_to_iommu(dev);
 415         if (!iommu)
 416                 goto out;
 417
 418         svm = intel_pasid_lookup_id(pasid);
 419         if (!svm)
 420                 goto out;
 421
 422         list_for_each_entry(sdev, &svm->devs, list) {
 423                 if (dev == sdev->dev) {
 424                         ret = 0;
 425                         sdev->users--;
 426                         if (!sdev->users) {
 427                                 list_del_rcu(&sdev->list);
 428                                 /* Flush the PASID cache and IOTLB for this device.
 429                                  * Note that we do depend on the hardware *not* using
 430                                  * the PASID any more. Just as we depend on other
 431                                  * devices never using PASIDs that they have no right
 432                                  * to use. We have a *shared* PASID table, because it's
 433                                  * large and has to be physically contiguous. So it's
 434                                  * hard to be as defensive as we might like. */
 435                                 intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
 436                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0);
 437                                 kfree_rcu(sdev, rcu);
 438
 439                                 if (list_empty(&svm->devs)) {
 440                                         intel_pasid_free_id(svm->pasid);
 441                                         if (svm->mm)
 442                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 443
 444                                         list_del(&svm->list);
 445
 446                                         /* We mandate that no page faults may be outstanding
 447                                          * for the PASID when intel_svm_unbind_mm() is called.
 448                                          * If that is not obeyed, subtle errors will happen.
 449                                          * Let's make them less subtle... */
 450                                         memset(svm, 0x6b, sizeof(*svm));
 451                                         kfree(svm);
 452                                 }
 453                         }
 454                         break;
 455                 }
 456         }
 457  out:
 458         mutex_unlock(&pasid_mutex);
 459
 460         return ret;
 461 }
 462 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 463
 464 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 465 {
 466         struct intel_iommu *iommu;
 467         struct intel_svm *svm;
 468         int ret = -EINVAL;
 469
 470         mutex_lock(&pasid_mutex);
 471         iommu = intel_svm_device_to_iommu(dev);
 472         if (!iommu)
 473                 goto out;
 474
 475         svm = intel_pasid_lookup_id(pasid);
 476         if (!svm)
 477                 goto out;
 478
 479         /* init_mm is used in this case */
 480         if (!svm->mm)
 481                 ret = 1;
 482         else if (atomic_read(&svm->mm->mm_users) > 0)
 483                 ret = 1;
 484         else
 485                 ret = 0;
 486
 487  out:
 488         mutex_unlock(&pasid_mutex);
 489
 490         return ret;
 491 }
 492 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 493
 494 /* Page request queue descriptor */
 495 struct page_req_dsc {
 496         union {
 497                 struct {
 498                         u64 type:8;
 499                         u64 pasid_present:1;
 500                         u64 priv_data_present:1;
 501                         u64 rsvd:6;
 502                         u64 rid:16;
 503                         u64 pasid:20;
 504                         u64 exe_req:1;
 505                         u64 pm_req:1;
 506                         u64 rsvd2:10;
 507                 };
 508                 u64 qw_0;
 509         };
 510         union {
 511                 struct {
 512                         u64 rd_req:1;
 513                         u64 wr_req:1;
 514                         u64 lpig:1;
 515                         u64 prg_index:9;
 516                         u64 addr:52;
 517                 };
 518                 u64 qw_1;
 519         };
 520         u64 priv_data[2];
 521 };
 522
 523 #define PRQ_RING_MASK   ((0x1000 << PRQ_ORDER) - 0x20)
 524
 525 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 526 {
 527         unsigned long requested = 0;
 528
 529         if (req->exe_req)
 530                 requested |= VM_EXEC;
 531
 532         if (req->rd_req)
 533                 requested |= VM_READ;
 534
 535         if (req->wr_req)
 536                 requested |= VM_WRITE;
 537
 538         return (requested & ~vma->vm_flags) != 0;
 539 }
 540
 541 static bool is_canonical_address(u64 addr)
 542 {
 543         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 544         long saddr = (long) addr;
 545
 546         return (((saddr << shift) >> shift) == saddr);
 547 }
 548
 549 static irqreturn_t prq_event_thread(int irq, void *d)
 550 {
 551         struct intel_iommu *iommu = d;
 552         struct intel_svm *svm = NULL;
 553         int head, tail, handled = 0;
 554
 555         /* Clear PPR bit before reading head/tail registers, to
 556          * ensure that we get a new interrupt if needed. */
 557         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 558
 559         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 560         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 561         while (head != tail) {
 562                 struct intel_svm_dev *sdev;
 563                 struct vm_area_struct *vma;
 564                 struct page_req_dsc *req;
 565                 struct qi_desc resp;
 566                 int result;
 567                 vm_fault_t ret;
 568                 u64 address;
 569
 570                 handled = 1;
 571
 572                 req = &iommu->prq[head / sizeof(*req)];
 573
 574                 result = QI_RESP_FAILURE;
 575                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 576                 if (!req->pasid_present) {
 577                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 578                                iommu->name, ((unsigned long long *)req)[0],
 579                                ((unsigned long long *)req)[1]);
 580                         goto no_pasid;
 581                 }
 582
 583                 if (!svm || svm->pasid != req->pasid) {
 584                         rcu_read_lock();
 585                         svm = intel_pasid_lookup_id(req->pasid);
 586                         /* It *can't* go away, because the driver is not permitted
 587                          * to unbind the mm while any page faults are outstanding.
 588                          * So we only need RCU to protect the internal idr code. */
 589                         rcu_read_unlock();
 590
 591                         if (!svm) {
 592                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 593                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 594                                        ((unsigned long long *)req)[1]);
 595                                 goto no_pasid;
 596                         }
 597                 }
 598
 599                 result = QI_RESP_INVALID;
 600                 /* Since we're using init_mm.pgd directly, we should never take
 601                  * any faults on kernel addresses. */
 602                 if (!svm->mm)
 603                         goto bad_req;
 604
 605                 /* If address is not canonical, return invalid response */
 606                 if (!is_canonical_address(address))
 607                         goto bad_req;
 608
 609                 /* If the mm is already defunct, don't handle faults. */
 610                 if (!mmget_not_zero(svm->mm))
 611                         goto bad_req;
 612
 613                 down_read(&svm->mm->mmap_sem);
 614                 vma = find_extend_vma(svm->mm, address);
 615                 if (!vma || address < vma->vm_start)
 616                         goto invalid;
 617
 618                 if (access_error(vma, req))
 619                         goto invalid;
 620
 621                 ret = handle_mm_fault(vma, address,
 622                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 623                 if (ret & VM_FAULT_ERROR)
 624                         goto invalid;
 625
 626                 result = QI_RESP_SUCCESS;
 627         invalid:
 628                 up_read(&svm->mm->mmap_sem);
 629                 mmput(svm->mm);
 630         bad_req:
 631                 /* Accounting for major/minor faults? */
 632                 rcu_read_lock();
 633                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 634                         if (sdev->sid == req->rid)
 635                                 break;
 636                 }
 637                 /* Other devices can go away, but the drivers are not permitted
 638                  * to unbind while any page faults might be in flight. So it's
 639                  * OK to drop the 'lock' here now we have it. */
 640                 rcu_read_unlock();
 641
 642                 if (WARN_ON(&sdev->list == &svm->devs))
 643                         sdev = NULL;
 644
 645                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 646                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 647                                 (req->exe_req << 1) | (req->pm_req);
 648                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr,
 649                                             req->priv_data, rwxp, result);
 650                 }
 651                 /* We get here in the error case where the PASID lookup failed,
 652                    and these can be NULL. Do not use them below this point! */
 653                 sdev = NULL;
 654                 svm = NULL;
 655         no_pasid:
 656                 if (req->lpig || req->priv_data_present) {
 657                         /*
 658                          * Per VT-d spec. v3.0 ch7.7, system software must
 659                          * respond with page group response if private data
 660                          * is present (PDP) or last page in group (LPIG) bit
 661                          * is set. This is an additional VT-d feature beyond
 662                          * PCI ATS spec.
 663                          */
 664                         resp.qw0 = QI_PGRP_PASID(req->pasid) |
 665                                 QI_PGRP_DID(req->rid) |
 666                                 QI_PGRP_PASID_P(req->pasid_present) |
 667                                 QI_PGRP_PDP(req->priv_data_present) |
 668                                 QI_PGRP_RESP_CODE(result) |
 669                                 QI_PGRP_RESP_TYPE;
 670                         resp.qw1 = QI_PGRP_IDX(req->prg_index) |
 671                                 QI_PGRP_LPIG(req->lpig);
 672
 673                         if (req->priv_data_present)
 674                                 memcpy(&resp.qw2, req->priv_data,
 675                                        sizeof(req->priv_data));
 676                         resp.qw2 = 0;
 677                         resp.qw3 = 0;
 678                         qi_submit_sync(&resp, iommu);
 679                 }
 680                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 681         }
 682
 683         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 684
 685         return IRQ_RETVAL(handled);
 686 }