drivers/iommu/intel-iommu-debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright © 2018 Intel Corporation.
   4  *
   5  * Authors: Gayatri Kammela <gayatri.kammela@intel.com>
   6  *          Sohil Mehta <sohil.mehta@intel.com>
   7  *          Jacob Pan <jacob.jun.pan@linux.intel.com>
   8  */
   9
  10 #include <linux/debugfs.h>
  11 #include <linux/dmar.h>
  12 #include <linux/intel-iommu.h>
  13 #include <linux/pci.h>
  14
  15 #include <asm/irq_remapping.h>
  16
  17 #include "intel-pasid.h"
  18
  19 struct tbl_walk {
  20         u16 bus;
  21         u16 devfn;
  22         u32 pasid;
  23         struct root_entry *rt_entry;
  24         struct context_entry *ctx_entry;
  25         struct pasid_entry *pasid_tbl_entry;
  26 };
  27
  28 struct iommu_regset {
  29         int offset;
  30         const char *regs;
  31 };
  32
  33 #define IOMMU_REGSET_ENTRY(_reg_)                                       \
  34         { DMAR_##_reg_##_REG, __stringify(_reg_) }
  35
  36 static const struct iommu_regset iommu_regs_32[] = {
  37         IOMMU_REGSET_ENTRY(VER),
  38         IOMMU_REGSET_ENTRY(GCMD),
  39         IOMMU_REGSET_ENTRY(GSTS),
  40         IOMMU_REGSET_ENTRY(FSTS),
  41         IOMMU_REGSET_ENTRY(FECTL),
  42         IOMMU_REGSET_ENTRY(FEDATA),
  43         IOMMU_REGSET_ENTRY(FEADDR),
  44         IOMMU_REGSET_ENTRY(FEUADDR),
  45         IOMMU_REGSET_ENTRY(PMEN),
  46         IOMMU_REGSET_ENTRY(PLMBASE),
  47         IOMMU_REGSET_ENTRY(PLMLIMIT),
  48         IOMMU_REGSET_ENTRY(ICS),
  49         IOMMU_REGSET_ENTRY(PRS),
  50         IOMMU_REGSET_ENTRY(PECTL),
  51         IOMMU_REGSET_ENTRY(PEDATA),
  52         IOMMU_REGSET_ENTRY(PEADDR),
  53         IOMMU_REGSET_ENTRY(PEUADDR),
  54 };
  55
  56 static const struct iommu_regset iommu_regs_64[] = {
  57         IOMMU_REGSET_ENTRY(CAP),
  58         IOMMU_REGSET_ENTRY(ECAP),
  59         IOMMU_REGSET_ENTRY(RTADDR),
  60         IOMMU_REGSET_ENTRY(CCMD),
  61         IOMMU_REGSET_ENTRY(AFLOG),
  62         IOMMU_REGSET_ENTRY(PHMBASE),
  63         IOMMU_REGSET_ENTRY(PHMLIMIT),
  64         IOMMU_REGSET_ENTRY(IQH),
  65         IOMMU_REGSET_ENTRY(IQT),
  66         IOMMU_REGSET_ENTRY(IQA),
  67         IOMMU_REGSET_ENTRY(IRTA),
  68         IOMMU_REGSET_ENTRY(PQH),
  69         IOMMU_REGSET_ENTRY(PQT),
  70         IOMMU_REGSET_ENTRY(PQA),
  71         IOMMU_REGSET_ENTRY(MTRRCAP),
  72         IOMMU_REGSET_ENTRY(MTRRDEF),
  73         IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
  74         IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
  75         IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
  76         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
  77         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
  78         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
  79         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
  80         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
  81         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
  82         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
  83         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
  84         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
  85         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
  86         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
  87         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
  88         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
  89         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
  90         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
  91         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
  92         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
  93         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
  94         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
  95         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
  96         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
  97         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
  98         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
  99         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
 100         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
 101         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
 102         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
 103         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
 104         IOMMU_REGSET_ENTRY(VCCAP),
 105         IOMMU_REGSET_ENTRY(VCMD),
 106         IOMMU_REGSET_ENTRY(VCRSP),
 107 };
 108
 109 static int iommu_regset_show(struct seq_file *m, void *unused)
 110 {
 111         struct dmar_drhd_unit *drhd;
 112         struct intel_iommu *iommu;
 113         unsigned long flag;
 114         int i, ret = 0;
 115         u64 value;
 116
 117         rcu_read_lock();
 118         for_each_active_iommu(iommu, drhd) {
 119                 if (!drhd->reg_base_addr) {
 120                         seq_puts(m, "IOMMU: Invalid base address\n");
 121                         ret = -EINVAL;
 122                         goto out;
 123                 }
 124
 125                 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
 126                            iommu->name, drhd->reg_base_addr);
 127                 seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
 128                 /*
 129                  * Publish the contents of the 64-bit hardware registers
 130                  * by adding the offset to the pointer (virtual address).
 131                  */
 132                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
 133                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
 134                         value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
 135                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 136                                    iommu_regs_32[i].regs, iommu_regs_32[i].offset,
 137                                    value);
 138                 }
 139                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
 140                         value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
 141                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 142                                    iommu_regs_64[i].regs, iommu_regs_64[i].offset,
 143                                    value);
 144                 }
 145                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 146                 seq_putc(m, '\n');
 147         }
 148 out:
 149         rcu_read_unlock();
 150
 151         return ret;
 152 }
 153 DEFINE_SHOW_ATTRIBUTE(iommu_regset);
 154
 155 static inline void print_tbl_walk(struct seq_file *m)
 156 {
 157         struct tbl_walk *tbl_wlk = m->private;
 158
 159         seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
 160                    tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
 161                    PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
 162                    tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
 163                    tbl_wlk->ctx_entry->lo);
 164
 165         /*
 166          * A legacy mode DMAR doesn't support PASID, hence default it to -1
 167          * indicating that it's invalid. Also, default all PASID related fields
 168          * to 0.
 169          */
 170         if (!tbl_wlk->pasid_tbl_entry)
 171                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
 172                            (u64)0, (u64)0, (u64)0);
 173         else
 174                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
 175                            tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
 176                            tbl_wlk->pasid_tbl_entry->val[1],
 177                            tbl_wlk->pasid_tbl_entry->val[0]);
 178 }
 179
 180 static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
 181                            u16 dir_idx)
 182 {
 183         struct tbl_walk *tbl_wlk = m->private;
 184         u8 tbl_idx;
 185
 186         for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
 187                 if (pasid_pte_is_present(tbl_entry)) {
 188                         tbl_wlk->pasid_tbl_entry = tbl_entry;
 189                         tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
 190                         print_tbl_walk(m);
 191                 }
 192
 193                 tbl_entry++;
 194         }
 195 }
 196
 197 static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
 198                            u16 pasid_dir_size)
 199 {
 200         struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
 201         struct pasid_entry *pasid_tbl;
 202         u16 dir_idx;
 203
 204         for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
 205                 pasid_tbl = get_pasid_table_from_pde(dir_entry);
 206                 if (pasid_tbl)
 207                         pasid_tbl_walk(m, pasid_tbl, dir_idx);
 208
 209                 dir_entry++;
 210         }
 211 }
 212
 213 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
 214 {
 215         struct context_entry *context;
 216         u16 devfn, pasid_dir_size;
 217         u64 pasid_dir_ptr;
 218
 219         for (devfn = 0; devfn < 256; devfn++) {
 220                 struct tbl_walk tbl_wlk = {0};
 221
 222                 /*
 223                  * Scalable mode root entry points to upper scalable mode
 224                  * context table and lower scalable mode context table. Each
 225                  * scalable mode context table has 128 context entries where as
 226                  * legacy mode context table has 256 context entries. So in
 227                  * scalable mode, the context entries for former 128 devices are
 228                  * in the lower scalable mode context table, while the latter
 229                  * 128 devices are in the upper scalable mode context table.
 230                  * In scalable mode, when devfn > 127, iommu_context_addr()
 231                  * automatically refers to upper scalable mode context table and
 232                  * hence the caller doesn't have to worry about differences
 233                  * between scalable mode and non scalable mode.
 234                  */
 235                 context = iommu_context_addr(iommu, bus, devfn, 0);
 236                 if (!context)
 237                         return;
 238
 239                 if (!context_present(context))
 240                         continue;
 241
 242                 tbl_wlk.bus = bus;
 243                 tbl_wlk.devfn = devfn;
 244                 tbl_wlk.rt_entry = &iommu->root_entry[bus];
 245                 tbl_wlk.ctx_entry = context;
 246                 m->private = &tbl_wlk;
 247
 248                 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
 249                         pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
 250                         pasid_dir_size = get_pasid_dir_size(context);
 251                         pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
 252                         continue;
 253                 }
 254
 255                 print_tbl_walk(m);
 256         }
 257 }
 258
 259 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
 260 {
 261         unsigned long flags;
 262         u16 bus;
 263
 264         spin_lock_irqsave(&iommu->lock, flags);
 265         seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
 266                    (u64)virt_to_phys(iommu->root_entry));
 267         seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
 268
 269         /*
 270          * No need to check if the root entry is present or not because
 271          * iommu_context_addr() performs the same check before returning
 272          * context entry.
 273          */
 274         for (bus = 0; bus < 256; bus++)
 275                 ctx_tbl_walk(m, iommu, bus);
 276
 277         spin_unlock_irqrestore(&iommu->lock, flags);
 278 }
 279
 280 static int dmar_translation_struct_show(struct seq_file *m, void *unused)
 281 {
 282         struct dmar_drhd_unit *drhd;
 283         struct intel_iommu *iommu;
 284         u32 sts;
 285
 286         rcu_read_lock();
 287         for_each_active_iommu(iommu, drhd) {
 288                 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
 289                 if (!(sts & DMA_GSTS_TES)) {
 290                         seq_printf(m, "DMA Remapping is not enabled on %s\n",
 291                                    iommu->name);
 292                         continue;
 293                 }
 294                 root_tbl_walk(m, iommu);
 295                 seq_putc(m, '\n');
 296         }
 297         rcu_read_unlock();
 298
 299         return 0;
 300 }
 301 DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
 302
 303 #ifdef CONFIG_IRQ_REMAP
 304 static void ir_tbl_remap_entry_show(struct seq_file *m,
 305                                     struct intel_iommu *iommu)
 306 {
 307         struct irte *ri_entry;
 308         unsigned long flags;
 309         int idx;
 310
 311         seq_puts(m, " Entry SrcID   DstID    Vct IRTE_high\t\tIRTE_low\n");
 312
 313         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 314         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 315                 ri_entry = &iommu->ir_table->base[idx];
 316                 if (!ri_entry->present || ri_entry->p_pst)
 317                         continue;
 318
 319                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x  %016llx\t%016llx\n",
 320                            idx, PCI_BUS_NUM(ri_entry->sid),
 321                            PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
 322                            ri_entry->dest_id, ri_entry->vector,
 323                            ri_entry->high, ri_entry->low);
 324         }
 325         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 326 }
 327
 328 static void ir_tbl_posted_entry_show(struct seq_file *m,
 329                                      struct intel_iommu *iommu)
 330 {
 331         struct irte *pi_entry;
 332         unsigned long flags;
 333         int idx;
 334
 335         seq_puts(m, " Entry SrcID   PDA_high PDA_low  Vct IRTE_high\t\tIRTE_low\n");
 336
 337         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 338         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 339                 pi_entry = &iommu->ir_table->base[idx];
 340                 if (!pi_entry->present || !pi_entry->p_pst)
 341                         continue;
 342
 343                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x  %016llx\t%016llx\n",
 344                            idx, PCI_BUS_NUM(pi_entry->sid),
 345                            PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
 346                            pi_entry->pda_h, pi_entry->pda_l << 6,
 347                            pi_entry->vector, pi_entry->high,
 348                            pi_entry->low);
 349         }
 350         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 351 }
 352
 353 /*
 354  * For active IOMMUs go through the Interrupt remapping
 355  * table and print valid entries in a table format for
 356  * Remapped and Posted Interrupts.
 357  */
 358 static int ir_translation_struct_show(struct seq_file *m, void *unused)
 359 {
 360         struct dmar_drhd_unit *drhd;
 361         struct intel_iommu *iommu;
 362         u64 irta;
 363         u32 sts;
 364
 365         rcu_read_lock();
 366         for_each_active_iommu(iommu, drhd) {
 367                 if (!ecap_ir_support(iommu->ecap))
 368                         continue;
 369
 370                 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
 371                            iommu->name);
 372
 373                 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
 374                 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
 375                         irta = virt_to_phys(iommu->ir_table->base);
 376                         seq_printf(m, " IR table address:%llx\n", irta);
 377                         ir_tbl_remap_entry_show(m, iommu);
 378                 } else {
 379                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 380                 }
 381                 seq_putc(m, '\n');
 382         }
 383
 384         seq_puts(m, "****\n\n");
 385
 386         for_each_active_iommu(iommu, drhd) {
 387                 if (!cap_pi_support(iommu->cap))
 388                         continue;
 389
 390                 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
 391                            iommu->name);
 392
 393                 if (iommu->ir_table) {
 394                         irta = virt_to_phys(iommu->ir_table->base);
 395                         seq_printf(m, " IR table address:%llx\n", irta);
 396                         ir_tbl_posted_entry_show(m, iommu);
 397                 } else {
 398                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 399                 }
 400                 seq_putc(m, '\n');
 401         }
 402         rcu_read_unlock();
 403
 404         return 0;
 405 }
 406 DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
 407 #endif
 408
 409 void __init intel_iommu_debugfs_init(void)
 410 {
 411         struct dentry *intel_iommu_debug = debugfs_create_dir("intel",
 412                                                 iommu_debugfs_dir);
 413
 414         debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
 415                             &iommu_regset_fops);
 416         debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
 417                             NULL, &dmar_translation_struct_fops);
 418 #ifdef CONFIG_IRQ_REMAP
 419         debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
 420                             NULL, &ir_translation_struct_fops);
 421 #endif
 422 }