drivers/iommu/exynos-iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  */
   6
   7 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/clk.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/iommu.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kmemleak.h>
  18 #include <linux/list.h>
  19 #include <linux/of.h>
  20 #include <linux/of_iommu.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/slab.h>
  25 #include <linux/dma-iommu.h>
  26
  27 typedef u32 sysmmu_iova_t;
  28 typedef u32 sysmmu_pte_t;
  29
  30 /* We do not consider super section mapping (16MB) */
  31 #define SECT_ORDER 20
  32 #define LPAGE_ORDER 16
  33 #define SPAGE_ORDER 12
  34
  35 #define SECT_SIZE (1 << SECT_ORDER)
  36 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  37 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  38
  39 #define SECT_MASK (~(SECT_SIZE - 1))
  40 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  41 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  42
  43 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  44                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  45 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  46 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  47 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  48                           ((*(sent) & 3) == 1))
  49 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  50
  51 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  52 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  53 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  54
  55 /*
  56  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  57  * v5.0 introduced support for 36bit physical address space by shifting
  58  * all page entry values by 4 bits.
  59  * All SYSMMU controllers in the system support the address spaces of the same
  60  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  61  * value (0 or 4).
  62  */
  63 static short PG_ENT_SHIFT = -1;
  64 #define SYSMMU_PG_ENT_SHIFT 0
  65 #define SYSMMU_V5_PG_ENT_SHIFT 4
  66
  67 static const sysmmu_pte_t *LV1_PROT;
  68 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = {
  69         ((0 << 15) | (0 << 10)), /* no access */
  70         ((1 << 15) | (1 << 10)), /* IOMMU_READ only */
  71         ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
  72         ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
  73 };
  74 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = {
  75         (0 << 4), /* no access */
  76         (1 << 4), /* IOMMU_READ only */
  77         (2 << 4), /* IOMMU_WRITE only */
  78         (3 << 4), /* IOMMU_READ | IOMMU_WRITE */
  79 };
  80
  81 static const sysmmu_pte_t *LV2_PROT;
  82 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = {
  83         ((0 << 9) | (0 << 4)), /* no access */
  84         ((1 << 9) | (1 << 4)), /* IOMMU_READ only */
  85         ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
  86         ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
  87 };
  88 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = {
  89         (0 << 2), /* no access */
  90         (1 << 2), /* IOMMU_READ only */
  91         (2 << 2), /* IOMMU_WRITE only */
  92         (3 << 2), /* IOMMU_READ | IOMMU_WRITE */
  93 };
  94
  95 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE)
  96
  97 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
  98 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
  99 #define section_offs(iova) (iova & (SECT_SIZE - 1))
 100 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
 101 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
 102 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
 103 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
 104
 105 #define NUM_LV1ENTRIES 4096
 106 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
 107
 108 static u32 lv1ent_offset(sysmmu_iova_t iova)
 109 {
 110         return iova >> SECT_ORDER;
 111 }
 112
 113 static u32 lv2ent_offset(sysmmu_iova_t iova)
 114 {
 115         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
 116 }
 117
 118 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
 119 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
 120
 121 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
 122 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
 123
 124 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2)
 125 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
 126 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1)
 127 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2)
 128
 129 #define CTRL_ENABLE     0x5
 130 #define CTRL_BLOCK      0x7
 131 #define CTRL_DISABLE    0x0
 132
 133 #define CFG_LRU         0x1
 134 #define CFG_EAP         (1 << 2)
 135 #define CFG_QOS(n)      ((n & 0xF) << 7)
 136 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 137 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 138 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 139
 140 /* common registers */
 141 #define REG_MMU_CTRL            0x000
 142 #define REG_MMU_CFG             0x004
 143 #define REG_MMU_STATUS          0x008
 144 #define REG_MMU_VERSION         0x034
 145
 146 #define MMU_MAJ_VER(val)        ((val) >> 7)
 147 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 148 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 149
 150 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 151
 152 /* v1.x - v3.x registers */
 153 #define REG_MMU_FLUSH           0x00C
 154 #define REG_MMU_FLUSH_ENTRY     0x010
 155 #define REG_PT_BASE_ADDR        0x014
 156 #define REG_INT_STATUS          0x018
 157 #define REG_INT_CLEAR           0x01C
 158
 159 #define REG_PAGE_FAULT_ADDR     0x024
 160 #define REG_AW_FAULT_ADDR       0x028
 161 #define REG_AR_FAULT_ADDR       0x02C
 162 #define REG_DEFAULT_SLAVE_ADDR  0x030
 163
 164 /* v5.x registers */
 165 #define REG_V5_PT_BASE_PFN      0x00C
 166 #define REG_V5_MMU_FLUSH_ALL    0x010
 167 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 168 #define REG_V5_MMU_FLUSH_RANGE  0x018
 169 #define REG_V5_MMU_FLUSH_START  0x020
 170 #define REG_V5_MMU_FLUSH_END    0x024
 171 #define REG_V5_INT_STATUS       0x060
 172 #define REG_V5_INT_CLEAR        0x064
 173 #define REG_V5_FAULT_AR_VA      0x070
 174 #define REG_V5_FAULT_AW_VA      0x080
 175
 176 #define has_sysmmu(dev)         (dev_iommu_priv_get(dev) != NULL)
 177
 178 static struct device *dma_dev;
 179 static struct kmem_cache *lv2table_kmem_cache;
 180 static sysmmu_pte_t *zero_lv2_table;
 181 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 182
 183 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 184 {
 185         return pgtable + lv1ent_offset(iova);
 186 }
 187
 188 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 189 {
 190         return (sysmmu_pte_t *)phys_to_virt(
 191                                 lv2table_base(sent)) + lv2ent_offset(iova);
 192 }
 193
 194 /*
 195  * IOMMU fault information register
 196  */
 197 struct sysmmu_fault_info {
 198         unsigned int bit;       /* bit number in STATUS register */
 199         unsigned short addr_reg; /* register to read VA fault address */
 200         const char *name;       /* human readable fault name */
 201         unsigned int type;      /* fault type for report_iommu_fault */
 202 };
 203
 204 static const struct sysmmu_fault_info sysmmu_faults[] = {
 205         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 206         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 207         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 208         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 209         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 210         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 211         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 212         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 213 };
 214
 215 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 216         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 217         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 218         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 219         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 220         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 221         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 222         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 223         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 224         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 225         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 226 };
 227
 228 /*
 229  * This structure is attached to dev->iommu->priv of the master device
 230  * on device add, contains a list of SYSMMU controllers defined by device tree,
 231  * which are bound to given master device. It is usually referenced by 'owner'
 232  * pointer.
 233 */
 234 struct exynos_iommu_owner {
 235         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 236         struct iommu_domain *domain;    /* domain this device is attached */
 237         struct mutex rpm_lock;          /* for runtime pm of all sysmmus */
 238 };
 239
 240 /*
 241  * This structure exynos specific generalization of struct iommu_domain.
 242  * It contains list of SYSMMU controllers from all master devices, which has
 243  * been attached to this domain and page tables of IO address space defined by
 244  * it. It is usually referenced by 'domain' pointer.
 245  */
 246 struct exynos_iommu_domain {
 247         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 248         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 249         short *lv2entcnt;       /* free lv2 entry counter for each section */
 250         spinlock_t lock;        /* lock for modyfying list of clients */
 251         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 252         struct iommu_domain domain; /* generic domain data structure */
 253 };
 254
 255 /*
 256  * This structure hold all data of a single SYSMMU controller, this includes
 257  * hw resources like registers and clocks, pointers and list nodes to connect
 258  * it to all other structures, internal state and parameters read from device
 259  * tree. It is usually referenced by 'data' pointer.
 260  */
 261 struct sysmmu_drvdata {
 262         struct device *sysmmu;          /* SYSMMU controller device */
 263         struct device *master;          /* master device (owner) */
 264         struct device_link *link;       /* runtime PM link to master */
 265         void __iomem *sfrbase;          /* our registers */
 266         struct clk *clk;                /* SYSMMU's clock */
 267         struct clk *aclk;               /* SYSMMU's aclk clock */
 268         struct clk *pclk;               /* SYSMMU's pclk clock */
 269         struct clk *clk_master;         /* master's device clock */
 270         spinlock_t lock;                /* lock for modyfying state */
 271         bool active;                    /* current status */
 272         struct exynos_iommu_domain *domain; /* domain we belong to */
 273         struct list_head domain_node;   /* node for domain clients list */
 274         struct list_head owner_node;    /* node for owner controllers list */
 275         phys_addr_t pgtable;            /* assigned page table structure */
 276         unsigned int version;           /* our version */
 277
 278         struct iommu_device iommu;      /* IOMMU core handle */
 279 };
 280
 281 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 282 {
 283         return container_of(dom, struct exynos_iommu_domain, domain);
 284 }
 285
 286 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 287 {
 288         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 289 }
 290
 291 static bool sysmmu_block(struct sysmmu_drvdata *data)
 292 {
 293         int i = 120;
 294
 295         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 296         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 297                 --i;
 298
 299         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 300                 sysmmu_unblock(data);
 301                 return false;
 302         }
 303
 304         return true;
 305 }
 306
 307 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 308 {
 309         if (MMU_MAJ_VER(data->version) < 5)
 310                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 311         else
 312                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 313 }
 314
 315 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 316                                 sysmmu_iova_t iova, unsigned int num_inv)
 317 {
 318         unsigned int i;
 319
 320         if (MMU_MAJ_VER(data->version) < 5) {
 321                 for (i = 0; i < num_inv; i++) {
 322                         writel((iova & SPAGE_MASK) | 1,
 323                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 324                         iova += SPAGE_SIZE;
 325                 }
 326         } else {
 327                 if (num_inv == 1) {
 328                         writel((iova & SPAGE_MASK) | 1,
 329                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 330                 } else {
 331                         writel((iova & SPAGE_MASK),
 332                                      data->sfrbase + REG_V5_MMU_FLUSH_START);
 333                         writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE,
 334                                      data->sfrbase + REG_V5_MMU_FLUSH_END);
 335                         writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE);
 336                 }
 337         }
 338 }
 339
 340 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 341 {
 342         if (MMU_MAJ_VER(data->version) < 5)
 343                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 344         else
 345                 writel(pgd >> PAGE_SHIFT,
 346                              data->sfrbase + REG_V5_PT_BASE_PFN);
 347
 348         __sysmmu_tlb_invalidate(data);
 349 }
 350
 351 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 352 {
 353         BUG_ON(clk_prepare_enable(data->clk_master));
 354         BUG_ON(clk_prepare_enable(data->clk));
 355         BUG_ON(clk_prepare_enable(data->pclk));
 356         BUG_ON(clk_prepare_enable(data->aclk));
 357 }
 358
 359 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 360 {
 361         clk_disable_unprepare(data->aclk);
 362         clk_disable_unprepare(data->pclk);
 363         clk_disable_unprepare(data->clk);
 364         clk_disable_unprepare(data->clk_master);
 365 }
 366
 367 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 368 {
 369         u32 ver;
 370
 371         __sysmmu_enable_clocks(data);
 372
 373         ver = readl(data->sfrbase + REG_MMU_VERSION);
 374
 375         /* controllers on some SoCs don't report proper version */
 376         if (ver == 0x80000001u)
 377                 data->version = MAKE_MMU_VER(1, 0);
 378         else
 379                 data->version = MMU_RAW_VER(ver);
 380
 381         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 382                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 383
 384         __sysmmu_disable_clocks(data);
 385 }
 386
 387 static void show_fault_information(struct sysmmu_drvdata *data,
 388                                    const struct sysmmu_fault_info *finfo,
 389                                    sysmmu_iova_t fault_addr)
 390 {
 391         sysmmu_pte_t *ent;
 392
 393         dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n",
 394                 dev_name(data->master), finfo->name, fault_addr);
 395         dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable);
 396         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 397         dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 398         if (lv1ent_page(ent)) {
 399                 ent = page_entry(ent, fault_addr);
 400                 dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 401         }
 402 }
 403
 404 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 405 {
 406         /* SYSMMU is in blocked state when interrupt occurred. */
 407         struct sysmmu_drvdata *data = dev_id;
 408         const struct sysmmu_fault_info *finfo;
 409         unsigned int i, n, itype;
 410         sysmmu_iova_t fault_addr = -1;
 411         unsigned short reg_status, reg_clear;
 412         int ret = -ENOSYS;
 413
 414         WARN_ON(!data->active);
 415
 416         if (MMU_MAJ_VER(data->version) < 5) {
 417                 reg_status = REG_INT_STATUS;
 418                 reg_clear = REG_INT_CLEAR;
 419                 finfo = sysmmu_faults;
 420                 n = ARRAY_SIZE(sysmmu_faults);
 421         } else {
 422                 reg_status = REG_V5_INT_STATUS;
 423                 reg_clear = REG_V5_INT_CLEAR;
 424                 finfo = sysmmu_v5_faults;
 425                 n = ARRAY_SIZE(sysmmu_v5_faults);
 426         }
 427
 428         spin_lock(&data->lock);
 429
 430         clk_enable(data->clk_master);
 431
 432         itype = __ffs(readl(data->sfrbase + reg_status));
 433         for (i = 0; i < n; i++, finfo++)
 434                 if (finfo->bit == itype)
 435                         break;
 436         /* unknown/unsupported fault */
 437         BUG_ON(i == n);
 438
 439         /* print debug message */
 440         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 441         show_fault_information(data, finfo, fault_addr);
 442
 443         if (data->domain)
 444                 ret = report_iommu_fault(&data->domain->domain,
 445                                         data->master, fault_addr, finfo->type);
 446         /* fault is not recovered by fault handler */
 447         BUG_ON(ret != 0);
 448
 449         writel(1 << itype, data->sfrbase + reg_clear);
 450
 451         sysmmu_unblock(data);
 452
 453         clk_disable(data->clk_master);
 454
 455         spin_unlock(&data->lock);
 456
 457         return IRQ_HANDLED;
 458 }
 459
 460 static void __sysmmu_disable(struct sysmmu_drvdata *data)
 461 {
 462         unsigned long flags;
 463
 464         clk_enable(data->clk_master);
 465
 466         spin_lock_irqsave(&data->lock, flags);
 467         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 468         writel(0, data->sfrbase + REG_MMU_CFG);
 469         data->active = false;
 470         spin_unlock_irqrestore(&data->lock, flags);
 471
 472         __sysmmu_disable_clocks(data);
 473 }
 474
 475 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 476 {
 477         unsigned int cfg;
 478
 479         if (data->version <= MAKE_MMU_VER(3, 1))
 480                 cfg = CFG_LRU | CFG_QOS(15);
 481         else if (data->version <= MAKE_MMU_VER(3, 2))
 482                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 483         else
 484                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 485
 486         cfg |= CFG_EAP; /* enable access protection bits check */
 487
 488         writel(cfg, data->sfrbase + REG_MMU_CFG);
 489 }
 490
 491 static void __sysmmu_enable(struct sysmmu_drvdata *data)
 492 {
 493         unsigned long flags;
 494
 495         __sysmmu_enable_clocks(data);
 496
 497         spin_lock_irqsave(&data->lock, flags);
 498         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 499         __sysmmu_init_config(data);
 500         __sysmmu_set_ptbase(data, data->pgtable);
 501         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 502         data->active = true;
 503         spin_unlock_irqrestore(&data->lock, flags);
 504
 505         /*
 506          * SYSMMU driver keeps master's clock enabled only for the short
 507          * time, while accessing the registers. For performing address
 508          * translation during DMA transaction it relies on the client
 509          * driver to enable it.
 510          */
 511         clk_disable(data->clk_master);
 512 }
 513
 514 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 515                                             sysmmu_iova_t iova)
 516 {
 517         unsigned long flags;
 518
 519         spin_lock_irqsave(&data->lock, flags);
 520         if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
 521                 clk_enable(data->clk_master);
 522                 if (sysmmu_block(data)) {
 523                         if (data->version >= MAKE_MMU_VER(5, 0))
 524                                 __sysmmu_tlb_invalidate(data);
 525                         else
 526                                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 527                         sysmmu_unblock(data);
 528                 }
 529                 clk_disable(data->clk_master);
 530         }
 531         spin_unlock_irqrestore(&data->lock, flags);
 532 }
 533
 534 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 535                                         sysmmu_iova_t iova, size_t size)
 536 {
 537         unsigned long flags;
 538
 539         spin_lock_irqsave(&data->lock, flags);
 540         if (data->active) {
 541                 unsigned int num_inv = 1;
 542
 543                 clk_enable(data->clk_master);
 544
 545                 /*
 546                  * L2TLB invalidation required
 547                  * 4KB page: 1 invalidation
 548                  * 64KB page: 16 invalidations
 549                  * 1MB page: 64 invalidations
 550                  * because it is set-associative TLB
 551                  * with 8-way and 64 sets.
 552                  * 1MB page can be cached in one of all sets.
 553                  * 64KB page can be one of 16 consecutive sets.
 554                  */
 555                 if (MMU_MAJ_VER(data->version) == 2)
 556                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 557
 558                 if (sysmmu_block(data)) {
 559                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 560                         sysmmu_unblock(data);
 561                 }
 562                 clk_disable(data->clk_master);
 563         }
 564         spin_unlock_irqrestore(&data->lock, flags);
 565 }
 566
 567 static const struct iommu_ops exynos_iommu_ops;
 568
 569 static int exynos_sysmmu_probe(struct platform_device *pdev)
 570 {
 571         int irq, ret;
 572         struct device *dev = &pdev->dev;
 573         struct sysmmu_drvdata *data;
 574         struct resource *res;
 575
 576         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 577         if (!data)
 578                 return -ENOMEM;
 579
 580         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 581         data->sfrbase = devm_ioremap_resource(dev, res);
 582         if (IS_ERR(data->sfrbase))
 583                 return PTR_ERR(data->sfrbase);
 584
 585         irq = platform_get_irq(pdev, 0);
 586         if (irq <= 0)
 587                 return irq;
 588
 589         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 590                                 dev_name(dev), data);
 591         if (ret) {
 592                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 593                 return ret;
 594         }
 595
 596         data->clk = devm_clk_get(dev, "sysmmu");
 597         if (PTR_ERR(data->clk) == -ENOENT)
 598                 data->clk = NULL;
 599         else if (IS_ERR(data->clk))
 600                 return PTR_ERR(data->clk);
 601
 602         data->aclk = devm_clk_get(dev, "aclk");
 603         if (PTR_ERR(data->aclk) == -ENOENT)
 604                 data->aclk = NULL;
 605         else if (IS_ERR(data->aclk))
 606                 return PTR_ERR(data->aclk);
 607
 608         data->pclk = devm_clk_get(dev, "pclk");
 609         if (PTR_ERR(data->pclk) == -ENOENT)
 610                 data->pclk = NULL;
 611         else if (IS_ERR(data->pclk))
 612                 return PTR_ERR(data->pclk);
 613
 614         if (!data->clk && (!data->aclk || !data->pclk)) {
 615                 dev_err(dev, "Failed to get device clock(s)!\n");
 616                 return -ENOSYS;
 617         }
 618
 619         data->clk_master = devm_clk_get(dev, "master");
 620         if (PTR_ERR(data->clk_master) == -ENOENT)
 621                 data->clk_master = NULL;
 622         else if (IS_ERR(data->clk_master))
 623                 return PTR_ERR(data->clk_master);
 624
 625         data->sysmmu = dev;
 626         spin_lock_init(&data->lock);
 627
 628         ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
 629                                      dev_name(data->sysmmu));
 630         if (ret)
 631                 return ret;
 632
 633         iommu_device_set_ops(&data->iommu, &exynos_iommu_ops);
 634         iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode);
 635
 636         ret = iommu_device_register(&data->iommu);
 637         if (ret)
 638                 goto err_iommu_register;
 639
 640         platform_set_drvdata(pdev, data);
 641
 642         __sysmmu_get_version(data);
 643         if (PG_ENT_SHIFT < 0) {
 644                 if (MMU_MAJ_VER(data->version) < 5) {
 645                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 646                         LV1_PROT = SYSMMU_LV1_PROT;
 647                         LV2_PROT = SYSMMU_LV2_PROT;
 648                 } else {
 649                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 650                         LV1_PROT = SYSMMU_V5_LV1_PROT;
 651                         LV2_PROT = SYSMMU_V5_LV2_PROT;
 652                 }
 653         }
 654
 655         /*
 656          * use the first registered sysmmu device for performing
 657          * dma mapping operations on iommu page tables (cpu cache flush)
 658          */
 659         if (!dma_dev)
 660                 dma_dev = &pdev->dev;
 661
 662         pm_runtime_enable(dev);
 663
 664         return 0;
 665
 666 err_iommu_register:
 667         iommu_device_sysfs_remove(&data->iommu);
 668         return ret;
 669 }
 670
 671 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev)
 672 {
 673         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 674         struct device *master = data->master;
 675
 676         if (master) {
 677                 struct exynos_iommu_owner *owner = dev_iommu_priv_get(master);
 678
 679                 mutex_lock(&owner->rpm_lock);
 680                 if (data->domain) {
 681                         dev_dbg(data->sysmmu, "saving state\n");
 682                         __sysmmu_disable(data);
 683                 }
 684                 mutex_unlock(&owner->rpm_lock);
 685         }
 686         return 0;
 687 }
 688
 689 static int __maybe_unused exynos_sysmmu_resume(struct device *dev)
 690 {
 691         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 692         struct device *master = data->master;
 693
 694         if (master) {
 695                 struct exynos_iommu_owner *owner = dev_iommu_priv_get(master);
 696
 697                 mutex_lock(&owner->rpm_lock);
 698                 if (data->domain) {
 699                         dev_dbg(data->sysmmu, "restoring state\n");
 700                         __sysmmu_enable(data);
 701                 }
 702                 mutex_unlock(&owner->rpm_lock);
 703         }
 704         return 0;
 705 }
 706
 707 static const struct dev_pm_ops sysmmu_pm_ops = {
 708         SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL)
 709         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 710                                 pm_runtime_force_resume)
 711 };
 712
 713 static const struct of_device_id sysmmu_of_match[] = {
 714         { .compatible   = "samsung,exynos-sysmmu", },
 715         { },
 716 };
 717
 718 static struct platform_driver exynos_sysmmu_driver __refdata = {
 719         .probe  = exynos_sysmmu_probe,
 720         .driver = {
 721                 .name           = "exynos-sysmmu",
 722                 .of_match_table = sysmmu_of_match,
 723                 .pm             = &sysmmu_pm_ops,
 724                 .suppress_bind_attrs = true,
 725         }
 726 };
 727
 728 static inline void exynos_iommu_set_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 729 {
 730         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 731                                 DMA_TO_DEVICE);
 732         *ent = cpu_to_le32(val);
 733         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 734                                    DMA_TO_DEVICE);
 735 }
 736
 737 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 738 {
 739         struct exynos_iommu_domain *domain;
 740         dma_addr_t handle;
 741         int i;
 742
 743         /* Check if correct PTE offsets are initialized */
 744         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 745
 746         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 747         if (!domain)
 748                 return NULL;
 749
 750         if (type == IOMMU_DOMAIN_DMA) {
 751                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 752                         goto err_pgtable;
 753         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 754                 goto err_pgtable;
 755         }
 756
 757         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 758         if (!domain->pgtable)
 759                 goto err_dma_cookie;
 760
 761         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 762         if (!domain->lv2entcnt)
 763                 goto err_counter;
 764
 765         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 766         for (i = 0; i < NUM_LV1ENTRIES; i++)
 767                 domain->pgtable[i] = ZERO_LV2LINK;
 768
 769         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 770                                 DMA_TO_DEVICE);
 771         /* For mapping page table entries we rely on dma == phys */
 772         BUG_ON(handle != virt_to_phys(domain->pgtable));
 773         if (dma_mapping_error(dma_dev, handle))
 774                 goto err_lv2ent;
 775
 776         spin_lock_init(&domain->lock);
 777         spin_lock_init(&domain->pgtablelock);
 778         INIT_LIST_HEAD(&domain->clients);
 779
 780         domain->domain.geometry.aperture_start = 0;
 781         domain->domain.geometry.aperture_end   = ~0UL;
 782         domain->domain.geometry.force_aperture = true;
 783
 784         return &domain->domain;
 785
 786 err_lv2ent:
 787         free_pages((unsigned long)domain->lv2entcnt, 1);
 788 err_counter:
 789         free_pages((unsigned long)domain->pgtable, 2);
 790 err_dma_cookie:
 791         if (type == IOMMU_DOMAIN_DMA)
 792                 iommu_put_dma_cookie(&domain->domain);
 793 err_pgtable:
 794         kfree(domain);
 795         return NULL;
 796 }
 797
 798 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 799 {
 800         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 801         struct sysmmu_drvdata *data, *next;
 802         unsigned long flags;
 803         int i;
 804
 805         WARN_ON(!list_empty(&domain->clients));
 806
 807         spin_lock_irqsave(&domain->lock, flags);
 808
 809         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 810                 spin_lock(&data->lock);
 811                 __sysmmu_disable(data);
 812                 data->pgtable = 0;
 813                 data->domain = NULL;
 814                 list_del_init(&data->domain_node);
 815                 spin_unlock(&data->lock);
 816         }
 817
 818         spin_unlock_irqrestore(&domain->lock, flags);
 819
 820         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 821                 iommu_put_dma_cookie(iommu_domain);
 822
 823         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 824                          DMA_TO_DEVICE);
 825
 826         for (i = 0; i < NUM_LV1ENTRIES; i++)
 827                 if (lv1ent_page(domain->pgtable + i)) {
 828                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 829
 830                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 831                                          DMA_TO_DEVICE);
 832                         kmem_cache_free(lv2table_kmem_cache,
 833                                         phys_to_virt(base));
 834                 }
 835
 836         free_pages((unsigned long)domain->pgtable, 2);
 837         free_pages((unsigned long)domain->lv2entcnt, 1);
 838         kfree(domain);
 839 }
 840
 841 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 842                                     struct device *dev)
 843 {
 844         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 845         struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
 846         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 847         struct sysmmu_drvdata *data, *next;
 848         unsigned long flags;
 849
 850         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 851                 return;
 852
 853         mutex_lock(&owner->rpm_lock);
 854
 855         list_for_each_entry(data, &owner->controllers, owner_node) {
 856                 pm_runtime_get_noresume(data->sysmmu);
 857                 if (pm_runtime_active(data->sysmmu))
 858                         __sysmmu_disable(data);
 859                 pm_runtime_put(data->sysmmu);
 860         }
 861
 862         spin_lock_irqsave(&domain->lock, flags);
 863         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 864                 spin_lock(&data->lock);
 865                 data->pgtable = 0;
 866                 data->domain = NULL;
 867                 list_del_init(&data->domain_node);
 868                 spin_unlock(&data->lock);
 869         }
 870         owner->domain = NULL;
 871         spin_unlock_irqrestore(&domain->lock, flags);
 872
 873         mutex_unlock(&owner->rpm_lock);
 874
 875         dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__,
 876                 &pagetable);
 877 }
 878
 879 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 880                                    struct device *dev)
 881 {
 882         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 883         struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
 884         struct sysmmu_drvdata *data;
 885         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 886         unsigned long flags;
 887
 888         if (!has_sysmmu(dev))
 889                 return -ENODEV;
 890
 891         if (owner->domain)
 892                 exynos_iommu_detach_device(owner->domain, dev);
 893
 894         mutex_lock(&owner->rpm_lock);
 895
 896         spin_lock_irqsave(&domain->lock, flags);
 897         list_for_each_entry(data, &owner->controllers, owner_node) {
 898                 spin_lock(&data->lock);
 899                 data->pgtable = pagetable;
 900                 data->domain = domain;
 901                 list_add_tail(&data->domain_node, &domain->clients);
 902                 spin_unlock(&data->lock);
 903         }
 904         owner->domain = iommu_domain;
 905         spin_unlock_irqrestore(&domain->lock, flags);
 906
 907         list_for_each_entry(data, &owner->controllers, owner_node) {
 908                 pm_runtime_get_noresume(data->sysmmu);
 909                 if (pm_runtime_active(data->sysmmu))
 910                         __sysmmu_enable(data);
 911                 pm_runtime_put(data->sysmmu);
 912         }
 913
 914         mutex_unlock(&owner->rpm_lock);
 915
 916         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__,
 917                 &pagetable);
 918
 919         return 0;
 920 }
 921
 922 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 923                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 924 {
 925         if (lv1ent_section(sent)) {
 926                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 927                 return ERR_PTR(-EADDRINUSE);
 928         }
 929
 930         if (lv1ent_fault(sent)) {
 931                 dma_addr_t handle;
 932                 sysmmu_pte_t *pent;
 933                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 934
 935                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 936                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 937                 if (!pent)
 938                         return ERR_PTR(-ENOMEM);
 939
 940                 exynos_iommu_set_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 941                 kmemleak_ignore(pent);
 942                 *pgcounter = NUM_LV2ENTRIES;
 943                 handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE,
 944                                         DMA_TO_DEVICE);
 945                 if (dma_mapping_error(dma_dev, handle)) {
 946                         kmem_cache_free(lv2table_kmem_cache, pent);
 947                         return ERR_PTR(-EADDRINUSE);
 948                 }
 949
 950                 /*
 951                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 952                  * FLPD cache may cache the address of zero_l2_table. This
 953                  * function replaces the zero_l2_table with new L2 page table
 954                  * to write valid mappings.
 955                  * Accessing the valid area may cause page fault since FLPD
 956                  * cache may still cache zero_l2_table for the valid area
 957                  * instead of new L2 page table that has the mapping
 958                  * information of the valid area.
 959                  * Thus any replacement of zero_l2_table with other valid L2
 960                  * page table must involve FLPD cache invalidation for System
 961                  * MMU v3.3.
 962                  * FLPD cache invalidation is performed with TLB invalidation
 963                  * by VPN without blocking. It is safe to invalidate TLB without
 964                  * blocking because the target address of TLB invalidation is
 965                  * not currently mapped.
 966                  */
 967                 if (need_flush_flpd_cache) {
 968                         struct sysmmu_drvdata *data;
 969
 970                         spin_lock(&domain->lock);
 971                         list_for_each_entry(data, &domain->clients, domain_node)
 972                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 973                         spin_unlock(&domain->lock);
 974                 }
 975         }
 976
 977         return page_entry(sent, iova);
 978 }
 979
 980 static int lv1set_section(struct exynos_iommu_domain *domain,
 981                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 982                           phys_addr_t paddr, int prot, short *pgcnt)
 983 {
 984         if (lv1ent_section(sent)) {
 985                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 986                         iova);
 987                 return -EADDRINUSE;
 988         }
 989
 990         if (lv1ent_page(sent)) {
 991                 if (*pgcnt != NUM_LV2ENTRIES) {
 992                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 993                                 iova);
 994                         return -EADDRINUSE;
 995                 }
 996
 997                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 998                 *pgcnt = 0;
 999         }
1000
1001         exynos_iommu_set_pte(sent, mk_lv1ent_sect(paddr, prot));
1002
1003         spin_lock(&domain->lock);
1004         if (lv1ent_page_zero(sent)) {
1005                 struct sysmmu_drvdata *data;
1006                 /*
1007                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
1008                  * entry by speculative prefetch of SLPD which has no mapping.
1009                  */
1010                 list_for_each_entry(data, &domain->clients, domain_node)
1011                         sysmmu_tlb_invalidate_flpdcache(data, iova);
1012         }
1013         spin_unlock(&domain->lock);
1014
1015         return 0;
1016 }
1017
1018 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
1019                        int prot, short *pgcnt)
1020 {
1021         if (size == SPAGE_SIZE) {
1022                 if (WARN_ON(!lv2ent_fault(pent)))
1023                         return -EADDRINUSE;
1024
1025                 exynos_iommu_set_pte(pent, mk_lv2ent_spage(paddr, prot));
1026                 *pgcnt -= 1;
1027         } else { /* size == LPAGE_SIZE */
1028                 int i;
1029                 dma_addr_t pent_base = virt_to_phys(pent);
1030
1031                 dma_sync_single_for_cpu(dma_dev, pent_base,
1032                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1033                                         DMA_TO_DEVICE);
1034                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1035                         if (WARN_ON(!lv2ent_fault(pent))) {
1036                                 if (i > 0)
1037                                         memset(pent - i, 0, sizeof(*pent) * i);
1038                                 return -EADDRINUSE;
1039                         }
1040
1041                         *pent = mk_lv2ent_lpage(paddr, prot);
1042                 }
1043                 dma_sync_single_for_device(dma_dev, pent_base,
1044                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1045                                            DMA_TO_DEVICE);
1046                 *pgcnt -= SPAGES_PER_LPAGE;
1047         }
1048
1049         return 0;
1050 }
1051
1052 /*
1053  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1054  *
1055  * System MMU v3.x has advanced logic to improve address translation
1056  * performance with caching more page table entries by a page table walk.
1057  * However, the logic has a bug that while caching faulty page table entries,
1058  * System MMU reports page fault if the cached fault entry is hit even though
1059  * the fault entry is updated to a valid entry after the entry is cached.
1060  * To prevent caching faulty page table entries which may be updated to valid
1061  * entries later, the virtual memory manager should care about the workaround
1062  * for the problem. The following describes the workaround.
1063  *
1064  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1065  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1066  *
1067  * Precisely, any start address of I/O virtual region must be aligned with
1068  * the following sizes for System MMU v3.1 and v3.2.
1069  * System MMU v3.1: 128KiB
1070  * System MMU v3.2: 256KiB
1071  *
1072  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1073  * more workarounds.
1074  * - Any two consecutive I/O virtual regions must have a hole of size larger
1075  *   than or equal to 128KiB.
1076  * - Start address of an I/O virtual region must be aligned by 128KiB.
1077  */
1078 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1079                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1080                             int prot, gfp_t gfp)
1081 {
1082         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1083         sysmmu_pte_t *entry;
1084         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1085         unsigned long flags;
1086         int ret = -ENOMEM;
1087
1088         BUG_ON(domain->pgtable == NULL);
1089         prot &= SYSMMU_SUPPORTED_PROT_BITS;
1090
1091         spin_lock_irqsave(&domain->pgtablelock, flags);
1092
1093         entry = section_entry(domain->pgtable, iova);
1094
1095         if (size == SECT_SIZE) {
1096                 ret = lv1set_section(domain, entry, iova, paddr, prot,
1097                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1098         } else {
1099                 sysmmu_pte_t *pent;
1100
1101                 pent = alloc_lv2entry(domain, entry, iova,
1102                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1103
1104                 if (IS_ERR(pent))
1105                         ret = PTR_ERR(pent);
1106                 else
1107                         ret = lv2set_page(pent, paddr, size, prot,
1108                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1109         }
1110
1111         if (ret)
1112                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1113                         __func__, ret, size, iova);
1114
1115         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1116
1117         return ret;
1118 }
1119
1120 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1121                                               sysmmu_iova_t iova, size_t size)
1122 {
1123         struct sysmmu_drvdata *data;
1124         unsigned long flags;
1125
1126         spin_lock_irqsave(&domain->lock, flags);
1127
1128         list_for_each_entry(data, &domain->clients, domain_node)
1129                 sysmmu_tlb_invalidate_entry(data, iova, size);
1130
1131         spin_unlock_irqrestore(&domain->lock, flags);
1132 }
1133
1134 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1135                                  unsigned long l_iova, size_t size,
1136                                  struct iommu_iotlb_gather *gather)
1137 {
1138         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1139         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1140         sysmmu_pte_t *ent;
1141         size_t err_pgsize;
1142         unsigned long flags;
1143
1144         BUG_ON(domain->pgtable == NULL);
1145
1146         spin_lock_irqsave(&domain->pgtablelock, flags);
1147
1148         ent = section_entry(domain->pgtable, iova);
1149
1150         if (lv1ent_section(ent)) {
1151                 if (WARN_ON(size < SECT_SIZE)) {
1152                         err_pgsize = SECT_SIZE;
1153                         goto err;
1154                 }
1155
1156                 /* workaround for h/w bug in System MMU v3.3 */
1157                 exynos_iommu_set_pte(ent, ZERO_LV2LINK);
1158                 size = SECT_SIZE;
1159                 goto done;
1160         }
1161
1162         if (unlikely(lv1ent_fault(ent))) {
1163                 if (size > SECT_SIZE)
1164                         size = SECT_SIZE;
1165                 goto done;
1166         }
1167
1168         /* lv1ent_page(sent) == true here */
1169
1170         ent = page_entry(ent, iova);
1171
1172         if (unlikely(lv2ent_fault(ent))) {
1173                 size = SPAGE_SIZE;
1174                 goto done;
1175         }
1176
1177         if (lv2ent_small(ent)) {
1178                 exynos_iommu_set_pte(ent, 0);
1179                 size = SPAGE_SIZE;
1180                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1181                 goto done;
1182         }
1183
1184         /* lv1ent_large(ent) == true here */
1185         if (WARN_ON(size < LPAGE_SIZE)) {
1186                 err_pgsize = LPAGE_SIZE;
1187                 goto err;
1188         }
1189
1190         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1191                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1192                                 DMA_TO_DEVICE);
1193         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1194         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1195                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1196                                    DMA_TO_DEVICE);
1197         size = LPAGE_SIZE;
1198         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1199 done:
1200         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1201
1202         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1203
1204         return size;
1205 err:
1206         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1207
1208         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1209                 __func__, size, iova, err_pgsize);
1210
1211         return 0;
1212 }
1213
1214 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1215                                           dma_addr_t iova)
1216 {
1217         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1218         sysmmu_pte_t *entry;
1219         unsigned long flags;
1220         phys_addr_t phys = 0;
1221
1222         spin_lock_irqsave(&domain->pgtablelock, flags);
1223
1224         entry = section_entry(domain->pgtable, iova);
1225
1226         if (lv1ent_section(entry)) {
1227                 phys = section_phys(entry) + section_offs(iova);
1228         } else if (lv1ent_page(entry)) {
1229                 entry = page_entry(entry, iova);
1230
1231                 if (lv2ent_large(entry))
1232                         phys = lpage_phys(entry) + lpage_offs(iova);
1233                 else if (lv2ent_small(entry))
1234                         phys = spage_phys(entry) + spage_offs(iova);
1235         }
1236
1237         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1238
1239         return phys;
1240 }
1241
1242 static struct iommu_device *exynos_iommu_probe_device(struct device *dev)
1243 {
1244         struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
1245         struct sysmmu_drvdata *data;
1246
1247         if (!has_sysmmu(dev))
1248                 return ERR_PTR(-ENODEV);
1249
1250         list_for_each_entry(data, &owner->controllers, owner_node) {
1251                 /*
1252                  * SYSMMU will be runtime activated via device link
1253                  * (dependency) to its master device, so there are no
1254                  * direct calls to pm_runtime_get/put in this driver.
1255                  */
1256                 data->link = device_link_add(dev, data->sysmmu,
1257                                              DL_FLAG_STATELESS |
1258                                              DL_FLAG_PM_RUNTIME);
1259         }
1260
1261         /* There is always at least one entry, see exynos_iommu_of_xlate() */
1262         data = list_first_entry(&owner->controllers,
1263                                 struct sysmmu_drvdata, owner_node);
1264
1265         return &data->iommu;
1266 }
1267
1268 static void exynos_iommu_release_device(struct device *dev)
1269 {
1270         struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
1271         struct sysmmu_drvdata *data;
1272
1273         if (!has_sysmmu(dev))
1274                 return;
1275
1276         if (owner->domain) {
1277                 struct iommu_group *group = iommu_group_get(dev);
1278
1279                 if (group) {
1280                         WARN_ON(owner->domain !=
1281                                 iommu_group_default_domain(group));
1282                         exynos_iommu_detach_device(owner->domain, dev);
1283                         iommu_group_put(group);
1284                 }
1285         }
1286
1287         list_for_each_entry(data, &owner->controllers, owner_node)
1288                 device_link_del(data->link);
1289 }
1290
1291 static int exynos_iommu_of_xlate(struct device *dev,
1292                                  struct of_phandle_args *spec)
1293 {
1294         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1295         struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
1296         struct sysmmu_drvdata *data, *entry;
1297
1298         if (!sysmmu)
1299                 return -ENODEV;
1300
1301         data = platform_get_drvdata(sysmmu);
1302         if (!data) {
1303                 put_device(&sysmmu->dev);
1304                 return -ENODEV;
1305         }
1306
1307         if (!owner) {
1308                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1309                 if (!owner) {
1310                         put_device(&sysmmu->dev);
1311                         return -ENOMEM;
1312                 }
1313
1314                 INIT_LIST_HEAD(&owner->controllers);
1315                 mutex_init(&owner->rpm_lock);
1316                 dev_iommu_priv_set(dev, owner);
1317         }
1318
1319         list_for_each_entry(entry, &owner->controllers, owner_node)
1320                 if (entry == data)
1321                         return 0;
1322
1323         list_add_tail(&data->owner_node, &owner->controllers);
1324         data->master = dev;
1325
1326         return 0;
1327 }
1328
1329 static const struct iommu_ops exynos_iommu_ops = {
1330         .domain_alloc = exynos_iommu_domain_alloc,
1331         .domain_free = exynos_iommu_domain_free,
1332         .attach_dev = exynos_iommu_attach_device,
1333         .detach_dev = exynos_iommu_detach_device,
1334         .map = exynos_iommu_map,
1335         .unmap = exynos_iommu_unmap,
1336         .iova_to_phys = exynos_iommu_iova_to_phys,
1337         .device_group = generic_device_group,
1338         .probe_device = exynos_iommu_probe_device,
1339         .release_device = exynos_iommu_release_device,
1340         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1341         .of_xlate = exynos_iommu_of_xlate,
1342 };
1343
1344 static int __init exynos_iommu_init(void)
1345 {
1346         struct device_node *np;
1347         int ret;
1348
1349         np = of_find_matching_node(NULL, sysmmu_of_match);
1350         if (!np)
1351                 return 0;
1352
1353         of_node_put(np);
1354
1355         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1356                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1357         if (!lv2table_kmem_cache) {
1358                 pr_err("%s: Failed to create kmem cache\n", __func__);
1359                 return -ENOMEM;
1360         }
1361
1362         ret = platform_driver_register(&exynos_sysmmu_driver);
1363         if (ret) {
1364                 pr_err("%s: Failed to register driver\n", __func__);
1365                 goto err_reg_driver;
1366         }
1367
1368         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1369         if (zero_lv2_table == NULL) {
1370                 pr_err("%s: Failed to allocate zero level2 page table\n",
1371                         __func__);
1372                 ret = -ENOMEM;
1373                 goto err_zero_lv2;
1374         }
1375
1376         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1377         if (ret) {
1378                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1379                                                                 __func__);
1380                 goto err_set_iommu;
1381         }
1382
1383         return 0;
1384 err_set_iommu:
1385         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1386 err_zero_lv2:
1387         platform_driver_unregister(&exynos_sysmmu_driver);
1388 err_reg_driver:
1389         kmem_cache_destroy(lv2table_kmem_cache);
1390         return ret;
1391 }
1392 core_initcall(exynos_iommu_init);