drivers/iommu/dmar.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  *
  22  * This file implements early detection/parsing of Remapping Devices
  23  * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
  24  * tables.
  25  *
  26  * These routines are used by both DMA-remapping and Interrupt-remapping
  27  */
  28
  29 #define pr_fmt(fmt)     "DMAR: " fmt
  30
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/iova.h>
  34 #include <linux/intel-iommu.h>
  35 #include <linux/timer.h>
  36 #include <linux/irq.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/tboot.h>
  39 #include <linux/dmi.h>
  40 #include <linux/slab.h>
  41 #include <linux/iommu.h>
  42 #include <linux/limits.h>
  43 #include <asm/irq_remapping.h>
  44 #include <asm/iommu_table.h>
  45
  46 #include "irq_remapping.h"
  47
  48 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
  49 struct dmar_res_callback {
  50         dmar_res_handler_t      cb[ACPI_DMAR_TYPE_RESERVED];
  51         void                    *arg[ACPI_DMAR_TYPE_RESERVED];
  52         bool                    ignore_unhandled;
  53         bool                    print_entry;
  54 };
  55
  56 /*
  57  * Assumptions:
  58  * 1) The hotplug framework guarentees that DMAR unit will be hot-added
  59  *    before IO devices managed by that unit.
  60  * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
  61  *    after IO devices managed by that unit.
  62  * 3) Hotplug events are rare.
  63  *
  64  * Locking rules for DMA and interrupt remapping related global data structures:
  65  * 1) Use dmar_global_lock in process context
  66  * 2) Use RCU in interrupt context
  67  */
  68 DECLARE_RWSEM(dmar_global_lock);
  69 LIST_HEAD(dmar_drhd_units);
  70
  71 struct acpi_table_header * __initdata dmar_tbl;
  72 static int dmar_dev_scope_status = 1;
  73 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
  74
  75 static int alloc_iommu(struct dmar_drhd_unit *drhd);
  76 static void free_iommu(struct intel_iommu *iommu);
  77
  78 extern const struct iommu_ops intel_iommu_ops;
  79
  80 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
  81 {
  82         /*
  83          * add INCLUDE_ALL at the tail, so scan the list will find it at
  84          * the very end.
  85          */
  86         if (drhd->include_all)
  87                 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
  88         else
  89                 list_add_rcu(&drhd->list, &dmar_drhd_units);
  90 }
  91
  92 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
  93 {
  94         struct acpi_dmar_device_scope *scope;
  95
  96         *cnt = 0;
  97         while (start < end) {
  98                 scope = start;
  99                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
 100                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
 101                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 102                         (*cnt)++;
 103                 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
 104                         scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
 105                         pr_warn("Unsupported device scope\n");
 106                 }
 107                 start += scope->length;
 108         }
 109         if (*cnt == 0)
 110                 return NULL;
 111
 112         return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
 113 }
 114
 115 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
 116 {
 117         int i;
 118         struct device *tmp_dev;
 119
 120         if (*devices && *cnt) {
 121                 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
 122                         put_device(tmp_dev);
 123                 kfree(*devices);
 124         }
 125
 126         *devices = NULL;
 127         *cnt = 0;
 128 }
 129
 130 /* Optimize out kzalloc()/kfree() for normal cases */
 131 static char dmar_pci_notify_info_buf[64];
 132
 133 static struct dmar_pci_notify_info *
 134 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
 135 {
 136         int level = 0;
 137         size_t size;
 138         struct pci_dev *tmp;
 139         struct dmar_pci_notify_info *info;
 140
 141         BUG_ON(dev->is_virtfn);
 142
 143         /*
 144          * Ignore devices that have a domain number higher than what can
 145          * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
 146          */
 147         if (pci_domain_nr(dev->bus) > U16_MAX)
 148                 return NULL;
 149
 150         /* Only generate path[] for device addition event */
 151         if (event == BUS_NOTIFY_ADD_DEVICE)
 152                 for (tmp = dev; tmp; tmp = tmp->bus->self)
 153                         level++;
 154
 155         size = sizeof(*info) + level * sizeof(info->path[0]);
 156         if (size <= sizeof(dmar_pci_notify_info_buf)) {
 157                 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
 158         } else {
 159                 info = kzalloc(size, GFP_KERNEL);
 160                 if (!info) {
 161                         pr_warn("Out of memory when allocating notify_info "
 162                                 "for %s.\n", pci_name(dev));
 163                         if (dmar_dev_scope_status == 0)
 164                                 dmar_dev_scope_status = -ENOMEM;
 165                         return NULL;
 166                 }
 167         }
 168
 169         info->event = event;
 170         info->dev = dev;
 171         info->seg = pci_domain_nr(dev->bus);
 172         info->level = level;
 173         if (event == BUS_NOTIFY_ADD_DEVICE) {
 174                 for (tmp = dev; tmp; tmp = tmp->bus->self) {
 175                         level--;
 176                         info->path[level].bus = tmp->bus->number;
 177                         info->path[level].device = PCI_SLOT(tmp->devfn);
 178                         info->path[level].function = PCI_FUNC(tmp->devfn);
 179                         if (pci_is_root_bus(tmp->bus))
 180                                 info->bus = tmp->bus->number;
 181                 }
 182         }
 183
 184         return info;
 185 }
 186
 187 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
 188 {
 189         if ((void *)info != dmar_pci_notify_info_buf)
 190                 kfree(info);
 191 }
 192
 193 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
 194                                 struct acpi_dmar_pci_path *path, int count)
 195 {
 196         int i;
 197
 198         if (info->bus != bus)
 199                 goto fallback;
 200         if (info->level != count)
 201                 goto fallback;
 202
 203         for (i = 0; i < count; i++) {
 204                 if (path[i].device != info->path[i].device ||
 205                     path[i].function != info->path[i].function)
 206                         goto fallback;
 207         }
 208
 209         return true;
 210
 211 fallback:
 212
 213         if (count != 1)
 214                 return false;
 215
 216         i = info->level - 1;
 217         if (bus              == info->path[i].bus &&
 218             path[0].device   == info->path[i].device &&
 219             path[0].function == info->path[i].function) {
 220                 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
 221                         bus, path[0].device, path[0].function);
 222                 return true;
 223         }
 224
 225         return false;
 226 }
 227
 228 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
 229 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
 230                           void *start, void*end, u16 segment,
 231                           struct dmar_dev_scope *devices,
 232                           int devices_cnt)
 233 {
 234         int i, level;
 235         struct device *tmp, *dev = &info->dev->dev;
 236         struct acpi_dmar_device_scope *scope;
 237         struct acpi_dmar_pci_path *path;
 238
 239         if (segment != info->seg)
 240                 return 0;
 241
 242         for (; start < end; start += scope->length) {
 243                 scope = start;
 244                 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 245                     scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 246                         continue;
 247
 248                 path = (struct acpi_dmar_pci_path *)(scope + 1);
 249                 level = (scope->length - sizeof(*scope)) / sizeof(*path);
 250                 if (!dmar_match_pci_path(info, scope->bus, path, level))
 251                         continue;
 252
 253                 /*
 254                  * We expect devices with endpoint scope to have normal PCI
 255                  * headers, and devices with bridge scope to have bridge PCI
 256                  * headers.  However PCI NTB devices may be listed in the
 257                  * DMAR table with bridge scope, even though they have a
 258                  * normal PCI header.  NTB devices are identified by class
 259                  * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
 260                  * for this special case.
 261                  */
 262                 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 263                      info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
 264                     (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
 265                      (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
 266                       info->dev->class >> 8 != PCI_CLASS_BRIDGE_OTHER))) {
 267                         pr_warn("Device scope type does not match for %s\n",
 268                                 pci_name(info->dev));
 269                         return -EINVAL;
 270                 }
 271
 272                 for_each_dev_scope(devices, devices_cnt, i, tmp)
 273                         if (tmp == NULL) {
 274                                 devices[i].bus = info->dev->bus->number;
 275                                 devices[i].devfn = info->dev->devfn;
 276                                 rcu_assign_pointer(devices[i].dev,
 277                                                    get_device(dev));
 278                                 return 1;
 279                         }
 280                 BUG_ON(i >= devices_cnt);
 281         }
 282
 283         return 0;
 284 }
 285
 286 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
 287                           struct dmar_dev_scope *devices, int count)
 288 {
 289         int index;
 290         struct device *tmp;
 291
 292         if (info->seg != segment)
 293                 return 0;
 294
 295         for_each_active_dev_scope(devices, count, index, tmp)
 296                 if (tmp == &info->dev->dev) {
 297                         RCU_INIT_POINTER(devices[index].dev, NULL);
 298                         synchronize_rcu();
 299                         put_device(tmp);
 300                         return 1;
 301                 }
 302
 303         return 0;
 304 }
 305
 306 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
 307 {
 308         int ret = 0;
 309         struct dmar_drhd_unit *dmaru;
 310         struct acpi_dmar_hardware_unit *drhd;
 311
 312         for_each_drhd_unit(dmaru) {
 313                 if (dmaru->include_all)
 314                         continue;
 315
 316                 drhd = container_of(dmaru->hdr,
 317                                     struct acpi_dmar_hardware_unit, header);
 318                 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
 319                                 ((void *)drhd) + drhd->header.length,
 320                                 dmaru->segment,
 321                                 dmaru->devices, dmaru->devices_cnt);
 322                 if (ret)
 323                         break;
 324         }
 325         if (ret >= 0)
 326                 ret = dmar_iommu_notify_scope_dev(info);
 327         if (ret < 0 && dmar_dev_scope_status == 0)
 328                 dmar_dev_scope_status = ret;
 329
 330         return ret;
 331 }
 332
 333 static void  dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
 334 {
 335         struct dmar_drhd_unit *dmaru;
 336
 337         for_each_drhd_unit(dmaru)
 338                 if (dmar_remove_dev_scope(info, dmaru->segment,
 339                         dmaru->devices, dmaru->devices_cnt))
 340                         break;
 341         dmar_iommu_notify_scope_dev(info);
 342 }
 343
 344 static int dmar_pci_bus_notifier(struct notifier_block *nb,
 345                                  unsigned long action, void *data)
 346 {
 347         struct pci_dev *pdev = to_pci_dev(data);
 348         struct dmar_pci_notify_info *info;
 349
 350         /* Only care about add/remove events for physical functions.
 351          * For VFs we actually do the lookup based on the corresponding
 352          * PF in device_to_iommu() anyway. */
 353         if (pdev->is_virtfn)
 354                 return NOTIFY_DONE;
 355         if (action != BUS_NOTIFY_ADD_DEVICE &&
 356             action != BUS_NOTIFY_REMOVED_DEVICE)
 357                 return NOTIFY_DONE;
 358
 359         info = dmar_alloc_pci_notify_info(pdev, action);
 360         if (!info)
 361                 return NOTIFY_DONE;
 362
 363         down_write(&dmar_global_lock);
 364         if (action == BUS_NOTIFY_ADD_DEVICE)
 365                 dmar_pci_bus_add_dev(info);
 366         else if (action == BUS_NOTIFY_REMOVED_DEVICE)
 367                 dmar_pci_bus_del_dev(info);
 368         up_write(&dmar_global_lock);
 369
 370         dmar_free_pci_notify_info(info);
 371
 372         return NOTIFY_OK;
 373 }
 374
 375 static struct notifier_block dmar_pci_bus_nb = {
 376         .notifier_call = dmar_pci_bus_notifier,
 377         .priority = 1,
 378 };
 379
 380 static struct dmar_drhd_unit *
 381 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
 382 {
 383         struct dmar_drhd_unit *dmaru;
 384
 385         list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list)
 386                 if (dmaru->segment == drhd->segment &&
 387                     dmaru->reg_base_addr == drhd->address)
 388                         return dmaru;
 389
 390         return NULL;
 391 }
 392
 393 /**
 394  * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
 395  * structure which uniquely represent one DMA remapping hardware unit
 396  * present in the platform
 397  */
 398 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
 399 {
 400         struct acpi_dmar_hardware_unit *drhd;
 401         struct dmar_drhd_unit *dmaru;
 402         int ret;
 403
 404         drhd = (struct acpi_dmar_hardware_unit *)header;
 405         dmaru = dmar_find_dmaru(drhd);
 406         if (dmaru)
 407                 goto out;
 408
 409         dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
 410         if (!dmaru)
 411                 return -ENOMEM;
 412
 413         /*
 414          * If header is allocated from slab by ACPI _DSM method, we need to
 415          * copy the content because the memory buffer will be freed on return.
 416          */
 417         dmaru->hdr = (void *)(dmaru + 1);
 418         memcpy(dmaru->hdr, header, header->length);
 419         dmaru->reg_base_addr = drhd->address;
 420         dmaru->segment = drhd->segment;
 421         dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
 422         dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
 423                                               ((void *)drhd) + drhd->header.length,
 424                                               &dmaru->devices_cnt);
 425         if (dmaru->devices_cnt && dmaru->devices == NULL) {
 426                 kfree(dmaru);
 427                 return -ENOMEM;
 428         }
 429
 430         ret = alloc_iommu(dmaru);
 431         if (ret) {
 432                 dmar_free_dev_scope(&dmaru->devices,
 433                                     &dmaru->devices_cnt);
 434                 kfree(dmaru);
 435                 return ret;
 436         }
 437         dmar_register_drhd_unit(dmaru);
 438
 439 out:
 440         if (arg)
 441                 (*(int *)arg)++;
 442
 443         return 0;
 444 }
 445
 446 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
 447 {
 448         if (dmaru->devices && dmaru->devices_cnt)
 449                 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
 450         if (dmaru->iommu)
 451                 free_iommu(dmaru->iommu);
 452         kfree(dmaru);
 453 }
 454
 455 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
 456                                       void *arg)
 457 {
 458         struct acpi_dmar_andd *andd = (void *)header;
 459
 460         /* Check for NUL termination within the designated length */
 461         if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
 462                 pr_warn(FW_BUG
 463                            "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
 464                            "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 465                            dmi_get_system_info(DMI_BIOS_VENDOR),
 466                            dmi_get_system_info(DMI_BIOS_VERSION),
 467                            dmi_get_system_info(DMI_PRODUCT_VERSION));
 468                 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 469                 return -EINVAL;
 470         }
 471         pr_info("ANDD device: %x name: %s\n", andd->device_number,
 472                 andd->device_name);
 473
 474         return 0;
 475 }
 476
 477 #ifdef CONFIG_ACPI_NUMA
 478 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
 479 {
 480         struct acpi_dmar_rhsa *rhsa;
 481         struct dmar_drhd_unit *drhd;
 482
 483         rhsa = (struct acpi_dmar_rhsa *)header;
 484         for_each_drhd_unit(drhd) {
 485                 if (drhd->reg_base_addr == rhsa->base_address) {
 486                         int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
 487
 488                         if (!node_online(node))
 489                                 node = -1;
 490                         drhd->iommu->node = node;
 491                         return 0;
 492                 }
 493         }
 494         pr_warn(FW_BUG
 495                 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
 496                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 497                 rhsa->base_address,
 498                 dmi_get_system_info(DMI_BIOS_VENDOR),
 499                 dmi_get_system_info(DMI_BIOS_VERSION),
 500                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 501         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 502
 503         return 0;
 504 }
 505 #else
 506 #define dmar_parse_one_rhsa             dmar_res_noop
 507 #endif
 508
 509 static void
 510 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
 511 {
 512         struct acpi_dmar_hardware_unit *drhd;
 513         struct acpi_dmar_reserved_memory *rmrr;
 514         struct acpi_dmar_atsr *atsr;
 515         struct acpi_dmar_rhsa *rhsa;
 516
 517         switch (header->type) {
 518         case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 519                 drhd = container_of(header, struct acpi_dmar_hardware_unit,
 520                                     header);
 521                 pr_info("DRHD base: %#016Lx flags: %#x\n",
 522                         (unsigned long long)drhd->address, drhd->flags);
 523                 break;
 524         case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 525                 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
 526                                     header);
 527                 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
 528                         (unsigned long long)rmrr->base_address,
 529                         (unsigned long long)rmrr->end_address);
 530                 break;
 531         case ACPI_DMAR_TYPE_ROOT_ATS:
 532                 atsr = container_of(header, struct acpi_dmar_atsr, header);
 533                 pr_info("ATSR flags: %#x\n", atsr->flags);
 534                 break;
 535         case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
 536                 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
 537                 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
 538                        (unsigned long long)rhsa->base_address,
 539                        rhsa->proximity_domain);
 540                 break;
 541         case ACPI_DMAR_TYPE_NAMESPACE:
 542                 /* We don't print this here because we need to sanity-check
 543                    it first. So print it in dmar_parse_one_andd() instead. */
 544                 break;
 545         }
 546 }
 547
 548 /**
 549  * dmar_table_detect - checks to see if the platform supports DMAR devices
 550  */
 551 static int __init dmar_table_detect(void)
 552 {
 553         acpi_status status = AE_OK;
 554
 555         /* if we could find DMAR table, then there are DMAR devices */
 556         status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
 557
 558         if (ACPI_SUCCESS(status) && !dmar_tbl) {
 559                 pr_warn("Unable to map DMAR\n");
 560                 status = AE_NOT_FOUND;
 561         }
 562
 563         return ACPI_SUCCESS(status) ? 0 : -ENOENT;
 564 }
 565
 566 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
 567                                        size_t len, struct dmar_res_callback *cb)
 568 {
 569         struct acpi_dmar_header *iter, *next;
 570         struct acpi_dmar_header *end = ((void *)start) + len;
 571
 572         for (iter = start; iter < end; iter = next) {
 573                 next = (void *)iter + iter->length;
 574                 if (iter->length == 0) {
 575                         /* Avoid looping forever on bad ACPI tables */
 576                         pr_debug(FW_BUG "Invalid 0-length structure\n");
 577                         break;
 578                 } else if (next > end) {
 579                         /* Avoid passing table end */
 580                         pr_warn(FW_BUG "Record passes table end\n");
 581                         return -EINVAL;
 582                 }
 583
 584                 if (cb->print_entry)
 585                         dmar_table_print_dmar_entry(iter);
 586
 587                 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
 588                         /* continue for forward compatibility */
 589                         pr_debug("Unknown DMAR structure type %d\n",
 590                                  iter->type);
 591                 } else if (cb->cb[iter->type]) {
 592                         int ret;
 593
 594                         ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
 595                         if (ret)
 596                                 return ret;
 597                 } else if (!cb->ignore_unhandled) {
 598                         pr_warn("No handler for DMAR structure type %d\n",
 599                                 iter->type);
 600                         return -EINVAL;
 601                 }
 602         }
 603
 604         return 0;
 605 }
 606
 607 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
 608                                        struct dmar_res_callback *cb)
 609 {
 610         return dmar_walk_remapping_entries((void *)(dmar + 1),
 611                         dmar->header.length - sizeof(*dmar), cb);
 612 }
 613
 614 /**
 615  * parse_dmar_table - parses the DMA reporting table
 616  */
 617 static int __init
 618 parse_dmar_table(void)
 619 {
 620         struct acpi_table_dmar *dmar;
 621         int drhd_count = 0;
 622         int ret;
 623         struct dmar_res_callback cb = {
 624                 .print_entry = true,
 625                 .ignore_unhandled = true,
 626                 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
 627                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
 628                 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
 629                 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
 630                 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
 631                 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
 632         };
 633
 634         /*
 635          * Do it again, earlier dmar_tbl mapping could be mapped with
 636          * fixed map.
 637          */
 638         dmar_table_detect();
 639
 640         /*
 641          * ACPI tables may not be DMA protected by tboot, so use DMAR copy
 642          * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
 643          */
 644         dmar_tbl = tboot_get_dmar_table(dmar_tbl);
 645
 646         dmar = (struct acpi_table_dmar *)dmar_tbl;
 647         if (!dmar)
 648                 return -ENODEV;
 649
 650         if (dmar->width < PAGE_SHIFT - 1) {
 651                 pr_warn("Invalid DMAR haw\n");
 652                 return -EINVAL;
 653         }
 654
 655         pr_info("Host address width %d\n", dmar->width + 1);
 656         ret = dmar_walk_dmar_table(dmar, &cb);
 657         if (ret == 0 && drhd_count == 0)
 658                 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
 659
 660         return ret;
 661 }
 662
 663 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
 664                                  int cnt, struct pci_dev *dev)
 665 {
 666         int index;
 667         struct device *tmp;
 668
 669         while (dev) {
 670                 for_each_active_dev_scope(devices, cnt, index, tmp)
 671                         if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
 672                                 return 1;
 673
 674                 /* Check our parent */
 675                 dev = dev->bus->self;
 676         }
 677
 678         return 0;
 679 }
 680
 681 struct dmar_drhd_unit *
 682 dmar_find_matched_drhd_unit(struct pci_dev *dev)
 683 {
 684         struct dmar_drhd_unit *dmaru;
 685         struct acpi_dmar_hardware_unit *drhd;
 686
 687         dev = pci_physfn(dev);
 688
 689         rcu_read_lock();
 690         for_each_drhd_unit(dmaru) {
 691                 drhd = container_of(dmaru->hdr,
 692                                     struct acpi_dmar_hardware_unit,
 693                                     header);
 694
 695                 if (dmaru->include_all &&
 696                     drhd->segment == pci_domain_nr(dev->bus))
 697                         goto out;
 698
 699                 if (dmar_pci_device_match(dmaru->devices,
 700                                           dmaru->devices_cnt, dev))
 701                         goto out;
 702         }
 703         dmaru = NULL;
 704 out:
 705         rcu_read_unlock();
 706
 707         return dmaru;
 708 }
 709
 710 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
 711                                               struct acpi_device *adev)
 712 {
 713         struct dmar_drhd_unit *dmaru;
 714         struct acpi_dmar_hardware_unit *drhd;
 715         struct acpi_dmar_device_scope *scope;
 716         struct device *tmp;
 717         int i;
 718         struct acpi_dmar_pci_path *path;
 719
 720         for_each_drhd_unit(dmaru) {
 721                 drhd = container_of(dmaru->hdr,
 722                                     struct acpi_dmar_hardware_unit,
 723                                     header);
 724
 725                 for (scope = (void *)(drhd + 1);
 726                      (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
 727                      scope = ((void *)scope) + scope->length) {
 728                         if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
 729                                 continue;
 730                         if (scope->enumeration_id != device_number)
 731                                 continue;
 732
 733                         path = (void *)(scope + 1);
 734                         pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
 735                                 dev_name(&adev->dev), dmaru->reg_base_addr,
 736                                 scope->bus, path->device, path->function);
 737                         for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
 738                                 if (tmp == NULL) {
 739                                         dmaru->devices[i].bus = scope->bus;
 740                                         dmaru->devices[i].devfn = PCI_DEVFN(path->device,
 741                                                                             path->function);
 742                                         rcu_assign_pointer(dmaru->devices[i].dev,
 743                                                            get_device(&adev->dev));
 744                                         return;
 745                                 }
 746                         BUG_ON(i >= dmaru->devices_cnt);
 747                 }
 748         }
 749         pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
 750                 device_number, dev_name(&adev->dev));
 751 }
 752
 753 static int __init dmar_acpi_dev_scope_init(void)
 754 {
 755         struct acpi_dmar_andd *andd;
 756
 757         if (dmar_tbl == NULL)
 758                 return -ENODEV;
 759
 760         for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
 761              ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
 762              andd = ((void *)andd) + andd->header.length) {
 763                 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
 764                         acpi_handle h;
 765                         struct acpi_device *adev;
 766
 767                         if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
 768                                                           andd->device_name,
 769                                                           &h))) {
 770                                 pr_err("Failed to find handle for ACPI object %s\n",
 771                                        andd->device_name);
 772                                 continue;
 773                         }
 774                         if (acpi_bus_get_device(h, &adev)) {
 775                                 pr_err("Failed to get device for ACPI object %s\n",
 776                                        andd->device_name);
 777                                 continue;
 778                         }
 779                         dmar_acpi_insert_dev_scope(andd->device_number, adev);
 780                 }
 781         }
 782         return 0;
 783 }
 784
 785 int __init dmar_dev_scope_init(void)
 786 {
 787         struct pci_dev *dev = NULL;
 788         struct dmar_pci_notify_info *info;
 789
 790         if (dmar_dev_scope_status != 1)
 791                 return dmar_dev_scope_status;
 792
 793         if (list_empty(&dmar_drhd_units)) {
 794                 dmar_dev_scope_status = -ENODEV;
 795         } else {
 796                 dmar_dev_scope_status = 0;
 797
 798                 dmar_acpi_dev_scope_init();
 799
 800                 for_each_pci_dev(dev) {
 801                         if (dev->is_virtfn)
 802                                 continue;
 803
 804                         info = dmar_alloc_pci_notify_info(dev,
 805                                         BUS_NOTIFY_ADD_DEVICE);
 806                         if (!info) {
 807                                 pci_dev_put(dev);
 808                                 return dmar_dev_scope_status;
 809                         } else {
 810                                 dmar_pci_bus_add_dev(info);
 811                                 dmar_free_pci_notify_info(info);
 812                         }
 813                 }
 814
 815                 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
 816         }
 817
 818         return dmar_dev_scope_status;
 819 }
 820
 821
 822 int __init dmar_table_init(void)
 823 {
 824         static int dmar_table_initialized;
 825         int ret;
 826
 827         if (dmar_table_initialized == 0) {
 828                 ret = parse_dmar_table();
 829                 if (ret < 0) {
 830                         if (ret != -ENODEV)
 831                                 pr_info("Parse DMAR table failure.\n");
 832                 } else  if (list_empty(&dmar_drhd_units)) {
 833                         pr_info("No DMAR devices found\n");
 834                         ret = -ENODEV;
 835                 }
 836
 837                 if (ret < 0)
 838                         dmar_table_initialized = ret;
 839                 else
 840                         dmar_table_initialized = 1;
 841         }
 842
 843         return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
 844 }
 845
 846 static void warn_invalid_dmar(u64 addr, const char *message)
 847 {
 848         pr_warn_once(FW_BUG
 849                 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
 850                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 851                 addr, message,
 852                 dmi_get_system_info(DMI_BIOS_VENDOR),
 853                 dmi_get_system_info(DMI_BIOS_VERSION),
 854                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 855         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 856 }
 857
 858 static int __ref
 859 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
 860 {
 861         struct acpi_dmar_hardware_unit *drhd;
 862         void __iomem *addr;
 863         u64 cap, ecap;
 864
 865         drhd = (void *)entry;
 866         if (!drhd->address) {
 867                 warn_invalid_dmar(0, "");
 868                 return -EINVAL;
 869         }
 870
 871         if (arg)
 872                 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
 873         else
 874                 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
 875         if (!addr) {
 876                 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
 877                 return -EINVAL;
 878         }
 879
 880         cap = dmar_readq(addr + DMAR_CAP_REG);
 881         ecap = dmar_readq(addr + DMAR_ECAP_REG);
 882
 883         if (arg)
 884                 iounmap(addr);
 885         else
 886                 early_iounmap(addr, VTD_PAGE_SIZE);
 887
 888         if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
 889                 warn_invalid_dmar(drhd->address, " returns all ones");
 890                 return -EINVAL;
 891         }
 892
 893         return 0;
 894 }
 895
 896 int __init detect_intel_iommu(void)
 897 {
 898         int ret;
 899         struct dmar_res_callback validate_drhd_cb = {
 900                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
 901                 .ignore_unhandled = true,
 902         };
 903
 904         down_write(&dmar_global_lock);
 905         ret = dmar_table_detect();
 906         if (!ret)
 907                 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
 908                                            &validate_drhd_cb);
 909         if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) {
 910                 iommu_detected = 1;
 911                 /* Make sure ACS will be enabled */
 912                 pci_request_acs();
 913         }
 914
 915 #ifdef CONFIG_X86
 916         if (!ret)
 917                 x86_init.iommu.iommu_init = intel_iommu_init;
 918 #endif
 919
 920         if (dmar_tbl) {
 921                 acpi_put_table(dmar_tbl);
 922                 dmar_tbl = NULL;
 923         }
 924         up_write(&dmar_global_lock);
 925
 926         return ret ? ret : 1;
 927 }
 928
 929 static void unmap_iommu(struct intel_iommu *iommu)
 930 {
 931         iounmap(iommu->reg);
 932         release_mem_region(iommu->reg_phys, iommu->reg_size);
 933 }
 934
 935 /**
 936  * map_iommu: map the iommu's registers
 937  * @iommu: the iommu to map
 938  * @phys_addr: the physical address of the base resgister
 939  *
 940  * Memory map the iommu's registers.  Start w/ a single page, and
 941  * possibly expand if that turns out to be insufficent.
 942  */
 943 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
 944 {
 945         int map_size, err=0;
 946
 947         iommu->reg_phys = phys_addr;
 948         iommu->reg_size = VTD_PAGE_SIZE;
 949
 950         if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
 951                 pr_err("Can't reserve memory\n");
 952                 err = -EBUSY;
 953                 goto out;
 954         }
 955
 956         iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 957         if (!iommu->reg) {
 958                 pr_err("Can't map the region\n");
 959                 err = -ENOMEM;
 960                 goto release;
 961         }
 962
 963         iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 964         iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 965
 966         if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
 967                 err = -EINVAL;
 968                 warn_invalid_dmar(phys_addr, " returns all ones");
 969                 goto unmap;
 970         }
 971
 972         /* the registers might be more than one page */
 973         map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
 974                          cap_max_fault_reg_offset(iommu->cap));
 975         map_size = VTD_PAGE_ALIGN(map_size);
 976         if (map_size > iommu->reg_size) {
 977                 iounmap(iommu->reg);
 978                 release_mem_region(iommu->reg_phys, iommu->reg_size);
 979                 iommu->reg_size = map_size;
 980                 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
 981                                         iommu->name)) {
 982                         pr_err("Can't reserve memory\n");
 983                         err = -EBUSY;
 984                         goto out;
 985                 }
 986                 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 987                 if (!iommu->reg) {
 988                         pr_err("Can't map the region\n");
 989                         err = -ENOMEM;
 990                         goto release;
 991                 }
 992         }
 993         err = 0;
 994         goto out;
 995
 996 unmap:
 997         iounmap(iommu->reg);
 998 release:
 999         release_mem_region(iommu->reg_phys, iommu->reg_size);
1000 out:
1001         return err;
1002 }
1003
1004 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
1005 {
1006         iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
1007                                             DMAR_UNITS_SUPPORTED);
1008         if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
1009                 iommu->seq_id = -1;
1010         } else {
1011                 set_bit(iommu->seq_id, dmar_seq_ids);
1012                 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1013         }
1014
1015         return iommu->seq_id;
1016 }
1017
1018 static void dmar_free_seq_id(struct intel_iommu *iommu)
1019 {
1020         if (iommu->seq_id >= 0) {
1021                 clear_bit(iommu->seq_id, dmar_seq_ids);
1022                 iommu->seq_id = -1;
1023         }
1024 }
1025
1026 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1027 {
1028         struct intel_iommu *iommu;
1029         u32 ver, sts;
1030         int agaw = -1;
1031         int msagaw = -1;
1032         int err;
1033
1034         if (!drhd->reg_base_addr) {
1035                 warn_invalid_dmar(0, "");
1036                 return -EINVAL;
1037         }
1038
1039         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1040         if (!iommu)
1041                 return -ENOMEM;
1042
1043         if (dmar_alloc_seq_id(iommu) < 0) {
1044                 pr_err("Failed to allocate seq_id\n");
1045                 err = -ENOSPC;
1046                 goto error;
1047         }
1048
1049         err = map_iommu(iommu, drhd->reg_base_addr);
1050         if (err) {
1051                 pr_err("Failed to map %s\n", iommu->name);
1052                 goto error_free_seq_id;
1053         }
1054
1055         err = -EINVAL;
1056         if (cap_sagaw(iommu->cap) == 0) {
1057                 pr_info("%s: No supported address widths. Not attempting DMA translation.\n",
1058                         iommu->name);
1059                 drhd->ignored = 1;
1060         }
1061
1062         if (!drhd->ignored) {
1063                 agaw = iommu_calculate_agaw(iommu);
1064                 if (agaw < 0) {
1065                         pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1066                                iommu->seq_id);
1067                         drhd->ignored = 1;
1068                 }
1069         }
1070         if (!drhd->ignored) {
1071                 msagaw = iommu_calculate_max_sagaw(iommu);
1072                 if (msagaw < 0) {
1073                         pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1074                                iommu->seq_id);
1075                         drhd->ignored = 1;
1076                         agaw = -1;
1077                 }
1078         }
1079         iommu->agaw = agaw;
1080         iommu->msagaw = msagaw;
1081         iommu->segment = drhd->segment;
1082
1083         iommu->node = -1;
1084
1085         ver = readl(iommu->reg + DMAR_VER_REG);
1086         pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1087                 iommu->name,
1088                 (unsigned long long)drhd->reg_base_addr,
1089                 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1090                 (unsigned long long)iommu->cap,
1091                 (unsigned long long)iommu->ecap);
1092
1093         /* Reflect status in gcmd */
1094         sts = readl(iommu->reg + DMAR_GSTS_REG);
1095         if (sts & DMA_GSTS_IRES)
1096                 iommu->gcmd |= DMA_GCMD_IRE;
1097         if (sts & DMA_GSTS_TES)
1098                 iommu->gcmd |= DMA_GCMD_TE;
1099         if (sts & DMA_GSTS_QIES)
1100                 iommu->gcmd |= DMA_GCMD_QIE;
1101
1102         raw_spin_lock_init(&iommu->register_lock);
1103
1104         /*
1105          * This is only for hotplug; at boot time intel_iommu_enabled won't
1106          * be set yet. When intel_iommu_init() runs, it registers the units
1107          * present at boot time, then sets intel_iommu_enabled.
1108          */
1109         if (intel_iommu_enabled && !drhd->ignored) {
1110                 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1111                                              intel_iommu_groups,
1112                                              "%s", iommu->name);
1113                 if (err)
1114                         goto err_unmap;
1115
1116                 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1117
1118                 err = iommu_device_register(&iommu->iommu);
1119                 if (err)
1120                         goto err_sysfs;
1121         }
1122
1123         drhd->iommu = iommu;
1124         iommu->drhd = drhd;
1125
1126         return 0;
1127
1128 err_sysfs:
1129         iommu_device_sysfs_remove(&iommu->iommu);
1130 err_unmap:
1131         unmap_iommu(iommu);
1132 error_free_seq_id:
1133         dmar_free_seq_id(iommu);
1134 error:
1135         kfree(iommu);
1136         return err;
1137 }
1138
1139 static void free_iommu(struct intel_iommu *iommu)
1140 {
1141         if (intel_iommu_enabled && !iommu->drhd->ignored) {
1142                 iommu_device_unregister(&iommu->iommu);
1143                 iommu_device_sysfs_remove(&iommu->iommu);
1144         }
1145
1146         if (iommu->irq) {
1147                 if (iommu->pr_irq) {
1148                         free_irq(iommu->pr_irq, iommu);
1149                         dmar_free_hwirq(iommu->pr_irq);
1150                         iommu->pr_irq = 0;
1151                 }
1152                 free_irq(iommu->irq, iommu);
1153                 dmar_free_hwirq(iommu->irq);
1154                 iommu->irq = 0;
1155         }
1156
1157         if (iommu->qi) {
1158                 free_page((unsigned long)iommu->qi->desc);
1159                 kfree(iommu->qi->desc_status);
1160                 kfree(iommu->qi);
1161         }
1162
1163         if (iommu->reg)
1164                 unmap_iommu(iommu);
1165
1166         dmar_free_seq_id(iommu);
1167         kfree(iommu);
1168 }
1169
1170 /*
1171  * Reclaim all the submitted descriptors which have completed its work.
1172  */
1173 static inline void reclaim_free_desc(struct q_inval *qi)
1174 {
1175         while (qi->desc_status[qi->free_tail] == QI_DONE ||
1176                qi->desc_status[qi->free_tail] == QI_ABORT) {
1177                 qi->desc_status[qi->free_tail] = QI_FREE;
1178                 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1179                 qi->free_cnt++;
1180         }
1181 }
1182
1183 static int qi_check_fault(struct intel_iommu *iommu, int index)
1184 {
1185         u32 fault;
1186         int head, tail;
1187         struct q_inval *qi = iommu->qi;
1188         int wait_index = (index + 1) % QI_LENGTH;
1189
1190         if (qi->desc_status[wait_index] == QI_ABORT)
1191                 return -EAGAIN;
1192
1193         fault = readl(iommu->reg + DMAR_FSTS_REG);
1194
1195         /*
1196          * If IQE happens, the head points to the descriptor associated
1197          * with the error. No new descriptors are fetched until the IQE
1198          * is cleared.
1199          */
1200         if (fault & DMA_FSTS_IQE) {
1201                 head = readl(iommu->reg + DMAR_IQH_REG);
1202                 if ((head >> DMAR_IQ_SHIFT) == index) {
1203                         pr_err("VT-d detected invalid descriptor: "
1204                                 "low=%llx, high=%llx\n",
1205                                 (unsigned long long)qi->desc[index].low,
1206                                 (unsigned long long)qi->desc[index].high);
1207                         memcpy(&qi->desc[index], &qi->desc[wait_index],
1208                                         sizeof(struct qi_desc));
1209                         writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1210                         return -EINVAL;
1211                 }
1212         }
1213
1214         /*
1215          * If ITE happens, all pending wait_desc commands are aborted.
1216          * No new descriptors are fetched until the ITE is cleared.
1217          */
1218         if (fault & DMA_FSTS_ITE) {
1219                 head = readl(iommu->reg + DMAR_IQH_REG);
1220                 head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1221                 head |= 1;
1222                 tail = readl(iommu->reg + DMAR_IQT_REG);
1223                 tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1224
1225                 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1226
1227                 do {
1228                         if (qi->desc_status[head] == QI_IN_USE)
1229                                 qi->desc_status[head] = QI_ABORT;
1230                         head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1231                 } while (head != tail);
1232
1233                 if (qi->desc_status[wait_index] == QI_ABORT)
1234                         return -EAGAIN;
1235         }
1236
1237         if (fault & DMA_FSTS_ICE)
1238                 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1239
1240         return 0;
1241 }
1242
1243 /*
1244  * Submit the queued invalidation descriptor to the remapping
1245  * hardware unit and wait for its completion.
1246  */
1247 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1248 {
1249         int rc;
1250         struct q_inval *qi = iommu->qi;
1251         struct qi_desc *hw, wait_desc;
1252         int wait_index, index;
1253         unsigned long flags;
1254
1255         if (!qi)
1256                 return 0;
1257
1258         hw = qi->desc;
1259
1260 restart:
1261         rc = 0;
1262
1263         raw_spin_lock_irqsave(&qi->q_lock, flags);
1264         while (qi->free_cnt < 3) {
1265                 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1266                 cpu_relax();
1267                 raw_spin_lock_irqsave(&qi->q_lock, flags);
1268         }
1269
1270         index = qi->free_head;
1271         wait_index = (index + 1) % QI_LENGTH;
1272
1273         qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1274
1275         hw[index] = *desc;
1276
1277         wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
1278                         QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1279         wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
1280
1281         hw[wait_index] = wait_desc;
1282
1283         qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1284         qi->free_cnt -= 2;
1285
1286         /*
1287          * update the HW tail register indicating the presence of
1288          * new descriptors.
1289          */
1290         writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);
1291
1292         while (qi->desc_status[wait_index] != QI_DONE) {
1293                 /*
1294                  * We will leave the interrupts disabled, to prevent interrupt
1295                  * context to queue another cmd while a cmd is already submitted
1296                  * and waiting for completion on this cpu. This is to avoid
1297                  * a deadlock where the interrupt context can wait indefinitely
1298                  * for free slots in the queue.
1299                  */
1300                 rc = qi_check_fault(iommu, index);
1301                 if (rc)
1302                         break;
1303
1304                 raw_spin_unlock(&qi->q_lock);
1305                 cpu_relax();
1306                 raw_spin_lock(&qi->q_lock);
1307         }
1308
1309         qi->desc_status[index] = QI_DONE;
1310
1311         reclaim_free_desc(qi);
1312         raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1313
1314         if (rc == -EAGAIN)
1315                 goto restart;
1316
1317         return rc;
1318 }
1319
1320 /*
1321  * Flush the global interrupt entry cache.
1322  */
1323 void qi_global_iec(struct intel_iommu *iommu)
1324 {
1325         struct qi_desc desc;
1326
1327         desc.low = QI_IEC_TYPE;
1328         desc.high = 0;
1329
1330         /* should never fail */
1331         qi_submit_sync(&desc, iommu);
1332 }
1333
1334 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1335                       u64 type)
1336 {
1337         struct qi_desc desc;
1338
1339         desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1340                         | QI_CC_GRAN(type) | QI_CC_TYPE;
1341         desc.high = 0;
1342
1343         qi_submit_sync(&desc, iommu);
1344 }
1345
1346 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1347                     unsigned int size_order, u64 type)
1348 {
1349         u8 dw = 0, dr = 0;
1350
1351         struct qi_desc desc;
1352         int ih = 0;
1353
1354         if (cap_write_drain(iommu->cap))
1355                 dw = 1;
1356
1357         if (cap_read_drain(iommu->cap))
1358                 dr = 1;
1359
1360         desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1361                 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1362         desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1363                 | QI_IOTLB_AM(size_order);
1364
1365         qi_submit_sync(&desc, iommu);
1366 }
1367
1368 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1369                         u16 qdep, u64 addr, unsigned mask)
1370 {
1371         struct qi_desc desc;
1372
1373         if (mask) {
1374                 BUG_ON(addr & ((1ULL << (VTD_PAGE_SHIFT + mask)) - 1));
1375                 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1376                 desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1377         } else
1378                 desc.high = QI_DEV_IOTLB_ADDR(addr);
1379
1380         if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1381                 qdep = 0;
1382
1383         desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1384                    QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1385
1386         qi_submit_sync(&desc, iommu);
1387 }
1388
1389 /*
1390  * Disable Queued Invalidation interface.
1391  */
1392 void dmar_disable_qi(struct intel_iommu *iommu)
1393 {
1394         unsigned long flags;
1395         u32 sts;
1396         cycles_t start_time = get_cycles();
1397
1398         if (!ecap_qis(iommu->ecap))
1399                 return;
1400
1401         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1402
1403         sts =  readl(iommu->reg + DMAR_GSTS_REG);
1404         if (!(sts & DMA_GSTS_QIES))
1405                 goto end;
1406
1407         /*
1408          * Give a chance to HW to complete the pending invalidation requests.
1409          */
1410         while ((readl(iommu->reg + DMAR_IQT_REG) !=
1411                 readl(iommu->reg + DMAR_IQH_REG)) &&
1412                 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1413                 cpu_relax();
1414
1415         iommu->gcmd &= ~DMA_GCMD_QIE;
1416         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1417
1418         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1419                       !(sts & DMA_GSTS_QIES), sts);
1420 end:
1421         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1422 }
1423
1424 /*
1425  * Enable queued invalidation.
1426  */
1427 static void __dmar_enable_qi(struct intel_iommu *iommu)
1428 {
1429         u32 sts;
1430         unsigned long flags;
1431         struct q_inval *qi = iommu->qi;
1432
1433         qi->free_head = qi->free_tail = 0;
1434         qi->free_cnt = QI_LENGTH;
1435
1436         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1437
1438         /* write zero to the tail reg */
1439         writel(0, iommu->reg + DMAR_IQT_REG);
1440
1441         dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
1442
1443         iommu->gcmd |= DMA_GCMD_QIE;
1444         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1445
1446         /* Make sure hardware complete it */
1447         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1448
1449         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1450 }
1451
1452 /*
1453  * Enable Queued Invalidation interface. This is a must to support
1454  * interrupt-remapping. Also used by DMA-remapping, which replaces
1455  * register based IOTLB invalidation.
1456  */
1457 int dmar_enable_qi(struct intel_iommu *iommu)
1458 {
1459         struct q_inval *qi;
1460         struct page *desc_page;
1461
1462         if (!ecap_qis(iommu->ecap))
1463                 return -ENOENT;
1464
1465         /*
1466          * queued invalidation is already setup and enabled.
1467          */
1468         if (iommu->qi)
1469                 return 0;
1470
1471         iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1472         if (!iommu->qi)
1473                 return -ENOMEM;
1474
1475         qi = iommu->qi;
1476
1477
1478         desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);
1479         if (!desc_page) {
1480                 kfree(qi);
1481                 iommu->qi = NULL;
1482                 return -ENOMEM;
1483         }
1484
1485         qi->desc = page_address(desc_page);
1486
1487         qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
1488         if (!qi->desc_status) {
1489                 free_page((unsigned long) qi->desc);
1490                 kfree(qi);
1491                 iommu->qi = NULL;
1492                 return -ENOMEM;
1493         }
1494
1495         raw_spin_lock_init(&qi->q_lock);
1496
1497         __dmar_enable_qi(iommu);
1498
1499         return 0;
1500 }
1501
1502 /* iommu interrupt handling. Most stuff are MSI-like. */
1503
1504 enum faulttype {
1505         DMA_REMAP,
1506         INTR_REMAP,
1507         UNKNOWN,
1508 };
1509
1510 static const char *dma_remap_fault_reasons[] =
1511 {
1512         "Software",
1513         "Present bit in root entry is clear",
1514         "Present bit in context entry is clear",
1515         "Invalid context entry",
1516         "Access beyond MGAW",
1517         "PTE Write access is not set",
1518         "PTE Read access is not set",
1519         "Next page table ptr is invalid",
1520         "Root table address invalid",
1521         "Context table ptr is invalid",
1522         "non-zero reserved fields in RTP",
1523         "non-zero reserved fields in CTP",
1524         "non-zero reserved fields in PTE",
1525         "PCE for translation request specifies blocking",
1526 };
1527
1528 static const char *irq_remap_fault_reasons[] =
1529 {
1530         "Detected reserved fields in the decoded interrupt-remapped request",
1531         "Interrupt index exceeded the interrupt-remapping table size",
1532         "Present field in the IRTE entry is clear",
1533         "Error accessing interrupt-remapping table pointed by IRTA_REG",
1534         "Detected reserved fields in the IRTE entry",
1535         "Blocked a compatibility format interrupt request",
1536         "Blocked an interrupt request due to source-id verification failure",
1537 };
1538
1539 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1540 {
1541         if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1542                                         ARRAY_SIZE(irq_remap_fault_reasons))) {
1543                 *fault_type = INTR_REMAP;
1544                 return irq_remap_fault_reasons[fault_reason - 0x20];
1545         } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1546                 *fault_type = DMA_REMAP;
1547                 return dma_remap_fault_reasons[fault_reason];
1548         } else {
1549                 *fault_type = UNKNOWN;
1550                 return "Unknown";
1551         }
1552 }
1553
1554
1555 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1556 {
1557         if (iommu->irq == irq)
1558                 return DMAR_FECTL_REG;
1559         else if (iommu->pr_irq == irq)
1560                 return DMAR_PECTL_REG;
1561         else
1562                 BUG();
1563 }
1564
1565 void dmar_msi_unmask(struct irq_data *data)
1566 {
1567         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1568         int reg = dmar_msi_reg(iommu, data->irq);
1569         unsigned long flag;
1570
1571         /* unmask it */
1572         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1573         writel(0, iommu->reg + reg);
1574         /* Read a reg to force flush the post write */
1575         readl(iommu->reg + reg);
1576         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1577 }
1578
1579 void dmar_msi_mask(struct irq_data *data)
1580 {
1581         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1582         int reg = dmar_msi_reg(iommu, data->irq);
1583         unsigned long flag;
1584
1585         /* mask it */
1586         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1587         writel(DMA_FECTL_IM, iommu->reg + reg);
1588         /* Read a reg to force flush the post write */
1589         readl(iommu->reg + reg);
1590         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1591 }
1592
1593 void dmar_msi_write(int irq, struct msi_msg *msg)
1594 {
1595         struct intel_iommu *iommu = irq_get_handler_data(irq);
1596         int reg = dmar_msi_reg(iommu, irq);
1597         unsigned long flag;
1598
1599         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1600         writel(msg->data, iommu->reg + reg + 4);
1601         writel(msg->address_lo, iommu->reg + reg + 8);
1602         writel(msg->address_hi, iommu->reg + reg + 12);
1603         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1604 }
1605
1606 void dmar_msi_read(int irq, struct msi_msg *msg)
1607 {
1608         struct intel_iommu *iommu = irq_get_handler_data(irq);
1609         int reg = dmar_msi_reg(iommu, irq);
1610         unsigned long flag;
1611
1612         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1613         msg->data = readl(iommu->reg + reg + 4);
1614         msg->address_lo = readl(iommu->reg + reg + 8);
1615         msg->address_hi = readl(iommu->reg + reg + 12);
1616         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1617 }
1618
1619 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1620                 u8 fault_reason, u16 source_id, unsigned long long addr)
1621 {
1622         const char *reason;
1623         int fault_type;
1624
1625         reason = dmar_get_fault_reason(fault_reason, &fault_type);
1626
1627         if (fault_type == INTR_REMAP)
1628                 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1629                         source_id >> 8, PCI_SLOT(source_id & 0xFF),
1630                         PCI_FUNC(source_id & 0xFF), addr >> 48,
1631                         fault_reason, reason);
1632         else
1633                 pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n",
1634                        type ? "DMA Read" : "DMA Write",
1635                        source_id >> 8, PCI_SLOT(source_id & 0xFF),
1636                        PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
1637         return 0;
1638 }
1639
1640 #define PRIMARY_FAULT_REG_LEN (16)
1641 irqreturn_t dmar_fault(int irq, void *dev_id)
1642 {
1643         struct intel_iommu *iommu = dev_id;
1644         int reg, fault_index;
1645         u32 fault_status;
1646         unsigned long flag;
1647         bool ratelimited;
1648         static DEFINE_RATELIMIT_STATE(rs,
1649                                       DEFAULT_RATELIMIT_INTERVAL,
1650                                       DEFAULT_RATELIMIT_BURST);
1651
1652         /* Disable printing, simply clear the fault when ratelimited */
1653         ratelimited = !__ratelimit(&rs);
1654
1655         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1656         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1657         if (fault_status && !ratelimited)
1658                 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1659
1660         /* TBD: ignore advanced fault log currently */
1661         if (!(fault_status & DMA_FSTS_PPF))
1662                 goto unlock_exit;
1663
1664         fault_index = dma_fsts_fault_record_index(fault_status);
1665         reg = cap_fault_reg_offset(iommu->cap);
1666         while (1) {
1667                 u8 fault_reason;
1668                 u16 source_id;
1669                 u64 guest_addr;
1670                 int type;
1671                 u32 data;
1672
1673                 /* highest 32 bits */
1674                 data = readl(iommu->reg + reg +
1675                                 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1676                 if (!(data & DMA_FRCD_F))
1677                         break;
1678
1679                 if (!ratelimited) {
1680                         fault_reason = dma_frcd_fault_reason(data);
1681                         type = dma_frcd_type(data);
1682
1683                         data = readl(iommu->reg + reg +
1684                                      fault_index * PRIMARY_FAULT_REG_LEN + 8);
1685                         source_id = dma_frcd_source_id(data);
1686
1687                         guest_addr = dmar_readq(iommu->reg + reg +
1688                                         fault_index * PRIMARY_FAULT_REG_LEN);
1689                         guest_addr = dma_frcd_page_addr(guest_addr);
1690                 }
1691
1692                 /* clear the fault */
1693                 writel(DMA_FRCD_F, iommu->reg + reg +
1694                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
1695
1696                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1697
1698                 if (!ratelimited)
1699                         dmar_fault_do_one(iommu, type, fault_reason,
1700                                           source_id, guest_addr);
1701
1702                 fault_index++;
1703                 if (fault_index >= cap_num_fault_regs(iommu->cap))
1704                         fault_index = 0;
1705                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1706         }
1707
1708         writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG);
1709
1710 unlock_exit:
1711         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1712         return IRQ_HANDLED;
1713 }
1714
1715 int dmar_set_interrupt(struct intel_iommu *iommu)
1716 {
1717         int irq, ret;
1718
1719         /*
1720          * Check if the fault interrupt is already initialized.
1721          */
1722         if (iommu->irq)
1723                 return 0;
1724
1725         irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1726         if (irq > 0) {
1727                 iommu->irq = irq;
1728         } else {
1729                 pr_err("No free IRQ vectors\n");
1730                 return -EINVAL;
1731         }
1732
1733         ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1734         if (ret)
1735                 pr_err("Can't request irq\n");
1736         return ret;
1737 }
1738
1739 int __init enable_drhd_fault_handling(void)
1740 {
1741         struct dmar_drhd_unit *drhd;
1742         struct intel_iommu *iommu;
1743
1744         /*
1745          * Enable fault control interrupt.
1746          */
1747         for_each_iommu(iommu, drhd) {
1748                 u32 fault_status;
1749                 int ret = dmar_set_interrupt(iommu);
1750
1751                 if (ret) {
1752                         pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1753                                (unsigned long long)drhd->reg_base_addr, ret);
1754                         return -1;
1755                 }
1756
1757                 /*
1758                  * Clear any previous faults.
1759                  */
1760                 dmar_fault(iommu->irq, iommu);
1761                 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1762                 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1763         }
1764
1765         return 0;
1766 }
1767
1768 /*
1769  * Re-enable Queued Invalidation interface.
1770  */
1771 int dmar_reenable_qi(struct intel_iommu *iommu)
1772 {
1773         if (!ecap_qis(iommu->ecap))
1774                 return -ENOENT;
1775
1776         if (!iommu->qi)
1777                 return -ENOENT;
1778
1779         /*
1780          * First disable queued invalidation.
1781          */
1782         dmar_disable_qi(iommu);
1783         /*
1784          * Then enable queued invalidation again. Since there is no pending
1785          * invalidation requests now, it's safe to re-enable queued
1786          * invalidation.
1787          */
1788         __dmar_enable_qi(iommu);
1789
1790         return 0;
1791 }
1792
1793 /*
1794  * Check interrupt remapping support in DMAR table description.
1795  */
1796 int __init dmar_ir_support(void)
1797 {
1798         struct acpi_table_dmar *dmar;
1799         dmar = (struct acpi_table_dmar *)dmar_tbl;
1800         if (!dmar)
1801                 return 0;
1802         return dmar->flags & 0x1;
1803 }
1804
1805 /* Check whether DMAR units are in use */
1806 static inline bool dmar_in_use(void)
1807 {
1808         return irq_remapping_enabled || intel_iommu_enabled;
1809 }
1810
1811 static int __init dmar_free_unused_resources(void)
1812 {
1813         struct dmar_drhd_unit *dmaru, *dmaru_n;
1814
1815         if (dmar_in_use())
1816                 return 0;
1817
1818         if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1819                 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1820
1821         down_write(&dmar_global_lock);
1822         list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1823                 list_del(&dmaru->list);
1824                 dmar_free_drhd(dmaru);
1825         }
1826         up_write(&dmar_global_lock);
1827
1828         return 0;
1829 }
1830
1831 late_initcall(dmar_free_unused_resources);
1832 IOMMU_INIT_POST(detect_intel_iommu);
1833
1834 /*
1835  * DMAR Hotplug Support
1836  * For more details, please refer to Intel(R) Virtualization Technology
1837  * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1838  * "Remapping Hardware Unit Hot Plug".
1839  */
1840 static guid_t dmar_hp_guid =
1841         GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
1842                   0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
1843
1844 /*
1845  * Currently there's only one revision and BIOS will not check the revision id,
1846  * so use 0 for safety.
1847  */
1848 #define DMAR_DSM_REV_ID                 0
1849 #define DMAR_DSM_FUNC_DRHD              1
1850 #define DMAR_DSM_FUNC_ATSR              2
1851 #define DMAR_DSM_FUNC_RHSA              3
1852
1853 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1854 {
1855         return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
1856 }
1857
1858 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1859                                   dmar_res_handler_t handler, void *arg)
1860 {
1861         int ret = -ENODEV;
1862         union acpi_object *obj;
1863         struct acpi_dmar_header *start;
1864         struct dmar_res_callback callback;
1865         static int res_type[] = {
1866                 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1867                 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1868                 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1869         };
1870
1871         if (!dmar_detect_dsm(handle, func))
1872                 return 0;
1873
1874         obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
1875                                       func, NULL, ACPI_TYPE_BUFFER);
1876         if (!obj)
1877                 return -ENODEV;
1878
1879         memset(&callback, 0, sizeof(callback));
1880         callback.cb[res_type[func]] = handler;
1881         callback.arg[res_type[func]] = arg;
1882         start = (struct acpi_dmar_header *)obj->buffer.pointer;
1883         ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1884
1885         ACPI_FREE(obj);
1886
1887         return ret;
1888 }
1889
1890 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
1891 {
1892         int ret;
1893         struct dmar_drhd_unit *dmaru;
1894
1895         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1896         if (!dmaru)
1897                 return -ENODEV;
1898
1899         ret = dmar_ir_hotplug(dmaru, true);
1900         if (ret == 0)
1901                 ret = dmar_iommu_hotplug(dmaru, true);
1902
1903         return ret;
1904 }
1905
1906 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
1907 {
1908         int i, ret;
1909         struct device *dev;
1910         struct dmar_drhd_unit *dmaru;
1911
1912         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1913         if (!dmaru)
1914                 return 0;
1915
1916         /*
1917          * All PCI devices managed by this unit should have been destroyed.
1918          */
1919         if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
1920                 for_each_active_dev_scope(dmaru->devices,
1921                                           dmaru->devices_cnt, i, dev)
1922                         return -EBUSY;
1923         }
1924
1925         ret = dmar_ir_hotplug(dmaru, false);
1926         if (ret == 0)
1927                 ret = dmar_iommu_hotplug(dmaru, false);
1928
1929         return ret;
1930 }
1931
1932 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
1933 {
1934         struct dmar_drhd_unit *dmaru;
1935
1936         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1937         if (dmaru) {
1938                 list_del_rcu(&dmaru->list);
1939                 synchronize_rcu();
1940                 dmar_free_drhd(dmaru);
1941         }
1942
1943         return 0;
1944 }
1945
1946 static int dmar_hotplug_insert(acpi_handle handle)
1947 {
1948         int ret;
1949         int drhd_count = 0;
1950
1951         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1952                                      &dmar_validate_one_drhd, (void *)1);
1953         if (ret)
1954                 goto out;
1955
1956         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1957                                      &dmar_parse_one_drhd, (void *)&drhd_count);
1958         if (ret == 0 && drhd_count == 0) {
1959                 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
1960                 goto out;
1961         } else if (ret) {
1962                 goto release_drhd;
1963         }
1964
1965         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
1966                                      &dmar_parse_one_rhsa, NULL);
1967         if (ret)
1968                 goto release_drhd;
1969
1970         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1971                                      &dmar_parse_one_atsr, NULL);
1972         if (ret)
1973                 goto release_atsr;
1974
1975         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1976                                      &dmar_hp_add_drhd, NULL);
1977         if (!ret)
1978                 return 0;
1979
1980         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1981                                &dmar_hp_remove_drhd, NULL);
1982 release_atsr:
1983         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1984                                &dmar_release_one_atsr, NULL);
1985 release_drhd:
1986         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1987                                &dmar_hp_release_drhd, NULL);
1988 out:
1989         return ret;
1990 }
1991
1992 static int dmar_hotplug_remove(acpi_handle handle)
1993 {
1994         int ret;
1995
1996         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1997                                      &dmar_check_one_atsr, NULL);
1998         if (ret)
1999                 return ret;
2000
2001         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2002                                      &dmar_hp_remove_drhd, NULL);
2003         if (ret == 0) {
2004                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2005                                                &dmar_release_one_atsr, NULL));
2006                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2007                                                &dmar_hp_release_drhd, NULL));
2008         } else {
2009                 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2010                                        &dmar_hp_add_drhd, NULL);
2011         }
2012
2013         return ret;
2014 }
2015
2016 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2017                                        void *context, void **retval)
2018 {
2019         acpi_handle *phdl = retval;
2020
2021         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2022                 *phdl = handle;
2023                 return AE_CTRL_TERMINATE;
2024         }
2025
2026         return AE_OK;
2027 }
2028
2029 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2030 {
2031         int ret;
2032         acpi_handle tmp = NULL;
2033         acpi_status status;
2034
2035         if (!dmar_in_use())
2036                 return 0;
2037
2038         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2039                 tmp = handle;
2040         } else {
2041                 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2042                                              ACPI_UINT32_MAX,
2043                                              dmar_get_dsm_handle,
2044                                              NULL, NULL, &tmp);
2045                 if (ACPI_FAILURE(status)) {
2046                         pr_warn("Failed to locate _DSM method.\n");
2047                         return -ENXIO;
2048                 }
2049         }
2050         if (tmp == NULL)
2051                 return 0;
2052
2053         down_write(&dmar_global_lock);
2054         if (insert)
2055                 ret = dmar_hotplug_insert(tmp);
2056         else
2057                 ret = dmar_hotplug_remove(tmp);
2058         up_write(&dmar_global_lock);
2059
2060         return ret;
2061 }
2062
2063 int dmar_device_add(acpi_handle handle)
2064 {
2065         return dmar_device_hotplug(handle, true);
2066 }
2067
2068 int dmar_device_remove(acpi_handle handle)
2069 {
2070         return dmar_device_hotplug(handle, false);
2071 }