2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
22 * This file implements early detection/parsing of Remapping Devices
23 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
26 * These routines are used by both DMA-remapping and Interrupt-remapping
29 #define pr_fmt(fmt) "DMAR: " fmt
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/iova.h>
34 #include <linux/intel-iommu.h>
35 #include <linux/timer.h>
36 #include <linux/irq.h>
37 #include <linux/interrupt.h>
38 #include <linux/tboot.h>
39 #include <linux/dmi.h>
40 #include <linux/slab.h>
41 #include <linux/iommu.h>
42 #include <linux/limits.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/iommu_table.h>
46 #include "irq_remapping.h"
48 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
49 struct dmar_res_callback {
50 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED];
51 void *arg[ACPI_DMAR_TYPE_RESERVED];
52 bool ignore_unhandled;
58 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
59 * before IO devices managed by that unit.
60 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
61 * after IO devices managed by that unit.
62 * 3) Hotplug events are rare.
64 * Locking rules for DMA and interrupt remapping related global data structures:
65 * 1) Use dmar_global_lock in process context
66 * 2) Use RCU in interrupt context
68 DECLARE_RWSEM(dmar_global_lock);
69 LIST_HEAD(dmar_drhd_units);
71 struct acpi_table_header * __initdata dmar_tbl;
72 static int dmar_dev_scope_status = 1;
73 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
75 static int alloc_iommu(struct dmar_drhd_unit *drhd);
76 static void free_iommu(struct intel_iommu *iommu);
78 extern const struct iommu_ops intel_iommu_ops;
80 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
83 * add INCLUDE_ALL at the tail, so scan the list will find it at
86 if (drhd->include_all)
87 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
89 list_add_rcu(&drhd->list, &dmar_drhd_units);
92 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
94 struct acpi_dmar_device_scope *scope;
99 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
100 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
101 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
103 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
104 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
105 pr_warn("Unsupported device scope\n");
107 start += scope->length;
112 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
115 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
118 struct device *tmp_dev;
120 if (*devices && *cnt) {
121 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
130 /* Optimize out kzalloc()/kfree() for normal cases */
131 static char dmar_pci_notify_info_buf[64];
133 static struct dmar_pci_notify_info *
134 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
139 struct dmar_pci_notify_info *info;
141 BUG_ON(dev->is_virtfn);
144 * Ignore devices that have a domain number higher than what can
145 * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
147 if (pci_domain_nr(dev->bus) > U16_MAX)
150 /* Only generate path[] for device addition event */
151 if (event == BUS_NOTIFY_ADD_DEVICE)
152 for (tmp = dev; tmp; tmp = tmp->bus->self)
155 size = sizeof(*info) + level * sizeof(info->path[0]);
156 if (size <= sizeof(dmar_pci_notify_info_buf)) {
157 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
159 info = kzalloc(size, GFP_KERNEL);
161 pr_warn("Out of memory when allocating notify_info "
162 "for %s.\n", pci_name(dev));
163 if (dmar_dev_scope_status == 0)
164 dmar_dev_scope_status = -ENOMEM;
171 info->seg = pci_domain_nr(dev->bus);
173 if (event == BUS_NOTIFY_ADD_DEVICE) {
174 for (tmp = dev; tmp; tmp = tmp->bus->self) {
176 info->path[level].bus = tmp->bus->number;
177 info->path[level].device = PCI_SLOT(tmp->devfn);
178 info->path[level].function = PCI_FUNC(tmp->devfn);
179 if (pci_is_root_bus(tmp->bus))
180 info->bus = tmp->bus->number;
187 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
189 if ((void *)info != dmar_pci_notify_info_buf)
193 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
194 struct acpi_dmar_pci_path *path, int count)
198 if (info->bus != bus)
200 if (info->level != count)
203 for (i = 0; i < count; i++) {
204 if (path[i].device != info->path[i].device ||
205 path[i].function != info->path[i].function)
217 if (bus == info->path[i].bus &&
218 path[0].device == info->path[i].device &&
219 path[0].function == info->path[i].function) {
220 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
221 bus, path[0].device, path[0].function);
228 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
229 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
230 void *start, void*end, u16 segment,
231 struct dmar_dev_scope *devices,
235 struct device *tmp, *dev = &info->dev->dev;
236 struct acpi_dmar_device_scope *scope;
237 struct acpi_dmar_pci_path *path;
239 if (segment != info->seg)
242 for (; start < end; start += scope->length) {
244 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
245 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
248 path = (struct acpi_dmar_pci_path *)(scope + 1);
249 level = (scope->length - sizeof(*scope)) / sizeof(*path);
250 if (!dmar_match_pci_path(info, scope->bus, path, level))
254 * We expect devices with endpoint scope to have normal PCI
255 * headers, and devices with bridge scope to have bridge PCI
256 * headers. However PCI NTB devices may be listed in the
257 * DMAR table with bridge scope, even though they have a
258 * normal PCI header. NTB devices are identified by class
259 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
260 * for this special case.
262 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
263 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
264 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
265 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
266 info->dev->class >> 8 != PCI_CLASS_BRIDGE_OTHER))) {
267 pr_warn("Device scope type does not match for %s\n",
268 pci_name(info->dev));
272 for_each_dev_scope(devices, devices_cnt, i, tmp)
274 devices[i].bus = info->dev->bus->number;
275 devices[i].devfn = info->dev->devfn;
276 rcu_assign_pointer(devices[i].dev,
280 BUG_ON(i >= devices_cnt);
286 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
287 struct dmar_dev_scope *devices, int count)
292 if (info->seg != segment)
295 for_each_active_dev_scope(devices, count, index, tmp)
296 if (tmp == &info->dev->dev) {
297 RCU_INIT_POINTER(devices[index].dev, NULL);
306 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
309 struct dmar_drhd_unit *dmaru;
310 struct acpi_dmar_hardware_unit *drhd;
312 for_each_drhd_unit(dmaru) {
313 if (dmaru->include_all)
316 drhd = container_of(dmaru->hdr,
317 struct acpi_dmar_hardware_unit, header);
318 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
319 ((void *)drhd) + drhd->header.length,
321 dmaru->devices, dmaru->devices_cnt);
326 ret = dmar_iommu_notify_scope_dev(info);
327 if (ret < 0 && dmar_dev_scope_status == 0)
328 dmar_dev_scope_status = ret;
333 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
335 struct dmar_drhd_unit *dmaru;
337 for_each_drhd_unit(dmaru)
338 if (dmar_remove_dev_scope(info, dmaru->segment,
339 dmaru->devices, dmaru->devices_cnt))
341 dmar_iommu_notify_scope_dev(info);
344 static int dmar_pci_bus_notifier(struct notifier_block *nb,
345 unsigned long action, void *data)
347 struct pci_dev *pdev = to_pci_dev(data);
348 struct dmar_pci_notify_info *info;
350 /* Only care about add/remove events for physical functions.
351 * For VFs we actually do the lookup based on the corresponding
352 * PF in device_to_iommu() anyway. */
355 if (action != BUS_NOTIFY_ADD_DEVICE &&
356 action != BUS_NOTIFY_REMOVED_DEVICE)
359 info = dmar_alloc_pci_notify_info(pdev, action);
363 down_write(&dmar_global_lock);
364 if (action == BUS_NOTIFY_ADD_DEVICE)
365 dmar_pci_bus_add_dev(info);
366 else if (action == BUS_NOTIFY_REMOVED_DEVICE)
367 dmar_pci_bus_del_dev(info);
368 up_write(&dmar_global_lock);
370 dmar_free_pci_notify_info(info);
375 static struct notifier_block dmar_pci_bus_nb = {
376 .notifier_call = dmar_pci_bus_notifier,
380 static struct dmar_drhd_unit *
381 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
383 struct dmar_drhd_unit *dmaru;
385 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list)
386 if (dmaru->segment == drhd->segment &&
387 dmaru->reg_base_addr == drhd->address)
394 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
395 * structure which uniquely represent one DMA remapping hardware unit
396 * present in the platform
398 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
400 struct acpi_dmar_hardware_unit *drhd;
401 struct dmar_drhd_unit *dmaru;
404 drhd = (struct acpi_dmar_hardware_unit *)header;
405 dmaru = dmar_find_dmaru(drhd);
409 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
414 * If header is allocated from slab by ACPI _DSM method, we need to
415 * copy the content because the memory buffer will be freed on return.
417 dmaru->hdr = (void *)(dmaru + 1);
418 memcpy(dmaru->hdr, header, header->length);
419 dmaru->reg_base_addr = drhd->address;
420 dmaru->segment = drhd->segment;
421 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
422 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
423 ((void *)drhd) + drhd->header.length,
424 &dmaru->devices_cnt);
425 if (dmaru->devices_cnt && dmaru->devices == NULL) {
430 ret = alloc_iommu(dmaru);
432 dmar_free_dev_scope(&dmaru->devices,
433 &dmaru->devices_cnt);
437 dmar_register_drhd_unit(dmaru);
446 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
448 if (dmaru->devices && dmaru->devices_cnt)
449 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
451 free_iommu(dmaru->iommu);
455 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
458 struct acpi_dmar_andd *andd = (void *)header;
460 /* Check for NUL termination within the designated length */
461 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
463 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
464 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
465 dmi_get_system_info(DMI_BIOS_VENDOR),
466 dmi_get_system_info(DMI_BIOS_VERSION),
467 dmi_get_system_info(DMI_PRODUCT_VERSION));
468 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
471 pr_info("ANDD device: %x name: %s\n", andd->device_number,
477 #ifdef CONFIG_ACPI_NUMA
478 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
480 struct acpi_dmar_rhsa *rhsa;
481 struct dmar_drhd_unit *drhd;
483 rhsa = (struct acpi_dmar_rhsa *)header;
484 for_each_drhd_unit(drhd) {
485 if (drhd->reg_base_addr == rhsa->base_address) {
486 int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
488 if (!node_online(node))
490 drhd->iommu->node = node;
495 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
496 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
498 dmi_get_system_info(DMI_BIOS_VENDOR),
499 dmi_get_system_info(DMI_BIOS_VERSION),
500 dmi_get_system_info(DMI_PRODUCT_VERSION));
501 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
506 #define dmar_parse_one_rhsa dmar_res_noop
510 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
512 struct acpi_dmar_hardware_unit *drhd;
513 struct acpi_dmar_reserved_memory *rmrr;
514 struct acpi_dmar_atsr *atsr;
515 struct acpi_dmar_rhsa *rhsa;
517 switch (header->type) {
518 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
519 drhd = container_of(header, struct acpi_dmar_hardware_unit,
521 pr_info("DRHD base: %#016Lx flags: %#x\n",
522 (unsigned long long)drhd->address, drhd->flags);
524 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
525 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
527 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
528 (unsigned long long)rmrr->base_address,
529 (unsigned long long)rmrr->end_address);
531 case ACPI_DMAR_TYPE_ROOT_ATS:
532 atsr = container_of(header, struct acpi_dmar_atsr, header);
533 pr_info("ATSR flags: %#x\n", atsr->flags);
535 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
536 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
537 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
538 (unsigned long long)rhsa->base_address,
539 rhsa->proximity_domain);
541 case ACPI_DMAR_TYPE_NAMESPACE:
542 /* We don't print this here because we need to sanity-check
543 it first. So print it in dmar_parse_one_andd() instead. */
549 * dmar_table_detect - checks to see if the platform supports DMAR devices
551 static int __init dmar_table_detect(void)
553 acpi_status status = AE_OK;
555 /* if we could find DMAR table, then there are DMAR devices */
556 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
558 if (ACPI_SUCCESS(status) && !dmar_tbl) {
559 pr_warn("Unable to map DMAR\n");
560 status = AE_NOT_FOUND;
563 return ACPI_SUCCESS(status) ? 0 : -ENOENT;
566 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
567 size_t len, struct dmar_res_callback *cb)
569 struct acpi_dmar_header *iter, *next;
570 struct acpi_dmar_header *end = ((void *)start) + len;
572 for (iter = start; iter < end; iter = next) {
573 next = (void *)iter + iter->length;
574 if (iter->length == 0) {
575 /* Avoid looping forever on bad ACPI tables */
576 pr_debug(FW_BUG "Invalid 0-length structure\n");
578 } else if (next > end) {
579 /* Avoid passing table end */
580 pr_warn(FW_BUG "Record passes table end\n");
585 dmar_table_print_dmar_entry(iter);
587 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
588 /* continue for forward compatibility */
589 pr_debug("Unknown DMAR structure type %d\n",
591 } else if (cb->cb[iter->type]) {
594 ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
597 } else if (!cb->ignore_unhandled) {
598 pr_warn("No handler for DMAR structure type %d\n",
607 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
608 struct dmar_res_callback *cb)
610 return dmar_walk_remapping_entries((void *)(dmar + 1),
611 dmar->header.length - sizeof(*dmar), cb);
615 * parse_dmar_table - parses the DMA reporting table
618 parse_dmar_table(void)
620 struct acpi_table_dmar *dmar;
623 struct dmar_res_callback cb = {
625 .ignore_unhandled = true,
626 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
627 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
628 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
629 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
630 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
631 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
635 * Do it again, earlier dmar_tbl mapping could be mapped with
641 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
642 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
644 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
646 dmar = (struct acpi_table_dmar *)dmar_tbl;
650 if (dmar->width < PAGE_SHIFT - 1) {
651 pr_warn("Invalid DMAR haw\n");
655 pr_info("Host address width %d\n", dmar->width + 1);
656 ret = dmar_walk_dmar_table(dmar, &cb);
657 if (ret == 0 && drhd_count == 0)
658 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
663 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
664 int cnt, struct pci_dev *dev)
670 for_each_active_dev_scope(devices, cnt, index, tmp)
671 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
674 /* Check our parent */
675 dev = dev->bus->self;
681 struct dmar_drhd_unit *
682 dmar_find_matched_drhd_unit(struct pci_dev *dev)
684 struct dmar_drhd_unit *dmaru;
685 struct acpi_dmar_hardware_unit *drhd;
687 dev = pci_physfn(dev);
690 for_each_drhd_unit(dmaru) {
691 drhd = container_of(dmaru->hdr,
692 struct acpi_dmar_hardware_unit,
695 if (dmaru->include_all &&
696 drhd->segment == pci_domain_nr(dev->bus))
699 if (dmar_pci_device_match(dmaru->devices,
700 dmaru->devices_cnt, dev))
710 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
711 struct acpi_device *adev)
713 struct dmar_drhd_unit *dmaru;
714 struct acpi_dmar_hardware_unit *drhd;
715 struct acpi_dmar_device_scope *scope;
718 struct acpi_dmar_pci_path *path;
720 for_each_drhd_unit(dmaru) {
721 drhd = container_of(dmaru->hdr,
722 struct acpi_dmar_hardware_unit,
725 for (scope = (void *)(drhd + 1);
726 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
727 scope = ((void *)scope) + scope->length) {
728 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
730 if (scope->enumeration_id != device_number)
733 path = (void *)(scope + 1);
734 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
735 dev_name(&adev->dev), dmaru->reg_base_addr,
736 scope->bus, path->device, path->function);
737 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
739 dmaru->devices[i].bus = scope->bus;
740 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
742 rcu_assign_pointer(dmaru->devices[i].dev,
743 get_device(&adev->dev));
746 BUG_ON(i >= dmaru->devices_cnt);
749 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
750 device_number, dev_name(&adev->dev));
753 static int __init dmar_acpi_dev_scope_init(void)
755 struct acpi_dmar_andd *andd;
757 if (dmar_tbl == NULL)
760 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
761 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
762 andd = ((void *)andd) + andd->header.length) {
763 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
765 struct acpi_device *adev;
767 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
770 pr_err("Failed to find handle for ACPI object %s\n",
774 if (acpi_bus_get_device(h, &adev)) {
775 pr_err("Failed to get device for ACPI object %s\n",
779 dmar_acpi_insert_dev_scope(andd->device_number, adev);
785 int __init dmar_dev_scope_init(void)
787 struct pci_dev *dev = NULL;
788 struct dmar_pci_notify_info *info;
790 if (dmar_dev_scope_status != 1)
791 return dmar_dev_scope_status;
793 if (list_empty(&dmar_drhd_units)) {
794 dmar_dev_scope_status = -ENODEV;
796 dmar_dev_scope_status = 0;
798 dmar_acpi_dev_scope_init();
800 for_each_pci_dev(dev) {
804 info = dmar_alloc_pci_notify_info(dev,
805 BUS_NOTIFY_ADD_DEVICE);
808 return dmar_dev_scope_status;
810 dmar_pci_bus_add_dev(info);
811 dmar_free_pci_notify_info(info);
815 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
818 return dmar_dev_scope_status;
822 int __init dmar_table_init(void)
824 static int dmar_table_initialized;
827 if (dmar_table_initialized == 0) {
828 ret = parse_dmar_table();
831 pr_info("Parse DMAR table failure.\n");
832 } else if (list_empty(&dmar_drhd_units)) {
833 pr_info("No DMAR devices found\n");
838 dmar_table_initialized = ret;
840 dmar_table_initialized = 1;
843 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
846 static void warn_invalid_dmar(u64 addr, const char *message)
849 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
850 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
852 dmi_get_system_info(DMI_BIOS_VENDOR),
853 dmi_get_system_info(DMI_BIOS_VERSION),
854 dmi_get_system_info(DMI_PRODUCT_VERSION));
855 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
859 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
861 struct acpi_dmar_hardware_unit *drhd;
865 drhd = (void *)entry;
866 if (!drhd->address) {
867 warn_invalid_dmar(0, "");
872 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
874 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
876 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
880 cap = dmar_readq(addr + DMAR_CAP_REG);
881 ecap = dmar_readq(addr + DMAR_ECAP_REG);
886 early_iounmap(addr, VTD_PAGE_SIZE);
888 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
889 warn_invalid_dmar(drhd->address, " returns all ones");
896 int __init detect_intel_iommu(void)
899 struct dmar_res_callback validate_drhd_cb = {
900 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
901 .ignore_unhandled = true,
904 down_write(&dmar_global_lock);
905 ret = dmar_table_detect();
907 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
909 if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) {
911 /* Make sure ACS will be enabled */
917 x86_init.iommu.iommu_init = intel_iommu_init;
921 acpi_put_table(dmar_tbl);
924 up_write(&dmar_global_lock);
926 return ret ? ret : 1;
929 static void unmap_iommu(struct intel_iommu *iommu)
932 release_mem_region(iommu->reg_phys, iommu->reg_size);
936 * map_iommu: map the iommu's registers
937 * @iommu: the iommu to map
938 * @phys_addr: the physical address of the base resgister
940 * Memory map the iommu's registers. Start w/ a single page, and
941 * possibly expand if that turns out to be insufficent.
943 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
947 iommu->reg_phys = phys_addr;
948 iommu->reg_size = VTD_PAGE_SIZE;
950 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
951 pr_err("Can't reserve memory\n");
956 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
958 pr_err("Can't map the region\n");
963 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
964 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
966 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
968 warn_invalid_dmar(phys_addr, " returns all ones");
972 /* the registers might be more than one page */
973 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
974 cap_max_fault_reg_offset(iommu->cap));
975 map_size = VTD_PAGE_ALIGN(map_size);
976 if (map_size > iommu->reg_size) {
978 release_mem_region(iommu->reg_phys, iommu->reg_size);
979 iommu->reg_size = map_size;
980 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
982 pr_err("Can't reserve memory\n");
986 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
988 pr_err("Can't map the region\n");
999 release_mem_region(iommu->reg_phys, iommu->reg_size);
1004 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
1006 iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
1007 DMAR_UNITS_SUPPORTED);
1008 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
1011 set_bit(iommu->seq_id, dmar_seq_ids);
1012 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1015 return iommu->seq_id;
1018 static void dmar_free_seq_id(struct intel_iommu *iommu)
1020 if (iommu->seq_id >= 0) {
1021 clear_bit(iommu->seq_id, dmar_seq_ids);
1026 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1028 struct intel_iommu *iommu;
1034 if (!drhd->reg_base_addr) {
1035 warn_invalid_dmar(0, "");
1039 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1043 if (dmar_alloc_seq_id(iommu) < 0) {
1044 pr_err("Failed to allocate seq_id\n");
1049 err = map_iommu(iommu, drhd->reg_base_addr);
1051 pr_err("Failed to map %s\n", iommu->name);
1052 goto error_free_seq_id;
1056 if (cap_sagaw(iommu->cap) == 0) {
1057 pr_info("%s: No supported address widths. Not attempting DMA translation.\n",
1062 if (!drhd->ignored) {
1063 agaw = iommu_calculate_agaw(iommu);
1065 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1070 if (!drhd->ignored) {
1071 msagaw = iommu_calculate_max_sagaw(iommu);
1073 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1080 iommu->msagaw = msagaw;
1081 iommu->segment = drhd->segment;
1085 ver = readl(iommu->reg + DMAR_VER_REG);
1086 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1088 (unsigned long long)drhd->reg_base_addr,
1089 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1090 (unsigned long long)iommu->cap,
1091 (unsigned long long)iommu->ecap);
1093 /* Reflect status in gcmd */
1094 sts = readl(iommu->reg + DMAR_GSTS_REG);
1095 if (sts & DMA_GSTS_IRES)
1096 iommu->gcmd |= DMA_GCMD_IRE;
1097 if (sts & DMA_GSTS_TES)
1098 iommu->gcmd |= DMA_GCMD_TE;
1099 if (sts & DMA_GSTS_QIES)
1100 iommu->gcmd |= DMA_GCMD_QIE;
1102 raw_spin_lock_init(&iommu->register_lock);
1105 * This is only for hotplug; at boot time intel_iommu_enabled won't
1106 * be set yet. When intel_iommu_init() runs, it registers the units
1107 * present at boot time, then sets intel_iommu_enabled.
1109 if (intel_iommu_enabled && !drhd->ignored) {
1110 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1116 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1118 err = iommu_device_register(&iommu->iommu);
1123 drhd->iommu = iommu;
1129 iommu_device_sysfs_remove(&iommu->iommu);
1133 dmar_free_seq_id(iommu);
1139 static void free_iommu(struct intel_iommu *iommu)
1141 if (intel_iommu_enabled && !iommu->drhd->ignored) {
1142 iommu_device_unregister(&iommu->iommu);
1143 iommu_device_sysfs_remove(&iommu->iommu);
1147 if (iommu->pr_irq) {
1148 free_irq(iommu->pr_irq, iommu);
1149 dmar_free_hwirq(iommu->pr_irq);
1152 free_irq(iommu->irq, iommu);
1153 dmar_free_hwirq(iommu->irq);
1158 free_page((unsigned long)iommu->qi->desc);
1159 kfree(iommu->qi->desc_status);
1166 dmar_free_seq_id(iommu);
1171 * Reclaim all the submitted descriptors which have completed its work.
1173 static inline void reclaim_free_desc(struct q_inval *qi)
1175 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1176 qi->desc_status[qi->free_tail] == QI_ABORT) {
1177 qi->desc_status[qi->free_tail] = QI_FREE;
1178 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1183 static int qi_check_fault(struct intel_iommu *iommu, int index)
1187 struct q_inval *qi = iommu->qi;
1188 int wait_index = (index + 1) % QI_LENGTH;
1190 if (qi->desc_status[wait_index] == QI_ABORT)
1193 fault = readl(iommu->reg + DMAR_FSTS_REG);
1196 * If IQE happens, the head points to the descriptor associated
1197 * with the error. No new descriptors are fetched until the IQE
1200 if (fault & DMA_FSTS_IQE) {
1201 head = readl(iommu->reg + DMAR_IQH_REG);
1202 if ((head >> DMAR_IQ_SHIFT) == index) {
1203 pr_err("VT-d detected invalid descriptor: "
1204 "low=%llx, high=%llx\n",
1205 (unsigned long long)qi->desc[index].low,
1206 (unsigned long long)qi->desc[index].high);
1207 memcpy(&qi->desc[index], &qi->desc[wait_index],
1208 sizeof(struct qi_desc));
1209 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1215 * If ITE happens, all pending wait_desc commands are aborted.
1216 * No new descriptors are fetched until the ITE is cleared.
1218 if (fault & DMA_FSTS_ITE) {
1219 head = readl(iommu->reg + DMAR_IQH_REG);
1220 head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1222 tail = readl(iommu->reg + DMAR_IQT_REG);
1223 tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1225 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1228 if (qi->desc_status[head] == QI_IN_USE)
1229 qi->desc_status[head] = QI_ABORT;
1230 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1231 } while (head != tail);
1233 if (qi->desc_status[wait_index] == QI_ABORT)
1237 if (fault & DMA_FSTS_ICE)
1238 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1244 * Submit the queued invalidation descriptor to the remapping
1245 * hardware unit and wait for its completion.
1247 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1250 struct q_inval *qi = iommu->qi;
1251 struct qi_desc *hw, wait_desc;
1252 int wait_index, index;
1253 unsigned long flags;
1263 raw_spin_lock_irqsave(&qi->q_lock, flags);
1264 while (qi->free_cnt < 3) {
1265 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1267 raw_spin_lock_irqsave(&qi->q_lock, flags);
1270 index = qi->free_head;
1271 wait_index = (index + 1) % QI_LENGTH;
1273 qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1277 wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
1278 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1279 wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
1281 hw[wait_index] = wait_desc;
1283 qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1287 * update the HW tail register indicating the presence of
1290 writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);
1292 while (qi->desc_status[wait_index] != QI_DONE) {
1294 * We will leave the interrupts disabled, to prevent interrupt
1295 * context to queue another cmd while a cmd is already submitted
1296 * and waiting for completion on this cpu. This is to avoid
1297 * a deadlock where the interrupt context can wait indefinitely
1298 * for free slots in the queue.
1300 rc = qi_check_fault(iommu, index);
1304 raw_spin_unlock(&qi->q_lock);
1306 raw_spin_lock(&qi->q_lock);
1309 qi->desc_status[index] = QI_DONE;
1311 reclaim_free_desc(qi);
1312 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1321 * Flush the global interrupt entry cache.
1323 void qi_global_iec(struct intel_iommu *iommu)
1325 struct qi_desc desc;
1327 desc.low = QI_IEC_TYPE;
1330 /* should never fail */
1331 qi_submit_sync(&desc, iommu);
1334 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1337 struct qi_desc desc;
1339 desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1340 | QI_CC_GRAN(type) | QI_CC_TYPE;
1343 qi_submit_sync(&desc, iommu);
1346 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1347 unsigned int size_order, u64 type)
1351 struct qi_desc desc;
1354 if (cap_write_drain(iommu->cap))
1357 if (cap_read_drain(iommu->cap))
1360 desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1361 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1362 desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1363 | QI_IOTLB_AM(size_order);
1365 qi_submit_sync(&desc, iommu);
1368 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1369 u16 qdep, u64 addr, unsigned mask)
1371 struct qi_desc desc;
1374 BUG_ON(addr & ((1ULL << (VTD_PAGE_SHIFT + mask)) - 1));
1375 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1376 desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1378 desc.high = QI_DEV_IOTLB_ADDR(addr);
1380 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1383 desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1384 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1386 qi_submit_sync(&desc, iommu);
1390 * Disable Queued Invalidation interface.
1392 void dmar_disable_qi(struct intel_iommu *iommu)
1394 unsigned long flags;
1396 cycles_t start_time = get_cycles();
1398 if (!ecap_qis(iommu->ecap))
1401 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1403 sts = readl(iommu->reg + DMAR_GSTS_REG);
1404 if (!(sts & DMA_GSTS_QIES))
1408 * Give a chance to HW to complete the pending invalidation requests.
1410 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1411 readl(iommu->reg + DMAR_IQH_REG)) &&
1412 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1415 iommu->gcmd &= ~DMA_GCMD_QIE;
1416 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1418 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1419 !(sts & DMA_GSTS_QIES), sts);
1421 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1425 * Enable queued invalidation.
1427 static void __dmar_enable_qi(struct intel_iommu *iommu)
1430 unsigned long flags;
1431 struct q_inval *qi = iommu->qi;
1433 qi->free_head = qi->free_tail = 0;
1434 qi->free_cnt = QI_LENGTH;
1436 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1438 /* write zero to the tail reg */
1439 writel(0, iommu->reg + DMAR_IQT_REG);
1441 dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
1443 iommu->gcmd |= DMA_GCMD_QIE;
1444 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1446 /* Make sure hardware complete it */
1447 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1449 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1453 * Enable Queued Invalidation interface. This is a must to support
1454 * interrupt-remapping. Also used by DMA-remapping, which replaces
1455 * register based IOTLB invalidation.
1457 int dmar_enable_qi(struct intel_iommu *iommu)
1460 struct page *desc_page;
1462 if (!ecap_qis(iommu->ecap))
1466 * queued invalidation is already setup and enabled.
1471 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1478 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);
1485 qi->desc = page_address(desc_page);
1487 qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
1488 if (!qi->desc_status) {
1489 free_page((unsigned long) qi->desc);
1495 raw_spin_lock_init(&qi->q_lock);
1497 __dmar_enable_qi(iommu);
1502 /* iommu interrupt handling. Most stuff are MSI-like. */
1510 static const char *dma_remap_fault_reasons[] =
1513 "Present bit in root entry is clear",
1514 "Present bit in context entry is clear",
1515 "Invalid context entry",
1516 "Access beyond MGAW",
1517 "PTE Write access is not set",
1518 "PTE Read access is not set",
1519 "Next page table ptr is invalid",
1520 "Root table address invalid",
1521 "Context table ptr is invalid",
1522 "non-zero reserved fields in RTP",
1523 "non-zero reserved fields in CTP",
1524 "non-zero reserved fields in PTE",
1525 "PCE for translation request specifies blocking",
1528 static const char *irq_remap_fault_reasons[] =
1530 "Detected reserved fields in the decoded interrupt-remapped request",
1531 "Interrupt index exceeded the interrupt-remapping table size",
1532 "Present field in the IRTE entry is clear",
1533 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1534 "Detected reserved fields in the IRTE entry",
1535 "Blocked a compatibility format interrupt request",
1536 "Blocked an interrupt request due to source-id verification failure",
1539 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1541 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1542 ARRAY_SIZE(irq_remap_fault_reasons))) {
1543 *fault_type = INTR_REMAP;
1544 return irq_remap_fault_reasons[fault_reason - 0x20];
1545 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1546 *fault_type = DMA_REMAP;
1547 return dma_remap_fault_reasons[fault_reason];
1549 *fault_type = UNKNOWN;
1555 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1557 if (iommu->irq == irq)
1558 return DMAR_FECTL_REG;
1559 else if (iommu->pr_irq == irq)
1560 return DMAR_PECTL_REG;
1565 void dmar_msi_unmask(struct irq_data *data)
1567 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1568 int reg = dmar_msi_reg(iommu, data->irq);
1572 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1573 writel(0, iommu->reg + reg);
1574 /* Read a reg to force flush the post write */
1575 readl(iommu->reg + reg);
1576 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1579 void dmar_msi_mask(struct irq_data *data)
1581 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1582 int reg = dmar_msi_reg(iommu, data->irq);
1586 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1587 writel(DMA_FECTL_IM, iommu->reg + reg);
1588 /* Read a reg to force flush the post write */
1589 readl(iommu->reg + reg);
1590 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1593 void dmar_msi_write(int irq, struct msi_msg *msg)
1595 struct intel_iommu *iommu = irq_get_handler_data(irq);
1596 int reg = dmar_msi_reg(iommu, irq);
1599 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1600 writel(msg->data, iommu->reg + reg + 4);
1601 writel(msg->address_lo, iommu->reg + reg + 8);
1602 writel(msg->address_hi, iommu->reg + reg + 12);
1603 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1606 void dmar_msi_read(int irq, struct msi_msg *msg)
1608 struct intel_iommu *iommu = irq_get_handler_data(irq);
1609 int reg = dmar_msi_reg(iommu, irq);
1612 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1613 msg->data = readl(iommu->reg + reg + 4);
1614 msg->address_lo = readl(iommu->reg + reg + 8);
1615 msg->address_hi = readl(iommu->reg + reg + 12);
1616 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1619 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1620 u8 fault_reason, u16 source_id, unsigned long long addr)
1625 reason = dmar_get_fault_reason(fault_reason, &fault_type);
1627 if (fault_type == INTR_REMAP)
1628 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1629 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1630 PCI_FUNC(source_id & 0xFF), addr >> 48,
1631 fault_reason, reason);
1633 pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n",
1634 type ? "DMA Read" : "DMA Write",
1635 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1636 PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
1640 #define PRIMARY_FAULT_REG_LEN (16)
1641 irqreturn_t dmar_fault(int irq, void *dev_id)
1643 struct intel_iommu *iommu = dev_id;
1644 int reg, fault_index;
1648 static DEFINE_RATELIMIT_STATE(rs,
1649 DEFAULT_RATELIMIT_INTERVAL,
1650 DEFAULT_RATELIMIT_BURST);
1652 /* Disable printing, simply clear the fault when ratelimited */
1653 ratelimited = !__ratelimit(&rs);
1655 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1656 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1657 if (fault_status && !ratelimited)
1658 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1660 /* TBD: ignore advanced fault log currently */
1661 if (!(fault_status & DMA_FSTS_PPF))
1664 fault_index = dma_fsts_fault_record_index(fault_status);
1665 reg = cap_fault_reg_offset(iommu->cap);
1673 /* highest 32 bits */
1674 data = readl(iommu->reg + reg +
1675 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1676 if (!(data & DMA_FRCD_F))
1680 fault_reason = dma_frcd_fault_reason(data);
1681 type = dma_frcd_type(data);
1683 data = readl(iommu->reg + reg +
1684 fault_index * PRIMARY_FAULT_REG_LEN + 8);
1685 source_id = dma_frcd_source_id(data);
1687 guest_addr = dmar_readq(iommu->reg + reg +
1688 fault_index * PRIMARY_FAULT_REG_LEN);
1689 guest_addr = dma_frcd_page_addr(guest_addr);
1692 /* clear the fault */
1693 writel(DMA_FRCD_F, iommu->reg + reg +
1694 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1696 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1699 dmar_fault_do_one(iommu, type, fault_reason,
1700 source_id, guest_addr);
1703 if (fault_index >= cap_num_fault_regs(iommu->cap))
1705 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1708 writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG);
1711 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1715 int dmar_set_interrupt(struct intel_iommu *iommu)
1720 * Check if the fault interrupt is already initialized.
1725 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1729 pr_err("No free IRQ vectors\n");
1733 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1735 pr_err("Can't request irq\n");
1739 int __init enable_drhd_fault_handling(void)
1741 struct dmar_drhd_unit *drhd;
1742 struct intel_iommu *iommu;
1745 * Enable fault control interrupt.
1747 for_each_iommu(iommu, drhd) {
1749 int ret = dmar_set_interrupt(iommu);
1752 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1753 (unsigned long long)drhd->reg_base_addr, ret);
1758 * Clear any previous faults.
1760 dmar_fault(iommu->irq, iommu);
1761 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1762 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1769 * Re-enable Queued Invalidation interface.
1771 int dmar_reenable_qi(struct intel_iommu *iommu)
1773 if (!ecap_qis(iommu->ecap))
1780 * First disable queued invalidation.
1782 dmar_disable_qi(iommu);
1784 * Then enable queued invalidation again. Since there is no pending
1785 * invalidation requests now, it's safe to re-enable queued
1788 __dmar_enable_qi(iommu);
1794 * Check interrupt remapping support in DMAR table description.
1796 int __init dmar_ir_support(void)
1798 struct acpi_table_dmar *dmar;
1799 dmar = (struct acpi_table_dmar *)dmar_tbl;
1802 return dmar->flags & 0x1;
1805 /* Check whether DMAR units are in use */
1806 static inline bool dmar_in_use(void)
1808 return irq_remapping_enabled || intel_iommu_enabled;
1811 static int __init dmar_free_unused_resources(void)
1813 struct dmar_drhd_unit *dmaru, *dmaru_n;
1818 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1819 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1821 down_write(&dmar_global_lock);
1822 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1823 list_del(&dmaru->list);
1824 dmar_free_drhd(dmaru);
1826 up_write(&dmar_global_lock);
1831 late_initcall(dmar_free_unused_resources);
1832 IOMMU_INIT_POST(detect_intel_iommu);
1835 * DMAR Hotplug Support
1836 * For more details, please refer to Intel(R) Virtualization Technology
1837 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1838 * "Remapping Hardware Unit Hot Plug".
1840 static guid_t dmar_hp_guid =
1841 GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
1842 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
1845 * Currently there's only one revision and BIOS will not check the revision id,
1846 * so use 0 for safety.
1848 #define DMAR_DSM_REV_ID 0
1849 #define DMAR_DSM_FUNC_DRHD 1
1850 #define DMAR_DSM_FUNC_ATSR 2
1851 #define DMAR_DSM_FUNC_RHSA 3
1853 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1855 return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
1858 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1859 dmar_res_handler_t handler, void *arg)
1862 union acpi_object *obj;
1863 struct acpi_dmar_header *start;
1864 struct dmar_res_callback callback;
1865 static int res_type[] = {
1866 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1867 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1868 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1871 if (!dmar_detect_dsm(handle, func))
1874 obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
1875 func, NULL, ACPI_TYPE_BUFFER);
1879 memset(&callback, 0, sizeof(callback));
1880 callback.cb[res_type[func]] = handler;
1881 callback.arg[res_type[func]] = arg;
1882 start = (struct acpi_dmar_header *)obj->buffer.pointer;
1883 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1890 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
1893 struct dmar_drhd_unit *dmaru;
1895 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1899 ret = dmar_ir_hotplug(dmaru, true);
1901 ret = dmar_iommu_hotplug(dmaru, true);
1906 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
1910 struct dmar_drhd_unit *dmaru;
1912 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1917 * All PCI devices managed by this unit should have been destroyed.
1919 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
1920 for_each_active_dev_scope(dmaru->devices,
1921 dmaru->devices_cnt, i, dev)
1925 ret = dmar_ir_hotplug(dmaru, false);
1927 ret = dmar_iommu_hotplug(dmaru, false);
1932 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
1934 struct dmar_drhd_unit *dmaru;
1936 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1938 list_del_rcu(&dmaru->list);
1940 dmar_free_drhd(dmaru);
1946 static int dmar_hotplug_insert(acpi_handle handle)
1951 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1952 &dmar_validate_one_drhd, (void *)1);
1956 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1957 &dmar_parse_one_drhd, (void *)&drhd_count);
1958 if (ret == 0 && drhd_count == 0) {
1959 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
1965 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
1966 &dmar_parse_one_rhsa, NULL);
1970 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1971 &dmar_parse_one_atsr, NULL);
1975 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1976 &dmar_hp_add_drhd, NULL);
1980 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1981 &dmar_hp_remove_drhd, NULL);
1983 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1984 &dmar_release_one_atsr, NULL);
1986 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1987 &dmar_hp_release_drhd, NULL);
1992 static int dmar_hotplug_remove(acpi_handle handle)
1996 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1997 &dmar_check_one_atsr, NULL);
2001 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2002 &dmar_hp_remove_drhd, NULL);
2004 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2005 &dmar_release_one_atsr, NULL));
2006 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2007 &dmar_hp_release_drhd, NULL));
2009 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2010 &dmar_hp_add_drhd, NULL);
2016 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2017 void *context, void **retval)
2019 acpi_handle *phdl = retval;
2021 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2023 return AE_CTRL_TERMINATE;
2029 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2032 acpi_handle tmp = NULL;
2038 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2041 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2043 dmar_get_dsm_handle,
2045 if (ACPI_FAILURE(status)) {
2046 pr_warn("Failed to locate _DSM method.\n");
2053 down_write(&dmar_global_lock);
2055 ret = dmar_hotplug_insert(tmp);
2057 ret = dmar_hotplug_remove(tmp);
2058 up_write(&dmar_global_lock);
2063 int dmar_device_add(acpi_handle handle)
2065 return dmar_device_hotplug(handle, true);
2068 int dmar_device_remove(acpi_handle handle)
2070 return dmar_device_hotplug(handle, false);