2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/iommu.h>
30 #include <asm/pci-direct.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 #include <asm/io_apic.h>
36 #include <asm/irq_remapping.h>
38 #include "amd_iommu_proto.h"
39 #include "amd_iommu_types.h"
40 #include "irq_remapping.h"
43 * definitions for the ACPI scanning code
45 #define IVRS_HEADER_LENGTH 48
47 #define ACPI_IVHD_TYPE 0x10
48 #define ACPI_IVMD_TYPE_ALL 0x20
49 #define ACPI_IVMD_TYPE 0x21
50 #define ACPI_IVMD_TYPE_RANGE 0x22
52 #define IVHD_DEV_ALL 0x01
53 #define IVHD_DEV_SELECT 0x02
54 #define IVHD_DEV_SELECT_RANGE_START 0x03
55 #define IVHD_DEV_RANGE_END 0x04
56 #define IVHD_DEV_ALIAS 0x42
57 #define IVHD_DEV_ALIAS_RANGE 0x43
58 #define IVHD_DEV_EXT_SELECT 0x46
59 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
60 #define IVHD_DEV_SPECIAL 0x48
62 #define IVHD_SPECIAL_IOAPIC 1
63 #define IVHD_SPECIAL_HPET 2
65 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
67 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68 #define IVHD_FLAG_ISOC_EN_MASK 0x08
70 #define IVMD_FLAG_EXCL_RANGE 0x08
71 #define IVMD_FLAG_UNITY_MAP 0x01
73 #define ACPI_DEVFLAG_INITPASS 0x01
74 #define ACPI_DEVFLAG_EXTINT 0x02
75 #define ACPI_DEVFLAG_NMI 0x04
76 #define ACPI_DEVFLAG_SYSMGT1 0x10
77 #define ACPI_DEVFLAG_SYSMGT2 0x20
78 #define ACPI_DEVFLAG_LINT0 0x40
79 #define ACPI_DEVFLAG_LINT1 0x80
80 #define ACPI_DEVFLAG_ATSDIS 0x10000000
83 * ACPI table definitions
85 * These data structures are laid over the table to parse the important values
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
103 } __attribute__((packed));
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
114 } __attribute__((packed));
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
129 } __attribute__((packed));
132 bool amd_iommu_irq_remap __read_mostly;
134 static bool amd_iommu_detected;
135 static bool __initdata amd_iommu_disabled;
137 u16 amd_iommu_last_bdf; /* largest PCI device id we have
139 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
141 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
143 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
146 /* Array to assign indices to IOMMUs*/
147 struct amd_iommu *amd_iommus[MAX_IOMMUS];
148 int amd_iommus_present;
150 /* IOMMUs have a non-present cache? */
151 bool amd_iommu_np_cache __read_mostly;
152 bool amd_iommu_iotlb_sup __read_mostly = true;
154 u32 amd_iommu_max_pasid __read_mostly = ~0;
156 bool amd_iommu_v2_present __read_mostly;
157 static bool amd_iommu_pc_present __read_mostly;
159 bool amd_iommu_force_isolation __read_mostly;
162 * List of protection domains - used during resume
164 LIST_HEAD(amd_iommu_pd_list);
165 spinlock_t amd_iommu_pd_lock;
168 * Pointer to the device table which is shared by all AMD IOMMUs
169 * it is indexed by the PCI device id or the HT unit id and contains
170 * information about the domain the device belongs to as well as the
171 * page table root pointer.
173 struct dev_table_entry *amd_iommu_dev_table;
176 * The alias table is a driver specific data structure which contains the
177 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
178 * More than one device can share the same requestor id.
180 u16 *amd_iommu_alias_table;
183 * The rlookup table is used to find the IOMMU which is responsible
184 * for a specific device. It is also indexed by the PCI device id.
186 struct amd_iommu **amd_iommu_rlookup_table;
189 * This table is used to find the irq remapping table for a given device id
192 struct irq_remap_table **irq_lookup_table;
195 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
196 * to know which ones are already in use.
198 unsigned long *amd_iommu_pd_alloc_bitmap;
200 static u32 dev_table_size; /* size of the device table */
201 static u32 alias_table_size; /* size of the alias table */
202 static u32 rlookup_table_size; /* size if the rlookup table */
204 enum iommu_init_state {
217 /* Early ioapic and hpet maps from kernel command line */
218 #define EARLY_MAP_SIZE 4
219 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
220 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
221 static int __initdata early_ioapic_map_size;
222 static int __initdata early_hpet_map_size;
223 static bool __initdata cmdline_maps;
225 static enum iommu_init_state init_state = IOMMU_START_STATE;
227 static int amd_iommu_enable_interrupts(void);
228 static int __init iommu_go_to_state(enum iommu_init_state state);
229 static void init_device_table_dma(void);
231 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
232 u8 bank, u8 cntr, u8 fxn,
233 u64 *value, bool is_write);
235 static inline void update_last_devid(u16 devid)
237 if (devid > amd_iommu_last_bdf)
238 amd_iommu_last_bdf = devid;
241 static inline unsigned long tbl_size(int entry_size)
243 unsigned shift = PAGE_SHIFT +
244 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
249 /* Access to l1 and l2 indexed register spaces */
251 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
255 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
256 pci_read_config_dword(iommu->dev, 0xfc, &val);
260 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
262 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
263 pci_write_config_dword(iommu->dev, 0xfc, val);
264 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
267 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
271 pci_write_config_dword(iommu->dev, 0xf0, address);
272 pci_read_config_dword(iommu->dev, 0xf4, &val);
276 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
278 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
279 pci_write_config_dword(iommu->dev, 0xf4, val);
282 /****************************************************************************
284 * AMD IOMMU MMIO register space handling functions
286 * These functions are used to program the IOMMU device registers in
287 * MMIO space required for that driver.
289 ****************************************************************************/
292 * This function set the exclusion range in the IOMMU. DMA accesses to the
293 * exclusion range are passed through untranslated
295 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
297 u64 start = iommu->exclusion_start & PAGE_MASK;
298 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
301 if (!iommu->exclusion_start)
304 entry = start | MMIO_EXCL_ENABLE_MASK;
305 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
306 &entry, sizeof(entry));
309 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
310 &entry, sizeof(entry));
313 /* Programs the physical address of the device table into the IOMMU hardware */
314 static void iommu_set_device_table(struct amd_iommu *iommu)
318 BUG_ON(iommu->mmio_base == NULL);
320 entry = virt_to_phys(amd_iommu_dev_table);
321 entry |= (dev_table_size >> 12) - 1;
322 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
323 &entry, sizeof(entry));
326 /* Generic functions to enable/disable certain features of the IOMMU. */
327 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
331 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
333 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
336 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
340 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
342 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
345 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
349 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
350 ctrl &= ~CTRL_INV_TO_MASK;
351 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
352 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
355 /* Function to enable the hardware */
356 static void iommu_enable(struct amd_iommu *iommu)
358 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
361 static void iommu_disable(struct amd_iommu *iommu)
363 if (!iommu->mmio_base)
366 /* Disable command buffer */
367 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
369 /* Disable event logging and event interrupts */
370 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
371 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
373 /* Disable IOMMU hardware itself */
374 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
378 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
379 * the system has one.
381 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
383 if (!request_mem_region(address, end, "amd_iommu")) {
384 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
386 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
390 return (u8 __iomem *)ioremap_nocache(address, end);
393 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
395 if (iommu->mmio_base)
396 iounmap(iommu->mmio_base);
397 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
400 /****************************************************************************
402 * The functions below belong to the first pass of AMD IOMMU ACPI table
403 * parsing. In this pass we try to find out the highest device id this
404 * code has to handle. Upon this information the size of the shared data
405 * structures is determined later.
407 ****************************************************************************/
410 * This function calculates the length of a given IVHD entry
412 static inline int ivhd_entry_length(u8 *ivhd)
414 return 0x04 << (*ivhd >> 6);
418 * After reading the highest device id from the IOMMU PCI capability header
419 * this function looks if there is a higher device id defined in the ACPI table
421 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
423 u8 *p = (void *)h, *end = (void *)h;
424 struct ivhd_entry *dev;
430 dev = (struct ivhd_entry *)p;
433 /* Use maximum BDF value for DEV_ALL */
434 update_last_devid(0xffff);
436 case IVHD_DEV_SELECT:
437 case IVHD_DEV_RANGE_END:
439 case IVHD_DEV_EXT_SELECT:
440 /* all the above subfield types refer to device ids */
441 update_last_devid(dev->devid);
446 p += ivhd_entry_length(p);
455 * Iterate over all IVHD entries in the ACPI table and find the highest device
456 * id which we need to handle. This is the first of three functions which parse
457 * the ACPI table. So we check the checksum here.
459 static int __init find_last_devid_acpi(struct acpi_table_header *table)
462 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
463 struct ivhd_header *h;
466 * Validate checksum here so we don't need to do it when
467 * we actually parse the table
469 for (i = 0; i < table->length; ++i)
472 /* ACPI table corrupt */
475 p += IVRS_HEADER_LENGTH;
477 end += table->length;
479 h = (struct ivhd_header *)p;
482 find_last_devid_from_ivhd(h);
494 /****************************************************************************
496 * The following functions belong to the code path which parses the ACPI table
497 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
498 * data structures, initialize the device/alias/rlookup table and also
499 * basically initialize the hardware.
501 ****************************************************************************/
504 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
505 * write commands to that buffer later and the IOMMU will execute them
508 static int __init alloc_command_buffer(struct amd_iommu *iommu)
510 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
511 get_order(CMD_BUFFER_SIZE));
513 return iommu->cmd_buf ? 0 : -ENOMEM;
517 * This function resets the command buffer if the IOMMU stopped fetching
520 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
522 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
524 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
525 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
527 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
531 * This function writes the command buffer address to the hardware and
534 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
538 BUG_ON(iommu->cmd_buf == NULL);
540 entry = (u64)virt_to_phys(iommu->cmd_buf);
541 entry |= MMIO_CMD_SIZE_512;
543 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
544 &entry, sizeof(entry));
546 amd_iommu_reset_cmd_buffer(iommu);
549 static void __init free_command_buffer(struct amd_iommu *iommu)
551 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
554 /* allocates the memory where the IOMMU will log its events to */
555 static int __init alloc_event_buffer(struct amd_iommu *iommu)
557 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
558 get_order(EVT_BUFFER_SIZE));
560 return iommu->evt_buf ? 0 : -ENOMEM;
563 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
567 BUG_ON(iommu->evt_buf == NULL);
569 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
571 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
572 &entry, sizeof(entry));
574 /* set head and tail to zero manually */
575 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
576 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
578 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
581 static void __init free_event_buffer(struct amd_iommu *iommu)
583 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
586 /* allocates the memory where the IOMMU will log its events to */
587 static int __init alloc_ppr_log(struct amd_iommu *iommu)
589 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
590 get_order(PPR_LOG_SIZE));
592 return iommu->ppr_log ? 0 : -ENOMEM;
595 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
599 if (iommu->ppr_log == NULL)
602 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
604 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
605 &entry, sizeof(entry));
607 /* set head and tail to zero manually */
608 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
609 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
611 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
612 iommu_feature_enable(iommu, CONTROL_PPR_EN);
615 static void __init free_ppr_log(struct amd_iommu *iommu)
617 if (iommu->ppr_log == NULL)
620 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
623 static void iommu_enable_gt(struct amd_iommu *iommu)
625 if (!iommu_feature(iommu, FEATURE_GT))
628 iommu_feature_enable(iommu, CONTROL_GT_EN);
631 /* sets a specific bit in the device table entry. */
632 static void set_dev_entry_bit(u16 devid, u8 bit)
634 int i = (bit >> 6) & 0x03;
635 int _bit = bit & 0x3f;
637 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
640 static int get_dev_entry_bit(u16 devid, u8 bit)
642 int i = (bit >> 6) & 0x03;
643 int _bit = bit & 0x3f;
645 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
649 void amd_iommu_apply_erratum_63(u16 devid)
653 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
654 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
657 set_dev_entry_bit(devid, DEV_ENTRY_IW);
660 /* Writes the specific IOMMU for a device into the rlookup table */
661 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
663 amd_iommu_rlookup_table[devid] = iommu;
667 * This function takes the device specific flags read from the ACPI
668 * table and sets up the device table entry with that information
670 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
671 u16 devid, u32 flags, u32 ext_flags)
673 if (flags & ACPI_DEVFLAG_INITPASS)
674 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
675 if (flags & ACPI_DEVFLAG_EXTINT)
676 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
677 if (flags & ACPI_DEVFLAG_NMI)
678 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
679 if (flags & ACPI_DEVFLAG_SYSMGT1)
680 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
681 if (flags & ACPI_DEVFLAG_SYSMGT2)
682 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
683 if (flags & ACPI_DEVFLAG_LINT0)
684 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
685 if (flags & ACPI_DEVFLAG_LINT1)
686 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
688 amd_iommu_apply_erratum_63(devid);
690 set_iommu_for_device(iommu, devid);
693 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
695 struct devid_map *entry;
696 struct list_head *list;
698 if (type == IVHD_SPECIAL_IOAPIC)
700 else if (type == IVHD_SPECIAL_HPET)
705 list_for_each_entry(entry, list, list) {
706 if (!(entry->id == id && entry->cmd_line))
709 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
710 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
712 *devid = entry->devid;
717 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
722 entry->devid = *devid;
723 entry->cmd_line = cmd_line;
725 list_add_tail(&entry->list, list);
730 static int __init add_early_maps(void)
734 for (i = 0; i < early_ioapic_map_size; ++i) {
735 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
736 early_ioapic_map[i].id,
737 &early_ioapic_map[i].devid,
738 early_ioapic_map[i].cmd_line);
743 for (i = 0; i < early_hpet_map_size; ++i) {
744 ret = add_special_device(IVHD_SPECIAL_HPET,
745 early_hpet_map[i].id,
746 &early_hpet_map[i].devid,
747 early_hpet_map[i].cmd_line);
756 * Reads the device exclusion range from ACPI and initializes the IOMMU with
759 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
761 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
763 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
768 * We only can configure exclusion ranges per IOMMU, not
769 * per device. But we can enable the exclusion range per
770 * device. This is done here
772 set_dev_entry_bit(devid, DEV_ENTRY_EX);
773 iommu->exclusion_start = m->range_start;
774 iommu->exclusion_length = m->range_length;
779 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
780 * initializes the hardware and our data structures with it.
782 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
783 struct ivhd_header *h)
786 u8 *end = p, flags = 0;
787 u16 devid = 0, devid_start = 0, devid_to = 0;
788 u32 dev_i, ext_flags = 0;
790 struct ivhd_entry *e;
794 ret = add_early_maps();
799 * First save the recommended feature enable bits from ACPI
801 iommu->acpi_flags = h->flags;
804 * Done. Now parse the device entries
806 p += sizeof(struct ivhd_header);
811 e = (struct ivhd_entry *)p;
815 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
817 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
818 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
820 case IVHD_DEV_SELECT:
822 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
824 PCI_BUS_NUM(e->devid),
830 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
832 case IVHD_DEV_SELECT_RANGE_START:
834 DUMP_printk(" DEV_SELECT_RANGE_START\t "
835 "devid: %02x:%02x.%x flags: %02x\n",
836 PCI_BUS_NUM(e->devid),
841 devid_start = e->devid;
848 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
849 "flags: %02x devid_to: %02x:%02x.%x\n",
850 PCI_BUS_NUM(e->devid),
854 PCI_BUS_NUM(e->ext >> 8),
855 PCI_SLOT(e->ext >> 8),
856 PCI_FUNC(e->ext >> 8));
859 devid_to = e->ext >> 8;
860 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
861 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
862 amd_iommu_alias_table[devid] = devid_to;
864 case IVHD_DEV_ALIAS_RANGE:
866 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
867 "devid: %02x:%02x.%x flags: %02x "
868 "devid_to: %02x:%02x.%x\n",
869 PCI_BUS_NUM(e->devid),
873 PCI_BUS_NUM(e->ext >> 8),
874 PCI_SLOT(e->ext >> 8),
875 PCI_FUNC(e->ext >> 8));
877 devid_start = e->devid;
879 devid_to = e->ext >> 8;
883 case IVHD_DEV_EXT_SELECT:
885 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
886 "flags: %02x ext: %08x\n",
887 PCI_BUS_NUM(e->devid),
893 set_dev_entry_from_acpi(iommu, devid, e->flags,
896 case IVHD_DEV_EXT_SELECT_RANGE:
898 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
899 "%02x:%02x.%x flags: %02x ext: %08x\n",
900 PCI_BUS_NUM(e->devid),
905 devid_start = e->devid;
910 case IVHD_DEV_RANGE_END:
912 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
913 PCI_BUS_NUM(e->devid),
918 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
920 amd_iommu_alias_table[dev_i] = devid_to;
921 set_dev_entry_from_acpi(iommu,
922 devid_to, flags, ext_flags);
924 set_dev_entry_from_acpi(iommu, dev_i,
928 case IVHD_DEV_SPECIAL: {
934 handle = e->ext & 0xff;
935 devid = (e->ext >> 8) & 0xffff;
936 type = (e->ext >> 24) & 0xff;
938 if (type == IVHD_SPECIAL_IOAPIC)
940 else if (type == IVHD_SPECIAL_HPET)
945 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
951 ret = add_special_device(type, handle, &devid, false);
956 * add_special_device might update the devid in case a
957 * command-line override is present. So call
958 * set_dev_entry_from_acpi after add_special_device.
960 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
968 p += ivhd_entry_length(p);
974 static void __init free_iommu_one(struct amd_iommu *iommu)
976 free_command_buffer(iommu);
977 free_event_buffer(iommu);
979 iommu_unmap_mmio_space(iommu);
982 static void __init free_iommu_all(void)
984 struct amd_iommu *iommu, *next;
986 for_each_iommu_safe(iommu, next) {
987 list_del(&iommu->list);
988 free_iommu_one(iommu);
994 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
996 * BIOS should disable L2B micellaneous clock gating by setting
997 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
999 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1003 if ((boot_cpu_data.x86 != 0x15) ||
1004 (boot_cpu_data.x86_model < 0x10) ||
1005 (boot_cpu_data.x86_model > 0x1f))
1008 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1009 pci_read_config_dword(iommu->dev, 0xf4, &value);
1014 /* Select NB indirect register 0x90 and enable writing */
1015 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1017 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1018 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1019 dev_name(&iommu->dev->dev));
1021 /* Clear the enable writing bit */
1022 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1026 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1028 * BIOS should enable ATS write permission check by setting
1029 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1031 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1035 if ((boot_cpu_data.x86 != 0x15) ||
1036 (boot_cpu_data.x86_model < 0x30) ||
1037 (boot_cpu_data.x86_model > 0x3f))
1040 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1041 value = iommu_read_l2(iommu, 0x47);
1046 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1047 iommu_write_l2(iommu, 0x47, value | BIT(0));
1049 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1050 dev_name(&iommu->dev->dev));
1054 * This function clues the initialization function for one IOMMU
1055 * together and also allocates the command buffer and programs the
1056 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1058 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1062 spin_lock_init(&iommu->lock);
1064 /* Add IOMMU to internal data structures */
1065 list_add_tail(&iommu->list, &amd_iommu_list);
1066 iommu->index = amd_iommus_present++;
1068 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1069 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1073 /* Index is fine - add IOMMU to the array */
1074 amd_iommus[iommu->index] = iommu;
1077 * Copy data from ACPI table entry to the iommu struct
1079 iommu->devid = h->devid;
1080 iommu->cap_ptr = h->cap_ptr;
1081 iommu->pci_seg = h->pci_seg;
1082 iommu->mmio_phys = h->mmio_phys;
1084 /* Check if IVHD EFR contains proper max banks/counters */
1085 if ((h->efr != 0) &&
1086 ((h->efr & (0xF << 13)) != 0) &&
1087 ((h->efr & (0x3F << 17)) != 0)) {
1088 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1090 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1093 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1094 iommu->mmio_phys_end);
1095 if (!iommu->mmio_base)
1098 if (alloc_command_buffer(iommu))
1101 if (alloc_event_buffer(iommu))
1104 iommu->int_enabled = false;
1106 ret = init_iommu_from_acpi(iommu, h);
1110 ret = amd_iommu_create_irq_domain(iommu);
1115 * Make sure IOMMU is not considered to translate itself. The IVRS
1116 * table tells us so, but this is a lie!
1118 amd_iommu_rlookup_table[iommu->devid] = NULL;
1124 * Iterates over all IOMMU entries in the ACPI table, allocates the
1125 * IOMMU structure and initializes it with init_iommu_one()
1127 static int __init init_iommu_all(struct acpi_table_header *table)
1129 u8 *p = (u8 *)table, *end = (u8 *)table;
1130 struct ivhd_header *h;
1131 struct amd_iommu *iommu;
1134 end += table->length;
1135 p += IVRS_HEADER_LENGTH;
1138 h = (struct ivhd_header *)p;
1140 case ACPI_IVHD_TYPE:
1142 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1143 "seg: %d flags: %01x info %04x\n",
1144 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1145 PCI_FUNC(h->devid), h->cap_ptr,
1146 h->pci_seg, h->flags, h->info);
1147 DUMP_printk(" mmio-addr: %016llx\n",
1150 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1154 ret = init_iommu_one(iommu, h);
1170 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1172 u64 val = 0xabcd, val2 = 0;
1174 if (!iommu_feature(iommu, FEATURE_PC))
1177 amd_iommu_pc_present = true;
1179 /* Check if the performance counters can be written to */
1180 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1181 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
1183 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1184 amd_iommu_pc_present = false;
1188 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1190 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1191 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1192 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1195 static ssize_t amd_iommu_show_cap(struct device *dev,
1196 struct device_attribute *attr,
1199 struct amd_iommu *iommu = dev_get_drvdata(dev);
1200 return sprintf(buf, "%x\n", iommu->cap);
1202 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1204 static ssize_t amd_iommu_show_features(struct device *dev,
1205 struct device_attribute *attr,
1208 struct amd_iommu *iommu = dev_get_drvdata(dev);
1209 return sprintf(buf, "%llx\n", iommu->features);
1211 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1213 static struct attribute *amd_iommu_attrs[] = {
1215 &dev_attr_features.attr,
1219 static struct attribute_group amd_iommu_group = {
1220 .name = "amd-iommu",
1221 .attrs = amd_iommu_attrs,
1224 static const struct attribute_group *amd_iommu_groups[] = {
1229 static int __init iommu_init_pci(struct amd_iommu *iommu)
1231 int cap_ptr = iommu->cap_ptr;
1232 u32 range, misc, low, high;
1234 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1235 iommu->devid & 0xff);
1239 /* Prevent binding other PCI device drivers to IOMMU devices */
1240 iommu->dev->match_driver = false;
1242 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1244 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1246 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1249 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1250 amd_iommu_iotlb_sup = false;
1252 /* read extended feature bits */
1253 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1254 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1256 iommu->features = ((u64)high << 32) | low;
1258 if (iommu_feature(iommu, FEATURE_GT)) {
1263 pasmax = iommu->features & FEATURE_PASID_MASK;
1264 pasmax >>= FEATURE_PASID_SHIFT;
1265 max_pasid = (1 << (pasmax + 1)) - 1;
1267 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1269 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1271 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1272 glxval >>= FEATURE_GLXVAL_SHIFT;
1274 if (amd_iommu_max_glx_val == -1)
1275 amd_iommu_max_glx_val = glxval;
1277 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1280 if (iommu_feature(iommu, FEATURE_GT) &&
1281 iommu_feature(iommu, FEATURE_PPR)) {
1282 iommu->is_iommu_v2 = true;
1283 amd_iommu_v2_present = true;
1286 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1289 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1290 amd_iommu_np_cache = true;
1292 init_iommu_perf_ctr(iommu);
1294 if (is_rd890_iommu(iommu->dev)) {
1297 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1301 * Some rd890 systems may not be fully reconfigured by the
1302 * BIOS, so it's necessary for us to store this information so
1303 * it can be reprogrammed on resume
1305 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1306 &iommu->stored_addr_lo);
1307 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1308 &iommu->stored_addr_hi);
1310 /* Low bit locks writes to configuration space */
1311 iommu->stored_addr_lo &= ~1;
1313 for (i = 0; i < 6; i++)
1314 for (j = 0; j < 0x12; j++)
1315 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1317 for (i = 0; i < 0x83; i++)
1318 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1321 amd_iommu_erratum_746_workaround(iommu);
1322 amd_iommu_ats_write_check_workaround(iommu);
1324 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1325 amd_iommu_groups, "ivhd%d",
1328 return pci_enable_device(iommu->dev);
1331 static void print_iommu_info(void)
1333 static const char * const feat_str[] = {
1334 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1335 "IA", "GA", "HE", "PC"
1337 struct amd_iommu *iommu;
1339 for_each_iommu(iommu) {
1342 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1343 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1345 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1346 pr_info("AMD-Vi: Extended features: ");
1347 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1348 if (iommu_feature(iommu, (1ULL << i)))
1349 pr_cont(" %s", feat_str[i]);
1354 if (irq_remapping_enabled)
1355 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1358 static int __init amd_iommu_init_pci(void)
1360 struct amd_iommu *iommu;
1363 for_each_iommu(iommu) {
1364 ret = iommu_init_pci(iommu);
1370 * Order is important here to make sure any unity map requirements are
1371 * fulfilled. The unity mappings are created and written to the device
1372 * table during the amd_iommu_init_api() call.
1374 * After that we call init_device_table_dma() to make sure any
1375 * uninitialized DTE will block DMA, and in the end we flush the caches
1376 * of all IOMMUs to make sure the changes to the device table are
1379 ret = amd_iommu_init_api();
1381 init_device_table_dma();
1383 for_each_iommu(iommu)
1384 iommu_flush_all_caches(iommu);
1392 /****************************************************************************
1394 * The following functions initialize the MSI interrupts for all IOMMUs
1395 * in the system. It's a bit challenging because there could be multiple
1396 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1399 ****************************************************************************/
1401 static int iommu_setup_msi(struct amd_iommu *iommu)
1405 r = pci_enable_msi(iommu->dev);
1409 r = request_threaded_irq(iommu->dev->irq,
1410 amd_iommu_int_handler,
1411 amd_iommu_int_thread,
1416 pci_disable_msi(iommu->dev);
1420 iommu->int_enabled = true;
1425 static int iommu_init_msi(struct amd_iommu *iommu)
1429 if (iommu->int_enabled)
1432 if (iommu->dev->msi_cap)
1433 ret = iommu_setup_msi(iommu);
1441 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1443 if (iommu->ppr_log != NULL)
1444 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1449 /****************************************************************************
1451 * The next functions belong to the third pass of parsing the ACPI
1452 * table. In this last pass the memory mapping requirements are
1453 * gathered (like exclusion and unity mapping ranges).
1455 ****************************************************************************/
1457 static void __init free_unity_maps(void)
1459 struct unity_map_entry *entry, *next;
1461 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1462 list_del(&entry->list);
1467 /* called when we find an exclusion range definition in ACPI */
1468 static int __init init_exclusion_range(struct ivmd_header *m)
1473 case ACPI_IVMD_TYPE:
1474 set_device_exclusion_range(m->devid, m);
1476 case ACPI_IVMD_TYPE_ALL:
1477 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1478 set_device_exclusion_range(i, m);
1480 case ACPI_IVMD_TYPE_RANGE:
1481 for (i = m->devid; i <= m->aux; ++i)
1482 set_device_exclusion_range(i, m);
1491 /* called for unity map ACPI definition */
1492 static int __init init_unity_map_range(struct ivmd_header *m)
1494 struct unity_map_entry *e = NULL;
1497 e = kzalloc(sizeof(*e), GFP_KERNEL);
1505 case ACPI_IVMD_TYPE:
1506 s = "IVMD_TYPEi\t\t\t";
1507 e->devid_start = e->devid_end = m->devid;
1509 case ACPI_IVMD_TYPE_ALL:
1510 s = "IVMD_TYPE_ALL\t\t";
1512 e->devid_end = amd_iommu_last_bdf;
1514 case ACPI_IVMD_TYPE_RANGE:
1515 s = "IVMD_TYPE_RANGE\t\t";
1516 e->devid_start = m->devid;
1517 e->devid_end = m->aux;
1520 e->address_start = PAGE_ALIGN(m->range_start);
1521 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1522 e->prot = m->flags >> 1;
1524 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1525 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1526 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1527 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1528 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1529 e->address_start, e->address_end, m->flags);
1531 list_add_tail(&e->list, &amd_iommu_unity_map);
1536 /* iterates over all memory definitions we find in the ACPI table */
1537 static int __init init_memory_definitions(struct acpi_table_header *table)
1539 u8 *p = (u8 *)table, *end = (u8 *)table;
1540 struct ivmd_header *m;
1542 end += table->length;
1543 p += IVRS_HEADER_LENGTH;
1546 m = (struct ivmd_header *)p;
1547 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1548 init_exclusion_range(m);
1549 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1550 init_unity_map_range(m);
1559 * Init the device table to not allow DMA access for devices and
1560 * suppress all page faults
1562 static void init_device_table_dma(void)
1566 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1567 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1568 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1572 static void __init uninit_device_table_dma(void)
1576 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1577 amd_iommu_dev_table[devid].data[0] = 0ULL;
1578 amd_iommu_dev_table[devid].data[1] = 0ULL;
1582 static void init_device_table(void)
1586 if (!amd_iommu_irq_remap)
1589 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1590 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1593 static void iommu_init_flags(struct amd_iommu *iommu)
1595 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1596 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1597 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1599 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1600 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1601 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1603 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1604 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1605 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1607 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1608 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1609 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1612 * make IOMMU memory accesses cache coherent
1614 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1616 /* Set IOTLB invalidation timeout to 1s */
1617 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1620 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1623 u32 ioc_feature_control;
1624 struct pci_dev *pdev = iommu->root_pdev;
1626 /* RD890 BIOSes may not have completely reconfigured the iommu */
1627 if (!is_rd890_iommu(iommu->dev) || !pdev)
1631 * First, we need to ensure that the iommu is enabled. This is
1632 * controlled by a register in the northbridge
1635 /* Select Northbridge indirect register 0x75 and enable writing */
1636 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1637 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1639 /* Enable the iommu */
1640 if (!(ioc_feature_control & 0x1))
1641 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1643 /* Restore the iommu BAR */
1644 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1645 iommu->stored_addr_lo);
1646 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1647 iommu->stored_addr_hi);
1649 /* Restore the l1 indirect regs for each of the 6 l1s */
1650 for (i = 0; i < 6; i++)
1651 for (j = 0; j < 0x12; j++)
1652 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1654 /* Restore the l2 indirect regs */
1655 for (i = 0; i < 0x83; i++)
1656 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1658 /* Lock PCI setup registers */
1659 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1660 iommu->stored_addr_lo | 1);
1664 * This function finally enables all IOMMUs found in the system after
1665 * they have been initialized
1667 static void early_enable_iommus(void)
1669 struct amd_iommu *iommu;
1671 for_each_iommu(iommu) {
1672 iommu_disable(iommu);
1673 iommu_init_flags(iommu);
1674 iommu_set_device_table(iommu);
1675 iommu_enable_command_buffer(iommu);
1676 iommu_enable_event_buffer(iommu);
1677 iommu_set_exclusion_range(iommu);
1678 iommu_enable(iommu);
1679 iommu_flush_all_caches(iommu);
1683 static void enable_iommus_v2(void)
1685 struct amd_iommu *iommu;
1687 for_each_iommu(iommu) {
1688 iommu_enable_ppr_log(iommu);
1689 iommu_enable_gt(iommu);
1693 static void enable_iommus(void)
1695 early_enable_iommus();
1700 static void disable_iommus(void)
1702 struct amd_iommu *iommu;
1704 for_each_iommu(iommu)
1705 iommu_disable(iommu);
1709 * Suspend/Resume support
1710 * disable suspend until real resume implemented
1713 static void amd_iommu_resume(void)
1715 struct amd_iommu *iommu;
1717 for_each_iommu(iommu)
1718 iommu_apply_resume_quirks(iommu);
1720 /* re-load the hardware */
1723 amd_iommu_enable_interrupts();
1726 static int amd_iommu_suspend(void)
1728 /* disable IOMMUs to go out of the way for BIOS */
1734 static struct syscore_ops amd_iommu_syscore_ops = {
1735 .suspend = amd_iommu_suspend,
1736 .resume = amd_iommu_resume,
1739 static void __init free_on_init_error(void)
1741 free_pages((unsigned long)irq_lookup_table,
1742 get_order(rlookup_table_size));
1744 kmem_cache_destroy(amd_iommu_irq_cache);
1745 amd_iommu_irq_cache = NULL;
1747 free_pages((unsigned long)amd_iommu_rlookup_table,
1748 get_order(rlookup_table_size));
1750 free_pages((unsigned long)amd_iommu_alias_table,
1751 get_order(alias_table_size));
1753 free_pages((unsigned long)amd_iommu_dev_table,
1754 get_order(dev_table_size));
1758 #ifdef CONFIG_GART_IOMMU
1760 * We failed to initialize the AMD IOMMU - try fallback to GART
1768 /* SB IOAPIC is always on this device in AMD systems */
1769 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1771 static bool __init check_ioapic_information(void)
1773 const char *fw_bug = FW_BUG;
1774 bool ret, has_sb_ioapic;
1777 has_sb_ioapic = false;
1781 * If we have map overrides on the kernel command line the
1782 * messages in this function might not describe firmware bugs
1783 * anymore - so be careful
1788 for (idx = 0; idx < nr_ioapics; idx++) {
1789 int devid, id = mpc_ioapic_id(idx);
1791 devid = get_ioapic_devid(id);
1793 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1796 } else if (devid == IOAPIC_SB_DEVID) {
1797 has_sb_ioapic = true;
1802 if (!has_sb_ioapic) {
1804 * We expect the SB IOAPIC to be listed in the IVRS
1805 * table. The system timer is connected to the SB IOAPIC
1806 * and if we don't have it in the list the system will
1807 * panic at boot time. This situation usually happens
1808 * when the BIOS is buggy and provides us the wrong
1809 * device id for the IOAPIC in the system.
1811 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
1815 pr_err("AMD-Vi: Disabling interrupt remapping\n");
1820 static void __init free_dma_resources(void)
1822 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1823 get_order(MAX_DOMAIN_ID/8));
1829 * This is the hardware init function for AMD IOMMU in the system.
1830 * This function is called either from amd_iommu_init or from the interrupt
1831 * remapping setup code.
1833 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1836 * 1 pass) Find the highest PCI device id the driver has to handle.
1837 * Upon this information the size of the data structures is
1838 * determined that needs to be allocated.
1840 * 2 pass) Initialize the data structures just allocated with the
1841 * information in the ACPI table about available AMD IOMMUs
1842 * in the system. It also maps the PCI devices in the
1843 * system to specific IOMMUs
1845 * 3 pass) After the basic data structures are allocated and
1846 * initialized we update them with information about memory
1847 * remapping requirements parsed out of the ACPI table in
1850 * After everything is set up the IOMMUs are enabled and the necessary
1851 * hotplug and suspend notifiers are registered.
1853 static int __init early_amd_iommu_init(void)
1855 struct acpi_table_header *ivrs_base;
1856 acpi_size ivrs_size;
1860 if (!amd_iommu_detected)
1863 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1864 if (status == AE_NOT_FOUND)
1866 else if (ACPI_FAILURE(status)) {
1867 const char *err = acpi_format_exception(status);
1868 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1873 * First parse ACPI tables to find the largest Bus/Dev/Func
1874 * we need to handle. Upon this information the shared data
1875 * structures for the IOMMUs in the system will be allocated
1877 ret = find_last_devid_acpi(ivrs_base);
1881 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1882 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1883 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1885 /* Device table - directly used by all IOMMUs */
1887 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1888 get_order(dev_table_size));
1889 if (amd_iommu_dev_table == NULL)
1893 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1894 * IOMMU see for that device
1896 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1897 get_order(alias_table_size));
1898 if (amd_iommu_alias_table == NULL)
1901 /* IOMMU rlookup table - find the IOMMU for a specific device */
1902 amd_iommu_rlookup_table = (void *)__get_free_pages(
1903 GFP_KERNEL | __GFP_ZERO,
1904 get_order(rlookup_table_size));
1905 if (amd_iommu_rlookup_table == NULL)
1908 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1909 GFP_KERNEL | __GFP_ZERO,
1910 get_order(MAX_DOMAIN_ID/8));
1911 if (amd_iommu_pd_alloc_bitmap == NULL)
1915 * let all alias entries point to itself
1917 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1918 amd_iommu_alias_table[i] = i;
1921 * never allocate domain 0 because its used as the non-allocated and
1922 * error value placeholder
1924 amd_iommu_pd_alloc_bitmap[0] = 1;
1926 spin_lock_init(&amd_iommu_pd_lock);
1929 * now the data structures are allocated and basically initialized
1930 * start the real acpi table scan
1932 ret = init_iommu_all(ivrs_base);
1936 if (amd_iommu_irq_remap)
1937 amd_iommu_irq_remap = check_ioapic_information();
1939 if (amd_iommu_irq_remap) {
1941 * Interrupt remapping enabled, create kmem_cache for the
1945 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1946 MAX_IRQS_PER_TABLE * sizeof(u32),
1947 IRQ_TABLE_ALIGNMENT,
1949 if (!amd_iommu_irq_cache)
1952 irq_lookup_table = (void *)__get_free_pages(
1953 GFP_KERNEL | __GFP_ZERO,
1954 get_order(rlookup_table_size));
1955 if (!irq_lookup_table)
1959 ret = init_memory_definitions(ivrs_base);
1963 /* init the device table */
1964 init_device_table();
1967 /* Don't leak any ACPI memory */
1968 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1974 static int amd_iommu_enable_interrupts(void)
1976 struct amd_iommu *iommu;
1979 for_each_iommu(iommu) {
1980 ret = iommu_init_msi(iommu);
1989 static bool detect_ivrs(void)
1991 struct acpi_table_header *ivrs_base;
1992 acpi_size ivrs_size;
1995 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1996 if (status == AE_NOT_FOUND)
1998 else if (ACPI_FAILURE(status)) {
1999 const char *err = acpi_format_exception(status);
2000 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2004 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2006 /* Make sure ACS will be enabled during PCI probe */
2012 /****************************************************************************
2014 * AMD IOMMU Initialization State Machine
2016 ****************************************************************************/
2018 static int __init state_next(void)
2022 switch (init_state) {
2023 case IOMMU_START_STATE:
2024 if (!detect_ivrs()) {
2025 init_state = IOMMU_NOT_FOUND;
2028 init_state = IOMMU_IVRS_DETECTED;
2031 case IOMMU_IVRS_DETECTED:
2032 ret = early_amd_iommu_init();
2033 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2035 case IOMMU_ACPI_FINISHED:
2036 early_enable_iommus();
2037 register_syscore_ops(&amd_iommu_syscore_ops);
2038 x86_platform.iommu_shutdown = disable_iommus;
2039 init_state = IOMMU_ENABLED;
2042 ret = amd_iommu_init_pci();
2043 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2046 case IOMMU_PCI_INIT:
2047 ret = amd_iommu_enable_interrupts();
2048 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2050 case IOMMU_INTERRUPTS_EN:
2051 ret = amd_iommu_init_dma_ops();
2052 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2055 init_state = IOMMU_INITIALIZED;
2057 case IOMMU_INITIALIZED:
2060 case IOMMU_NOT_FOUND:
2061 case IOMMU_INIT_ERROR:
2062 /* Error states => do nothing */
2073 static int __init iommu_go_to_state(enum iommu_init_state state)
2077 while (init_state != state) {
2079 if (init_state == IOMMU_NOT_FOUND ||
2080 init_state == IOMMU_INIT_ERROR)
2087 #ifdef CONFIG_IRQ_REMAP
2088 int __init amd_iommu_prepare(void)
2092 amd_iommu_irq_remap = true;
2094 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2097 return amd_iommu_irq_remap ? 0 : -ENODEV;
2100 int __init amd_iommu_enable(void)
2104 ret = iommu_go_to_state(IOMMU_ENABLED);
2108 irq_remapping_enabled = 1;
2113 void amd_iommu_disable(void)
2115 amd_iommu_suspend();
2118 int amd_iommu_reenable(int mode)
2125 int __init amd_iommu_enable_faulting(void)
2127 /* We enable MSI later when PCI is initialized */
2133 * This is the core init function for AMD IOMMU hardware in the system.
2134 * This function is called from the generic x86 DMA layer initialization
2137 static int __init amd_iommu_init(void)
2141 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2143 free_dma_resources();
2144 if (!irq_remapping_enabled) {
2146 free_on_init_error();
2148 struct amd_iommu *iommu;
2150 uninit_device_table_dma();
2151 for_each_iommu(iommu)
2152 iommu_flush_all_caches(iommu);
2159 /****************************************************************************
2161 * Early detect code. This code runs at IOMMU detection time in the DMA
2162 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2165 ****************************************************************************/
2166 int __init amd_iommu_detect(void)
2170 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2173 if (amd_iommu_disabled)
2176 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2180 amd_iommu_detected = true;
2182 x86_init.iommu.iommu_init = amd_iommu_init;
2187 /****************************************************************************
2189 * Parsing functions for the AMD IOMMU specific kernel command line
2192 ****************************************************************************/
2194 static int __init parse_amd_iommu_dump(char *str)
2196 amd_iommu_dump = true;
2201 static int __init parse_amd_iommu_options(char *str)
2203 for (; *str; ++str) {
2204 if (strncmp(str, "fullflush", 9) == 0)
2205 amd_iommu_unmap_flush = true;
2206 if (strncmp(str, "off", 3) == 0)
2207 amd_iommu_disabled = true;
2208 if (strncmp(str, "force_isolation", 15) == 0)
2209 amd_iommu_force_isolation = true;
2215 static int __init parse_ivrs_ioapic(char *str)
2217 unsigned int bus, dev, fn;
2221 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2224 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2228 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2229 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2234 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2236 cmdline_maps = true;
2237 i = early_ioapic_map_size++;
2238 early_ioapic_map[i].id = id;
2239 early_ioapic_map[i].devid = devid;
2240 early_ioapic_map[i].cmd_line = true;
2245 static int __init parse_ivrs_hpet(char *str)
2247 unsigned int bus, dev, fn;
2251 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2254 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2258 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2259 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2264 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2266 cmdline_maps = true;
2267 i = early_hpet_map_size++;
2268 early_hpet_map[i].id = id;
2269 early_hpet_map[i].devid = devid;
2270 early_hpet_map[i].cmd_line = true;
2275 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2276 __setup("amd_iommu=", parse_amd_iommu_options);
2277 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2278 __setup("ivrs_hpet", parse_ivrs_hpet);
2280 IOMMU_INIT_FINISH(amd_iommu_detect,
2281 gart_iommu_hole_init,
2285 bool amd_iommu_v2_supported(void)
2287 return amd_iommu_v2_present;
2289 EXPORT_SYMBOL(amd_iommu_v2_supported);
2291 /****************************************************************************
2293 * IOMMU EFR Performance Counter support functionality. This code allows
2294 * access to the IOMMU PC functionality.
2296 ****************************************************************************/
2298 u8 amd_iommu_pc_get_max_banks(u16 devid)
2300 struct amd_iommu *iommu;
2303 /* locate the iommu governing the devid */
2304 iommu = amd_iommu_rlookup_table[devid];
2306 ret = iommu->max_banks;
2310 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2312 bool amd_iommu_pc_supported(void)
2314 return amd_iommu_pc_present;
2316 EXPORT_SYMBOL(amd_iommu_pc_supported);
2318 u8 amd_iommu_pc_get_max_counters(u16 devid)
2320 struct amd_iommu *iommu;
2323 /* locate the iommu governing the devid */
2324 iommu = amd_iommu_rlookup_table[devid];
2326 ret = iommu->max_counters;
2330 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2332 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2333 u8 bank, u8 cntr, u8 fxn,
2334 u64 *value, bool is_write)
2339 /* Check for valid iommu and pc register indexing */
2340 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
2343 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2345 /* Limit the offset to the hw defined mmio region aperture */
2346 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2347 (iommu->max_counters << 8) | 0x28);
2348 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2349 (offset > max_offset_lim))
2353 writel((u32)*value, iommu->mmio_base + offset);
2354 writel((*value >> 32), iommu->mmio_base + offset + 4);
2356 *value = readl(iommu->mmio_base + offset + 4);
2358 *value = readl(iommu->mmio_base + offset);
2363 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
2365 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2366 u64 *value, bool is_write)
2368 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2370 /* Make sure the IOMMU PC resource is available */
2371 if (!amd_iommu_pc_present || iommu == NULL)
2374 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,