2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
58 #define AMD_IOMMU_MAPPING_ERROR 0
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
62 #define LOOP_TIMEOUT 100000
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
90 LIST_HEAD(ioapic_map);
92 LIST_HEAD(acpihid_map);
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
98 const struct iommu_ops amd_iommu_ops;
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
103 static const struct dma_map_ops amd_iommu_dma_ops;
106 * general struct to manage commands send to an IOMMU
112 struct kmem_cache *amd_iommu_irq_cache;
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
120 * Data container for a dma_ops specific protection domain
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
127 struct iova_domain iovad;
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
133 /****************************************************************************
137 ****************************************************************************/
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
142 struct acpi_device *adev = ACPI_COMPANION(dev);
143 const char *hid, *uid;
148 hid = acpi_device_hid(adev);
149 uid = acpi_device_uid(adev);
155 return strcmp(hid, entry->hid);
158 return strcmp(hid, entry->hid);
160 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
163 static inline u16 get_pci_device_id(struct device *dev)
165 struct pci_dev *pdev = to_pci_dev(dev);
167 return PCI_DEVID(pdev->bus->number, pdev->devfn);
170 static inline int get_acpihid_device_id(struct device *dev,
171 struct acpihid_map_entry **entry)
173 struct acpihid_map_entry *p;
175 list_for_each_entry(p, &acpihid_map, list) {
176 if (!match_hid_uid(dev, p)) {
185 static inline int get_device_id(struct device *dev)
190 devid = get_pci_device_id(dev);
192 devid = get_acpihid_device_id(dev, NULL);
197 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
199 return container_of(dom, struct protection_domain, domain);
202 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
204 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
205 return container_of(domain, struct dma_ops_domain, domain);
208 static struct iommu_dev_data *alloc_dev_data(u16 devid)
210 struct iommu_dev_data *dev_data;
212 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
216 dev_data->devid = devid;
217 ratelimit_default_init(&dev_data->rs);
219 llist_add(&dev_data->dev_data_list, &dev_data_list);
223 static struct iommu_dev_data *search_dev_data(u16 devid)
225 struct iommu_dev_data *dev_data;
226 struct llist_node *node;
228 if (llist_empty(&dev_data_list))
231 node = dev_data_list.first;
232 llist_for_each_entry(dev_data, node, dev_data_list) {
233 if (dev_data->devid == devid)
240 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
242 *(u16 *)data = alias;
246 static u16 get_alias(struct device *dev)
248 struct pci_dev *pdev = to_pci_dev(dev);
249 u16 devid, ivrs_alias, pci_alias;
251 /* The callers make sure that get_device_id() does not fail here */
252 devid = get_device_id(dev);
254 /* For ACPI HID devices, we simply return the devid as such */
255 if (!dev_is_pci(dev))
258 ivrs_alias = amd_iommu_alias_table[devid];
260 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
262 if (ivrs_alias == pci_alias)
268 * The IVRS is fairly reliable in telling us about aliases, but it
269 * can't know about every screwy device. If we don't have an IVRS
270 * reported alias, use the PCI reported alias. In that case we may
271 * still need to initialize the rlookup and dev_table entries if the
272 * alias is to a non-existent device.
274 if (ivrs_alias == devid) {
275 if (!amd_iommu_rlookup_table[pci_alias]) {
276 amd_iommu_rlookup_table[pci_alias] =
277 amd_iommu_rlookup_table[devid];
278 memcpy(amd_iommu_dev_table[pci_alias].data,
279 amd_iommu_dev_table[devid].data,
280 sizeof(amd_iommu_dev_table[pci_alias].data));
286 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
287 "for device %s[%04x:%04x], kernel reported alias "
288 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
289 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
290 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
291 PCI_FUNC(pci_alias));
294 * If we don't have a PCI DMA alias and the IVRS alias is on the same
295 * bus, then the IVRS table may know about a quirk that we don't.
297 if (pci_alias == devid &&
298 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
299 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
300 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
301 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
308 static struct iommu_dev_data *find_dev_data(u16 devid)
310 struct iommu_dev_data *dev_data;
311 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
313 dev_data = search_dev_data(devid);
315 if (dev_data == NULL) {
316 dev_data = alloc_dev_data(devid);
320 if (translation_pre_enabled(iommu))
321 dev_data->defer_attach = true;
327 struct iommu_dev_data *get_dev_data(struct device *dev)
329 return dev->archdata.iommu;
331 EXPORT_SYMBOL(get_dev_data);
334 * Find or create an IOMMU group for a acpihid device.
336 static struct iommu_group *acpihid_device_group(struct device *dev)
338 struct acpihid_map_entry *p, *entry = NULL;
341 devid = get_acpihid_device_id(dev, &entry);
343 return ERR_PTR(devid);
345 list_for_each_entry(p, &acpihid_map, list) {
346 if ((devid == p->devid) && p->group)
347 entry->group = p->group;
351 entry->group = generic_device_group(dev);
353 iommu_group_ref_get(entry->group);
358 static bool pci_iommuv2_capable(struct pci_dev *pdev)
360 static const int caps[] = {
363 PCI_EXT_CAP_ID_PASID,
367 if (pci_ats_disabled())
370 for (i = 0; i < 3; ++i) {
371 pos = pci_find_ext_capability(pdev, caps[i]);
379 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
381 struct iommu_dev_data *dev_data;
383 dev_data = get_dev_data(&pdev->dev);
385 return dev_data->errata & (1 << erratum) ? true : false;
389 * This function checks if the driver got a valid device from the caller to
390 * avoid dereferencing invalid pointers.
392 static bool check_device(struct device *dev)
396 if (!dev || !dev->dma_mask)
399 devid = get_device_id(dev);
403 /* Out of our scope? */
404 if (devid > amd_iommu_last_bdf)
407 if (amd_iommu_rlookup_table[devid] == NULL)
413 static void init_iommu_group(struct device *dev)
415 struct iommu_group *group;
417 group = iommu_group_get_for_dev(dev);
421 iommu_group_put(group);
424 static int iommu_init_device(struct device *dev)
426 struct iommu_dev_data *dev_data;
427 struct amd_iommu *iommu;
430 if (dev->archdata.iommu)
433 devid = get_device_id(dev);
437 iommu = amd_iommu_rlookup_table[devid];
439 dev_data = find_dev_data(devid);
443 dev_data->alias = get_alias(dev);
446 * By default we use passthrough mode for IOMMUv2 capable device.
447 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
448 * invalid address), we ignore the capability for the device so
449 * it'll be forced to go into translation mode.
451 if ((iommu_pass_through || !amd_iommu_force_isolation) &&
452 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
453 struct amd_iommu *iommu;
455 iommu = amd_iommu_rlookup_table[dev_data->devid];
456 dev_data->iommu_v2 = iommu->is_iommu_v2;
459 dev->archdata.iommu = dev_data;
461 iommu_device_link(&iommu->iommu, dev);
466 static void iommu_ignore_device(struct device *dev)
471 devid = get_device_id(dev);
475 alias = get_alias(dev);
477 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
478 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
480 amd_iommu_rlookup_table[devid] = NULL;
481 amd_iommu_rlookup_table[alias] = NULL;
484 static void iommu_uninit_device(struct device *dev)
486 struct iommu_dev_data *dev_data;
487 struct amd_iommu *iommu;
490 devid = get_device_id(dev);
494 iommu = amd_iommu_rlookup_table[devid];
496 dev_data = search_dev_data(devid);
500 if (dev_data->domain)
503 iommu_device_unlink(&iommu->iommu, dev);
505 iommu_group_remove_device(dev);
511 * We keep dev_data around for unplugged devices and reuse it when the
512 * device is re-plugged - not doing so would introduce a ton of races.
516 /****************************************************************************
518 * Interrupt handling functions
520 ****************************************************************************/
522 static void dump_dte_entry(u16 devid)
526 for (i = 0; i < 4; ++i)
527 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
528 amd_iommu_dev_table[devid].data[i]);
531 static void dump_command(unsigned long phys_addr)
533 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
536 for (i = 0; i < 4; ++i)
537 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
540 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
541 u64 address, int flags)
543 struct iommu_dev_data *dev_data = NULL;
544 struct pci_dev *pdev;
546 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
549 dev_data = get_dev_data(&pdev->dev);
551 if (dev_data && __ratelimit(&dev_data->rs)) {
552 dev_err(&pdev->dev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
553 domain_id, address, flags);
554 } else if (printk_ratelimit()) {
555 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
556 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
557 domain_id, address, flags);
564 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
566 struct device *dev = iommu->iommu.dev;
567 int type, devid, pasid, flags, tag;
568 volatile u32 *event = __evt;
573 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
574 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
575 pasid = PPR_PASID(*(u64 *)&event[0]);
576 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
577 address = (u64)(((u64)event[3]) << 32) | event[2];
580 /* Did we hit the erratum? */
581 if (++count == LOOP_TIMEOUT) {
582 pr_err("AMD-Vi: No event written to event log\n");
589 if (type == EVENT_TYPE_IO_FAULT) {
590 amd_iommu_report_page_fault(devid, pasid, address, flags);
595 case EVENT_TYPE_ILL_DEV:
596 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
599 dump_dte_entry(devid);
601 case EVENT_TYPE_DEV_TAB_ERR:
602 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
603 "address=0x%016llx flags=0x%04x]\n",
604 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
607 case EVENT_TYPE_PAGE_TAB_ERR:
608 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
609 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
610 pasid, address, flags);
612 case EVENT_TYPE_ILL_CMD:
613 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
614 dump_command(address);
616 case EVENT_TYPE_CMD_HARD_ERR:
617 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
620 case EVENT_TYPE_IOTLB_INV_TO:
621 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
622 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
625 case EVENT_TYPE_INV_DEV_REQ:
626 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 pasid, address, flags);
630 case EVENT_TYPE_INV_PPR_REQ:
631 pasid = ((event[0] >> 16) & 0xFFFF)
632 | ((event[1] << 6) & 0xF0000);
633 tag = event[1] & 0x03FF;
634 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
635 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
636 pasid, address, flags);
639 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
640 event[0], event[1], event[2], event[3]);
643 memset(__evt, 0, 4 * sizeof(u32));
646 static void iommu_poll_events(struct amd_iommu *iommu)
650 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
651 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
653 while (head != tail) {
654 iommu_print_event(iommu, iommu->evt_buf + head);
655 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
658 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
661 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
663 struct amd_iommu_fault fault;
665 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
666 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
670 fault.address = raw[1];
671 fault.pasid = PPR_PASID(raw[0]);
672 fault.device_id = PPR_DEVID(raw[0]);
673 fault.tag = PPR_TAG(raw[0]);
674 fault.flags = PPR_FLAGS(raw[0]);
676 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
679 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
683 if (iommu->ppr_log == NULL)
686 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
687 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
689 while (head != tail) {
694 raw = (u64 *)(iommu->ppr_log + head);
697 * Hardware bug: Interrupt may arrive before the entry is
698 * written to memory. If this happens we need to wait for the
701 for (i = 0; i < LOOP_TIMEOUT; ++i) {
702 if (PPR_REQ_TYPE(raw[0]) != 0)
707 /* Avoid memcpy function-call overhead */
712 * To detect the hardware bug we need to clear the entry
715 raw[0] = raw[1] = 0UL;
717 /* Update head pointer of hardware ring-buffer */
718 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
719 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
721 /* Handle PPR entry */
722 iommu_handle_ppr_entry(iommu, entry);
724 /* Refresh ring-buffer information */
725 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
726 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
730 #ifdef CONFIG_IRQ_REMAP
731 static int (*iommu_ga_log_notifier)(u32);
733 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
735 iommu_ga_log_notifier = notifier;
739 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
741 static void iommu_poll_ga_log(struct amd_iommu *iommu)
743 u32 head, tail, cnt = 0;
745 if (iommu->ga_log == NULL)
748 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
749 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
751 while (head != tail) {
755 raw = (u64 *)(iommu->ga_log + head);
758 /* Avoid memcpy function-call overhead */
761 /* Update head pointer of hardware ring-buffer */
762 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
763 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
765 /* Handle GA entry */
766 switch (GA_REQ_TYPE(log_entry)) {
768 if (!iommu_ga_log_notifier)
771 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
772 __func__, GA_DEVID(log_entry),
775 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
776 pr_err("AMD-Vi: GA log notifier failed.\n");
783 #endif /* CONFIG_IRQ_REMAP */
785 #define AMD_IOMMU_INT_MASK \
786 (MMIO_STATUS_EVT_INT_MASK | \
787 MMIO_STATUS_PPR_INT_MASK | \
788 MMIO_STATUS_GALOG_INT_MASK)
790 irqreturn_t amd_iommu_int_thread(int irq, void *data)
792 struct amd_iommu *iommu = (struct amd_iommu *) data;
793 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
795 while (status & AMD_IOMMU_INT_MASK) {
796 /* Enable EVT and PPR and GA interrupts again */
797 writel(AMD_IOMMU_INT_MASK,
798 iommu->mmio_base + MMIO_STATUS_OFFSET);
800 if (status & MMIO_STATUS_EVT_INT_MASK) {
801 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
802 iommu_poll_events(iommu);
805 if (status & MMIO_STATUS_PPR_INT_MASK) {
806 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
807 iommu_poll_ppr_log(iommu);
810 #ifdef CONFIG_IRQ_REMAP
811 if (status & MMIO_STATUS_GALOG_INT_MASK) {
812 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
813 iommu_poll_ga_log(iommu);
818 * Hardware bug: ERBT1312
819 * When re-enabling interrupt (by writing 1
820 * to clear the bit), the hardware might also try to set
821 * the interrupt bit in the event status register.
822 * In this scenario, the bit will be set, and disable
823 * subsequent interrupts.
825 * Workaround: The IOMMU driver should read back the
826 * status register and check if the interrupt bits are cleared.
827 * If not, driver will need to go through the interrupt handler
828 * again and re-clear the bits
830 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
835 irqreturn_t amd_iommu_int_handler(int irq, void *data)
837 return IRQ_WAKE_THREAD;
840 /****************************************************************************
842 * IOMMU command queuing functions
844 ****************************************************************************/
846 static int wait_on_sem(volatile u64 *sem)
850 while (*sem == 0 && i < LOOP_TIMEOUT) {
855 if (i == LOOP_TIMEOUT) {
856 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
863 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
864 struct iommu_cmd *cmd)
868 target = iommu->cmd_buf + iommu->cmd_buf_tail;
870 iommu->cmd_buf_tail += sizeof(*cmd);
871 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
873 /* Copy command to buffer */
874 memcpy(target, cmd, sizeof(*cmd));
876 /* Tell the IOMMU about it */
877 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
880 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
882 u64 paddr = iommu_virt_to_phys((void *)address);
884 WARN_ON(address & 0x7ULL);
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
888 cmd->data[1] = upper_32_bits(paddr);
890 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
893 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
895 memset(cmd, 0, sizeof(*cmd));
896 cmd->data[0] = devid;
897 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
900 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
901 size_t size, u16 domid, int pde)
906 pages = iommu_num_pages(address, size, PAGE_SIZE);
911 * If we have to flush more than one page, flush all
912 * TLB entries for this domain
914 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
918 address &= PAGE_MASK;
920 memset(cmd, 0, sizeof(*cmd));
921 cmd->data[1] |= domid;
922 cmd->data[2] = lower_32_bits(address);
923 cmd->data[3] = upper_32_bits(address);
924 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
925 if (s) /* size bit - we flush more than one 4kb page */
926 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
927 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
928 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
931 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
932 u64 address, size_t size)
937 pages = iommu_num_pages(address, size, PAGE_SIZE);
942 * If we have to flush more than one page, flush all
943 * TLB entries for this domain
945 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
949 address &= PAGE_MASK;
951 memset(cmd, 0, sizeof(*cmd));
952 cmd->data[0] = devid;
953 cmd->data[0] |= (qdep & 0xff) << 24;
954 cmd->data[1] = devid;
955 cmd->data[2] = lower_32_bits(address);
956 cmd->data[3] = upper_32_bits(address);
957 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
963 u64 address, bool size)
965 memset(cmd, 0, sizeof(*cmd));
967 address &= ~(0xfffULL);
969 cmd->data[0] = pasid;
970 cmd->data[1] = domid;
971 cmd->data[2] = lower_32_bits(address);
972 cmd->data[3] = upper_32_bits(address);
973 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
976 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
977 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
980 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
981 int qdep, u64 address, bool size)
983 memset(cmd, 0, sizeof(*cmd));
985 address &= ~(0xfffULL);
987 cmd->data[0] = devid;
988 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
989 cmd->data[0] |= (qdep & 0xff) << 24;
990 cmd->data[1] = devid;
991 cmd->data[1] |= (pasid & 0xff) << 16;
992 cmd->data[2] = lower_32_bits(address);
993 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
994 cmd->data[3] = upper_32_bits(address);
996 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
997 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1000 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1001 int status, int tag, bool gn)
1003 memset(cmd, 0, sizeof(*cmd));
1005 cmd->data[0] = devid;
1007 cmd->data[1] = pasid;
1008 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1010 cmd->data[3] = tag & 0x1ff;
1011 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1013 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1016 static void build_inv_all(struct iommu_cmd *cmd)
1018 memset(cmd, 0, sizeof(*cmd));
1019 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1022 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1024 memset(cmd, 0, sizeof(*cmd));
1025 cmd->data[0] = devid;
1026 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1030 * Writes the command to the IOMMUs command buffer and informs the
1031 * hardware about the new command.
1033 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1034 struct iommu_cmd *cmd,
1037 unsigned int count = 0;
1038 u32 left, next_tail;
1040 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1042 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1045 /* Skip udelay() the first time around */
1047 if (count == LOOP_TIMEOUT) {
1048 pr_err("AMD-Vi: Command buffer timeout\n");
1055 /* Update head and recheck remaining space */
1056 iommu->cmd_buf_head = readl(iommu->mmio_base +
1057 MMIO_CMD_HEAD_OFFSET);
1062 copy_cmd_to_buffer(iommu, cmd);
1064 /* Do we need to make sure all commands are processed? */
1065 iommu->need_sync = sync;
1070 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1071 struct iommu_cmd *cmd,
1074 unsigned long flags;
1077 raw_spin_lock_irqsave(&iommu->lock, flags);
1078 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1079 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1084 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1086 return iommu_queue_command_sync(iommu, cmd, true);
1090 * This function queues a completion wait command into the command
1091 * buffer of an IOMMU
1093 static int iommu_completion_wait(struct amd_iommu *iommu)
1095 struct iommu_cmd cmd;
1096 unsigned long flags;
1099 if (!iommu->need_sync)
1103 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1105 raw_spin_lock_irqsave(&iommu->lock, flags);
1109 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1113 ret = wait_on_sem(&iommu->cmd_sem);
1116 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1121 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1123 struct iommu_cmd cmd;
1125 build_inv_dte(&cmd, devid);
1127 return iommu_queue_command(iommu, &cmd);
1130 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1134 for (devid = 0; devid <= 0xffff; ++devid)
1135 iommu_flush_dte(iommu, devid);
1137 iommu_completion_wait(iommu);
1141 * This function uses heavy locking and may disable irqs for some time. But
1142 * this is no issue because it is only called during resume.
1144 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1148 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1149 struct iommu_cmd cmd;
1150 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1152 iommu_queue_command(iommu, &cmd);
1155 iommu_completion_wait(iommu);
1158 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1160 struct iommu_cmd cmd;
1162 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1164 iommu_queue_command(iommu, &cmd);
1166 iommu_completion_wait(iommu);
1169 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1171 struct iommu_cmd cmd;
1173 build_inv_all(&cmd);
1175 iommu_queue_command(iommu, &cmd);
1176 iommu_completion_wait(iommu);
1179 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1181 struct iommu_cmd cmd;
1183 build_inv_irt(&cmd, devid);
1185 iommu_queue_command(iommu, &cmd);
1188 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1192 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1193 iommu_flush_irt(iommu, devid);
1195 iommu_completion_wait(iommu);
1198 void iommu_flush_all_caches(struct amd_iommu *iommu)
1200 if (iommu_feature(iommu, FEATURE_IA)) {
1201 amd_iommu_flush_all(iommu);
1203 amd_iommu_flush_dte_all(iommu);
1204 amd_iommu_flush_irt_all(iommu);
1205 amd_iommu_flush_tlb_all(iommu);
1210 * Command send function for flushing on-device TLB
1212 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1213 u64 address, size_t size)
1215 struct amd_iommu *iommu;
1216 struct iommu_cmd cmd;
1219 qdep = dev_data->ats.qdep;
1220 iommu = amd_iommu_rlookup_table[dev_data->devid];
1222 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1224 return iommu_queue_command(iommu, &cmd);
1228 * Command send function for invalidating a device table entry
1230 static int device_flush_dte(struct iommu_dev_data *dev_data)
1232 struct amd_iommu *iommu;
1236 iommu = amd_iommu_rlookup_table[dev_data->devid];
1237 alias = dev_data->alias;
1239 ret = iommu_flush_dte(iommu, dev_data->devid);
1240 if (!ret && alias != dev_data->devid)
1241 ret = iommu_flush_dte(iommu, alias);
1245 if (dev_data->ats.enabled)
1246 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1252 * TLB invalidation function which is called from the mapping functions.
1253 * It invalidates a single PTE if the range to flush is within a single
1254 * page. Otherwise it flushes the whole TLB of the IOMMU.
1256 static void __domain_flush_pages(struct protection_domain *domain,
1257 u64 address, size_t size, int pde)
1259 struct iommu_dev_data *dev_data;
1260 struct iommu_cmd cmd;
1263 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1265 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1266 if (!domain->dev_iommu[i])
1270 * Devices of this domain are behind this IOMMU
1271 * We need a TLB flush
1273 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1276 list_for_each_entry(dev_data, &domain->dev_list, list) {
1278 if (!dev_data->ats.enabled)
1281 ret |= device_flush_iotlb(dev_data, address, size);
1287 static void domain_flush_pages(struct protection_domain *domain,
1288 u64 address, size_t size)
1290 __domain_flush_pages(domain, address, size, 0);
1293 /* Flush the whole IO/TLB for a given protection domain */
1294 static void domain_flush_tlb(struct protection_domain *domain)
1296 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1299 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1300 static void domain_flush_tlb_pde(struct protection_domain *domain)
1302 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1305 static void domain_flush_complete(struct protection_domain *domain)
1309 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1310 if (domain && !domain->dev_iommu[i])
1314 * Devices of this domain are behind this IOMMU
1315 * We need to wait for completion of all commands.
1317 iommu_completion_wait(amd_iommus[i]);
1323 * This function flushes the DTEs for all devices in domain
1325 static void domain_flush_devices(struct protection_domain *domain)
1327 struct iommu_dev_data *dev_data;
1329 list_for_each_entry(dev_data, &domain->dev_list, list)
1330 device_flush_dte(dev_data);
1333 /****************************************************************************
1335 * The functions below are used the create the page table mappings for
1336 * unity mapped regions.
1338 ****************************************************************************/
1341 * This function is used to add another level to an IO page table. Adding
1342 * another level increases the size of the address space by 9 bits to a size up
1345 static void increase_address_space(struct protection_domain *domain,
1348 unsigned long flags;
1351 pte = (void *)get_zeroed_page(gfp);
1355 spin_lock_irqsave(&domain->lock, flags);
1357 if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1358 /* address space already 64 bit large */
1361 *pte = PM_LEVEL_PDE(domain->mode,
1362 iommu_virt_to_phys(domain->pt_root));
1363 domain->pt_root = pte;
1365 domain->updated = true;
1369 spin_unlock_irqrestore(&domain->lock, flags);
1370 free_page((unsigned long)pte);
1375 static u64 *alloc_pte(struct protection_domain *domain,
1376 unsigned long address,
1377 unsigned long page_size,
1384 BUG_ON(!is_power_of_2(page_size));
1386 while (address > PM_LEVEL_SIZE(domain->mode))
1387 increase_address_space(domain, gfp);
1389 level = domain->mode - 1;
1390 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1391 address = PAGE_SIZE_ALIGN(address, page_size);
1392 end_lvl = PAGE_SIZE_LEVEL(page_size);
1394 while (level > end_lvl) {
1399 if (!IOMMU_PTE_PRESENT(__pte)) {
1400 page = (u64 *)get_zeroed_page(gfp);
1404 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1406 /* pte could have been changed somewhere. */
1407 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1408 free_page((unsigned long)page);
1413 /* No level skipping support yet */
1414 if (PM_PTE_LEVEL(*pte) != level)
1419 pte = IOMMU_PTE_PAGE(*pte);
1421 if (pte_page && level == end_lvl)
1424 pte = &pte[PM_LEVEL_INDEX(level, address)];
1431 * This function checks if there is a PTE for a given dma address. If
1432 * there is one, it returns the pointer to it.
1434 static u64 *fetch_pte(struct protection_domain *domain,
1435 unsigned long address,
1436 unsigned long *page_size)
1443 if (address > PM_LEVEL_SIZE(domain->mode))
1446 level = domain->mode - 1;
1447 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1448 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1453 if (!IOMMU_PTE_PRESENT(*pte))
1457 if (PM_PTE_LEVEL(*pte) == 7 ||
1458 PM_PTE_LEVEL(*pte) == 0)
1461 /* No level skipping support yet */
1462 if (PM_PTE_LEVEL(*pte) != level)
1467 /* Walk to the next level */
1468 pte = IOMMU_PTE_PAGE(*pte);
1469 pte = &pte[PM_LEVEL_INDEX(level, address)];
1470 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1473 if (PM_PTE_LEVEL(*pte) == 0x07) {
1474 unsigned long pte_mask;
1477 * If we have a series of large PTEs, make
1478 * sure to return a pointer to the first one.
1480 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1481 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1482 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1489 * Generic mapping functions. It maps a physical address into a DMA
1490 * address space. It allocates the page table pages if necessary.
1491 * In the future it can be extended to a generic mapping function
1492 * supporting all features of AMD IOMMU page tables like level skipping
1493 * and full 64 bit address spaces.
1495 static int iommu_map_page(struct protection_domain *dom,
1496 unsigned long bus_addr,
1497 unsigned long phys_addr,
1498 unsigned long page_size,
1505 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1506 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1508 if (!(prot & IOMMU_PROT_MASK))
1511 count = PAGE_SIZE_PTE_COUNT(page_size);
1512 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1517 for (i = 0; i < count; ++i)
1518 if (IOMMU_PTE_PRESENT(pte[i]))
1522 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1523 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1525 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1527 if (prot & IOMMU_PROT_IR)
1528 __pte |= IOMMU_PTE_IR;
1529 if (prot & IOMMU_PROT_IW)
1530 __pte |= IOMMU_PTE_IW;
1532 for (i = 0; i < count; ++i)
1540 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1541 unsigned long bus_addr,
1542 unsigned long page_size)
1544 unsigned long long unmapped;
1545 unsigned long unmap_size;
1548 BUG_ON(!is_power_of_2(page_size));
1552 while (unmapped < page_size) {
1554 pte = fetch_pte(dom, bus_addr, &unmap_size);
1559 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1560 for (i = 0; i < count; i++)
1564 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1565 unmapped += unmap_size;
1568 BUG_ON(unmapped && !is_power_of_2(unmapped));
1573 /****************************************************************************
1575 * The next functions belong to the address allocator for the dma_ops
1576 * interface functions.
1578 ****************************************************************************/
1581 static unsigned long dma_ops_alloc_iova(struct device *dev,
1582 struct dma_ops_domain *dma_dom,
1583 unsigned int pages, u64 dma_mask)
1585 unsigned long pfn = 0;
1587 pages = __roundup_pow_of_two(pages);
1589 if (dma_mask > DMA_BIT_MASK(32))
1590 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1591 IOVA_PFN(DMA_BIT_MASK(32)), false);
1594 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1595 IOVA_PFN(dma_mask), true);
1597 return (pfn << PAGE_SHIFT);
1600 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1601 unsigned long address,
1604 pages = __roundup_pow_of_two(pages);
1605 address >>= PAGE_SHIFT;
1607 free_iova_fast(&dma_dom->iovad, address, pages);
1610 /****************************************************************************
1612 * The next functions belong to the domain allocation. A domain is
1613 * allocated for every IOMMU as the default domain. If device isolation
1614 * is enabled, every device get its own domain. The most important thing
1615 * about domains is the page table mapping the DMA address space they
1618 ****************************************************************************/
1621 * This function adds a protection domain to the global protection domain list
1623 static void add_domain_to_list(struct protection_domain *domain)
1625 unsigned long flags;
1627 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1628 list_add(&domain->list, &amd_iommu_pd_list);
1629 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1633 * This function removes a protection domain to the global
1634 * protection domain list
1636 static void del_domain_from_list(struct protection_domain *domain)
1638 unsigned long flags;
1640 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1641 list_del(&domain->list);
1642 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1645 static u16 domain_id_alloc(void)
1649 spin_lock(&pd_bitmap_lock);
1650 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1652 if (id > 0 && id < MAX_DOMAIN_ID)
1653 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1656 spin_unlock(&pd_bitmap_lock);
1661 static void domain_id_free(int id)
1663 spin_lock(&pd_bitmap_lock);
1664 if (id > 0 && id < MAX_DOMAIN_ID)
1665 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1666 spin_unlock(&pd_bitmap_lock);
1669 #define DEFINE_FREE_PT_FN(LVL, FN) \
1670 static void free_pt_##LVL (unsigned long __pt) \
1678 for (i = 0; i < 512; ++i) { \
1679 /* PTE present? */ \
1680 if (!IOMMU_PTE_PRESENT(pt[i])) \
1684 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1685 PM_PTE_LEVEL(pt[i]) == 7) \
1688 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1691 free_page((unsigned long)pt); \
1694 DEFINE_FREE_PT_FN(l2, free_page)
1695 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1696 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1697 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1698 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1700 static void free_pagetable(struct protection_domain *domain)
1702 unsigned long root = (unsigned long)domain->pt_root;
1704 switch (domain->mode) {
1705 case PAGE_MODE_NONE:
1707 case PAGE_MODE_1_LEVEL:
1710 case PAGE_MODE_2_LEVEL:
1713 case PAGE_MODE_3_LEVEL:
1716 case PAGE_MODE_4_LEVEL:
1719 case PAGE_MODE_5_LEVEL:
1722 case PAGE_MODE_6_LEVEL:
1730 static void free_gcr3_tbl_level1(u64 *tbl)
1735 for (i = 0; i < 512; ++i) {
1736 if (!(tbl[i] & GCR3_VALID))
1739 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1741 free_page((unsigned long)ptr);
1745 static void free_gcr3_tbl_level2(u64 *tbl)
1750 for (i = 0; i < 512; ++i) {
1751 if (!(tbl[i] & GCR3_VALID))
1754 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1756 free_gcr3_tbl_level1(ptr);
1760 static void free_gcr3_table(struct protection_domain *domain)
1762 if (domain->glx == 2)
1763 free_gcr3_tbl_level2(domain->gcr3_tbl);
1764 else if (domain->glx == 1)
1765 free_gcr3_tbl_level1(domain->gcr3_tbl);
1767 BUG_ON(domain->glx != 0);
1769 free_page((unsigned long)domain->gcr3_tbl);
1772 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1774 domain_flush_tlb(&dom->domain);
1775 domain_flush_complete(&dom->domain);
1778 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1780 struct dma_ops_domain *dom;
1782 dom = container_of(iovad, struct dma_ops_domain, iovad);
1784 dma_ops_domain_flush_tlb(dom);
1788 * Free a domain, only used if something went wrong in the
1789 * allocation path and we need to free an already allocated page table
1791 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1796 del_domain_from_list(&dom->domain);
1798 put_iova_domain(&dom->iovad);
1800 free_pagetable(&dom->domain);
1803 domain_id_free(dom->domain.id);
1809 * Allocates a new protection domain usable for the dma_ops functions.
1810 * It also initializes the page table and the address allocator data
1811 * structures required for the dma_ops interface
1813 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1815 struct dma_ops_domain *dma_dom;
1817 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1821 if (protection_domain_init(&dma_dom->domain))
1824 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1825 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1826 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1827 if (!dma_dom->domain.pt_root)
1830 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1832 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1835 /* Initialize reserved ranges */
1836 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1838 add_domain_to_list(&dma_dom->domain);
1843 dma_ops_domain_free(dma_dom);
1849 * little helper function to check whether a given protection domain is a
1852 static bool dma_ops_domain(struct protection_domain *domain)
1854 return domain->flags & PD_DMA_OPS_MASK;
1857 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1864 if (domain->mode != PAGE_MODE_NONE)
1865 pte_root = iommu_virt_to_phys(domain->pt_root);
1867 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1868 << DEV_ENTRY_MODE_SHIFT;
1869 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1871 flags = amd_iommu_dev_table[devid].data[1];
1874 flags |= DTE_FLAG_IOTLB;
1877 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1879 if (iommu_feature(iommu, FEATURE_EPHSUP))
1880 pte_root |= 1ULL << DEV_ENTRY_PPR;
1883 if (domain->flags & PD_IOMMUV2_MASK) {
1884 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1885 u64 glx = domain->glx;
1888 pte_root |= DTE_FLAG_GV;
1889 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1891 /* First mask out possible old values for GCR3 table */
1892 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1895 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1898 /* Encode GCR3 table into DTE */
1899 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1902 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1905 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1909 flags &= ~DEV_DOMID_MASK;
1910 flags |= domain->id;
1912 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1913 amd_iommu_dev_table[devid].data[1] = flags;
1914 amd_iommu_dev_table[devid].data[0] = pte_root;
1917 * A kdump kernel might be replacing a domain ID that was copied from
1918 * the previous kernel--if so, it needs to flush the translation cache
1919 * entries for the old domain ID that is being overwritten
1922 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1924 amd_iommu_flush_tlb_domid(iommu, old_domid);
1928 static void clear_dte_entry(u16 devid)
1930 /* remove entry from the device table seen by the hardware */
1931 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1932 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1934 amd_iommu_apply_erratum_63(devid);
1937 static void do_attach(struct iommu_dev_data *dev_data,
1938 struct protection_domain *domain)
1940 struct amd_iommu *iommu;
1944 iommu = amd_iommu_rlookup_table[dev_data->devid];
1945 alias = dev_data->alias;
1946 ats = dev_data->ats.enabled;
1948 /* Update data structures */
1949 dev_data->domain = domain;
1950 list_add(&dev_data->list, &domain->dev_list);
1952 /* Do reference counting */
1953 domain->dev_iommu[iommu->index] += 1;
1954 domain->dev_cnt += 1;
1956 /* Update device table */
1957 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1958 if (alias != dev_data->devid)
1959 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1961 device_flush_dte(dev_data);
1964 static void do_detach(struct iommu_dev_data *dev_data)
1966 struct protection_domain *domain = dev_data->domain;
1967 struct amd_iommu *iommu;
1970 iommu = amd_iommu_rlookup_table[dev_data->devid];
1971 alias = dev_data->alias;
1973 /* Update data structures */
1974 dev_data->domain = NULL;
1975 list_del(&dev_data->list);
1976 clear_dte_entry(dev_data->devid);
1977 if (alias != dev_data->devid)
1978 clear_dte_entry(alias);
1980 /* Flush the DTE entry */
1981 device_flush_dte(dev_data);
1984 domain_flush_tlb_pde(domain);
1986 /* Wait for the flushes to finish */
1987 domain_flush_complete(domain);
1989 /* decrease reference counters - needs to happen after the flushes */
1990 domain->dev_iommu[iommu->index] -= 1;
1991 domain->dev_cnt -= 1;
1995 * If a device is not yet associated with a domain, this function makes the
1996 * device visible in the domain
1998 static int __attach_device(struct iommu_dev_data *dev_data,
1999 struct protection_domain *domain)
2004 spin_lock(&domain->lock);
2007 if (dev_data->domain != NULL)
2010 /* Attach alias group root */
2011 do_attach(dev_data, domain);
2018 spin_unlock(&domain->lock);
2024 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2026 pci_disable_ats(pdev);
2027 pci_disable_pri(pdev);
2028 pci_disable_pasid(pdev);
2031 /* FIXME: Change generic reset-function to do the same */
2032 static int pri_reset_while_enabled(struct pci_dev *pdev)
2037 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2041 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2042 control |= PCI_PRI_CTRL_RESET;
2043 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2048 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2053 /* FIXME: Hardcode number of outstanding requests for now */
2055 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2057 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2059 /* Only allow access to user-accessible pages */
2060 ret = pci_enable_pasid(pdev, 0);
2064 /* First reset the PRI state of the device */
2065 ret = pci_reset_pri(pdev);
2070 ret = pci_enable_pri(pdev, reqs);
2075 ret = pri_reset_while_enabled(pdev);
2080 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2087 pci_disable_pri(pdev);
2088 pci_disable_pasid(pdev);
2093 /* FIXME: Move this to PCI code */
2094 #define PCI_PRI_TLP_OFF (1 << 15)
2096 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2101 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2105 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2107 return (status & PCI_PRI_TLP_OFF) ? true : false;
2111 * If a device is not yet associated with a domain, this function makes the
2112 * device visible in the domain
2114 static int attach_device(struct device *dev,
2115 struct protection_domain *domain)
2117 struct pci_dev *pdev;
2118 struct iommu_dev_data *dev_data;
2119 unsigned long flags;
2122 dev_data = get_dev_data(dev);
2124 if (!dev_is_pci(dev))
2125 goto skip_ats_check;
2127 pdev = to_pci_dev(dev);
2128 if (domain->flags & PD_IOMMUV2_MASK) {
2129 if (!dev_data->passthrough)
2132 if (dev_data->iommu_v2) {
2133 if (pdev_iommuv2_enable(pdev) != 0)
2136 dev_data->ats.enabled = true;
2137 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2138 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2140 } else if (amd_iommu_iotlb_sup &&
2141 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2142 dev_data->ats.enabled = true;
2143 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2147 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2148 ret = __attach_device(dev_data, domain);
2149 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2152 * We might boot into a crash-kernel here. The crashed kernel
2153 * left the caches in the IOMMU dirty. So we have to flush
2154 * here to evict all dirty stuff.
2156 domain_flush_tlb_pde(domain);
2158 domain_flush_complete(domain);
2164 * Removes a device from a protection domain (unlocked)
2166 static void __detach_device(struct iommu_dev_data *dev_data)
2168 struct protection_domain *domain;
2170 domain = dev_data->domain;
2172 spin_lock(&domain->lock);
2174 do_detach(dev_data);
2176 spin_unlock(&domain->lock);
2180 * Removes a device from a protection domain (with devtable_lock held)
2182 static void detach_device(struct device *dev)
2184 struct protection_domain *domain;
2185 struct iommu_dev_data *dev_data;
2186 unsigned long flags;
2188 dev_data = get_dev_data(dev);
2189 domain = dev_data->domain;
2192 * First check if the device is still attached. It might already
2193 * be detached from its domain because the generic
2194 * iommu_detach_group code detached it and we try again here in
2195 * our alias handling.
2197 if (WARN_ON(!dev_data->domain))
2200 /* lock device table */
2201 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2202 __detach_device(dev_data);
2203 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2205 if (!dev_is_pci(dev))
2208 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2209 pdev_iommuv2_disable(to_pci_dev(dev));
2210 else if (dev_data->ats.enabled)
2211 pci_disable_ats(to_pci_dev(dev));
2213 dev_data->ats.enabled = false;
2216 static int amd_iommu_add_device(struct device *dev)
2218 struct iommu_dev_data *dev_data;
2219 struct iommu_domain *domain;
2220 struct amd_iommu *iommu;
2223 if (!check_device(dev) || get_dev_data(dev))
2226 devid = get_device_id(dev);
2230 iommu = amd_iommu_rlookup_table[devid];
2232 ret = iommu_init_device(dev);
2234 if (ret != -ENOTSUPP)
2235 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2238 iommu_ignore_device(dev);
2239 dev->dma_ops = &dma_direct_ops;
2242 init_iommu_group(dev);
2244 dev_data = get_dev_data(dev);
2248 if (iommu_pass_through || dev_data->iommu_v2)
2249 iommu_request_dm_for_dev(dev);
2251 /* Domains are initialized for this device - have a look what we ended up with */
2252 domain = iommu_get_domain_for_dev(dev);
2253 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2254 dev_data->passthrough = true;
2256 dev->dma_ops = &amd_iommu_dma_ops;
2259 iommu_completion_wait(iommu);
2264 static void amd_iommu_remove_device(struct device *dev)
2266 struct amd_iommu *iommu;
2269 if (!check_device(dev))
2272 devid = get_device_id(dev);
2276 iommu = amd_iommu_rlookup_table[devid];
2278 iommu_uninit_device(dev);
2279 iommu_completion_wait(iommu);
2282 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2284 if (dev_is_pci(dev))
2285 return pci_device_group(dev);
2287 return acpihid_device_group(dev);
2290 /*****************************************************************************
2292 * The next functions belong to the dma_ops mapping/unmapping code.
2294 *****************************************************************************/
2297 * In the dma_ops path we only have the struct device. This function
2298 * finds the corresponding IOMMU, the protection domain and the
2299 * requestor id for a given device.
2300 * If the device is not yet associated with a domain this is also done
2303 static struct protection_domain *get_domain(struct device *dev)
2305 struct protection_domain *domain;
2306 struct iommu_domain *io_domain;
2308 if (!check_device(dev))
2309 return ERR_PTR(-EINVAL);
2311 domain = get_dev_data(dev)->domain;
2312 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2313 get_dev_data(dev)->defer_attach = false;
2314 io_domain = iommu_get_domain_for_dev(dev);
2315 domain = to_pdomain(io_domain);
2316 attach_device(dev, domain);
2319 return ERR_PTR(-EBUSY);
2321 if (!dma_ops_domain(domain))
2322 return ERR_PTR(-EBUSY);
2327 static void update_device_table(struct protection_domain *domain)
2329 struct iommu_dev_data *dev_data;
2331 list_for_each_entry(dev_data, &domain->dev_list, list) {
2332 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2333 dev_data->iommu_v2);
2335 if (dev_data->devid == dev_data->alias)
2338 /* There is an alias, update device table entry for it */
2339 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2340 dev_data->iommu_v2);
2344 static void update_domain(struct protection_domain *domain)
2346 if (!domain->updated)
2349 update_device_table(domain);
2351 domain_flush_devices(domain);
2352 domain_flush_tlb_pde(domain);
2354 domain->updated = false;
2357 static int dir2prot(enum dma_data_direction direction)
2359 if (direction == DMA_TO_DEVICE)
2360 return IOMMU_PROT_IR;
2361 else if (direction == DMA_FROM_DEVICE)
2362 return IOMMU_PROT_IW;
2363 else if (direction == DMA_BIDIRECTIONAL)
2364 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2370 * This function contains common code for mapping of a physically
2371 * contiguous memory region into DMA address space. It is used by all
2372 * mapping functions provided with this IOMMU driver.
2373 * Must be called with the domain lock held.
2375 static dma_addr_t __map_single(struct device *dev,
2376 struct dma_ops_domain *dma_dom,
2379 enum dma_data_direction direction,
2382 dma_addr_t offset = paddr & ~PAGE_MASK;
2383 dma_addr_t address, start, ret;
2388 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2391 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2392 if (address == AMD_IOMMU_MAPPING_ERROR)
2395 prot = dir2prot(direction);
2398 for (i = 0; i < pages; ++i) {
2399 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2400 PAGE_SIZE, prot, GFP_ATOMIC);
2409 if (unlikely(amd_iommu_np_cache)) {
2410 domain_flush_pages(&dma_dom->domain, address, size);
2411 domain_flush_complete(&dma_dom->domain);
2419 for (--i; i >= 0; --i) {
2421 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2424 domain_flush_tlb(&dma_dom->domain);
2425 domain_flush_complete(&dma_dom->domain);
2427 dma_ops_free_iova(dma_dom, address, pages);
2429 return AMD_IOMMU_MAPPING_ERROR;
2433 * Does the reverse of the __map_single function. Must be called with
2434 * the domain lock held too
2436 static void __unmap_single(struct dma_ops_domain *dma_dom,
2437 dma_addr_t dma_addr,
2441 dma_addr_t i, start;
2444 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2445 dma_addr &= PAGE_MASK;
2448 for (i = 0; i < pages; ++i) {
2449 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2453 if (amd_iommu_unmap_flush) {
2454 domain_flush_tlb(&dma_dom->domain);
2455 domain_flush_complete(&dma_dom->domain);
2456 dma_ops_free_iova(dma_dom, dma_addr, pages);
2458 pages = __roundup_pow_of_two(pages);
2459 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2464 * The exported map_single function for dma_ops.
2466 static dma_addr_t map_page(struct device *dev, struct page *page,
2467 unsigned long offset, size_t size,
2468 enum dma_data_direction dir,
2469 unsigned long attrs)
2471 phys_addr_t paddr = page_to_phys(page) + offset;
2472 struct protection_domain *domain;
2473 struct dma_ops_domain *dma_dom;
2476 domain = get_domain(dev);
2477 if (PTR_ERR(domain) == -EINVAL)
2478 return (dma_addr_t)paddr;
2479 else if (IS_ERR(domain))
2480 return AMD_IOMMU_MAPPING_ERROR;
2482 dma_mask = *dev->dma_mask;
2483 dma_dom = to_dma_ops_domain(domain);
2485 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2489 * The exported unmap_single function for dma_ops.
2491 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2492 enum dma_data_direction dir, unsigned long attrs)
2494 struct protection_domain *domain;
2495 struct dma_ops_domain *dma_dom;
2497 domain = get_domain(dev);
2501 dma_dom = to_dma_ops_domain(domain);
2503 __unmap_single(dma_dom, dma_addr, size, dir);
2506 static int sg_num_pages(struct device *dev,
2507 struct scatterlist *sglist,
2510 unsigned long mask, boundary_size;
2511 struct scatterlist *s;
2514 mask = dma_get_seg_boundary(dev);
2515 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2516 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2518 for_each_sg(sglist, s, nelems, i) {
2521 s->dma_address = npages << PAGE_SHIFT;
2522 p = npages % boundary_size;
2523 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2524 if (p + n > boundary_size)
2525 npages += boundary_size - p;
2533 * The exported map_sg function for dma_ops (handles scatter-gather
2536 static int map_sg(struct device *dev, struct scatterlist *sglist,
2537 int nelems, enum dma_data_direction direction,
2538 unsigned long attrs)
2540 int mapped_pages = 0, npages = 0, prot = 0, i;
2541 struct protection_domain *domain;
2542 struct dma_ops_domain *dma_dom;
2543 struct scatterlist *s;
2544 unsigned long address;
2547 domain = get_domain(dev);
2551 dma_dom = to_dma_ops_domain(domain);
2552 dma_mask = *dev->dma_mask;
2554 npages = sg_num_pages(dev, sglist, nelems);
2556 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2557 if (address == AMD_IOMMU_MAPPING_ERROR)
2560 prot = dir2prot(direction);
2562 /* Map all sg entries */
2563 for_each_sg(sglist, s, nelems, i) {
2564 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2566 for (j = 0; j < pages; ++j) {
2567 unsigned long bus_addr, phys_addr;
2570 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2571 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2572 ret = iommu_map_page(domain, bus_addr, phys_addr,
2574 GFP_ATOMIC | __GFP_NOWARN);
2582 /* Everything is mapped - write the right values into s->dma_address */
2583 for_each_sg(sglist, s, nelems, i) {
2585 * Add in the remaining piece of the scatter-gather offset that
2586 * was masked out when we were determining the physical address
2587 * via (sg_phys(s) & PAGE_MASK) earlier.
2589 s->dma_address += address + (s->offset & ~PAGE_MASK);
2590 s->dma_length = s->length;
2596 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2597 dev_name(dev), npages);
2599 for_each_sg(sglist, s, nelems, i) {
2600 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2602 for (j = 0; j < pages; ++j) {
2603 unsigned long bus_addr;
2605 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2606 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2608 if (--mapped_pages == 0)
2614 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2621 * The exported map_sg function for dma_ops (handles scatter-gather
2624 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2625 int nelems, enum dma_data_direction dir,
2626 unsigned long attrs)
2628 struct protection_domain *domain;
2629 struct dma_ops_domain *dma_dom;
2630 unsigned long startaddr;
2633 domain = get_domain(dev);
2637 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2638 dma_dom = to_dma_ops_domain(domain);
2639 npages = sg_num_pages(dev, sglist, nelems);
2641 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2645 * The exported alloc_coherent function for dma_ops.
2647 static void *alloc_coherent(struct device *dev, size_t size,
2648 dma_addr_t *dma_addr, gfp_t flag,
2649 unsigned long attrs)
2651 u64 dma_mask = dev->coherent_dma_mask;
2652 struct protection_domain *domain;
2653 struct dma_ops_domain *dma_dom;
2656 domain = get_domain(dev);
2657 if (PTR_ERR(domain) == -EINVAL) {
2658 page = alloc_pages(flag, get_order(size));
2659 *dma_addr = page_to_phys(page);
2660 return page_address(page);
2661 } else if (IS_ERR(domain))
2664 dma_dom = to_dma_ops_domain(domain);
2665 size = PAGE_ALIGN(size);
2666 dma_mask = dev->coherent_dma_mask;
2667 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2670 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2672 if (!gfpflags_allow_blocking(flag))
2675 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2676 get_order(size), flag & __GFP_NOWARN);
2682 dma_mask = *dev->dma_mask;
2684 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2685 size, DMA_BIDIRECTIONAL, dma_mask);
2687 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2690 return page_address(page);
2694 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2695 __free_pages(page, get_order(size));
2701 * The exported free_coherent function for dma_ops.
2703 static void free_coherent(struct device *dev, size_t size,
2704 void *virt_addr, dma_addr_t dma_addr,
2705 unsigned long attrs)
2707 struct protection_domain *domain;
2708 struct dma_ops_domain *dma_dom;
2711 page = virt_to_page(virt_addr);
2712 size = PAGE_ALIGN(size);
2714 domain = get_domain(dev);
2718 dma_dom = to_dma_ops_domain(domain);
2720 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2723 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2724 __free_pages(page, get_order(size));
2728 * This function is called by the DMA layer to find out if we can handle a
2729 * particular device. It is part of the dma_ops.
2731 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2733 if (!dma_direct_supported(dev, mask))
2735 return check_device(dev);
2738 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2740 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2743 static const struct dma_map_ops amd_iommu_dma_ops = {
2744 .alloc = alloc_coherent,
2745 .free = free_coherent,
2746 .map_page = map_page,
2747 .unmap_page = unmap_page,
2749 .unmap_sg = unmap_sg,
2750 .dma_supported = amd_iommu_dma_supported,
2751 .mapping_error = amd_iommu_mapping_error,
2754 static int init_reserved_iova_ranges(void)
2756 struct pci_dev *pdev = NULL;
2759 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2761 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2762 &reserved_rbtree_key);
2764 /* MSI memory range */
2765 val = reserve_iova(&reserved_iova_ranges,
2766 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2768 pr_err("Reserving MSI range failed\n");
2772 /* HT memory range */
2773 val = reserve_iova(&reserved_iova_ranges,
2774 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2776 pr_err("Reserving HT range failed\n");
2781 * Memory used for PCI resources
2782 * FIXME: Check whether we can reserve the PCI-hole completly
2784 for_each_pci_dev(pdev) {
2787 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2788 struct resource *r = &pdev->resource[i];
2790 if (!(r->flags & IORESOURCE_MEM))
2793 val = reserve_iova(&reserved_iova_ranges,
2797 pr_err("Reserve pci-resource range failed\n");
2806 int __init amd_iommu_init_api(void)
2810 ret = iova_cache_get();
2814 ret = init_reserved_iova_ranges();
2818 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2821 #ifdef CONFIG_ARM_AMBA
2822 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2826 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2833 int __init amd_iommu_init_dma_ops(void)
2835 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2839 * In case we don't initialize SWIOTLB (actually the common case
2840 * when AMD IOMMU is enabled and SME is not active), make sure there
2841 * are global dma_ops set as a fall-back for devices not handled by
2842 * this driver (for example non-PCI devices). When SME is active,
2843 * make sure that swiotlb variable remains set so the global dma_ops
2844 * continue to be SWIOTLB.
2847 dma_ops = &dma_direct_ops;
2849 if (amd_iommu_unmap_flush)
2850 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2852 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2858 /*****************************************************************************
2860 * The following functions belong to the exported interface of AMD IOMMU
2862 * This interface allows access to lower level functions of the IOMMU
2863 * like protection domain handling and assignement of devices to domains
2864 * which is not possible with the dma_ops interface.
2866 *****************************************************************************/
2868 static void cleanup_domain(struct protection_domain *domain)
2870 struct iommu_dev_data *entry;
2871 unsigned long flags;
2873 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2875 while (!list_empty(&domain->dev_list)) {
2876 entry = list_first_entry(&domain->dev_list,
2877 struct iommu_dev_data, list);
2878 BUG_ON(!entry->domain);
2879 __detach_device(entry);
2882 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2885 static void protection_domain_free(struct protection_domain *domain)
2890 del_domain_from_list(domain);
2893 domain_id_free(domain->id);
2898 static int protection_domain_init(struct protection_domain *domain)
2900 spin_lock_init(&domain->lock);
2901 mutex_init(&domain->api_lock);
2902 domain->id = domain_id_alloc();
2905 INIT_LIST_HEAD(&domain->dev_list);
2910 static struct protection_domain *protection_domain_alloc(void)
2912 struct protection_domain *domain;
2914 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2918 if (protection_domain_init(domain))
2921 add_domain_to_list(domain);
2931 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2933 struct protection_domain *pdomain;
2934 struct dma_ops_domain *dma_domain;
2937 case IOMMU_DOMAIN_UNMANAGED:
2938 pdomain = protection_domain_alloc();
2942 pdomain->mode = PAGE_MODE_3_LEVEL;
2943 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2944 if (!pdomain->pt_root) {
2945 protection_domain_free(pdomain);
2949 pdomain->domain.geometry.aperture_start = 0;
2950 pdomain->domain.geometry.aperture_end = ~0ULL;
2951 pdomain->domain.geometry.force_aperture = true;
2954 case IOMMU_DOMAIN_DMA:
2955 dma_domain = dma_ops_domain_alloc();
2957 pr_err("AMD-Vi: Failed to allocate\n");
2960 pdomain = &dma_domain->domain;
2962 case IOMMU_DOMAIN_IDENTITY:
2963 pdomain = protection_domain_alloc();
2967 pdomain->mode = PAGE_MODE_NONE;
2973 return &pdomain->domain;
2976 static void amd_iommu_domain_free(struct iommu_domain *dom)
2978 struct protection_domain *domain;
2979 struct dma_ops_domain *dma_dom;
2981 domain = to_pdomain(dom);
2983 if (domain->dev_cnt > 0)
2984 cleanup_domain(domain);
2986 BUG_ON(domain->dev_cnt != 0);
2991 switch (dom->type) {
2992 case IOMMU_DOMAIN_DMA:
2993 /* Now release the domain */
2994 dma_dom = to_dma_ops_domain(domain);
2995 dma_ops_domain_free(dma_dom);
2998 if (domain->mode != PAGE_MODE_NONE)
2999 free_pagetable(domain);
3001 if (domain->flags & PD_IOMMUV2_MASK)
3002 free_gcr3_table(domain);
3004 protection_domain_free(domain);
3009 static void amd_iommu_detach_device(struct iommu_domain *dom,
3012 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3013 struct amd_iommu *iommu;
3016 if (!check_device(dev))
3019 devid = get_device_id(dev);
3023 if (dev_data->domain != NULL)
3026 iommu = amd_iommu_rlookup_table[devid];
3030 #ifdef CONFIG_IRQ_REMAP
3031 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3032 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3033 dev_data->use_vapic = 0;
3036 iommu_completion_wait(iommu);
3039 static int amd_iommu_attach_device(struct iommu_domain *dom,
3042 struct protection_domain *domain = to_pdomain(dom);
3043 struct iommu_dev_data *dev_data;
3044 struct amd_iommu *iommu;
3047 if (!check_device(dev))
3050 dev_data = dev->archdata.iommu;
3052 iommu = amd_iommu_rlookup_table[dev_data->devid];
3056 if (dev_data->domain)
3059 ret = attach_device(dev, domain);
3061 #ifdef CONFIG_IRQ_REMAP
3062 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3063 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3064 dev_data->use_vapic = 1;
3066 dev_data->use_vapic = 0;
3070 iommu_completion_wait(iommu);
3075 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3076 phys_addr_t paddr, size_t page_size, int iommu_prot)
3078 struct protection_domain *domain = to_pdomain(dom);
3082 if (domain->mode == PAGE_MODE_NONE)
3085 if (iommu_prot & IOMMU_READ)
3086 prot |= IOMMU_PROT_IR;
3087 if (iommu_prot & IOMMU_WRITE)
3088 prot |= IOMMU_PROT_IW;
3090 mutex_lock(&domain->api_lock);
3091 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3092 mutex_unlock(&domain->api_lock);
3097 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3100 struct protection_domain *domain = to_pdomain(dom);
3103 if (domain->mode == PAGE_MODE_NONE)
3106 mutex_lock(&domain->api_lock);
3107 unmap_size = iommu_unmap_page(domain, iova, page_size);
3108 mutex_unlock(&domain->api_lock);
3113 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3116 struct protection_domain *domain = to_pdomain(dom);
3117 unsigned long offset_mask, pte_pgsize;
3120 if (domain->mode == PAGE_MODE_NONE)
3123 pte = fetch_pte(domain, iova, &pte_pgsize);
3125 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3128 offset_mask = pte_pgsize - 1;
3129 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3131 return (__pte & ~offset_mask) | (iova & offset_mask);
3134 static bool amd_iommu_capable(enum iommu_cap cap)
3137 case IOMMU_CAP_CACHE_COHERENCY:
3139 case IOMMU_CAP_INTR_REMAP:
3140 return (irq_remapping_enabled == 1);
3141 case IOMMU_CAP_NOEXEC:
3148 static void amd_iommu_get_resv_regions(struct device *dev,
3149 struct list_head *head)
3151 struct iommu_resv_region *region;
3152 struct unity_map_entry *entry;
3155 devid = get_device_id(dev);
3159 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3163 if (devid < entry->devid_start || devid > entry->devid_end)
3166 type = IOMMU_RESV_DIRECT;
3167 length = entry->address_end - entry->address_start;
3168 if (entry->prot & IOMMU_PROT_IR)
3170 if (entry->prot & IOMMU_PROT_IW)
3171 prot |= IOMMU_WRITE;
3172 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3173 /* Exclusion range */
3174 type = IOMMU_RESV_RESERVED;
3176 region = iommu_alloc_resv_region(entry->address_start,
3177 length, prot, type);
3179 pr_err("Out of memory allocating dm-regions for %s\n",
3183 list_add_tail(®ion->list, head);
3186 region = iommu_alloc_resv_region(MSI_RANGE_START,
3187 MSI_RANGE_END - MSI_RANGE_START + 1,
3191 list_add_tail(®ion->list, head);
3193 region = iommu_alloc_resv_region(HT_RANGE_START,
3194 HT_RANGE_END - HT_RANGE_START + 1,
3195 0, IOMMU_RESV_RESERVED);
3198 list_add_tail(®ion->list, head);
3201 static void amd_iommu_put_resv_regions(struct device *dev,
3202 struct list_head *head)
3204 struct iommu_resv_region *entry, *next;
3206 list_for_each_entry_safe(entry, next, head, list)
3210 static void amd_iommu_apply_resv_region(struct device *dev,
3211 struct iommu_domain *domain,
3212 struct iommu_resv_region *region)
3214 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3215 unsigned long start, end;
3217 start = IOVA_PFN(region->start);
3218 end = IOVA_PFN(region->start + region->length - 1);
3220 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3223 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3226 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3227 return dev_data->defer_attach;
3230 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3232 struct protection_domain *dom = to_pdomain(domain);
3234 domain_flush_tlb_pde(dom);
3235 domain_flush_complete(dom);
3238 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3239 unsigned long iova, size_t size)
3243 const struct iommu_ops amd_iommu_ops = {
3244 .capable = amd_iommu_capable,
3245 .domain_alloc = amd_iommu_domain_alloc,
3246 .domain_free = amd_iommu_domain_free,
3247 .attach_dev = amd_iommu_attach_device,
3248 .detach_dev = amd_iommu_detach_device,
3249 .map = amd_iommu_map,
3250 .unmap = amd_iommu_unmap,
3251 .iova_to_phys = amd_iommu_iova_to_phys,
3252 .add_device = amd_iommu_add_device,
3253 .remove_device = amd_iommu_remove_device,
3254 .device_group = amd_iommu_device_group,
3255 .get_resv_regions = amd_iommu_get_resv_regions,
3256 .put_resv_regions = amd_iommu_put_resv_regions,
3257 .apply_resv_region = amd_iommu_apply_resv_region,
3258 .is_attach_deferred = amd_iommu_is_attach_deferred,
3259 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3260 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3261 .iotlb_range_add = amd_iommu_iotlb_range_add,
3262 .iotlb_sync = amd_iommu_flush_iotlb_all,
3265 /*****************************************************************************
3267 * The next functions do a basic initialization of IOMMU for pass through
3270 * In passthrough mode the IOMMU is initialized and enabled but not used for
3271 * DMA-API translation.
3273 *****************************************************************************/
3275 /* IOMMUv2 specific functions */
3276 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3278 return atomic_notifier_chain_register(&ppr_notifier, nb);
3280 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3282 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3284 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3286 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3288 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3290 struct protection_domain *domain = to_pdomain(dom);
3291 unsigned long flags;
3293 spin_lock_irqsave(&domain->lock, flags);
3295 /* Update data structure */
3296 domain->mode = PAGE_MODE_NONE;
3297 domain->updated = true;
3299 /* Make changes visible to IOMMUs */
3300 update_domain(domain);
3302 /* Page-table is not visible to IOMMU anymore, so free it */
3303 free_pagetable(domain);
3305 spin_unlock_irqrestore(&domain->lock, flags);
3307 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3309 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3311 struct protection_domain *domain = to_pdomain(dom);
3312 unsigned long flags;
3315 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3318 /* Number of GCR3 table levels required */
3319 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3322 if (levels > amd_iommu_max_glx_val)
3325 spin_lock_irqsave(&domain->lock, flags);
3328 * Save us all sanity checks whether devices already in the
3329 * domain support IOMMUv2. Just force that the domain has no
3330 * devices attached when it is switched into IOMMUv2 mode.
3333 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3337 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3338 if (domain->gcr3_tbl == NULL)
3341 domain->glx = levels;
3342 domain->flags |= PD_IOMMUV2_MASK;
3343 domain->updated = true;
3345 update_domain(domain);
3350 spin_unlock_irqrestore(&domain->lock, flags);
3354 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3356 static int __flush_pasid(struct protection_domain *domain, int pasid,
3357 u64 address, bool size)
3359 struct iommu_dev_data *dev_data;
3360 struct iommu_cmd cmd;
3363 if (!(domain->flags & PD_IOMMUV2_MASK))
3366 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3369 * IOMMU TLB needs to be flushed before Device TLB to
3370 * prevent device TLB refill from IOMMU TLB
3372 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3373 if (domain->dev_iommu[i] == 0)
3376 ret = iommu_queue_command(amd_iommus[i], &cmd);
3381 /* Wait until IOMMU TLB flushes are complete */
3382 domain_flush_complete(domain);
3384 /* Now flush device TLBs */
3385 list_for_each_entry(dev_data, &domain->dev_list, list) {
3386 struct amd_iommu *iommu;
3390 There might be non-IOMMUv2 capable devices in an IOMMUv2
3393 if (!dev_data->ats.enabled)
3396 qdep = dev_data->ats.qdep;
3397 iommu = amd_iommu_rlookup_table[dev_data->devid];
3399 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3400 qdep, address, size);
3402 ret = iommu_queue_command(iommu, &cmd);
3407 /* Wait until all device TLBs are flushed */
3408 domain_flush_complete(domain);
3417 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3420 return __flush_pasid(domain, pasid, address, false);
3423 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3426 struct protection_domain *domain = to_pdomain(dom);
3427 unsigned long flags;
3430 spin_lock_irqsave(&domain->lock, flags);
3431 ret = __amd_iommu_flush_page(domain, pasid, address);
3432 spin_unlock_irqrestore(&domain->lock, flags);
3436 EXPORT_SYMBOL(amd_iommu_flush_page);
3438 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3440 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3444 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3446 struct protection_domain *domain = to_pdomain(dom);
3447 unsigned long flags;
3450 spin_lock_irqsave(&domain->lock, flags);
3451 ret = __amd_iommu_flush_tlb(domain, pasid);
3452 spin_unlock_irqrestore(&domain->lock, flags);
3456 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3458 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3465 index = (pasid >> (9 * level)) & 0x1ff;
3471 if (!(*pte & GCR3_VALID)) {
3475 root = (void *)get_zeroed_page(GFP_ATOMIC);
3479 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3482 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3490 static int __set_gcr3(struct protection_domain *domain, int pasid,
3495 if (domain->mode != PAGE_MODE_NONE)
3498 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3502 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3504 return __amd_iommu_flush_tlb(domain, pasid);
3507 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3511 if (domain->mode != PAGE_MODE_NONE)
3514 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3520 return __amd_iommu_flush_tlb(domain, pasid);
3523 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3526 struct protection_domain *domain = to_pdomain(dom);
3527 unsigned long flags;
3530 spin_lock_irqsave(&domain->lock, flags);
3531 ret = __set_gcr3(domain, pasid, cr3);
3532 spin_unlock_irqrestore(&domain->lock, flags);
3536 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3538 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3540 struct protection_domain *domain = to_pdomain(dom);
3541 unsigned long flags;
3544 spin_lock_irqsave(&domain->lock, flags);
3545 ret = __clear_gcr3(domain, pasid);
3546 spin_unlock_irqrestore(&domain->lock, flags);
3550 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3552 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3553 int status, int tag)
3555 struct iommu_dev_data *dev_data;
3556 struct amd_iommu *iommu;
3557 struct iommu_cmd cmd;
3559 dev_data = get_dev_data(&pdev->dev);
3560 iommu = amd_iommu_rlookup_table[dev_data->devid];
3562 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3563 tag, dev_data->pri_tlp);
3565 return iommu_queue_command(iommu, &cmd);
3567 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3569 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3571 struct protection_domain *pdomain;
3573 pdomain = get_domain(&pdev->dev);
3574 if (IS_ERR(pdomain))
3577 /* Only return IOMMUv2 domains */
3578 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3581 return &pdomain->domain;
3583 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3585 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3587 struct iommu_dev_data *dev_data;
3589 if (!amd_iommu_v2_supported())
3592 dev_data = get_dev_data(&pdev->dev);
3593 dev_data->errata |= (1 << erratum);
3595 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3597 int amd_iommu_device_info(struct pci_dev *pdev,
3598 struct amd_iommu_device_info *info)
3603 if (pdev == NULL || info == NULL)
3606 if (!amd_iommu_v2_supported())
3609 memset(info, 0, sizeof(*info));
3611 if (!pci_ats_disabled()) {
3612 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3614 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3617 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3619 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3621 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3625 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3626 max_pasids = min(max_pasids, (1 << 20));
3628 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3629 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3631 features = pci_pasid_features(pdev);
3632 if (features & PCI_PASID_CAP_EXEC)
3633 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3634 if (features & PCI_PASID_CAP_PRIV)
3635 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3640 EXPORT_SYMBOL(amd_iommu_device_info);
3642 #ifdef CONFIG_IRQ_REMAP
3644 /*****************************************************************************
3646 * Interrupt Remapping Implementation
3648 *****************************************************************************/
3650 static struct irq_chip amd_ir_chip;
3651 static DEFINE_SPINLOCK(iommu_table_lock);
3653 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3657 dte = amd_iommu_dev_table[devid].data[2];
3658 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3659 dte |= iommu_virt_to_phys(table->table);
3660 dte |= DTE_IRQ_REMAP_INTCTL;
3661 dte |= DTE_IRQ_TABLE_LEN;
3662 dte |= DTE_IRQ_REMAP_ENABLE;
3664 amd_iommu_dev_table[devid].data[2] = dte;
3667 static struct irq_remap_table *get_irq_table(u16 devid)
3669 struct irq_remap_table *table;
3671 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3672 "%s: no iommu for devid %x\n", __func__, devid))
3675 table = irq_lookup_table[devid];
3676 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3682 static struct irq_remap_table *__alloc_irq_table(void)
3684 struct irq_remap_table *table;
3686 table = kzalloc(sizeof(*table), GFP_KERNEL);
3690 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3691 if (!table->table) {
3695 raw_spin_lock_init(&table->lock);
3697 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3698 memset(table->table, 0,
3699 MAX_IRQS_PER_TABLE * sizeof(u32));
3701 memset(table->table, 0,
3702 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3706 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3707 struct irq_remap_table *table)
3709 irq_lookup_table[devid] = table;
3710 set_dte_irq_entry(devid, table);
3711 iommu_flush_dte(iommu, devid);
3714 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3717 struct irq_remap_table *table = data;
3719 irq_lookup_table[alias] = table;
3720 set_dte_irq_entry(alias, table);
3722 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3727 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3729 struct irq_remap_table *table = NULL;
3730 struct irq_remap_table *new_table = NULL;
3731 struct amd_iommu *iommu;
3732 unsigned long flags;
3735 spin_lock_irqsave(&iommu_table_lock, flags);
3737 iommu = amd_iommu_rlookup_table[devid];
3741 table = irq_lookup_table[devid];
3745 alias = amd_iommu_alias_table[devid];
3746 table = irq_lookup_table[alias];
3748 set_remap_table_entry(iommu, devid, table);
3751 spin_unlock_irqrestore(&iommu_table_lock, flags);
3753 /* Nothing there yet, allocate new irq remapping table */
3754 new_table = __alloc_irq_table();
3758 spin_lock_irqsave(&iommu_table_lock, flags);
3760 table = irq_lookup_table[devid];
3764 table = irq_lookup_table[alias];
3766 set_remap_table_entry(iommu, devid, table);
3774 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3777 set_remap_table_entry(iommu, devid, table);
3780 set_remap_table_entry(iommu, alias, table);
3783 iommu_completion_wait(iommu);
3786 spin_unlock_irqrestore(&iommu_table_lock, flags);
3789 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3795 static int alloc_irq_index(u16 devid, int count, bool align,
3796 struct pci_dev *pdev)
3798 struct irq_remap_table *table;
3799 int index, c, alignment = 1;
3800 unsigned long flags;
3801 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3806 table = alloc_irq_table(devid, pdev);
3811 alignment = roundup_pow_of_two(count);
3813 raw_spin_lock_irqsave(&table->lock, flags);
3815 /* Scan table for free entries */
3816 for (index = ALIGN(table->min_index, alignment), c = 0;
3817 index < MAX_IRQS_PER_TABLE;) {
3818 if (!iommu->irte_ops->is_allocated(table, index)) {
3822 index = ALIGN(index + 1, alignment);
3828 iommu->irte_ops->set_allocated(table, index - c + 1);
3840 raw_spin_unlock_irqrestore(&table->lock, flags);
3845 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3846 struct amd_ir_data *data)
3848 struct irq_remap_table *table;
3849 struct amd_iommu *iommu;
3850 unsigned long flags;
3851 struct irte_ga *entry;
3853 iommu = amd_iommu_rlookup_table[devid];
3857 table = get_irq_table(devid);
3861 raw_spin_lock_irqsave(&table->lock, flags);
3863 entry = (struct irte_ga *)table->table;
3864 entry = &entry[index];
3865 entry->lo.fields_remap.valid = 0;
3866 entry->hi.val = irte->hi.val;
3867 entry->lo.val = irte->lo.val;
3868 entry->lo.fields_remap.valid = 1;
3872 raw_spin_unlock_irqrestore(&table->lock, flags);
3874 iommu_flush_irt(iommu, devid);
3875 iommu_completion_wait(iommu);
3880 static int modify_irte(u16 devid, int index, union irte *irte)
3882 struct irq_remap_table *table;
3883 struct amd_iommu *iommu;
3884 unsigned long flags;
3886 iommu = amd_iommu_rlookup_table[devid];
3890 table = get_irq_table(devid);
3894 raw_spin_lock_irqsave(&table->lock, flags);
3895 table->table[index] = irte->val;
3896 raw_spin_unlock_irqrestore(&table->lock, flags);
3898 iommu_flush_irt(iommu, devid);
3899 iommu_completion_wait(iommu);
3904 static void free_irte(u16 devid, int index)
3906 struct irq_remap_table *table;
3907 struct amd_iommu *iommu;
3908 unsigned long flags;
3910 iommu = amd_iommu_rlookup_table[devid];
3914 table = get_irq_table(devid);
3918 raw_spin_lock_irqsave(&table->lock, flags);
3919 iommu->irte_ops->clear_allocated(table, index);
3920 raw_spin_unlock_irqrestore(&table->lock, flags);
3922 iommu_flush_irt(iommu, devid);
3923 iommu_completion_wait(iommu);
3926 static void irte_prepare(void *entry,
3927 u32 delivery_mode, u32 dest_mode,
3928 u8 vector, u32 dest_apicid, int devid)
3930 union irte *irte = (union irte *) entry;
3933 irte->fields.vector = vector;
3934 irte->fields.int_type = delivery_mode;
3935 irte->fields.destination = dest_apicid;
3936 irte->fields.dm = dest_mode;
3937 irte->fields.valid = 1;
3940 static void irte_ga_prepare(void *entry,
3941 u32 delivery_mode, u32 dest_mode,
3942 u8 vector, u32 dest_apicid, int devid)
3944 struct irte_ga *irte = (struct irte_ga *) entry;
3948 irte->lo.fields_remap.int_type = delivery_mode;
3949 irte->lo.fields_remap.dm = dest_mode;
3950 irte->hi.fields.vector = vector;
3951 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3952 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3953 irte->lo.fields_remap.valid = 1;
3956 static void irte_activate(void *entry, u16 devid, u16 index)
3958 union irte *irte = (union irte *) entry;
3960 irte->fields.valid = 1;
3961 modify_irte(devid, index, irte);
3964 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3966 struct irte_ga *irte = (struct irte_ga *) entry;
3968 irte->lo.fields_remap.valid = 1;
3969 modify_irte_ga(devid, index, irte, NULL);
3972 static void irte_deactivate(void *entry, u16 devid, u16 index)
3974 union irte *irte = (union irte *) entry;
3976 irte->fields.valid = 0;
3977 modify_irte(devid, index, irte);
3980 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3982 struct irte_ga *irte = (struct irte_ga *) entry;
3984 irte->lo.fields_remap.valid = 0;
3985 modify_irte_ga(devid, index, irte, NULL);
3988 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3989 u8 vector, u32 dest_apicid)
3991 union irte *irte = (union irte *) entry;
3993 irte->fields.vector = vector;
3994 irte->fields.destination = dest_apicid;
3995 modify_irte(devid, index, irte);
3998 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3999 u8 vector, u32 dest_apicid)
4001 struct irte_ga *irte = (struct irte_ga *) entry;
4003 if (!irte->lo.fields_remap.guest_mode) {
4004 irte->hi.fields.vector = vector;
4005 irte->lo.fields_remap.destination =
4006 APICID_TO_IRTE_DEST_LO(dest_apicid);
4007 irte->hi.fields.destination =
4008 APICID_TO_IRTE_DEST_HI(dest_apicid);
4009 modify_irte_ga(devid, index, irte, NULL);
4013 #define IRTE_ALLOCATED (~1U)
4014 static void irte_set_allocated(struct irq_remap_table *table, int index)
4016 table->table[index] = IRTE_ALLOCATED;
4019 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4021 struct irte_ga *ptr = (struct irte_ga *)table->table;
4022 struct irte_ga *irte = &ptr[index];
4024 memset(&irte->lo.val, 0, sizeof(u64));
4025 memset(&irte->hi.val, 0, sizeof(u64));
4026 irte->hi.fields.vector = 0xff;
4029 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4031 union irte *ptr = (union irte *)table->table;
4032 union irte *irte = &ptr[index];
4034 return irte->val != 0;
4037 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4039 struct irte_ga *ptr = (struct irte_ga *)table->table;
4040 struct irte_ga *irte = &ptr[index];
4042 return irte->hi.fields.vector != 0;
4045 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4047 table->table[index] = 0;
4050 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4052 struct irte_ga *ptr = (struct irte_ga *)table->table;
4053 struct irte_ga *irte = &ptr[index];
4055 memset(&irte->lo.val, 0, sizeof(u64));
4056 memset(&irte->hi.val, 0, sizeof(u64));
4059 static int get_devid(struct irq_alloc_info *info)
4063 switch (info->type) {
4064 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4065 devid = get_ioapic_devid(info->ioapic_id);
4067 case X86_IRQ_ALLOC_TYPE_HPET:
4068 devid = get_hpet_devid(info->hpet_id);
4070 case X86_IRQ_ALLOC_TYPE_MSI:
4071 case X86_IRQ_ALLOC_TYPE_MSIX:
4072 devid = get_device_id(&info->msi_dev->dev);
4082 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4084 struct amd_iommu *iommu;
4090 devid = get_devid(info);
4092 iommu = amd_iommu_rlookup_table[devid];
4094 return iommu->ir_domain;
4100 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4102 struct amd_iommu *iommu;
4108 switch (info->type) {
4109 case X86_IRQ_ALLOC_TYPE_MSI:
4110 case X86_IRQ_ALLOC_TYPE_MSIX:
4111 devid = get_device_id(&info->msi_dev->dev);
4115 iommu = amd_iommu_rlookup_table[devid];
4117 return iommu->msi_domain;
4126 struct irq_remap_ops amd_iommu_irq_ops = {
4127 .prepare = amd_iommu_prepare,
4128 .enable = amd_iommu_enable,
4129 .disable = amd_iommu_disable,
4130 .reenable = amd_iommu_reenable,
4131 .enable_faulting = amd_iommu_enable_faulting,
4132 .get_ir_irq_domain = get_ir_irq_domain,
4133 .get_irq_domain = get_irq_domain,
4136 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4137 struct irq_cfg *irq_cfg,
4138 struct irq_alloc_info *info,
4139 int devid, int index, int sub_handle)
4141 struct irq_2_irte *irte_info = &data->irq_2_irte;
4142 struct msi_msg *msg = &data->msi_entry;
4143 struct IO_APIC_route_entry *entry;
4144 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4149 data->irq_2_irte.devid = devid;
4150 data->irq_2_irte.index = index + sub_handle;
4151 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4152 apic->irq_dest_mode, irq_cfg->vector,
4153 irq_cfg->dest_apicid, devid);
4155 switch (info->type) {
4156 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4157 /* Setup IOAPIC entry */
4158 entry = info->ioapic_entry;
4159 info->ioapic_entry = NULL;
4160 memset(entry, 0, sizeof(*entry));
4161 entry->vector = index;
4163 entry->trigger = info->ioapic_trigger;
4164 entry->polarity = info->ioapic_polarity;
4165 /* Mask level triggered irqs. */
4166 if (info->ioapic_trigger)
4170 case X86_IRQ_ALLOC_TYPE_HPET:
4171 case X86_IRQ_ALLOC_TYPE_MSI:
4172 case X86_IRQ_ALLOC_TYPE_MSIX:
4173 msg->address_hi = MSI_ADDR_BASE_HI;
4174 msg->address_lo = MSI_ADDR_BASE_LO;
4175 msg->data = irte_info->index;
4184 struct amd_irte_ops irte_32_ops = {
4185 .prepare = irte_prepare,
4186 .activate = irte_activate,
4187 .deactivate = irte_deactivate,
4188 .set_affinity = irte_set_affinity,
4189 .set_allocated = irte_set_allocated,
4190 .is_allocated = irte_is_allocated,
4191 .clear_allocated = irte_clear_allocated,
4194 struct amd_irte_ops irte_128_ops = {
4195 .prepare = irte_ga_prepare,
4196 .activate = irte_ga_activate,
4197 .deactivate = irte_ga_deactivate,
4198 .set_affinity = irte_ga_set_affinity,
4199 .set_allocated = irte_ga_set_allocated,
4200 .is_allocated = irte_ga_is_allocated,
4201 .clear_allocated = irte_ga_clear_allocated,
4204 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4205 unsigned int nr_irqs, void *arg)
4207 struct irq_alloc_info *info = arg;
4208 struct irq_data *irq_data;
4209 struct amd_ir_data *data = NULL;
4210 struct irq_cfg *cfg;
4216 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4217 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4221 * With IRQ remapping enabled, don't need contiguous CPU vectors
4222 * to support multiple MSI interrupts.
4224 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4225 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4227 devid = get_devid(info);
4231 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4235 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4236 struct irq_remap_table *table;
4237 struct amd_iommu *iommu;
4239 table = alloc_irq_table(devid, NULL);
4241 if (!table->min_index) {
4243 * Keep the first 32 indexes free for IOAPIC
4246 table->min_index = 32;
4247 iommu = amd_iommu_rlookup_table[devid];
4248 for (i = 0; i < 32; ++i)
4249 iommu->irte_ops->set_allocated(table, i);
4251 WARN_ON(table->min_index != 32);
4252 index = info->ioapic_pin;
4256 } else if (info->type == X86_IRQ_ALLOC_TYPE_MSI ||
4257 info->type == X86_IRQ_ALLOC_TYPE_MSIX) {
4258 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4260 index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev);
4262 index = alloc_irq_index(devid, nr_irqs, false, NULL);
4266 pr_warn("Failed to allocate IRTE\n");
4268 goto out_free_parent;
4271 for (i = 0; i < nr_irqs; i++) {
4272 irq_data = irq_domain_get_irq_data(domain, virq + i);
4273 cfg = irqd_cfg(irq_data);
4274 if (!irq_data || !cfg) {
4280 data = kzalloc(sizeof(*data), GFP_KERNEL);
4284 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4285 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4287 data->entry = kzalloc(sizeof(struct irte_ga),
4294 irq_data->hwirq = (devid << 16) + i;
4295 irq_data->chip_data = data;
4296 irq_data->chip = &amd_ir_chip;
4297 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4298 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4304 for (i--; i >= 0; i--) {
4305 irq_data = irq_domain_get_irq_data(domain, virq + i);
4307 kfree(irq_data->chip_data);
4309 for (i = 0; i < nr_irqs; i++)
4310 free_irte(devid, index + i);
4312 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4316 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4317 unsigned int nr_irqs)
4319 struct irq_2_irte *irte_info;
4320 struct irq_data *irq_data;
4321 struct amd_ir_data *data;
4324 for (i = 0; i < nr_irqs; i++) {
4325 irq_data = irq_domain_get_irq_data(domain, virq + i);
4326 if (irq_data && irq_data->chip_data) {
4327 data = irq_data->chip_data;
4328 irte_info = &data->irq_2_irte;
4329 free_irte(irte_info->devid, irte_info->index);
4334 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4337 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4338 struct amd_ir_data *ir_data,
4339 struct irq_2_irte *irte_info,
4340 struct irq_cfg *cfg);
4342 static int irq_remapping_activate(struct irq_domain *domain,
4343 struct irq_data *irq_data, bool reserve)
4345 struct amd_ir_data *data = irq_data->chip_data;
4346 struct irq_2_irte *irte_info = &data->irq_2_irte;
4347 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4348 struct irq_cfg *cfg = irqd_cfg(irq_data);
4353 iommu->irte_ops->activate(data->entry, irte_info->devid,
4355 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4359 static void irq_remapping_deactivate(struct irq_domain *domain,
4360 struct irq_data *irq_data)
4362 struct amd_ir_data *data = irq_data->chip_data;
4363 struct irq_2_irte *irte_info = &data->irq_2_irte;
4364 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4367 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4371 static const struct irq_domain_ops amd_ir_domain_ops = {
4372 .alloc = irq_remapping_alloc,
4373 .free = irq_remapping_free,
4374 .activate = irq_remapping_activate,
4375 .deactivate = irq_remapping_deactivate,
4378 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4380 struct amd_iommu *iommu;
4381 struct amd_iommu_pi_data *pi_data = vcpu_info;
4382 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4383 struct amd_ir_data *ir_data = data->chip_data;
4384 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4385 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4386 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4389 * This device has never been set up for guest mode.
4390 * we should not modify the IRTE
4392 if (!dev_data || !dev_data->use_vapic)
4395 pi_data->ir_data = ir_data;
4398 * SVM tries to set up for VAPIC mode, but we are in
4399 * legacy mode. So, we force legacy mode instead.
4401 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4402 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4404 pi_data->is_guest_mode = false;
4407 iommu = amd_iommu_rlookup_table[irte_info->devid];
4411 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4412 if (pi_data->is_guest_mode) {
4414 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4415 irte->hi.fields.vector = vcpu_pi_info->vector;
4416 irte->lo.fields_vapic.ga_log_intr = 1;
4417 irte->lo.fields_vapic.guest_mode = 1;
4418 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4420 ir_data->cached_ga_tag = pi_data->ga_tag;
4423 struct irq_cfg *cfg = irqd_cfg(data);
4427 irte->hi.fields.vector = cfg->vector;
4428 irte->lo.fields_remap.guest_mode = 0;
4429 irte->lo.fields_remap.destination =
4430 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4431 irte->hi.fields.destination =
4432 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4433 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4434 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4437 * This communicates the ga_tag back to the caller
4438 * so that it can do all the necessary clean up.
4440 ir_data->cached_ga_tag = 0;
4443 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4447 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4448 struct amd_ir_data *ir_data,
4449 struct irq_2_irte *irte_info,
4450 struct irq_cfg *cfg)
4454 * Atomically updates the IRTE with the new destination, vector
4455 * and flushes the interrupt entry cache.
4457 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4458 irte_info->index, cfg->vector,
4462 static int amd_ir_set_affinity(struct irq_data *data,
4463 const struct cpumask *mask, bool force)
4465 struct amd_ir_data *ir_data = data->chip_data;
4466 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4467 struct irq_cfg *cfg = irqd_cfg(data);
4468 struct irq_data *parent = data->parent_data;
4469 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4475 ret = parent->chip->irq_set_affinity(parent, mask, force);
4476 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4479 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4481 * After this point, all the interrupts will start arriving
4482 * at the new destination. So, time to cleanup the previous
4483 * vector allocation.
4485 send_cleanup_vector(cfg);
4487 return IRQ_SET_MASK_OK_DONE;
4490 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4492 struct amd_ir_data *ir_data = irq_data->chip_data;
4494 *msg = ir_data->msi_entry;
4497 static struct irq_chip amd_ir_chip = {
4499 .irq_ack = apic_ack_irq,
4500 .irq_set_affinity = amd_ir_set_affinity,
4501 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4502 .irq_compose_msi_msg = ir_compose_msi_msg,
4505 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4507 struct fwnode_handle *fn;
4509 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4512 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4513 if (!iommu->ir_domain) {
4514 irq_domain_free_fwnode(fn);
4518 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4519 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4525 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4527 unsigned long flags;
4528 struct amd_iommu *iommu;
4529 struct irq_remap_table *table;
4530 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4531 int devid = ir_data->irq_2_irte.devid;
4532 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4533 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4535 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4536 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4539 iommu = amd_iommu_rlookup_table[devid];
4543 table = get_irq_table(devid);
4547 raw_spin_lock_irqsave(&table->lock, flags);
4549 if (ref->lo.fields_vapic.guest_mode) {
4551 ref->lo.fields_vapic.destination =
4552 APICID_TO_IRTE_DEST_LO(cpu);
4553 ref->hi.fields.destination =
4554 APICID_TO_IRTE_DEST_HI(cpu);
4556 ref->lo.fields_vapic.is_run = is_run;
4560 raw_spin_unlock_irqrestore(&table->lock, flags);
4562 iommu_flush_irt(iommu, devid);
4563 iommu_completion_wait(iommu);
4566 EXPORT_SYMBOL(amd_iommu_update_ga);