1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-map-ops.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/irqdomain.h>
32 #include <linux/percpu.h>
33 #include <linux/iova.h>
34 #include <asm/irq_remapping.h>
35 #include <asm/io_apic.h>
37 #include <asm/hw_irq.h>
38 #include <asm/msidef.h>
39 #include <asm/proto.h>
40 #include <asm/iommu.h>
44 #include "amd_iommu.h"
45 #include "../irq_remapping.h"
47 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
49 #define LOOP_TIMEOUT 100000
51 /* IO virtual address start page frame number */
52 #define IOVA_START_PFN (1)
53 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
55 /* Reserved IOVA ranges */
56 #define MSI_RANGE_START (0xfee00000)
57 #define MSI_RANGE_END (0xfeefffff)
58 #define HT_RANGE_START (0xfd00000000ULL)
59 #define HT_RANGE_END (0xffffffffffULL)
62 * This bitmap is used to advertise the page sizes our hardware support
63 * to the IOMMU core, which will then use this information to split
64 * physically contiguous memory regions it is mapping into page sizes
67 * 512GB Pages are not supported due to a hardware bug
69 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
71 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
73 static DEFINE_SPINLOCK(pd_bitmap_lock);
75 /* List of all available dev_data structures */
76 static LLIST_HEAD(dev_data_list);
78 LIST_HEAD(ioapic_map);
80 LIST_HEAD(acpihid_map);
83 * Domain for untranslated devices - only allocated
84 * if iommu=pt passed on kernel cmd line.
86 const struct iommu_ops amd_iommu_ops;
88 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
89 int amd_iommu_max_glx_val = -1;
92 * general struct to manage commands send to an IOMMU
98 struct kmem_cache *amd_iommu_irq_cache;
100 static void update_domain(struct protection_domain *domain);
101 static void detach_device(struct device *dev);
102 static void update_and_flush_device_table(struct protection_domain *domain,
103 struct domain_pgtable *pgtable);
105 /****************************************************************************
109 ****************************************************************************/
111 static inline u16 get_pci_device_id(struct device *dev)
113 struct pci_dev *pdev = to_pci_dev(dev);
115 return pci_dev_id(pdev);
118 static inline int get_acpihid_device_id(struct device *dev,
119 struct acpihid_map_entry **entry)
121 struct acpi_device *adev = ACPI_COMPANION(dev);
122 struct acpihid_map_entry *p;
127 list_for_each_entry(p, &acpihid_map, list) {
128 if (acpi_dev_hid_uid_match(adev, p->hid,
129 p->uid[0] ? p->uid : NULL)) {
138 static inline int get_device_id(struct device *dev)
143 devid = get_pci_device_id(dev);
145 devid = get_acpihid_device_id(dev, NULL);
150 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
152 return container_of(dom, struct protection_domain, domain);
155 static void amd_iommu_domain_get_pgtable(struct protection_domain *domain,
156 struct domain_pgtable *pgtable)
158 u64 pt_root = atomic64_read(&domain->pt_root);
160 pgtable->root = (u64 *)(pt_root & PAGE_MASK);
161 pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */
164 static void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
166 atomic64_set(&domain->pt_root, root);
169 static void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
171 amd_iommu_domain_set_pt_root(domain, 0);
174 static void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
179 /* lowest 3 bits encode pgtable mode */
181 pt_root |= (u64)root;
183 amd_iommu_domain_set_pt_root(domain, pt_root);
186 static struct iommu_dev_data *alloc_dev_data(u16 devid)
188 struct iommu_dev_data *dev_data;
190 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
194 spin_lock_init(&dev_data->lock);
195 dev_data->devid = devid;
196 ratelimit_default_init(&dev_data->rs);
198 llist_add(&dev_data->dev_data_list, &dev_data_list);
202 static struct iommu_dev_data *search_dev_data(u16 devid)
204 struct iommu_dev_data *dev_data;
205 struct llist_node *node;
207 if (llist_empty(&dev_data_list))
210 node = dev_data_list.first;
211 llist_for_each_entry(dev_data, node, dev_data_list) {
212 if (dev_data->devid == devid)
219 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
221 u16 devid = pci_dev_id(pdev);
226 amd_iommu_rlookup_table[alias] =
227 amd_iommu_rlookup_table[devid];
228 memcpy(amd_iommu_dev_table[alias].data,
229 amd_iommu_dev_table[devid].data,
230 sizeof(amd_iommu_dev_table[alias].data));
235 static void clone_aliases(struct pci_dev *pdev)
241 * The IVRS alias stored in the alias table may not be
242 * part of the PCI DMA aliases if it's bus differs
243 * from the original device.
245 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
247 pci_for_each_dma_alias(pdev, clone_alias, NULL);
250 static struct pci_dev *setup_aliases(struct device *dev)
252 struct pci_dev *pdev = to_pci_dev(dev);
255 /* For ACPI HID devices, there are no aliases */
256 if (!dev_is_pci(dev))
260 * Add the IVRS alias to the pci aliases if it is on the same
261 * bus. The IVRS table may know about a quirk that we don't.
263 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
264 if (ivrs_alias != pci_dev_id(pdev) &&
265 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
266 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
273 static struct iommu_dev_data *find_dev_data(u16 devid)
275 struct iommu_dev_data *dev_data;
276 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
278 dev_data = search_dev_data(devid);
280 if (dev_data == NULL) {
281 dev_data = alloc_dev_data(devid);
285 if (translation_pre_enabled(iommu))
286 dev_data->defer_attach = true;
293 * Find or create an IOMMU group for a acpihid device.
295 static struct iommu_group *acpihid_device_group(struct device *dev)
297 struct acpihid_map_entry *p, *entry = NULL;
300 devid = get_acpihid_device_id(dev, &entry);
302 return ERR_PTR(devid);
304 list_for_each_entry(p, &acpihid_map, list) {
305 if ((devid == p->devid) && p->group)
306 entry->group = p->group;
310 entry->group = generic_device_group(dev);
312 iommu_group_ref_get(entry->group);
317 static bool pci_iommuv2_capable(struct pci_dev *pdev)
319 static const int caps[] = {
321 PCI_EXT_CAP_ID_PASID,
325 if (!pci_ats_supported(pdev))
328 for (i = 0; i < 2; ++i) {
329 pos = pci_find_ext_capability(pdev, caps[i]);
337 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
339 struct iommu_dev_data *dev_data;
341 dev_data = dev_iommu_priv_get(&pdev->dev);
343 return dev_data->errata & (1 << erratum) ? true : false;
347 * This function checks if the driver got a valid device from the caller to
348 * avoid dereferencing invalid pointers.
350 static bool check_device(struct device *dev)
357 devid = get_device_id(dev);
361 /* Out of our scope? */
362 if (devid > amd_iommu_last_bdf)
365 if (amd_iommu_rlookup_table[devid] == NULL)
371 static int iommu_init_device(struct device *dev)
373 struct iommu_dev_data *dev_data;
376 if (dev_iommu_priv_get(dev))
379 devid = get_device_id(dev);
383 dev_data = find_dev_data(devid);
387 dev_data->pdev = setup_aliases(dev);
390 * By default we use passthrough mode for IOMMUv2 capable device.
391 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
392 * invalid address), we ignore the capability for the device so
393 * it'll be forced to go into translation mode.
395 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
396 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
397 struct amd_iommu *iommu;
399 iommu = amd_iommu_rlookup_table[dev_data->devid];
400 dev_data->iommu_v2 = iommu->is_iommu_v2;
403 dev_iommu_priv_set(dev, dev_data);
408 static void iommu_ignore_device(struct device *dev)
412 devid = get_device_id(dev);
416 amd_iommu_rlookup_table[devid] = NULL;
417 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
422 static void amd_iommu_uninit_device(struct device *dev)
424 struct iommu_dev_data *dev_data;
426 dev_data = dev_iommu_priv_get(dev);
430 if (dev_data->domain)
433 dev_iommu_priv_set(dev, NULL);
436 * We keep dev_data around for unplugged devices and reuse it when the
437 * device is re-plugged - not doing so would introduce a ton of races.
442 * Helper function to get the first pte of a large mapping
444 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
445 unsigned long *count)
447 unsigned long pte_mask, pg_size, cnt;
450 pg_size = PTE_PAGE_SIZE(*pte);
451 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
452 pte_mask = ~((cnt << 3) - 1);
453 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
456 *page_size = pg_size;
464 /****************************************************************************
466 * Interrupt handling functions
468 ****************************************************************************/
470 static void dump_dte_entry(u16 devid)
474 for (i = 0; i < 4; ++i)
475 pr_err("DTE[%d]: %016llx\n", i,
476 amd_iommu_dev_table[devid].data[i]);
479 static void dump_command(unsigned long phys_addr)
481 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
484 for (i = 0; i < 4; ++i)
485 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
488 static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
490 struct iommu_dev_data *dev_data = NULL;
491 int devid, vmg_tag, flags;
492 struct pci_dev *pdev;
495 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
496 vmg_tag = (event[1]) & 0xFFFF;
497 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
498 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
500 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
503 dev_data = dev_iommu_priv_get(&pdev->dev);
505 if (dev_data && __ratelimit(&dev_data->rs)) {
506 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
507 vmg_tag, spa, flags);
509 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
510 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
511 vmg_tag, spa, flags);
518 static void amd_iommu_report_rmp_fault(volatile u32 *event)
520 struct iommu_dev_data *dev_data = NULL;
521 int devid, flags_rmp, vmg_tag, flags;
522 struct pci_dev *pdev;
525 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
526 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
527 vmg_tag = (event[1]) & 0xFFFF;
528 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
529 gpa = ((u64)event[3] << 32) | event[2];
531 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
534 dev_data = dev_iommu_priv_get(&pdev->dev);
536 if (dev_data && __ratelimit(&dev_data->rs)) {
537 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
538 vmg_tag, gpa, flags_rmp, flags);
540 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
541 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
542 vmg_tag, gpa, flags_rmp, flags);
549 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
550 u64 address, int flags)
552 struct iommu_dev_data *dev_data = NULL;
553 struct pci_dev *pdev;
555 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
558 dev_data = dev_iommu_priv_get(&pdev->dev);
560 if (dev_data && __ratelimit(&dev_data->rs)) {
561 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
562 domain_id, address, flags);
563 } else if (printk_ratelimit()) {
564 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
565 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
566 domain_id, address, flags);
573 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
575 struct device *dev = iommu->iommu.dev;
576 int type, devid, flags, tag;
577 volatile u32 *event = __evt;
583 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
584 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
585 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
586 (event[1] & EVENT_DOMID_MASK_LO);
587 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
588 address = (u64)(((u64)event[3]) << 32) | event[2];
591 /* Did we hit the erratum? */
592 if (++count == LOOP_TIMEOUT) {
593 pr_err("No event written to event log\n");
600 if (type == EVENT_TYPE_IO_FAULT) {
601 amd_iommu_report_page_fault(devid, pasid, address, flags);
606 case EVENT_TYPE_ILL_DEV:
607 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
608 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 pasid, address, flags);
610 dump_dte_entry(devid);
612 case EVENT_TYPE_DEV_TAB_ERR:
613 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
614 "address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
618 case EVENT_TYPE_PAGE_TAB_ERR:
619 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
623 case EVENT_TYPE_ILL_CMD:
624 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
625 dump_command(address);
627 case EVENT_TYPE_CMD_HARD_ERR:
628 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
631 case EVENT_TYPE_IOTLB_INV_TO:
632 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
633 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
636 case EVENT_TYPE_INV_DEV_REQ:
637 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
638 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
639 pasid, address, flags);
641 case EVENT_TYPE_RMP_FAULT:
642 amd_iommu_report_rmp_fault(event);
644 case EVENT_TYPE_RMP_HW_ERR:
645 amd_iommu_report_rmp_hw_error(event);
647 case EVENT_TYPE_INV_PPR_REQ:
648 pasid = PPR_PASID(*((u64 *)__evt));
649 tag = event[1] & 0x03FF;
650 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
651 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
652 pasid, address, flags, tag);
655 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
656 event[0], event[1], event[2], event[3]);
659 memset(__evt, 0, 4 * sizeof(u32));
662 static void iommu_poll_events(struct amd_iommu *iommu)
666 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
669 while (head != tail) {
670 iommu_print_event(iommu, iommu->evt_buf + head);
671 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
674 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
677 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
679 struct amd_iommu_fault fault;
681 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
682 pr_err_ratelimited("Unknown PPR request received\n");
686 fault.address = raw[1];
687 fault.pasid = PPR_PASID(raw[0]);
688 fault.device_id = PPR_DEVID(raw[0]);
689 fault.tag = PPR_TAG(raw[0]);
690 fault.flags = PPR_FLAGS(raw[0]);
692 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
695 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
699 if (iommu->ppr_log == NULL)
702 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
703 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
705 while (head != tail) {
710 raw = (u64 *)(iommu->ppr_log + head);
713 * Hardware bug: Interrupt may arrive before the entry is
714 * written to memory. If this happens we need to wait for the
717 for (i = 0; i < LOOP_TIMEOUT; ++i) {
718 if (PPR_REQ_TYPE(raw[0]) != 0)
723 /* Avoid memcpy function-call overhead */
728 * To detect the hardware bug we need to clear the entry
731 raw[0] = raw[1] = 0UL;
733 /* Update head pointer of hardware ring-buffer */
734 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
735 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
737 /* Handle PPR entry */
738 iommu_handle_ppr_entry(iommu, entry);
740 /* Refresh ring-buffer information */
741 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
742 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
746 #ifdef CONFIG_IRQ_REMAP
747 static int (*iommu_ga_log_notifier)(u32);
749 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
751 iommu_ga_log_notifier = notifier;
755 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
757 static void iommu_poll_ga_log(struct amd_iommu *iommu)
759 u32 head, tail, cnt = 0;
761 if (iommu->ga_log == NULL)
764 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
765 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
767 while (head != tail) {
771 raw = (u64 *)(iommu->ga_log + head);
774 /* Avoid memcpy function-call overhead */
777 /* Update head pointer of hardware ring-buffer */
778 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
779 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
781 /* Handle GA entry */
782 switch (GA_REQ_TYPE(log_entry)) {
784 if (!iommu_ga_log_notifier)
787 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
788 __func__, GA_DEVID(log_entry),
791 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
792 pr_err("GA log notifier failed.\n");
801 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
803 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
804 pci_dev_has_special_msi_domain(to_pci_dev(dev)))
807 dev_set_msi_domain(dev, iommu->msi_domain);
810 #else /* CONFIG_IRQ_REMAP */
812 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
813 #endif /* !CONFIG_IRQ_REMAP */
815 #define AMD_IOMMU_INT_MASK \
816 (MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \
817 MMIO_STATUS_EVT_INT_MASK | \
818 MMIO_STATUS_PPR_INT_MASK | \
819 MMIO_STATUS_GALOG_INT_MASK)
821 irqreturn_t amd_iommu_int_thread(int irq, void *data)
823 struct amd_iommu *iommu = (struct amd_iommu *) data;
824 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
826 while (status & AMD_IOMMU_INT_MASK) {
827 /* Enable interrupt sources again */
828 writel(AMD_IOMMU_INT_MASK,
829 iommu->mmio_base + MMIO_STATUS_OFFSET);
831 if (status & MMIO_STATUS_EVT_INT_MASK) {
832 pr_devel("Processing IOMMU Event Log\n");
833 iommu_poll_events(iommu);
836 if (status & MMIO_STATUS_PPR_INT_MASK) {
837 pr_devel("Processing IOMMU PPR Log\n");
838 iommu_poll_ppr_log(iommu);
841 #ifdef CONFIG_IRQ_REMAP
842 if (status & MMIO_STATUS_GALOG_INT_MASK) {
843 pr_devel("Processing IOMMU GA Log\n");
844 iommu_poll_ga_log(iommu);
848 if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) {
849 pr_info_ratelimited("IOMMU event log overflow\n");
850 amd_iommu_restart_event_logging(iommu);
854 * Hardware bug: ERBT1312
855 * When re-enabling interrupt (by writing 1
856 * to clear the bit), the hardware might also try to set
857 * the interrupt bit in the event status register.
858 * In this scenario, the bit will be set, and disable
859 * subsequent interrupts.
861 * Workaround: The IOMMU driver should read back the
862 * status register and check if the interrupt bits are cleared.
863 * If not, driver will need to go through the interrupt handler
864 * again and re-clear the bits
866 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
871 irqreturn_t amd_iommu_int_handler(int irq, void *data)
873 return IRQ_WAKE_THREAD;
876 /****************************************************************************
878 * IOMMU command queuing functions
880 ****************************************************************************/
882 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
886 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
891 if (i == LOOP_TIMEOUT) {
892 pr_alert("Completion-Wait loop timed out\n");
899 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
900 struct iommu_cmd *cmd)
905 /* Copy command to buffer */
906 tail = iommu->cmd_buf_tail;
907 target = iommu->cmd_buf + tail;
908 memcpy(target, cmd, sizeof(*cmd));
910 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
911 iommu->cmd_buf_tail = tail;
913 /* Tell the IOMMU about it */
914 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
917 static void build_completion_wait(struct iommu_cmd *cmd,
918 struct amd_iommu *iommu,
921 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
923 memset(cmd, 0, sizeof(*cmd));
924 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
925 cmd->data[1] = upper_32_bits(paddr);
926 cmd->data[2] = lower_32_bits(data);
927 cmd->data[3] = upper_32_bits(data);
928 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
931 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
933 memset(cmd, 0, sizeof(*cmd));
934 cmd->data[0] = devid;
935 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
938 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
939 size_t size, u16 domid, int pde)
944 pages = iommu_num_pages(address, size, PAGE_SIZE);
949 * If we have to flush more than one page, flush all
950 * TLB entries for this domain
952 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
956 address &= PAGE_MASK;
958 memset(cmd, 0, sizeof(*cmd));
959 cmd->data[1] |= domid;
960 cmd->data[2] = lower_32_bits(address);
961 cmd->data[3] = upper_32_bits(address);
962 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
963 if (s) /* size bit - we flush more than one 4kb page */
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
965 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
966 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
969 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
970 u64 address, size_t size)
975 pages = iommu_num_pages(address, size, PAGE_SIZE);
980 * If we have to flush more than one page, flush all
981 * TLB entries for this domain
983 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
987 address &= PAGE_MASK;
989 memset(cmd, 0, sizeof(*cmd));
990 cmd->data[0] = devid;
991 cmd->data[0] |= (qdep & 0xff) << 24;
992 cmd->data[1] = devid;
993 cmd->data[2] = lower_32_bits(address);
994 cmd->data[3] = upper_32_bits(address);
995 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
997 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1000 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
1001 u64 address, bool size)
1003 memset(cmd, 0, sizeof(*cmd));
1005 address &= ~(0xfffULL);
1007 cmd->data[0] = pasid;
1008 cmd->data[1] = domid;
1009 cmd->data[2] = lower_32_bits(address);
1010 cmd->data[3] = upper_32_bits(address);
1011 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1012 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1014 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1015 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1018 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1019 int qdep, u64 address, bool size)
1021 memset(cmd, 0, sizeof(*cmd));
1023 address &= ~(0xfffULL);
1025 cmd->data[0] = devid;
1026 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1027 cmd->data[0] |= (qdep & 0xff) << 24;
1028 cmd->data[1] = devid;
1029 cmd->data[1] |= (pasid & 0xff) << 16;
1030 cmd->data[2] = lower_32_bits(address);
1031 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1032 cmd->data[3] = upper_32_bits(address);
1034 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1035 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1038 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1039 int status, int tag, bool gn)
1041 memset(cmd, 0, sizeof(*cmd));
1043 cmd->data[0] = devid;
1045 cmd->data[1] = pasid;
1046 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1048 cmd->data[3] = tag & 0x1ff;
1049 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1051 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1054 static void build_inv_all(struct iommu_cmd *cmd)
1056 memset(cmd, 0, sizeof(*cmd));
1057 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1060 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1062 memset(cmd, 0, sizeof(*cmd));
1063 cmd->data[0] = devid;
1064 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1068 * Writes the command to the IOMMUs command buffer and informs the
1069 * hardware about the new command.
1071 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1072 struct iommu_cmd *cmd,
1075 unsigned int count = 0;
1076 u32 left, next_tail;
1078 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1080 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1083 /* Skip udelay() the first time around */
1085 if (count == LOOP_TIMEOUT) {
1086 pr_err("Command buffer timeout\n");
1093 /* Update head and recheck remaining space */
1094 iommu->cmd_buf_head = readl(iommu->mmio_base +
1095 MMIO_CMD_HEAD_OFFSET);
1100 copy_cmd_to_buffer(iommu, cmd);
1102 /* Do we need to make sure all commands are processed? */
1103 iommu->need_sync = sync;
1108 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1109 struct iommu_cmd *cmd,
1112 unsigned long flags;
1115 raw_spin_lock_irqsave(&iommu->lock, flags);
1116 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1117 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1122 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1124 return iommu_queue_command_sync(iommu, cmd, true);
1128 * This function queues a completion wait command into the command
1129 * buffer of an IOMMU
1131 static int iommu_completion_wait(struct amd_iommu *iommu)
1133 struct iommu_cmd cmd;
1134 unsigned long flags;
1138 if (!iommu->need_sync)
1141 raw_spin_lock_irqsave(&iommu->lock, flags);
1143 data = ++iommu->cmd_sem_val;
1144 build_completion_wait(&cmd, iommu, data);
1146 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1150 ret = wait_on_sem(iommu, data);
1153 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1158 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1160 struct iommu_cmd cmd;
1162 build_inv_dte(&cmd, devid);
1164 return iommu_queue_command(iommu, &cmd);
1167 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1171 for (devid = 0; devid <= 0xffff; ++devid)
1172 iommu_flush_dte(iommu, devid);
1174 iommu_completion_wait(iommu);
1178 * This function uses heavy locking and may disable irqs for some time. But
1179 * this is no issue because it is only called during resume.
1181 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1185 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1186 struct iommu_cmd cmd;
1187 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1189 iommu_queue_command(iommu, &cmd);
1192 iommu_completion_wait(iommu);
1195 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1197 struct iommu_cmd cmd;
1199 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1201 iommu_queue_command(iommu, &cmd);
1203 iommu_completion_wait(iommu);
1206 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1208 struct iommu_cmd cmd;
1210 build_inv_all(&cmd);
1212 iommu_queue_command(iommu, &cmd);
1213 iommu_completion_wait(iommu);
1216 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1218 struct iommu_cmd cmd;
1220 build_inv_irt(&cmd, devid);
1222 iommu_queue_command(iommu, &cmd);
1225 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1229 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1230 iommu_flush_irt(iommu, devid);
1232 iommu_completion_wait(iommu);
1235 void iommu_flush_all_caches(struct amd_iommu *iommu)
1237 if (iommu_feature(iommu, FEATURE_IA)) {
1238 amd_iommu_flush_all(iommu);
1240 amd_iommu_flush_dte_all(iommu);
1241 amd_iommu_flush_irt_all(iommu);
1242 amd_iommu_flush_tlb_all(iommu);
1247 * Command send function for flushing on-device TLB
1249 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1250 u64 address, size_t size)
1252 struct amd_iommu *iommu;
1253 struct iommu_cmd cmd;
1256 qdep = dev_data->ats.qdep;
1257 iommu = amd_iommu_rlookup_table[dev_data->devid];
1259 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1261 return iommu_queue_command(iommu, &cmd);
1264 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1266 struct amd_iommu *iommu = data;
1268 return iommu_flush_dte(iommu, alias);
1272 * Command send function for invalidating a device table entry
1274 static int device_flush_dte(struct iommu_dev_data *dev_data)
1276 struct amd_iommu *iommu;
1280 iommu = amd_iommu_rlookup_table[dev_data->devid];
1283 ret = pci_for_each_dma_alias(dev_data->pdev,
1284 device_flush_dte_alias, iommu);
1286 ret = iommu_flush_dte(iommu, dev_data->devid);
1290 alias = amd_iommu_alias_table[dev_data->devid];
1291 if (alias != dev_data->devid) {
1292 ret = iommu_flush_dte(iommu, alias);
1297 if (dev_data->ats.enabled)
1298 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1304 * TLB invalidation function which is called from the mapping functions.
1305 * It invalidates a single PTE if the range to flush is within a single
1306 * page. Otherwise it flushes the whole TLB of the IOMMU.
1308 static void __domain_flush_pages(struct protection_domain *domain,
1309 u64 address, size_t size, int pde)
1311 struct iommu_dev_data *dev_data;
1312 struct iommu_cmd cmd;
1315 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1317 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1318 if (!domain->dev_iommu[i])
1322 * Devices of this domain are behind this IOMMU
1323 * We need a TLB flush
1325 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1328 list_for_each_entry(dev_data, &domain->dev_list, list) {
1330 if (!dev_data->ats.enabled)
1333 ret |= device_flush_iotlb(dev_data, address, size);
1339 static void domain_flush_pages(struct protection_domain *domain,
1340 u64 address, size_t size)
1342 __domain_flush_pages(domain, address, size, 0);
1345 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1346 static void domain_flush_tlb_pde(struct protection_domain *domain)
1348 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1351 static void domain_flush_complete(struct protection_domain *domain)
1355 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1356 if (domain && !domain->dev_iommu[i])
1360 * Devices of this domain are behind this IOMMU
1361 * We need to wait for completion of all commands.
1363 iommu_completion_wait(amd_iommus[i]);
1367 /* Flush the not present cache if it exists */
1368 static void domain_flush_np_cache(struct protection_domain *domain,
1369 dma_addr_t iova, size_t size)
1371 if (unlikely(amd_iommu_np_cache)) {
1372 unsigned long flags;
1374 spin_lock_irqsave(&domain->lock, flags);
1375 domain_flush_pages(domain, iova, size);
1376 domain_flush_complete(domain);
1377 spin_unlock_irqrestore(&domain->lock, flags);
1383 * This function flushes the DTEs for all devices in domain
1385 static void domain_flush_devices(struct protection_domain *domain)
1387 struct iommu_dev_data *dev_data;
1389 list_for_each_entry(dev_data, &domain->dev_list, list)
1390 device_flush_dte(dev_data);
1393 /****************************************************************************
1395 * The functions below are used the create the page table mappings for
1396 * unity mapped regions.
1398 ****************************************************************************/
1400 static void free_page_list(struct page *freelist)
1402 while (freelist != NULL) {
1403 unsigned long p = (unsigned long)page_address(freelist);
1404 freelist = freelist->freelist;
1409 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1411 struct page *p = virt_to_page((void *)pt);
1413 p->freelist = freelist;
1418 #define DEFINE_FREE_PT_FN(LVL, FN) \
1419 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1427 for (i = 0; i < 512; ++i) { \
1428 /* PTE present? */ \
1429 if (!IOMMU_PTE_PRESENT(pt[i])) \
1433 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1434 PM_PTE_LEVEL(pt[i]) == 7) \
1437 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1438 freelist = FN(p, freelist); \
1441 return free_pt_page((unsigned long)pt, freelist); \
1444 DEFINE_FREE_PT_FN(l2, free_pt_page)
1445 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1446 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1447 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1448 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1450 static struct page *free_sub_pt(unsigned long root, int mode,
1451 struct page *freelist)
1454 case PAGE_MODE_NONE:
1455 case PAGE_MODE_7_LEVEL:
1457 case PAGE_MODE_1_LEVEL:
1458 freelist = free_pt_page(root, freelist);
1460 case PAGE_MODE_2_LEVEL:
1461 freelist = free_pt_l2(root, freelist);
1463 case PAGE_MODE_3_LEVEL:
1464 freelist = free_pt_l3(root, freelist);
1466 case PAGE_MODE_4_LEVEL:
1467 freelist = free_pt_l4(root, freelist);
1469 case PAGE_MODE_5_LEVEL:
1470 freelist = free_pt_l5(root, freelist);
1472 case PAGE_MODE_6_LEVEL:
1473 freelist = free_pt_l6(root, freelist);
1482 static void free_pagetable(struct domain_pgtable *pgtable)
1484 struct page *freelist = NULL;
1487 if (pgtable->mode == PAGE_MODE_NONE)
1490 BUG_ON(pgtable->mode < PAGE_MODE_NONE ||
1491 pgtable->mode > PAGE_MODE_6_LEVEL);
1493 root = (unsigned long)pgtable->root;
1494 freelist = free_sub_pt(root, pgtable->mode, freelist);
1496 free_page_list(freelist);
1500 * This function is used to add another level to an IO page table. Adding
1501 * another level increases the size of the address space by 9 bits to a size up
1504 static bool increase_address_space(struct protection_domain *domain,
1505 unsigned long address,
1508 struct domain_pgtable pgtable;
1509 unsigned long flags;
1513 pte = (void *)get_zeroed_page(gfp);
1517 spin_lock_irqsave(&domain->lock, flags);
1519 amd_iommu_domain_get_pgtable(domain, &pgtable);
1521 if (address <= PM_LEVEL_SIZE(pgtable.mode))
1525 if (WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL))
1528 *pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root));
1532 update_and_flush_device_table(domain, &pgtable);
1533 domain_flush_complete(domain);
1536 * Device Table needs to be updated and flushed before the new root can
1539 amd_iommu_domain_set_pgtable(domain, pte, pgtable.mode);
1545 spin_unlock_irqrestore(&domain->lock, flags);
1546 free_page((unsigned long)pte);
1551 static u64 *alloc_pte(struct protection_domain *domain,
1552 unsigned long address,
1553 unsigned long page_size,
1558 struct domain_pgtable pgtable;
1562 BUG_ON(!is_power_of_2(page_size));
1564 amd_iommu_domain_get_pgtable(domain, &pgtable);
1566 while (address > PM_LEVEL_SIZE(pgtable.mode)) {
1568 * Return an error if there is no memory to update the
1571 if (!increase_address_space(domain, address, gfp))
1574 /* Read new values to check if update was successful */
1575 amd_iommu_domain_get_pgtable(domain, &pgtable);
1579 level = pgtable.mode - 1;
1580 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1581 address = PAGE_SIZE_ALIGN(address, page_size);
1582 end_lvl = PAGE_SIZE_LEVEL(page_size);
1584 while (level > end_lvl) {
1589 pte_level = PM_PTE_LEVEL(__pte);
1592 * If we replace a series of large PTEs, we need
1593 * to tear down all of them.
1595 if (IOMMU_PTE_PRESENT(__pte) &&
1596 pte_level == PAGE_MODE_7_LEVEL) {
1597 unsigned long count, i;
1600 lpte = first_pte_l7(pte, NULL, &count);
1603 * Unmap the replicated PTEs that still match the
1604 * original large mapping
1606 for (i = 0; i < count; ++i)
1607 cmpxchg64(&lpte[i], __pte, 0ULL);
1613 if (!IOMMU_PTE_PRESENT(__pte) ||
1614 pte_level == PAGE_MODE_NONE) {
1615 page = (u64 *)get_zeroed_page(gfp);
1620 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1622 /* pte could have been changed somewhere. */
1623 if (cmpxchg64(pte, __pte, __npte) != __pte)
1624 free_page((unsigned long)page);
1625 else if (IOMMU_PTE_PRESENT(__pte))
1631 /* No level skipping support yet */
1632 if (pte_level != level)
1637 pte = IOMMU_PTE_PAGE(__pte);
1639 if (pte_page && level == end_lvl)
1642 pte = &pte[PM_LEVEL_INDEX(level, address)];
1649 * This function checks if there is a PTE for a given dma address. If
1650 * there is one, it returns the pointer to it.
1652 static u64 *fetch_pte(struct protection_domain *domain,
1653 unsigned long address,
1654 unsigned long *page_size)
1656 struct domain_pgtable pgtable;
1662 amd_iommu_domain_get_pgtable(domain, &pgtable);
1664 if (address > PM_LEVEL_SIZE(pgtable.mode))
1667 level = pgtable.mode - 1;
1668 pte = &pgtable.root[PM_LEVEL_INDEX(level, address)];
1669 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1674 if (!IOMMU_PTE_PRESENT(*pte))
1678 if (PM_PTE_LEVEL(*pte) == 7 ||
1679 PM_PTE_LEVEL(*pte) == 0)
1682 /* No level skipping support yet */
1683 if (PM_PTE_LEVEL(*pte) != level)
1688 /* Walk to the next level */
1689 pte = IOMMU_PTE_PAGE(*pte);
1690 pte = &pte[PM_LEVEL_INDEX(level, address)];
1691 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1695 * If we have a series of large PTEs, make
1696 * sure to return a pointer to the first one.
1698 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1699 pte = first_pte_l7(pte, page_size, NULL);
1704 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1709 while (cmpxchg64(pte, pteval, 0) != pteval) {
1710 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1714 if (!IOMMU_PTE_PRESENT(pteval))
1717 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1718 mode = IOMMU_PTE_MODE(pteval);
1720 return free_sub_pt(pt, mode, freelist);
1724 * Generic mapping functions. It maps a physical address into a DMA
1725 * address space. It allocates the page table pages if necessary.
1726 * In the future it can be extended to a generic mapping function
1727 * supporting all features of AMD IOMMU page tables like level skipping
1728 * and full 64 bit address spaces.
1730 static int iommu_map_page(struct protection_domain *dom,
1731 unsigned long bus_addr,
1732 unsigned long phys_addr,
1733 unsigned long page_size,
1737 struct page *freelist = NULL;
1738 bool updated = false;
1742 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1743 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1746 if (!(prot & IOMMU_PROT_MASK))
1749 count = PAGE_SIZE_PTE_COUNT(page_size);
1750 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1756 for (i = 0; i < count; ++i)
1757 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1759 if (freelist != NULL)
1763 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1764 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1766 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1768 if (prot & IOMMU_PROT_IR)
1769 __pte |= IOMMU_PTE_IR;
1770 if (prot & IOMMU_PROT_IW)
1771 __pte |= IOMMU_PTE_IW;
1773 for (i = 0; i < count; ++i)
1780 unsigned long flags;
1782 spin_lock_irqsave(&dom->lock, flags);
1784 * Flush domain TLB(s) and wait for completion. Any Device-Table
1785 * Updates and flushing already happened in
1786 * increase_address_space().
1788 domain_flush_tlb_pde(dom);
1789 domain_flush_complete(dom);
1790 spin_unlock_irqrestore(&dom->lock, flags);
1793 /* Everything flushed out, free pages now */
1794 free_page_list(freelist);
1799 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1800 unsigned long bus_addr,
1801 unsigned long page_size)
1803 unsigned long long unmapped;
1804 unsigned long unmap_size;
1807 BUG_ON(!is_power_of_2(page_size));
1811 while (unmapped < page_size) {
1813 pte = fetch_pte(dom, bus_addr, &unmap_size);
1818 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1819 for (i = 0; i < count; i++)
1823 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1824 unmapped += unmap_size;
1827 BUG_ON(unmapped && !is_power_of_2(unmapped));
1832 /****************************************************************************
1834 * The next functions belong to the domain allocation. A domain is
1835 * allocated for every IOMMU as the default domain. If device isolation
1836 * is enabled, every device get its own domain. The most important thing
1837 * about domains is the page table mapping the DMA address space they
1840 ****************************************************************************/
1842 static u16 domain_id_alloc(void)
1846 spin_lock(&pd_bitmap_lock);
1847 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1849 if (id > 0 && id < MAX_DOMAIN_ID)
1850 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1853 spin_unlock(&pd_bitmap_lock);
1858 static void domain_id_free(int id)
1860 spin_lock(&pd_bitmap_lock);
1861 if (id > 0 && id < MAX_DOMAIN_ID)
1862 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1863 spin_unlock(&pd_bitmap_lock);
1866 static void free_gcr3_tbl_level1(u64 *tbl)
1871 for (i = 0; i < 512; ++i) {
1872 if (!(tbl[i] & GCR3_VALID))
1875 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1877 free_page((unsigned long)ptr);
1881 static void free_gcr3_tbl_level2(u64 *tbl)
1886 for (i = 0; i < 512; ++i) {
1887 if (!(tbl[i] & GCR3_VALID))
1890 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1892 free_gcr3_tbl_level1(ptr);
1896 static void free_gcr3_table(struct protection_domain *domain)
1898 if (domain->glx == 2)
1899 free_gcr3_tbl_level2(domain->gcr3_tbl);
1900 else if (domain->glx == 1)
1901 free_gcr3_tbl_level1(domain->gcr3_tbl);
1903 BUG_ON(domain->glx != 0);
1905 free_page((unsigned long)domain->gcr3_tbl);
1908 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1909 struct domain_pgtable *pgtable,
1916 if (pgtable->mode != PAGE_MODE_NONE)
1917 pte_root = iommu_virt_to_phys(pgtable->root);
1919 pte_root |= (pgtable->mode & DEV_ENTRY_MODE_MASK)
1920 << DEV_ENTRY_MODE_SHIFT;
1921 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1923 flags = amd_iommu_dev_table[devid].data[1];
1926 flags |= DTE_FLAG_IOTLB;
1929 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1931 if (iommu_feature(iommu, FEATURE_EPHSUP))
1932 pte_root |= 1ULL << DEV_ENTRY_PPR;
1935 if (domain->flags & PD_IOMMUV2_MASK) {
1936 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1937 u64 glx = domain->glx;
1940 pte_root |= DTE_FLAG_GV;
1941 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1943 /* First mask out possible old values for GCR3 table */
1944 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1947 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1950 /* Encode GCR3 table into DTE */
1951 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1954 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1957 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1961 flags &= ~DEV_DOMID_MASK;
1962 flags |= domain->id;
1964 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1965 amd_iommu_dev_table[devid].data[1] = flags;
1966 amd_iommu_dev_table[devid].data[0] = pte_root;
1969 * A kdump kernel might be replacing a domain ID that was copied from
1970 * the previous kernel--if so, it needs to flush the translation cache
1971 * entries for the old domain ID that is being overwritten
1974 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1976 amd_iommu_flush_tlb_domid(iommu, old_domid);
1980 static void clear_dte_entry(u16 devid)
1982 /* remove entry from the device table seen by the hardware */
1983 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1984 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1986 amd_iommu_apply_erratum_63(devid);
1989 static void do_attach(struct iommu_dev_data *dev_data,
1990 struct protection_domain *domain)
1992 struct domain_pgtable pgtable;
1993 struct amd_iommu *iommu;
1996 iommu = amd_iommu_rlookup_table[dev_data->devid];
1997 ats = dev_data->ats.enabled;
1999 /* Update data structures */
2000 dev_data->domain = domain;
2001 list_add(&dev_data->list, &domain->dev_list);
2003 /* Do reference counting */
2004 domain->dev_iommu[iommu->index] += 1;
2005 domain->dev_cnt += 1;
2007 /* Update device table */
2008 amd_iommu_domain_get_pgtable(domain, &pgtable);
2009 set_dte_entry(dev_data->devid, domain, &pgtable,
2010 ats, dev_data->iommu_v2);
2011 clone_aliases(dev_data->pdev);
2013 device_flush_dte(dev_data);
2016 static void do_detach(struct iommu_dev_data *dev_data)
2018 struct protection_domain *domain = dev_data->domain;
2019 struct amd_iommu *iommu;
2021 iommu = amd_iommu_rlookup_table[dev_data->devid];
2023 /* Update data structures */
2024 dev_data->domain = NULL;
2025 list_del(&dev_data->list);
2026 clear_dte_entry(dev_data->devid);
2027 clone_aliases(dev_data->pdev);
2029 /* Flush the DTE entry */
2030 device_flush_dte(dev_data);
2033 domain_flush_tlb_pde(domain);
2035 /* Wait for the flushes to finish */
2036 domain_flush_complete(domain);
2038 /* decrease reference counters - needs to happen after the flushes */
2039 domain->dev_iommu[iommu->index] -= 1;
2040 domain->dev_cnt -= 1;
2043 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2045 pci_disable_ats(pdev);
2046 pci_disable_pri(pdev);
2047 pci_disable_pasid(pdev);
2050 /* FIXME: Change generic reset-function to do the same */
2051 static int pri_reset_while_enabled(struct pci_dev *pdev)
2056 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2060 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2061 control |= PCI_PRI_CTRL_RESET;
2062 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2067 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2072 /* FIXME: Hardcode number of outstanding requests for now */
2074 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2076 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2078 /* Only allow access to user-accessible pages */
2079 ret = pci_enable_pasid(pdev, 0);
2083 /* First reset the PRI state of the device */
2084 ret = pci_reset_pri(pdev);
2089 ret = pci_enable_pri(pdev, reqs);
2094 ret = pri_reset_while_enabled(pdev);
2099 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2106 pci_disable_pri(pdev);
2107 pci_disable_pasid(pdev);
2113 * If a device is not yet associated with a domain, this function makes the
2114 * device visible in the domain
2116 static int attach_device(struct device *dev,
2117 struct protection_domain *domain)
2119 struct iommu_dev_data *dev_data;
2120 struct pci_dev *pdev;
2121 unsigned long flags;
2124 spin_lock_irqsave(&domain->lock, flags);
2126 dev_data = dev_iommu_priv_get(dev);
2128 spin_lock(&dev_data->lock);
2131 if (dev_data->domain != NULL)
2134 if (!dev_is_pci(dev))
2135 goto skip_ats_check;
2137 pdev = to_pci_dev(dev);
2138 if (domain->flags & PD_IOMMUV2_MASK) {
2139 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
2142 if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
2145 if (dev_data->iommu_v2) {
2146 if (pdev_iommuv2_enable(pdev) != 0)
2149 dev_data->ats.enabled = true;
2150 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2151 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2153 } else if (amd_iommu_iotlb_sup &&
2154 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2155 dev_data->ats.enabled = true;
2156 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2162 do_attach(dev_data, domain);
2165 * We might boot into a crash-kernel here. The crashed kernel
2166 * left the caches in the IOMMU dirty. So we have to flush
2167 * here to evict all dirty stuff.
2169 domain_flush_tlb_pde(domain);
2171 domain_flush_complete(domain);
2174 spin_unlock(&dev_data->lock);
2176 spin_unlock_irqrestore(&domain->lock, flags);
2182 * Removes a device from a protection domain (with devtable_lock held)
2184 static void detach_device(struct device *dev)
2186 struct protection_domain *domain;
2187 struct iommu_dev_data *dev_data;
2188 unsigned long flags;
2190 dev_data = dev_iommu_priv_get(dev);
2191 domain = dev_data->domain;
2193 spin_lock_irqsave(&domain->lock, flags);
2195 spin_lock(&dev_data->lock);
2198 * First check if the device is still attached. It might already
2199 * be detached from its domain because the generic
2200 * iommu_detach_group code detached it and we try again here in
2201 * our alias handling.
2203 if (WARN_ON(!dev_data->domain))
2206 do_detach(dev_data);
2208 if (!dev_is_pci(dev))
2211 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2212 pdev_iommuv2_disable(to_pci_dev(dev));
2213 else if (dev_data->ats.enabled)
2214 pci_disable_ats(to_pci_dev(dev));
2216 dev_data->ats.enabled = false;
2219 spin_unlock(&dev_data->lock);
2221 spin_unlock_irqrestore(&domain->lock, flags);
2224 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
2226 struct iommu_device *iommu_dev;
2227 struct amd_iommu *iommu;
2230 if (!check_device(dev))
2231 return ERR_PTR(-ENODEV);
2233 devid = get_device_id(dev);
2235 return ERR_PTR(devid);
2237 iommu = amd_iommu_rlookup_table[devid];
2239 if (dev_iommu_priv_get(dev))
2240 return &iommu->iommu;
2242 ret = iommu_init_device(dev);
2244 if (ret != -ENOTSUPP)
2245 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2246 iommu_dev = ERR_PTR(ret);
2247 iommu_ignore_device(dev);
2249 amd_iommu_set_pci_msi_domain(dev, iommu);
2250 iommu_dev = &iommu->iommu;
2253 iommu_completion_wait(iommu);
2258 static void amd_iommu_probe_finalize(struct device *dev)
2260 struct iommu_domain *domain;
2262 /* Domains are initialized for this device - have a look what we ended up with */
2263 domain = iommu_get_domain_for_dev(dev);
2264 if (domain->type == IOMMU_DOMAIN_DMA)
2265 iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
2268 static void amd_iommu_release_device(struct device *dev)
2270 int devid = get_device_id(dev);
2271 struct amd_iommu *iommu;
2273 if (!check_device(dev))
2276 iommu = amd_iommu_rlookup_table[devid];
2278 amd_iommu_uninit_device(dev);
2279 iommu_completion_wait(iommu);
2282 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2284 if (dev_is_pci(dev))
2285 return pci_device_group(dev);
2287 return acpihid_device_group(dev);
2290 static int amd_iommu_domain_get_attr(struct iommu_domain *domain,
2291 enum iommu_attr attr, void *data)
2293 switch (domain->type) {
2294 case IOMMU_DOMAIN_UNMANAGED:
2296 case IOMMU_DOMAIN_DMA:
2298 case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
2299 *(int *)data = !amd_iommu_unmap_flush;
2310 /*****************************************************************************
2312 * The next functions belong to the dma_ops mapping/unmapping code.
2314 *****************************************************************************/
2316 static void update_device_table(struct protection_domain *domain,
2317 struct domain_pgtable *pgtable)
2319 struct iommu_dev_data *dev_data;
2321 list_for_each_entry(dev_data, &domain->dev_list, list) {
2322 set_dte_entry(dev_data->devid, domain, pgtable,
2323 dev_data->ats.enabled, dev_data->iommu_v2);
2324 clone_aliases(dev_data->pdev);
2328 static void update_and_flush_device_table(struct protection_domain *domain,
2329 struct domain_pgtable *pgtable)
2331 update_device_table(domain, pgtable);
2332 domain_flush_devices(domain);
2335 static void update_domain(struct protection_domain *domain)
2337 struct domain_pgtable pgtable;
2339 /* Update device table */
2340 amd_iommu_domain_get_pgtable(domain, &pgtable);
2341 update_and_flush_device_table(domain, &pgtable);
2343 /* Flush domain TLB(s) and wait for completion */
2344 domain_flush_tlb_pde(domain);
2345 domain_flush_complete(domain);
2348 int __init amd_iommu_init_api(void)
2352 ret = iova_cache_get();
2356 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2359 #ifdef CONFIG_ARM_AMBA
2360 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2364 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2371 int __init amd_iommu_init_dma_ops(void)
2373 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2375 if (amd_iommu_unmap_flush)
2376 pr_info("IO/TLB flush on unmap enabled\n");
2378 pr_info("Lazy IO/TLB flushing enabled\n");
2384 /*****************************************************************************
2386 * The following functions belong to the exported interface of AMD IOMMU
2388 * This interface allows access to lower level functions of the IOMMU
2389 * like protection domain handling and assignement of devices to domains
2390 * which is not possible with the dma_ops interface.
2392 *****************************************************************************/
2394 static void cleanup_domain(struct protection_domain *domain)
2396 struct iommu_dev_data *entry;
2397 unsigned long flags;
2399 spin_lock_irqsave(&domain->lock, flags);
2401 while (!list_empty(&domain->dev_list)) {
2402 entry = list_first_entry(&domain->dev_list,
2403 struct iommu_dev_data, list);
2404 BUG_ON(!entry->domain);
2408 spin_unlock_irqrestore(&domain->lock, flags);
2411 static void protection_domain_free(struct protection_domain *domain)
2413 struct domain_pgtable pgtable;
2419 domain_id_free(domain->id);
2421 amd_iommu_domain_get_pgtable(domain, &pgtable);
2422 amd_iommu_domain_clr_pt_root(domain);
2423 free_pagetable(&pgtable);
2428 static int protection_domain_init(struct protection_domain *domain, int mode)
2430 u64 *pt_root = NULL;
2432 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
2434 spin_lock_init(&domain->lock);
2435 domain->id = domain_id_alloc();
2438 INIT_LIST_HEAD(&domain->dev_list);
2440 if (mode != PAGE_MODE_NONE) {
2441 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2446 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
2451 static struct protection_domain *protection_domain_alloc(int mode)
2453 struct protection_domain *domain;
2455 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2459 if (protection_domain_init(domain, mode))
2470 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2472 struct protection_domain *domain;
2473 int mode = DEFAULT_PGTABLE_LEVEL;
2475 if (type == IOMMU_DOMAIN_IDENTITY)
2476 mode = PAGE_MODE_NONE;
2478 domain = protection_domain_alloc(mode);
2482 domain->domain.geometry.aperture_start = 0;
2483 domain->domain.geometry.aperture_end = ~0ULL;
2484 domain->domain.geometry.force_aperture = true;
2486 if (type == IOMMU_DOMAIN_DMA &&
2487 iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
2490 return &domain->domain;
2493 protection_domain_free(domain);
2498 static void amd_iommu_domain_free(struct iommu_domain *dom)
2500 struct protection_domain *domain;
2502 domain = to_pdomain(dom);
2504 if (domain->dev_cnt > 0)
2505 cleanup_domain(domain);
2507 BUG_ON(domain->dev_cnt != 0);
2512 if (dom->type == IOMMU_DOMAIN_DMA)
2513 iommu_put_dma_cookie(&domain->domain);
2515 if (domain->flags & PD_IOMMUV2_MASK)
2516 free_gcr3_table(domain);
2518 protection_domain_free(domain);
2521 static void amd_iommu_detach_device(struct iommu_domain *dom,
2524 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2525 struct amd_iommu *iommu;
2528 if (!check_device(dev))
2531 devid = get_device_id(dev);
2535 if (dev_data->domain != NULL)
2538 iommu = amd_iommu_rlookup_table[devid];
2542 #ifdef CONFIG_IRQ_REMAP
2543 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2544 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2545 dev_data->use_vapic = 0;
2548 iommu_completion_wait(iommu);
2551 static int amd_iommu_attach_device(struct iommu_domain *dom,
2554 struct protection_domain *domain = to_pdomain(dom);
2555 struct iommu_dev_data *dev_data;
2556 struct amd_iommu *iommu;
2559 if (!check_device(dev))
2562 dev_data = dev_iommu_priv_get(dev);
2563 dev_data->defer_attach = false;
2565 iommu = amd_iommu_rlookup_table[dev_data->devid];
2569 if (dev_data->domain)
2572 ret = attach_device(dev, domain);
2574 #ifdef CONFIG_IRQ_REMAP
2575 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2576 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2577 dev_data->use_vapic = 1;
2579 dev_data->use_vapic = 0;
2583 iommu_completion_wait(iommu);
2588 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2589 phys_addr_t paddr, size_t page_size, int iommu_prot,
2592 struct protection_domain *domain = to_pdomain(dom);
2593 struct domain_pgtable pgtable;
2597 amd_iommu_domain_get_pgtable(domain, &pgtable);
2598 if (pgtable.mode == PAGE_MODE_NONE)
2601 if (iommu_prot & IOMMU_READ)
2602 prot |= IOMMU_PROT_IR;
2603 if (iommu_prot & IOMMU_WRITE)
2604 prot |= IOMMU_PROT_IW;
2606 ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp);
2608 domain_flush_np_cache(domain, iova, page_size);
2613 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2615 struct iommu_iotlb_gather *gather)
2617 struct protection_domain *domain = to_pdomain(dom);
2618 struct domain_pgtable pgtable;
2620 amd_iommu_domain_get_pgtable(domain, &pgtable);
2621 if (pgtable.mode == PAGE_MODE_NONE)
2624 return iommu_unmap_page(domain, iova, page_size);
2627 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2630 struct protection_domain *domain = to_pdomain(dom);
2631 unsigned long offset_mask, pte_pgsize;
2632 struct domain_pgtable pgtable;
2635 amd_iommu_domain_get_pgtable(domain, &pgtable);
2636 if (pgtable.mode == PAGE_MODE_NONE)
2639 pte = fetch_pte(domain, iova, &pte_pgsize);
2641 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2644 offset_mask = pte_pgsize - 1;
2645 __pte = __sme_clr(*pte & PM_ADDR_MASK);
2647 return (__pte & ~offset_mask) | (iova & offset_mask);
2650 static bool amd_iommu_capable(enum iommu_cap cap)
2653 case IOMMU_CAP_CACHE_COHERENCY:
2655 case IOMMU_CAP_INTR_REMAP:
2656 return (irq_remapping_enabled == 1);
2657 case IOMMU_CAP_NOEXEC:
2666 static void amd_iommu_get_resv_regions(struct device *dev,
2667 struct list_head *head)
2669 struct iommu_resv_region *region;
2670 struct unity_map_entry *entry;
2673 devid = get_device_id(dev);
2677 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2681 if (devid < entry->devid_start || devid > entry->devid_end)
2684 type = IOMMU_RESV_DIRECT;
2685 length = entry->address_end - entry->address_start;
2686 if (entry->prot & IOMMU_PROT_IR)
2688 if (entry->prot & IOMMU_PROT_IW)
2689 prot |= IOMMU_WRITE;
2690 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2691 /* Exclusion range */
2692 type = IOMMU_RESV_RESERVED;
2694 region = iommu_alloc_resv_region(entry->address_start,
2695 length, prot, type);
2697 dev_err(dev, "Out of memory allocating dm-regions\n");
2700 list_add_tail(®ion->list, head);
2703 region = iommu_alloc_resv_region(MSI_RANGE_START,
2704 MSI_RANGE_END - MSI_RANGE_START + 1,
2708 list_add_tail(®ion->list, head);
2710 region = iommu_alloc_resv_region(HT_RANGE_START,
2711 HT_RANGE_END - HT_RANGE_START + 1,
2712 0, IOMMU_RESV_RESERVED);
2715 list_add_tail(®ion->list, head);
2718 bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2721 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2723 return dev_data->defer_attach;
2725 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2727 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2729 struct protection_domain *dom = to_pdomain(domain);
2730 unsigned long flags;
2732 spin_lock_irqsave(&dom->lock, flags);
2733 domain_flush_tlb_pde(dom);
2734 domain_flush_complete(dom);
2735 spin_unlock_irqrestore(&dom->lock, flags);
2738 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2739 struct iommu_iotlb_gather *gather)
2741 amd_iommu_flush_iotlb_all(domain);
2744 static int amd_iommu_def_domain_type(struct device *dev)
2746 struct iommu_dev_data *dev_data;
2748 dev_data = dev_iommu_priv_get(dev);
2753 * Do not identity map IOMMUv2 capable devices when memory encryption is
2754 * active, because some of those devices (AMD GPUs) don't have the
2755 * encryption bit in their DMA-mask and require remapping.
2757 if (!mem_encrypt_active() && dev_data->iommu_v2)
2758 return IOMMU_DOMAIN_IDENTITY;
2763 const struct iommu_ops amd_iommu_ops = {
2764 .capable = amd_iommu_capable,
2765 .domain_alloc = amd_iommu_domain_alloc,
2766 .domain_free = amd_iommu_domain_free,
2767 .attach_dev = amd_iommu_attach_device,
2768 .detach_dev = amd_iommu_detach_device,
2769 .map = amd_iommu_map,
2770 .unmap = amd_iommu_unmap,
2771 .iova_to_phys = amd_iommu_iova_to_phys,
2772 .probe_device = amd_iommu_probe_device,
2773 .release_device = amd_iommu_release_device,
2774 .probe_finalize = amd_iommu_probe_finalize,
2775 .device_group = amd_iommu_device_group,
2776 .domain_get_attr = amd_iommu_domain_get_attr,
2777 .get_resv_regions = amd_iommu_get_resv_regions,
2778 .put_resv_regions = generic_iommu_put_resv_regions,
2779 .is_attach_deferred = amd_iommu_is_attach_deferred,
2780 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2781 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2782 .iotlb_sync = amd_iommu_iotlb_sync,
2783 .def_domain_type = amd_iommu_def_domain_type,
2786 /*****************************************************************************
2788 * The next functions do a basic initialization of IOMMU for pass through
2791 * In passthrough mode the IOMMU is initialized and enabled but not used for
2792 * DMA-API translation.
2794 *****************************************************************************/
2796 /* IOMMUv2 specific functions */
2797 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2799 return atomic_notifier_chain_register(&ppr_notifier, nb);
2801 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2803 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2805 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2807 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2809 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2811 struct protection_domain *domain = to_pdomain(dom);
2812 struct domain_pgtable pgtable;
2813 unsigned long flags;
2815 spin_lock_irqsave(&domain->lock, flags);
2817 /* First save pgtable configuration*/
2818 amd_iommu_domain_get_pgtable(domain, &pgtable);
2820 /* Remove page-table from domain */
2821 amd_iommu_domain_clr_pt_root(domain);
2823 /* Make changes visible to IOMMUs */
2824 update_domain(domain);
2826 /* Page-table is not visible to IOMMU anymore, so free it */
2827 free_pagetable(&pgtable);
2829 spin_unlock_irqrestore(&domain->lock, flags);
2831 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2833 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2835 struct protection_domain *domain = to_pdomain(dom);
2836 unsigned long flags;
2839 if (pasids <= 0 || pasids > (PASID_MASK + 1))
2842 /* Number of GCR3 table levels required */
2843 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2846 if (levels > amd_iommu_max_glx_val)
2849 spin_lock_irqsave(&domain->lock, flags);
2852 * Save us all sanity checks whether devices already in the
2853 * domain support IOMMUv2. Just force that the domain has no
2854 * devices attached when it is switched into IOMMUv2 mode.
2857 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2861 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2862 if (domain->gcr3_tbl == NULL)
2865 domain->glx = levels;
2866 domain->flags |= PD_IOMMUV2_MASK;
2868 update_domain(domain);
2873 spin_unlock_irqrestore(&domain->lock, flags);
2877 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2879 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2880 u64 address, bool size)
2882 struct iommu_dev_data *dev_data;
2883 struct iommu_cmd cmd;
2886 if (!(domain->flags & PD_IOMMUV2_MASK))
2889 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2892 * IOMMU TLB needs to be flushed before Device TLB to
2893 * prevent device TLB refill from IOMMU TLB
2895 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2896 if (domain->dev_iommu[i] == 0)
2899 ret = iommu_queue_command(amd_iommus[i], &cmd);
2904 /* Wait until IOMMU TLB flushes are complete */
2905 domain_flush_complete(domain);
2907 /* Now flush device TLBs */
2908 list_for_each_entry(dev_data, &domain->dev_list, list) {
2909 struct amd_iommu *iommu;
2913 There might be non-IOMMUv2 capable devices in an IOMMUv2
2916 if (!dev_data->ats.enabled)
2919 qdep = dev_data->ats.qdep;
2920 iommu = amd_iommu_rlookup_table[dev_data->devid];
2922 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2923 qdep, address, size);
2925 ret = iommu_queue_command(iommu, &cmd);
2930 /* Wait until all device TLBs are flushed */
2931 domain_flush_complete(domain);
2940 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2943 return __flush_pasid(domain, pasid, address, false);
2946 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2949 struct protection_domain *domain = to_pdomain(dom);
2950 unsigned long flags;
2953 spin_lock_irqsave(&domain->lock, flags);
2954 ret = __amd_iommu_flush_page(domain, pasid, address);
2955 spin_unlock_irqrestore(&domain->lock, flags);
2959 EXPORT_SYMBOL(amd_iommu_flush_page);
2961 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2963 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2967 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2969 struct protection_domain *domain = to_pdomain(dom);
2970 unsigned long flags;
2973 spin_lock_irqsave(&domain->lock, flags);
2974 ret = __amd_iommu_flush_tlb(domain, pasid);
2975 spin_unlock_irqrestore(&domain->lock, flags);
2979 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2981 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2988 index = (pasid >> (9 * level)) & 0x1ff;
2994 if (!(*pte & GCR3_VALID)) {
2998 root = (void *)get_zeroed_page(GFP_ATOMIC);
3002 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3005 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3013 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
3016 struct domain_pgtable pgtable;
3019 amd_iommu_domain_get_pgtable(domain, &pgtable);
3020 if (pgtable.mode != PAGE_MODE_NONE)
3023 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3027 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3029 return __amd_iommu_flush_tlb(domain, pasid);
3032 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
3034 struct domain_pgtable pgtable;
3037 amd_iommu_domain_get_pgtable(domain, &pgtable);
3038 if (pgtable.mode != PAGE_MODE_NONE)
3041 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3047 return __amd_iommu_flush_tlb(domain, pasid);
3050 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
3053 struct protection_domain *domain = to_pdomain(dom);
3054 unsigned long flags;
3057 spin_lock_irqsave(&domain->lock, flags);
3058 ret = __set_gcr3(domain, pasid, cr3);
3059 spin_unlock_irqrestore(&domain->lock, flags);
3063 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3065 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
3067 struct protection_domain *domain = to_pdomain(dom);
3068 unsigned long flags;
3071 spin_lock_irqsave(&domain->lock, flags);
3072 ret = __clear_gcr3(domain, pasid);
3073 spin_unlock_irqrestore(&domain->lock, flags);
3077 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3079 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
3080 int status, int tag)
3082 struct iommu_dev_data *dev_data;
3083 struct amd_iommu *iommu;
3084 struct iommu_cmd cmd;
3086 dev_data = dev_iommu_priv_get(&pdev->dev);
3087 iommu = amd_iommu_rlookup_table[dev_data->devid];
3089 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3090 tag, dev_data->pri_tlp);
3092 return iommu_queue_command(iommu, &cmd);
3094 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3096 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3098 struct protection_domain *pdomain;
3099 struct iommu_dev_data *dev_data;
3100 struct device *dev = &pdev->dev;
3101 struct iommu_domain *io_domain;
3103 if (!check_device(dev))
3106 dev_data = dev_iommu_priv_get(&pdev->dev);
3107 pdomain = dev_data->domain;
3108 io_domain = iommu_get_domain_for_dev(dev);
3110 if (pdomain == NULL && dev_data->defer_attach) {
3111 dev_data->defer_attach = false;
3112 pdomain = to_pdomain(io_domain);
3113 attach_device(dev, pdomain);
3116 if (pdomain == NULL)
3119 if (io_domain->type != IOMMU_DOMAIN_DMA)
3122 /* Only return IOMMUv2 domains */
3123 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3126 return &pdomain->domain;
3128 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3130 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3132 struct iommu_dev_data *dev_data;
3134 if (!amd_iommu_v2_supported())
3137 dev_data = dev_iommu_priv_get(&pdev->dev);
3138 dev_data->errata |= (1 << erratum);
3140 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3142 int amd_iommu_device_info(struct pci_dev *pdev,
3143 struct amd_iommu_device_info *info)
3148 if (pdev == NULL || info == NULL)
3151 if (!amd_iommu_v2_supported())
3154 memset(info, 0, sizeof(*info));
3156 if (pci_ats_supported(pdev))
3157 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3159 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3161 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3163 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3167 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3168 max_pasids = min(max_pasids, (1 << 20));
3170 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3171 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3173 features = pci_pasid_features(pdev);
3174 if (features & PCI_PASID_CAP_EXEC)
3175 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3176 if (features & PCI_PASID_CAP_PRIV)
3177 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3182 EXPORT_SYMBOL(amd_iommu_device_info);
3184 #ifdef CONFIG_IRQ_REMAP
3186 /*****************************************************************************
3188 * Interrupt Remapping Implementation
3190 *****************************************************************************/
3192 static struct irq_chip amd_ir_chip;
3193 static DEFINE_SPINLOCK(iommu_table_lock);
3195 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3199 dte = amd_iommu_dev_table[devid].data[2];
3200 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3201 dte |= iommu_virt_to_phys(table->table);
3202 dte |= DTE_IRQ_REMAP_INTCTL;
3203 dte |= DTE_IRQ_TABLE_LEN;
3204 dte |= DTE_IRQ_REMAP_ENABLE;
3206 amd_iommu_dev_table[devid].data[2] = dte;
3209 static struct irq_remap_table *get_irq_table(u16 devid)
3211 struct irq_remap_table *table;
3213 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3214 "%s: no iommu for devid %x\n", __func__, devid))
3217 table = irq_lookup_table[devid];
3218 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3224 static struct irq_remap_table *__alloc_irq_table(void)
3226 struct irq_remap_table *table;
3228 table = kzalloc(sizeof(*table), GFP_KERNEL);
3232 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3233 if (!table->table) {
3237 raw_spin_lock_init(&table->lock);
3239 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3240 memset(table->table, 0,
3241 MAX_IRQS_PER_TABLE * sizeof(u32));
3243 memset(table->table, 0,
3244 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3248 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3249 struct irq_remap_table *table)
3251 irq_lookup_table[devid] = table;
3252 set_dte_irq_entry(devid, table);
3253 iommu_flush_dte(iommu, devid);
3256 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3259 struct irq_remap_table *table = data;
3261 irq_lookup_table[alias] = table;
3262 set_dte_irq_entry(alias, table);
3264 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3269 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3271 struct irq_remap_table *table = NULL;
3272 struct irq_remap_table *new_table = NULL;
3273 struct amd_iommu *iommu;
3274 unsigned long flags;
3277 spin_lock_irqsave(&iommu_table_lock, flags);
3279 iommu = amd_iommu_rlookup_table[devid];
3283 table = irq_lookup_table[devid];
3287 alias = amd_iommu_alias_table[devid];
3288 table = irq_lookup_table[alias];
3290 set_remap_table_entry(iommu, devid, table);
3293 spin_unlock_irqrestore(&iommu_table_lock, flags);
3295 /* Nothing there yet, allocate new irq remapping table */
3296 new_table = __alloc_irq_table();
3300 spin_lock_irqsave(&iommu_table_lock, flags);
3302 table = irq_lookup_table[devid];
3306 table = irq_lookup_table[alias];
3308 set_remap_table_entry(iommu, devid, table);
3316 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3319 set_remap_table_entry(iommu, devid, table);
3322 set_remap_table_entry(iommu, alias, table);
3325 iommu_completion_wait(iommu);
3328 spin_unlock_irqrestore(&iommu_table_lock, flags);
3331 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3337 static int alloc_irq_index(u16 devid, int count, bool align,
3338 struct pci_dev *pdev)
3340 struct irq_remap_table *table;
3341 int index, c, alignment = 1;
3342 unsigned long flags;
3343 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3348 table = alloc_irq_table(devid, pdev);
3353 alignment = roundup_pow_of_two(count);
3355 raw_spin_lock_irqsave(&table->lock, flags);
3357 /* Scan table for free entries */
3358 for (index = ALIGN(table->min_index, alignment), c = 0;
3359 index < MAX_IRQS_PER_TABLE;) {
3360 if (!iommu->irte_ops->is_allocated(table, index)) {
3364 index = ALIGN(index + 1, alignment);
3370 iommu->irte_ops->set_allocated(table, index - c + 1);
3382 raw_spin_unlock_irqrestore(&table->lock, flags);
3387 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3388 struct amd_ir_data *data)
3391 struct irq_remap_table *table;
3392 struct amd_iommu *iommu;
3393 unsigned long flags;
3394 struct irte_ga *entry;
3396 iommu = amd_iommu_rlookup_table[devid];
3400 table = get_irq_table(devid);
3404 raw_spin_lock_irqsave(&table->lock, flags);
3406 entry = (struct irte_ga *)table->table;
3407 entry = &entry[index];
3409 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
3410 entry->lo.val, entry->hi.val,
3411 irte->lo.val, irte->hi.val);
3413 * We use cmpxchg16 to atomically update the 128-bit IRTE,
3414 * and it cannot be updated by the hardware or other processors
3415 * behind us, so the return value of cmpxchg16 should be the
3416 * same as the old value.
3423 raw_spin_unlock_irqrestore(&table->lock, flags);
3425 iommu_flush_irt(iommu, devid);
3426 iommu_completion_wait(iommu);
3431 static int modify_irte(u16 devid, int index, union irte *irte)
3433 struct irq_remap_table *table;
3434 struct amd_iommu *iommu;
3435 unsigned long flags;
3437 iommu = amd_iommu_rlookup_table[devid];
3441 table = get_irq_table(devid);
3445 raw_spin_lock_irqsave(&table->lock, flags);
3446 table->table[index] = irte->val;
3447 raw_spin_unlock_irqrestore(&table->lock, flags);
3449 iommu_flush_irt(iommu, devid);
3450 iommu_completion_wait(iommu);
3455 static void free_irte(u16 devid, int index)
3457 struct irq_remap_table *table;
3458 struct amd_iommu *iommu;
3459 unsigned long flags;
3461 iommu = amd_iommu_rlookup_table[devid];
3465 table = get_irq_table(devid);
3469 raw_spin_lock_irqsave(&table->lock, flags);
3470 iommu->irte_ops->clear_allocated(table, index);
3471 raw_spin_unlock_irqrestore(&table->lock, flags);
3473 iommu_flush_irt(iommu, devid);
3474 iommu_completion_wait(iommu);
3477 static void irte_prepare(void *entry,
3478 u32 delivery_mode, u32 dest_mode,
3479 u8 vector, u32 dest_apicid, int devid)
3481 union irte *irte = (union irte *) entry;
3484 irte->fields.vector = vector;
3485 irte->fields.int_type = delivery_mode;
3486 irte->fields.destination = dest_apicid;
3487 irte->fields.dm = dest_mode;
3488 irte->fields.valid = 1;
3491 static void irte_ga_prepare(void *entry,
3492 u32 delivery_mode, u32 dest_mode,
3493 u8 vector, u32 dest_apicid, int devid)
3495 struct irte_ga *irte = (struct irte_ga *) entry;
3499 irte->lo.fields_remap.int_type = delivery_mode;
3500 irte->lo.fields_remap.dm = dest_mode;
3501 irte->hi.fields.vector = vector;
3502 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3503 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3504 irte->lo.fields_remap.valid = 1;
3507 static void irte_activate(void *entry, u16 devid, u16 index)
3509 union irte *irte = (union irte *) entry;
3511 irte->fields.valid = 1;
3512 modify_irte(devid, index, irte);
3515 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3517 struct irte_ga *irte = (struct irte_ga *) entry;
3519 irte->lo.fields_remap.valid = 1;
3520 modify_irte_ga(devid, index, irte, NULL);
3523 static void irte_deactivate(void *entry, u16 devid, u16 index)
3525 union irte *irte = (union irte *) entry;
3527 irte->fields.valid = 0;
3528 modify_irte(devid, index, irte);
3531 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3533 struct irte_ga *irte = (struct irte_ga *) entry;
3535 irte->lo.fields_remap.valid = 0;
3536 modify_irte_ga(devid, index, irte, NULL);
3539 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3540 u8 vector, u32 dest_apicid)
3542 union irte *irte = (union irte *) entry;
3544 irte->fields.vector = vector;
3545 irte->fields.destination = dest_apicid;
3546 modify_irte(devid, index, irte);
3549 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3550 u8 vector, u32 dest_apicid)
3552 struct irte_ga *irte = (struct irte_ga *) entry;
3554 if (!irte->lo.fields_remap.guest_mode) {
3555 irte->hi.fields.vector = vector;
3556 irte->lo.fields_remap.destination =
3557 APICID_TO_IRTE_DEST_LO(dest_apicid);
3558 irte->hi.fields.destination =
3559 APICID_TO_IRTE_DEST_HI(dest_apicid);
3560 modify_irte_ga(devid, index, irte, NULL);
3564 #define IRTE_ALLOCATED (~1U)
3565 static void irte_set_allocated(struct irq_remap_table *table, int index)
3567 table->table[index] = IRTE_ALLOCATED;
3570 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3572 struct irte_ga *ptr = (struct irte_ga *)table->table;
3573 struct irte_ga *irte = &ptr[index];
3575 memset(&irte->lo.val, 0, sizeof(u64));
3576 memset(&irte->hi.val, 0, sizeof(u64));
3577 irte->hi.fields.vector = 0xff;
3580 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3582 union irte *ptr = (union irte *)table->table;
3583 union irte *irte = &ptr[index];
3585 return irte->val != 0;
3588 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3590 struct irte_ga *ptr = (struct irte_ga *)table->table;
3591 struct irte_ga *irte = &ptr[index];
3593 return irte->hi.fields.vector != 0;
3596 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3598 table->table[index] = 0;
3601 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3603 struct irte_ga *ptr = (struct irte_ga *)table->table;
3604 struct irte_ga *irte = &ptr[index];
3606 memset(&irte->lo.val, 0, sizeof(u64));
3607 memset(&irte->hi.val, 0, sizeof(u64));
3610 static int get_devid(struct irq_alloc_info *info)
3612 switch (info->type) {
3613 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3614 case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT:
3615 return get_ioapic_devid(info->devid);
3616 case X86_IRQ_ALLOC_TYPE_HPET:
3617 case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT:
3618 return get_hpet_devid(info->devid);
3619 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3620 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3621 return get_device_id(msi_desc_to_dev(info->desc));
3628 static struct irq_domain *get_irq_domain_for_devid(struct irq_alloc_info *info,
3631 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3636 switch (info->type) {
3637 case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT:
3638 case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT:
3639 return iommu->ir_domain;
3646 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3653 devid = get_devid(info);
3656 return get_irq_domain_for_devid(info, devid);
3659 struct irq_remap_ops amd_iommu_irq_ops = {
3660 .prepare = amd_iommu_prepare,
3661 .enable = amd_iommu_enable,
3662 .disable = amd_iommu_disable,
3663 .reenable = amd_iommu_reenable,
3664 .enable_faulting = amd_iommu_enable_faulting,
3665 .get_irq_domain = get_irq_domain,
3668 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3669 struct irq_cfg *irq_cfg,
3670 struct irq_alloc_info *info,
3671 int devid, int index, int sub_handle)
3673 struct irq_2_irte *irte_info = &data->irq_2_irte;
3674 struct msi_msg *msg = &data->msi_entry;
3675 struct IO_APIC_route_entry *entry;
3676 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3681 data->irq_2_irte.devid = devid;
3682 data->irq_2_irte.index = index + sub_handle;
3683 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
3684 apic->irq_dest_mode, irq_cfg->vector,
3685 irq_cfg->dest_apicid, devid);
3687 switch (info->type) {
3688 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3689 /* Setup IOAPIC entry */
3690 entry = info->ioapic.entry;
3691 info->ioapic.entry = NULL;
3692 memset(entry, 0, sizeof(*entry));
3693 entry->vector = index;
3695 entry->trigger = info->ioapic.trigger;
3696 entry->polarity = info->ioapic.polarity;
3697 /* Mask level triggered irqs. */
3698 if (info->ioapic.trigger)
3702 case X86_IRQ_ALLOC_TYPE_HPET:
3703 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3704 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3705 msg->address_hi = MSI_ADDR_BASE_HI;
3706 msg->address_lo = MSI_ADDR_BASE_LO;
3707 msg->data = irte_info->index;
3716 struct amd_irte_ops irte_32_ops = {
3717 .prepare = irte_prepare,
3718 .activate = irte_activate,
3719 .deactivate = irte_deactivate,
3720 .set_affinity = irte_set_affinity,
3721 .set_allocated = irte_set_allocated,
3722 .is_allocated = irte_is_allocated,
3723 .clear_allocated = irte_clear_allocated,
3726 struct amd_irte_ops irte_128_ops = {
3727 .prepare = irte_ga_prepare,
3728 .activate = irte_ga_activate,
3729 .deactivate = irte_ga_deactivate,
3730 .set_affinity = irte_ga_set_affinity,
3731 .set_allocated = irte_ga_set_allocated,
3732 .is_allocated = irte_ga_is_allocated,
3733 .clear_allocated = irte_ga_clear_allocated,
3736 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3737 unsigned int nr_irqs, void *arg)
3739 struct irq_alloc_info *info = arg;
3740 struct irq_data *irq_data;
3741 struct amd_ir_data *data = NULL;
3742 struct irq_cfg *cfg;
3748 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3749 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3753 * With IRQ remapping enabled, don't need contiguous CPU vectors
3754 * to support multiple MSI interrupts.
3756 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3757 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3759 devid = get_devid(info);
3763 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3767 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3768 struct irq_remap_table *table;
3769 struct amd_iommu *iommu;
3771 table = alloc_irq_table(devid, NULL);
3773 if (!table->min_index) {
3775 * Keep the first 32 indexes free for IOAPIC
3778 table->min_index = 32;
3779 iommu = amd_iommu_rlookup_table[devid];
3780 for (i = 0; i < 32; ++i)
3781 iommu->irte_ops->set_allocated(table, i);
3783 WARN_ON(table->min_index != 32);
3784 index = info->ioapic.pin;
3788 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3789 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3790 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3792 index = alloc_irq_index(devid, nr_irqs, align,
3793 msi_desc_to_pci_dev(info->desc));
3795 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3799 pr_warn("Failed to allocate IRTE\n");
3801 goto out_free_parent;
3804 for (i = 0; i < nr_irqs; i++) {
3805 irq_data = irq_domain_get_irq_data(domain, virq + i);
3806 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3813 data = kzalloc(sizeof(*data), GFP_KERNEL);
3817 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3818 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3820 data->entry = kzalloc(sizeof(struct irte_ga),
3827 irq_data->hwirq = (devid << 16) + i;
3828 irq_data->chip_data = data;
3829 irq_data->chip = &amd_ir_chip;
3830 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3831 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3837 for (i--; i >= 0; i--) {
3838 irq_data = irq_domain_get_irq_data(domain, virq + i);
3840 kfree(irq_data->chip_data);
3842 for (i = 0; i < nr_irqs; i++)
3843 free_irte(devid, index + i);
3845 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3849 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3850 unsigned int nr_irqs)
3852 struct irq_2_irte *irte_info;
3853 struct irq_data *irq_data;
3854 struct amd_ir_data *data;
3857 for (i = 0; i < nr_irqs; i++) {
3858 irq_data = irq_domain_get_irq_data(domain, virq + i);
3859 if (irq_data && irq_data->chip_data) {
3860 data = irq_data->chip_data;
3861 irte_info = &data->irq_2_irte;
3862 free_irte(irte_info->devid, irte_info->index);
3867 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3870 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3871 struct amd_ir_data *ir_data,
3872 struct irq_2_irte *irte_info,
3873 struct irq_cfg *cfg);
3875 static int irq_remapping_activate(struct irq_domain *domain,
3876 struct irq_data *irq_data, bool reserve)
3878 struct amd_ir_data *data = irq_data->chip_data;
3879 struct irq_2_irte *irte_info = &data->irq_2_irte;
3880 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3881 struct irq_cfg *cfg = irqd_cfg(irq_data);
3886 iommu->irte_ops->activate(data->entry, irte_info->devid,
3888 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3892 static void irq_remapping_deactivate(struct irq_domain *domain,
3893 struct irq_data *irq_data)
3895 struct amd_ir_data *data = irq_data->chip_data;
3896 struct irq_2_irte *irte_info = &data->irq_2_irte;
3897 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3900 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3904 static const struct irq_domain_ops amd_ir_domain_ops = {
3905 .alloc = irq_remapping_alloc,
3906 .free = irq_remapping_free,
3907 .activate = irq_remapping_activate,
3908 .deactivate = irq_remapping_deactivate,
3911 int amd_iommu_activate_guest_mode(void *data)
3913 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3914 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3917 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3918 !entry || entry->lo.fields_vapic.guest_mode)
3921 valid = entry->lo.fields_vapic.valid;
3926 entry->lo.fields_vapic.valid = valid;
3927 entry->lo.fields_vapic.guest_mode = 1;
3928 entry->lo.fields_vapic.ga_log_intr = 1;
3929 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3930 entry->hi.fields.vector = ir_data->ga_vector;
3931 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3933 return modify_irte_ga(ir_data->irq_2_irte.devid,
3934 ir_data->irq_2_irte.index, entry, ir_data);
3936 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3938 int amd_iommu_deactivate_guest_mode(void *data)
3940 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3941 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3942 struct irq_cfg *cfg = ir_data->cfg;
3945 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3946 !entry || !entry->lo.fields_vapic.guest_mode)
3949 valid = entry->lo.fields_remap.valid;
3954 entry->lo.fields_remap.valid = valid;
3955 entry->lo.fields_remap.dm = apic->irq_dest_mode;
3956 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
3957 entry->hi.fields.vector = cfg->vector;
3958 entry->lo.fields_remap.destination =
3959 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3960 entry->hi.fields.destination =
3961 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3963 return modify_irte_ga(ir_data->irq_2_irte.devid,
3964 ir_data->irq_2_irte.index, entry, ir_data);
3966 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3968 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3971 struct amd_iommu *iommu;
3972 struct amd_iommu_pi_data *pi_data = vcpu_info;
3973 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3974 struct amd_ir_data *ir_data = data->chip_data;
3975 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3976 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3979 * This device has never been set up for guest mode.
3980 * we should not modify the IRTE
3982 if (!dev_data || !dev_data->use_vapic)
3985 ir_data->cfg = irqd_cfg(data);
3986 pi_data->ir_data = ir_data;
3989 * SVM tries to set up for VAPIC mode, but we are in
3990 * legacy mode. So, we force legacy mode instead.
3992 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3993 pr_debug("%s: Fall back to using intr legacy remap\n",
3995 pi_data->is_guest_mode = false;
3998 iommu = amd_iommu_rlookup_table[irte_info->devid];
4002 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4003 if (pi_data->is_guest_mode) {
4004 ir_data->ga_root_ptr = (pi_data->base >> 12);
4005 ir_data->ga_vector = vcpu_pi_info->vector;
4006 ir_data->ga_tag = pi_data->ga_tag;
4007 ret = amd_iommu_activate_guest_mode(ir_data);
4009 ir_data->cached_ga_tag = pi_data->ga_tag;
4011 ret = amd_iommu_deactivate_guest_mode(ir_data);
4014 * This communicates the ga_tag back to the caller
4015 * so that it can do all the necessary clean up.
4018 ir_data->cached_ga_tag = 0;
4025 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4026 struct amd_ir_data *ir_data,
4027 struct irq_2_irte *irte_info,
4028 struct irq_cfg *cfg)
4032 * Atomically updates the IRTE with the new destination, vector
4033 * and flushes the interrupt entry cache.
4035 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4036 irte_info->index, cfg->vector,
4040 static int amd_ir_set_affinity(struct irq_data *data,
4041 const struct cpumask *mask, bool force)
4043 struct amd_ir_data *ir_data = data->chip_data;
4044 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4045 struct irq_cfg *cfg = irqd_cfg(data);
4046 struct irq_data *parent = data->parent_data;
4047 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4053 ret = parent->chip->irq_set_affinity(parent, mask, force);
4054 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4057 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4059 * After this point, all the interrupts will start arriving
4060 * at the new destination. So, time to cleanup the previous
4061 * vector allocation.
4063 send_cleanup_vector(cfg);
4065 return IRQ_SET_MASK_OK_DONE;
4068 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4070 struct amd_ir_data *ir_data = irq_data->chip_data;
4072 *msg = ir_data->msi_entry;
4075 static struct irq_chip amd_ir_chip = {
4077 .irq_ack = apic_ack_irq,
4078 .irq_set_affinity = amd_ir_set_affinity,
4079 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4080 .irq_compose_msi_msg = ir_compose_msi_msg,
4083 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4085 struct fwnode_handle *fn;
4087 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4090 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4091 if (!iommu->ir_domain) {
4092 irq_domain_free_fwnode(fn);
4096 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4097 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4103 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4105 unsigned long flags;
4106 struct amd_iommu *iommu;
4107 struct irq_remap_table *table;
4108 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4109 int devid = ir_data->irq_2_irte.devid;
4110 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4111 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4113 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4114 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4117 iommu = amd_iommu_rlookup_table[devid];
4121 table = get_irq_table(devid);
4125 raw_spin_lock_irqsave(&table->lock, flags);
4127 if (ref->lo.fields_vapic.guest_mode) {
4129 ref->lo.fields_vapic.destination =
4130 APICID_TO_IRTE_DEST_LO(cpu);
4131 ref->hi.fields.destination =
4132 APICID_TO_IRTE_DEST_HI(cpu);
4134 ref->lo.fields_vapic.is_run = is_run;
4138 raw_spin_unlock_irqrestore(&table->lock, flags);
4140 iommu_flush_irt(iommu, devid);
4141 iommu_completion_wait(iommu);
4144 EXPORT_SYMBOL(amd_iommu_update_ga);