drivers/interconnect/qcom/sm8550.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
   5  * Copyright (c) 2022, Linaro Limited
   6  *
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/interconnect.h>
  11 #include <linux/interconnect-provider.h>
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/property.h>
  16 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  17
  18 #include "bcm-voter.h"
  19 #include "icc-common.h"
  20 #include "icc-rpmh.h"
  21 #include "sm8550.h"
  22
  23 static struct qcom_icc_node qhm_qspi = {
  24         .name = "qhm_qspi",
  25         .id = SM8550_MASTER_QSPI_0,
  26         .channels = 1,
  27         .buswidth = 4,
  28         .num_links = 1,
  29         .links = { SM8550_SLAVE_A1NOC_SNOC },
  30 };
  31
  32 static struct qcom_icc_node qhm_qup1 = {
  33         .name = "qhm_qup1",
  34         .id = SM8550_MASTER_QUP_1,
  35         .channels = 1,
  36         .buswidth = 4,
  37         .num_links = 1,
  38         .links = { SM8550_SLAVE_A1NOC_SNOC },
  39 };
  40
  41 static struct qcom_icc_node xm_sdc4 = {
  42         .name = "xm_sdc4",
  43         .id = SM8550_MASTER_SDCC_4,
  44         .channels = 1,
  45         .buswidth = 8,
  46         .num_links = 1,
  47         .links = { SM8550_SLAVE_A1NOC_SNOC },
  48 };
  49
  50 static struct qcom_icc_node xm_ufs_mem = {
  51         .name = "xm_ufs_mem",
  52         .id = SM8550_MASTER_UFS_MEM,
  53         .channels = 1,
  54         .buswidth = 16,
  55         .num_links = 1,
  56         .links = { SM8550_SLAVE_A1NOC_SNOC },
  57 };
  58
  59 static struct qcom_icc_node xm_usb3_0 = {
  60         .name = "xm_usb3_0",
  61         .id = SM8550_MASTER_USB3_0,
  62         .channels = 1,
  63         .buswidth = 8,
  64         .num_links = 1,
  65         .links = { SM8550_SLAVE_A1NOC_SNOC },
  66 };
  67
  68 static struct qcom_icc_node qhm_qdss_bam = {
  69         .name = "qhm_qdss_bam",
  70         .id = SM8550_MASTER_QDSS_BAM,
  71         .channels = 1,
  72         .buswidth = 4,
  73         .num_links = 1,
  74         .links = { SM8550_SLAVE_A2NOC_SNOC },
  75 };
  76
  77 static struct qcom_icc_node qhm_qup2 = {
  78         .name = "qhm_qup2",
  79         .id = SM8550_MASTER_QUP_2,
  80         .channels = 1,
  81         .buswidth = 4,
  82         .num_links = 1,
  83         .links = { SM8550_SLAVE_A2NOC_SNOC },
  84 };
  85
  86 static struct qcom_icc_node qxm_crypto = {
  87         .name = "qxm_crypto",
  88         .id = SM8550_MASTER_CRYPTO,
  89         .channels = 1,
  90         .buswidth = 8,
  91         .num_links = 1,
  92         .links = { SM8550_SLAVE_A2NOC_SNOC },
  93 };
  94
  95 static struct qcom_icc_node qxm_ipa = {
  96         .name = "qxm_ipa",
  97         .id = SM8550_MASTER_IPA,
  98         .channels = 1,
  99         .buswidth = 8,
 100         .num_links = 1,
 101         .links = { SM8550_SLAVE_A2NOC_SNOC },
 102 };
 103
 104 static struct qcom_icc_node qxm_sp = {
 105         .name = "qxm_sp",
 106         .id = SM8550_MASTER_SP,
 107         .channels = 1,
 108         .buswidth = 8,
 109         .num_links = 1,
 110         .links = { SM8550_SLAVE_A2NOC_SNOC },
 111 };
 112
 113 static struct qcom_icc_node xm_qdss_etr_0 = {
 114         .name = "xm_qdss_etr_0",
 115         .id = SM8550_MASTER_QDSS_ETR,
 116         .channels = 1,
 117         .buswidth = 8,
 118         .num_links = 1,
 119         .links = { SM8550_SLAVE_A2NOC_SNOC },
 120 };
 121
 122 static struct qcom_icc_node xm_qdss_etr_1 = {
 123         .name = "xm_qdss_etr_1",
 124         .id = SM8550_MASTER_QDSS_ETR_1,
 125         .channels = 1,
 126         .buswidth = 8,
 127         .num_links = 1,
 128         .links = { SM8550_SLAVE_A2NOC_SNOC },
 129 };
 130
 131 static struct qcom_icc_node xm_sdc2 = {
 132         .name = "xm_sdc2",
 133         .id = SM8550_MASTER_SDCC_2,
 134         .channels = 1,
 135         .buswidth = 8,
 136         .num_links = 1,
 137         .links = { SM8550_SLAVE_A2NOC_SNOC },
 138 };
 139
 140 static struct qcom_icc_node qup0_core_master = {
 141         .name = "qup0_core_master",
 142         .id = SM8550_MASTER_QUP_CORE_0,
 143         .channels = 1,
 144         .buswidth = 4,
 145         .num_links = 1,
 146         .links = { SM8550_SLAVE_QUP_CORE_0 },
 147 };
 148
 149 static struct qcom_icc_node qup1_core_master = {
 150         .name = "qup1_core_master",
 151         .id = SM8550_MASTER_QUP_CORE_1,
 152         .channels = 1,
 153         .buswidth = 4,
 154         .num_links = 1,
 155         .links = { SM8550_SLAVE_QUP_CORE_1 },
 156 };
 157
 158 static struct qcom_icc_node qup2_core_master = {
 159         .name = "qup2_core_master",
 160         .id = SM8550_MASTER_QUP_CORE_2,
 161         .channels = 1,
 162         .buswidth = 4,
 163         .num_links = 1,
 164         .links = { SM8550_SLAVE_QUP_CORE_2 },
 165 };
 166
 167 static struct qcom_icc_node qsm_cfg = {
 168         .name = "qsm_cfg",
 169         .id = SM8550_MASTER_CNOC_CFG,
 170         .channels = 1,
 171         .buswidth = 4,
 172         .num_links = 44,
 173         .links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH,
 174                    SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG,
 175                    SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG,
 176                    SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG,
 177                    SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX,
 178                    SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM,
 179                    SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG,
 180                    SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG,
 181                    SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG,
 182                    SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM,
 183                    SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG,
 184                    SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG,
 185                    SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG,
 186                    SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1,
 187                    SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2,
 188                    SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG,
 189                    SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM,
 190                    SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0,
 191                    SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG,
 192                    SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG,
 193                    SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG,
 194                    SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU },
 195 };
 196
 197 static struct qcom_icc_node qnm_gemnoc_cnoc = {
 198         .name = "qnm_gemnoc_cnoc",
 199         .id = SM8550_MASTER_GEM_NOC_CNOC,
 200         .channels = 1,
 201         .buswidth = 16,
 202         .num_links = 6,
 203         .links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG,
 204                    SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG,
 205                    SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM },
 206 };
 207
 208 static struct qcom_icc_node qnm_gemnoc_pcie = {
 209         .name = "qnm_gemnoc_pcie",
 210         .id = SM8550_MASTER_GEM_NOC_PCIE_SNOC,
 211         .channels = 1,
 212         .buswidth = 8,
 213         .num_links = 2,
 214         .links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 },
 215 };
 216
 217 static struct qcom_icc_node alm_gpu_tcu = {
 218         .name = "alm_gpu_tcu",
 219         .id = SM8550_MASTER_GPU_TCU,
 220         .channels = 1,
 221         .buswidth = 8,
 222         .num_links = 2,
 223         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 224 };
 225
 226 static struct qcom_icc_node alm_sys_tcu = {
 227         .name = "alm_sys_tcu",
 228         .id = SM8550_MASTER_SYS_TCU,
 229         .channels = 1,
 230         .buswidth = 8,
 231         .num_links = 2,
 232         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 233 };
 234
 235 static struct qcom_icc_node chm_apps = {
 236         .name = "chm_apps",
 237         .id = SM8550_MASTER_APPSS_PROC,
 238         .channels = 3,
 239         .buswidth = 32,
 240         .num_links = 3,
 241         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 242                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 243 };
 244
 245 static struct qcom_icc_node qnm_gpu = {
 246         .name = "qnm_gpu",
 247         .id = SM8550_MASTER_GFX3D,
 248         .channels = 2,
 249         .buswidth = 32,
 250         .num_links = 2,
 251         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 252 };
 253
 254 static struct qcom_icc_node qnm_lpass_gemnoc = {
 255         .name = "qnm_lpass_gemnoc",
 256         .id = SM8550_MASTER_LPASS_GEM_NOC,
 257         .channels = 1,
 258         .buswidth = 16,
 259         .num_links = 3,
 260         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 261                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 262 };
 263
 264 static struct qcom_icc_node qnm_mdsp = {
 265         .name = "qnm_mdsp",
 266         .id = SM8550_MASTER_MSS_PROC,
 267         .channels = 1,
 268         .buswidth = 16,
 269         .num_links = 3,
 270         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 271                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 272 };
 273
 274 static struct qcom_icc_node qnm_mnoc_hf = {
 275         .name = "qnm_mnoc_hf",
 276         .id = SM8550_MASTER_MNOC_HF_MEM_NOC,
 277         .channels = 2,
 278         .buswidth = 32,
 279         .num_links = 2,
 280         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 281 };
 282
 283 static struct qcom_icc_node qnm_mnoc_sf = {
 284         .name = "qnm_mnoc_sf",
 285         .id = SM8550_MASTER_MNOC_SF_MEM_NOC,
 286         .channels = 2,
 287         .buswidth = 32,
 288         .num_links = 2,
 289         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 290 };
 291
 292 static struct qcom_icc_node qnm_nsp_gemnoc = {
 293         .name = "qnm_nsp_gemnoc",
 294         .id = SM8550_MASTER_COMPUTE_NOC,
 295         .channels = 2,
 296         .buswidth = 32,
 297         .num_links = 2,
 298         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 299 };
 300
 301 static struct qcom_icc_node qnm_pcie = {
 302         .name = "qnm_pcie",
 303         .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC,
 304         .channels = 1,
 305         .buswidth = 16,
 306         .num_links = 2,
 307         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
 308 };
 309
 310 static struct qcom_icc_node qnm_snoc_gc = {
 311         .name = "qnm_snoc_gc",
 312         .id = SM8550_MASTER_SNOC_GC_MEM_NOC,
 313         .channels = 1,
 314         .buswidth = 8,
 315         .num_links = 1,
 316         .links = { SM8550_SLAVE_LLCC },
 317 };
 318
 319 static struct qcom_icc_node qnm_snoc_sf = {
 320         .name = "qnm_snoc_sf",
 321         .id = SM8550_MASTER_SNOC_SF_MEM_NOC,
 322         .channels = 1,
 323         .buswidth = 16,
 324         .num_links = 3,
 325         .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
 326                    SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
 327 };
 328
 329 static struct qcom_icc_node qnm_lpiaon_noc = {
 330         .name = "qnm_lpiaon_noc",
 331         .id = SM8550_MASTER_LPIAON_NOC,
 332         .channels = 1,
 333         .buswidth = 16,
 334         .num_links = 1,
 335         .links = { SM8550_SLAVE_LPASS_GEM_NOC },
 336 };
 337
 338 static struct qcom_icc_node qnm_lpass_lpinoc = {
 339         .name = "qnm_lpass_lpinoc",
 340         .id = SM8550_MASTER_LPASS_LPINOC,
 341         .channels = 1,
 342         .buswidth = 16,
 343         .num_links = 1,
 344         .links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
 345 };
 346
 347 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
 348         .name = "qxm_lpinoc_dsp_axim",
 349         .id = SM8550_MASTER_LPASS_PROC,
 350         .channels = 1,
 351         .buswidth = 16,
 352         .num_links = 1,
 353         .links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC },
 354 };
 355
 356 static struct qcom_icc_node llcc_mc = {
 357         .name = "llcc_mc",
 358         .id = SM8550_MASTER_LLCC,
 359         .channels = 4,
 360         .buswidth = 4,
 361         .num_links = 1,
 362         .links = { SM8550_SLAVE_EBI1 },
 363 };
 364
 365 static struct qcom_icc_node qnm_camnoc_hf = {
 366         .name = "qnm_camnoc_hf",
 367         .id = SM8550_MASTER_CAMNOC_HF,
 368         .channels = 2,
 369         .buswidth = 32,
 370         .num_links = 1,
 371         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
 372 };
 373
 374 static struct qcom_icc_node qnm_camnoc_icp = {
 375         .name = "qnm_camnoc_icp",
 376         .id = SM8550_MASTER_CAMNOC_ICP,
 377         .channels = 1,
 378         .buswidth = 8,
 379         .num_links = 1,
 380         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 381 };
 382
 383 static struct qcom_icc_node qnm_camnoc_sf = {
 384         .name = "qnm_camnoc_sf",
 385         .id = SM8550_MASTER_CAMNOC_SF,
 386         .channels = 2,
 387         .buswidth = 32,
 388         .num_links = 1,
 389         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 390 };
 391
 392 static struct qcom_icc_node qnm_mdp = {
 393         .name = "qnm_mdp",
 394         .id = SM8550_MASTER_MDP,
 395         .channels = 2,
 396         .buswidth = 32,
 397         .num_links = 1,
 398         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
 399 };
 400
 401 static struct qcom_icc_node qnm_vapss_hcp = {
 402         .name = "qnm_vapss_hcp",
 403         .id = SM8550_MASTER_CDSP_HCP,
 404         .channels = 1,
 405         .buswidth = 32,
 406         .num_links = 1,
 407         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 408 };
 409
 410 static struct qcom_icc_node qnm_video = {
 411         .name = "qnm_video",
 412         .id = SM8550_MASTER_VIDEO,
 413         .channels = 2,
 414         .buswidth = 32,
 415         .num_links = 1,
 416         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 417 };
 418
 419 static struct qcom_icc_node qnm_video_cv_cpu = {
 420         .name = "qnm_video_cv_cpu",
 421         .id = SM8550_MASTER_VIDEO_CV_PROC,
 422         .channels = 1,
 423         .buswidth = 8,
 424         .num_links = 1,
 425         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 426 };
 427
 428 static struct qcom_icc_node qnm_video_cvp = {
 429         .name = "qnm_video_cvp",
 430         .id = SM8550_MASTER_VIDEO_PROC,
 431         .channels = 1,
 432         .buswidth = 32,
 433         .num_links = 1,
 434         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 435 };
 436
 437 static struct qcom_icc_node qnm_video_v_cpu = {
 438         .name = "qnm_video_v_cpu",
 439         .id = SM8550_MASTER_VIDEO_V_PROC,
 440         .channels = 1,
 441         .buswidth = 8,
 442         .num_links = 1,
 443         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
 444 };
 445
 446 static struct qcom_icc_node qsm_mnoc_cfg = {
 447         .name = "qsm_mnoc_cfg",
 448         .id = SM8550_MASTER_CNOC_MNOC_CFG,
 449         .channels = 1,
 450         .buswidth = 4,
 451         .num_links = 1,
 452         .links = { SM8550_SLAVE_SERVICE_MNOC },
 453 };
 454
 455 static struct qcom_icc_node qxm_nsp = {
 456         .name = "qxm_nsp",
 457         .id = SM8550_MASTER_CDSP_PROC,
 458         .channels = 2,
 459         .buswidth = 32,
 460         .num_links = 1,
 461         .links = { SM8550_SLAVE_CDSP_MEM_NOC },
 462 };
 463
 464 static struct qcom_icc_node qsm_pcie_anoc_cfg = {
 465         .name = "qsm_pcie_anoc_cfg",
 466         .id = SM8550_MASTER_PCIE_ANOC_CFG,
 467         .channels = 1,
 468         .buswidth = 4,
 469         .num_links = 1,
 470         .links = { SM8550_SLAVE_SERVICE_PCIE_ANOC },
 471 };
 472
 473 static struct qcom_icc_node xm_pcie3_0 = {
 474         .name = "xm_pcie3_0",
 475         .id = SM8550_MASTER_PCIE_0,
 476         .channels = 1,
 477         .buswidth = 8,
 478         .num_links = 1,
 479         .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
 480 };
 481
 482 static struct qcom_icc_node xm_pcie3_1 = {
 483         .name = "xm_pcie3_1",
 484         .id = SM8550_MASTER_PCIE_1,
 485         .channels = 1,
 486         .buswidth = 16,
 487         .num_links = 1,
 488         .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
 489 };
 490
 491 static struct qcom_icc_node qhm_gic = {
 492         .name = "qhm_gic",
 493         .id = SM8550_MASTER_GIC_AHB,
 494         .channels = 1,
 495         .buswidth = 4,
 496         .num_links = 1,
 497         .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
 498 };
 499
 500 static struct qcom_icc_node qnm_aggre1_noc = {
 501         .name = "qnm_aggre1_noc",
 502         .id = SM8550_MASTER_A1NOC_SNOC,
 503         .channels = 1,
 504         .buswidth = 16,
 505         .num_links = 1,
 506         .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
 507 };
 508
 509 static struct qcom_icc_node qnm_aggre2_noc = {
 510         .name = "qnm_aggre2_noc",
 511         .id = SM8550_MASTER_A2NOC_SNOC,
 512         .channels = 1,
 513         .buswidth = 16,
 514         .num_links = 1,
 515         .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
 516 };
 517
 518 static struct qcom_icc_node xm_gic = {
 519         .name = "xm_gic",
 520         .id = SM8550_MASTER_GIC,
 521         .channels = 1,
 522         .buswidth = 8,
 523         .num_links = 1,
 524         .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
 525 };
 526
 527 static struct qcom_icc_node qnm_mnoc_hf_disp = {
 528         .name = "qnm_mnoc_hf_disp",
 529         .id = SM8550_MASTER_MNOC_HF_MEM_NOC_DISP,
 530         .channels = 2,
 531         .buswidth = 32,
 532         .num_links = 1,
 533         .links = { SM8550_SLAVE_LLCC_DISP },
 534 };
 535
 536 static struct qcom_icc_node qnm_pcie_disp = {
 537         .name = "qnm_pcie_disp",
 538         .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP,
 539         .channels = 1,
 540         .buswidth = 16,
 541         .num_links = 1,
 542         .links = { SM8550_SLAVE_LLCC_DISP },
 543 };
 544
 545 static struct qcom_icc_node llcc_mc_disp = {
 546         .name = "llcc_mc_disp",
 547         .id = SM8550_MASTER_LLCC_DISP,
 548         .channels = 4,
 549         .buswidth = 4,
 550         .num_links = 1,
 551         .links = { SM8550_SLAVE_EBI1_DISP },
 552 };
 553
 554 static struct qcom_icc_node qnm_mdp_disp = {
 555         .name = "qnm_mdp_disp",
 556         .id = SM8550_MASTER_MDP_DISP,
 557         .channels = 2,
 558         .buswidth = 32,
 559         .num_links = 1,
 560         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP },
 561 };
 562
 563 static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = {
 564         .name = "qnm_mnoc_hf_cam_ife_0",
 565         .id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0,
 566         .channels = 2,
 567         .buswidth = 32,
 568         .num_links = 1,
 569         .links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
 570 };
 571
 572 static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = {
 573         .name = "qnm_mnoc_sf_cam_ife_0",
 574         .id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0,
 575         .channels = 2,
 576         .buswidth = 32,
 577         .num_links = 1,
 578         .links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
 579 };
 580
 581 static struct qcom_icc_node qnm_pcie_cam_ife_0 = {
 582         .name = "qnm_pcie_cam_ife_0",
 583         .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0,
 584         .channels = 1,
 585         .buswidth = 16,
 586         .num_links = 1,
 587         .links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
 588 };
 589
 590 static struct qcom_icc_node llcc_mc_cam_ife_0 = {
 591         .name = "llcc_mc_cam_ife_0",
 592         .id = SM8550_MASTER_LLCC_CAM_IFE_0,
 593         .channels = 4,
 594         .buswidth = 4,
 595         .num_links = 1,
 596         .links = { SM8550_SLAVE_EBI1_CAM_IFE_0 },
 597 };
 598
 599 static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = {
 600         .name = "qnm_camnoc_hf_cam_ife_0",
 601         .id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_0,
 602         .channels = 2,
 603         .buswidth = 32,
 604         .num_links = 1,
 605         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 },
 606 };
 607
 608 static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = {
 609         .name = "qnm_camnoc_icp_cam_ife_0",
 610         .id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0,
 611         .channels = 1,
 612         .buswidth = 8,
 613         .num_links = 1,
 614         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
 615 };
 616
 617 static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = {
 618         .name = "qnm_camnoc_sf_cam_ife_0",
 619         .id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_0,
 620         .channels = 2,
 621         .buswidth = 32,
 622         .num_links = 1,
 623         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
 624 };
 625
 626 static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = {
 627         .name = "qnm_mnoc_hf_cam_ife_1",
 628         .id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1,
 629         .channels = 2,
 630         .buswidth = 32,
 631         .num_links = 1,
 632         .links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
 633 };
 634
 635 static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = {
 636         .name = "qnm_mnoc_sf_cam_ife_1",
 637         .id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1,
 638         .channels = 2,
 639         .buswidth = 32,
 640         .num_links = 1,
 641         .links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
 642 };
 643
 644 static struct qcom_icc_node qnm_pcie_cam_ife_1 = {
 645         .name = "qnm_pcie_cam_ife_1",
 646         .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1,
 647         .channels = 1,
 648         .buswidth = 16,
 649         .num_links = 1,
 650         .links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
 651 };
 652
 653 static struct qcom_icc_node llcc_mc_cam_ife_1 = {
 654         .name = "llcc_mc_cam_ife_1",
 655         .id = SM8550_MASTER_LLCC_CAM_IFE_1,
 656         .channels = 4,
 657         .buswidth = 4,
 658         .num_links = 1,
 659         .links = { SM8550_SLAVE_EBI1_CAM_IFE_1 },
 660 };
 661
 662 static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = {
 663         .name = "qnm_camnoc_hf_cam_ife_1",
 664         .id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_1,
 665         .channels = 2,
 666         .buswidth = 32,
 667         .num_links = 1,
 668         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 },
 669 };
 670
 671 static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = {
 672         .name = "qnm_camnoc_icp_cam_ife_1",
 673         .id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1,
 674         .channels = 1,
 675         .buswidth = 8,
 676         .num_links = 1,
 677         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
 678 };
 679
 680 static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = {
 681         .name = "qnm_camnoc_sf_cam_ife_1",
 682         .id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_1,
 683         .channels = 2,
 684         .buswidth = 32,
 685         .num_links = 1,
 686         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
 687 };
 688
 689 static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = {
 690         .name = "qnm_mnoc_hf_cam_ife_2",
 691         .id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2,
 692         .channels = 2,
 693         .buswidth = 32,
 694         .num_links = 1,
 695         .links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
 696 };
 697
 698 static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = {
 699         .name = "qnm_mnoc_sf_cam_ife_2",
 700         .id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2,
 701         .channels = 2,
 702         .buswidth = 32,
 703         .num_links = 1,
 704         .links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
 705 };
 706
 707 static struct qcom_icc_node qnm_pcie_cam_ife_2 = {
 708         .name = "qnm_pcie_cam_ife_2",
 709         .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2,
 710         .channels = 1,
 711         .buswidth = 16,
 712         .num_links = 1,
 713         .links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
 714 };
 715
 716 static struct qcom_icc_node llcc_mc_cam_ife_2 = {
 717         .name = "llcc_mc_cam_ife_2",
 718         .id = SM8550_MASTER_LLCC_CAM_IFE_2,
 719         .channels = 4,
 720         .buswidth = 4,
 721         .num_links = 1,
 722         .links = { SM8550_SLAVE_EBI1_CAM_IFE_2 },
 723 };
 724
 725 static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = {
 726         .name = "qnm_camnoc_hf_cam_ife_2",
 727         .id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_2,
 728         .channels = 2,
 729         .buswidth = 32,
 730         .num_links = 1,
 731         .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 },
 732 };
 733
 734 static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = {
 735         .name = "qnm_camnoc_icp_cam_ife_2",
 736         .id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2,
 737         .channels = 1,
 738         .buswidth = 8,
 739         .num_links = 1,
 740         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
 741 };
 742
 743 static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = {
 744         .name = "qnm_camnoc_sf_cam_ife_2",
 745         .id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_2,
 746         .channels = 2,
 747         .buswidth = 32,
 748         .num_links = 1,
 749         .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
 750 };
 751
 752 static struct qcom_icc_node qns_a1noc_snoc = {
 753         .name = "qns_a1noc_snoc",
 754         .id = SM8550_SLAVE_A1NOC_SNOC,
 755         .channels = 1,
 756         .buswidth = 16,
 757         .num_links = 1,
 758         .links = { SM8550_MASTER_A1NOC_SNOC },
 759 };
 760
 761 static struct qcom_icc_node qns_a2noc_snoc = {
 762         .name = "qns_a2noc_snoc",
 763         .id = SM8550_SLAVE_A2NOC_SNOC,
 764         .channels = 1,
 765         .buswidth = 16,
 766         .num_links = 1,
 767         .links = { SM8550_MASTER_A2NOC_SNOC },
 768 };
 769
 770 static struct qcom_icc_node qup0_core_slave = {
 771         .name = "qup0_core_slave",
 772         .id = SM8550_SLAVE_QUP_CORE_0,
 773         .channels = 1,
 774         .buswidth = 4,
 775         .num_links = 0,
 776 };
 777
 778 static struct qcom_icc_node qup1_core_slave = {
 779         .name = "qup1_core_slave",
 780         .id = SM8550_SLAVE_QUP_CORE_1,
 781         .channels = 1,
 782         .buswidth = 4,
 783         .num_links = 0,
 784 };
 785
 786 static struct qcom_icc_node qup2_core_slave = {
 787         .name = "qup2_core_slave",
 788         .id = SM8550_SLAVE_QUP_CORE_2,
 789         .channels = 1,
 790         .buswidth = 4,
 791         .num_links = 0,
 792 };
 793
 794 static struct qcom_icc_node qhs_ahb2phy0 = {
 795         .name = "qhs_ahb2phy0",
 796         .id = SM8550_SLAVE_AHB2PHY_SOUTH,
 797         .channels = 1,
 798         .buswidth = 4,
 799         .num_links = 0,
 800 };
 801
 802 static struct qcom_icc_node qhs_ahb2phy1 = {
 803         .name = "qhs_ahb2phy1",
 804         .id = SM8550_SLAVE_AHB2PHY_NORTH,
 805         .channels = 1,
 806         .buswidth = 4,
 807         .num_links = 0,
 808 };
 809
 810 static struct qcom_icc_node qhs_apss = {
 811         .name = "qhs_apss",
 812         .id = SM8550_SLAVE_APPSS,
 813         .channels = 1,
 814         .buswidth = 8,
 815         .num_links = 0,
 816 };
 817
 818 static struct qcom_icc_node qhs_camera_cfg = {
 819         .name = "qhs_camera_cfg",
 820         .id = SM8550_SLAVE_CAMERA_CFG,
 821         .channels = 1,
 822         .buswidth = 4,
 823         .num_links = 0,
 824 };
 825
 826 static struct qcom_icc_node qhs_clk_ctl = {
 827         .name = "qhs_clk_ctl",
 828         .id = SM8550_SLAVE_CLK_CTL,
 829         .channels = 1,
 830         .buswidth = 4,
 831         .num_links = 0,
 832 };
 833
 834 static struct qcom_icc_node qhs_cpr_cx = {
 835         .name = "qhs_cpr_cx",
 836         .id = SM8550_SLAVE_RBCPR_CX_CFG,
 837         .channels = 1,
 838         .buswidth = 4,
 839         .num_links = 0,
 840 };
 841
 842 static struct qcom_icc_node qhs_cpr_mmcx = {
 843         .name = "qhs_cpr_mmcx",
 844         .id = SM8550_SLAVE_RBCPR_MMCX_CFG,
 845         .channels = 1,
 846         .buswidth = 4,
 847         .num_links = 0,
 848 };
 849
 850 static struct qcom_icc_node qhs_cpr_mxa = {
 851         .name = "qhs_cpr_mxa",
 852         .id = SM8550_SLAVE_RBCPR_MXA_CFG,
 853         .channels = 1,
 854         .buswidth = 4,
 855         .num_links = 0,
 856 };
 857
 858 static struct qcom_icc_node qhs_cpr_mxc = {
 859         .name = "qhs_cpr_mxc",
 860         .id = SM8550_SLAVE_RBCPR_MXC_CFG,
 861         .channels = 1,
 862         .buswidth = 4,
 863         .num_links = 0,
 864 };
 865
 866 static struct qcom_icc_node qhs_cpr_nspcx = {
 867         .name = "qhs_cpr_nspcx",
 868         .id = SM8550_SLAVE_CPR_NSPCX,
 869         .channels = 1,
 870         .buswidth = 4,
 871         .num_links = 0,
 872 };
 873
 874 static struct qcom_icc_node qhs_crypto0_cfg = {
 875         .name = "qhs_crypto0_cfg",
 876         .id = SM8550_SLAVE_CRYPTO_0_CFG,
 877         .channels = 1,
 878         .buswidth = 4,
 879         .num_links = 0,
 880 };
 881
 882 static struct qcom_icc_node qhs_cx_rdpm = {
 883         .name = "qhs_cx_rdpm",
 884         .id = SM8550_SLAVE_CX_RDPM,
 885         .channels = 1,
 886         .buswidth = 4,
 887         .num_links = 0,
 888 };
 889
 890 static struct qcom_icc_node qhs_display_cfg = {
 891         .name = "qhs_display_cfg",
 892         .id = SM8550_SLAVE_DISPLAY_CFG,
 893         .channels = 1,
 894         .buswidth = 4,
 895         .num_links = 0,
 896 };
 897
 898 static struct qcom_icc_node qhs_gpuss_cfg = {
 899         .name = "qhs_gpuss_cfg",
 900         .id = SM8550_SLAVE_GFX3D_CFG,
 901         .channels = 1,
 902         .buswidth = 8,
 903         .num_links = 0,
 904 };
 905
 906 static struct qcom_icc_node qhs_i2c = {
 907         .name = "qhs_i2c",
 908         .id = SM8550_SLAVE_I2C,
 909         .channels = 1,
 910         .buswidth = 4,
 911         .num_links = 0,
 912 };
 913
 914 static struct qcom_icc_node qhs_imem_cfg = {
 915         .name = "qhs_imem_cfg",
 916         .id = SM8550_SLAVE_IMEM_CFG,
 917         .channels = 1,
 918         .buswidth = 4,
 919         .num_links = 0,
 920 };
 921
 922 static struct qcom_icc_node qhs_ipa = {
 923         .name = "qhs_ipa",
 924         .id = SM8550_SLAVE_IPA_CFG,
 925         .channels = 1,
 926         .buswidth = 4,
 927         .num_links = 0,
 928 };
 929
 930 static struct qcom_icc_node qhs_ipc_router = {
 931         .name = "qhs_ipc_router",
 932         .id = SM8550_SLAVE_IPC_ROUTER_CFG,
 933         .channels = 1,
 934         .buswidth = 4,
 935         .num_links = 0,
 936 };
 937
 938 static struct qcom_icc_node qhs_mss_cfg = {
 939         .name = "qhs_mss_cfg",
 940         .id = SM8550_SLAVE_CNOC_MSS,
 941         .channels = 1,
 942         .buswidth = 4,
 943         .num_links = 0,
 944 };
 945
 946 static struct qcom_icc_node qhs_mx_rdpm = {
 947         .name = "qhs_mx_rdpm",
 948         .id = SM8550_SLAVE_MX_RDPM,
 949         .channels = 1,
 950         .buswidth = 4,
 951         .num_links = 0,
 952 };
 953
 954 static struct qcom_icc_node qhs_pcie0_cfg = {
 955         .name = "qhs_pcie0_cfg",
 956         .id = SM8550_SLAVE_PCIE_0_CFG,
 957         .channels = 1,
 958         .buswidth = 4,
 959         .num_links = 0,
 960 };
 961
 962 static struct qcom_icc_node qhs_pcie1_cfg = {
 963         .name = "qhs_pcie1_cfg",
 964         .id = SM8550_SLAVE_PCIE_1_CFG,
 965         .channels = 1,
 966         .buswidth = 4,
 967         .num_links = 0,
 968 };
 969
 970 static struct qcom_icc_node qhs_pdm = {
 971         .name = "qhs_pdm",
 972         .id = SM8550_SLAVE_PDM,
 973         .channels = 1,
 974         .buswidth = 4,
 975         .num_links = 0,
 976 };
 977
 978 static struct qcom_icc_node qhs_pimem_cfg = {
 979         .name = "qhs_pimem_cfg",
 980         .id = SM8550_SLAVE_PIMEM_CFG,
 981         .channels = 1,
 982         .buswidth = 4,
 983         .num_links = 0,
 984 };
 985
 986 static struct qcom_icc_node qhs_prng = {
 987         .name = "qhs_prng",
 988         .id = SM8550_SLAVE_PRNG,
 989         .channels = 1,
 990         .buswidth = 4,
 991         .num_links = 0,
 992 };
 993
 994 static struct qcom_icc_node qhs_qdss_cfg = {
 995         .name = "qhs_qdss_cfg",
 996         .id = SM8550_SLAVE_QDSS_CFG,
 997         .channels = 1,
 998         .buswidth = 4,
 999         .num_links = 0,
1000 };
1001
1002 static struct qcom_icc_node qhs_qspi = {
1003         .name = "qhs_qspi",
1004         .id = SM8550_SLAVE_QSPI_0,
1005         .channels = 1,
1006         .buswidth = 4,
1007         .num_links = 0,
1008 };
1009
1010 static struct qcom_icc_node qhs_qup1 = {
1011         .name = "qhs_qup1",
1012         .id = SM8550_SLAVE_QUP_1,
1013         .channels = 1,
1014         .buswidth = 4,
1015         .num_links = 0,
1016 };
1017
1018 static struct qcom_icc_node qhs_qup2 = {
1019         .name = "qhs_qup2",
1020         .id = SM8550_SLAVE_QUP_2,
1021         .channels = 1,
1022         .buswidth = 4,
1023         .num_links = 0,
1024 };
1025
1026 static struct qcom_icc_node qhs_sdc2 = {
1027         .name = "qhs_sdc2",
1028         .id = SM8550_SLAVE_SDCC_2,
1029         .channels = 1,
1030         .buswidth = 4,
1031         .num_links = 0,
1032 };
1033
1034 static struct qcom_icc_node qhs_sdc4 = {
1035         .name = "qhs_sdc4",
1036         .id = SM8550_SLAVE_SDCC_4,
1037         .channels = 1,
1038         .buswidth = 4,
1039         .num_links = 0,
1040 };
1041
1042 static struct qcom_icc_node qhs_spss_cfg = {
1043         .name = "qhs_spss_cfg",
1044         .id = SM8550_SLAVE_SPSS_CFG,
1045         .channels = 1,
1046         .buswidth = 4,
1047         .num_links = 0,
1048 };
1049
1050 static struct qcom_icc_node qhs_tcsr = {
1051         .name = "qhs_tcsr",
1052         .id = SM8550_SLAVE_TCSR,
1053         .channels = 1,
1054         .buswidth = 4,
1055         .num_links = 0,
1056 };
1057
1058 static struct qcom_icc_node qhs_tlmm = {
1059         .name = "qhs_tlmm",
1060         .id = SM8550_SLAVE_TLMM,
1061         .channels = 1,
1062         .buswidth = 4,
1063         .num_links = 0,
1064 };
1065
1066 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1067         .name = "qhs_ufs_mem_cfg",
1068         .id = SM8550_SLAVE_UFS_MEM_CFG,
1069         .channels = 1,
1070         .buswidth = 4,
1071         .num_links = 0,
1072 };
1073
1074 static struct qcom_icc_node qhs_usb3_0 = {
1075         .name = "qhs_usb3_0",
1076         .id = SM8550_SLAVE_USB3_0,
1077         .channels = 1,
1078         .buswidth = 4,
1079         .num_links = 0,
1080 };
1081
1082 static struct qcom_icc_node qhs_venus_cfg = {
1083         .name = "qhs_venus_cfg",
1084         .id = SM8550_SLAVE_VENUS_CFG,
1085         .channels = 1,
1086         .buswidth = 4,
1087         .num_links = 0,
1088 };
1089
1090 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1091         .name = "qhs_vsense_ctrl_cfg",
1092         .id = SM8550_SLAVE_VSENSE_CTRL_CFG,
1093         .channels = 1,
1094         .buswidth = 4,
1095         .num_links = 0,
1096 };
1097
1098 static struct qcom_icc_node qss_lpass_qtb_cfg = {
1099         .name = "qss_lpass_qtb_cfg",
1100         .id = SM8550_SLAVE_LPASS_QTB_CFG,
1101         .channels = 1,
1102         .buswidth = 4,
1103         .num_links = 0,
1104 };
1105
1106 static struct qcom_icc_node qss_mnoc_cfg = {
1107         .name = "qss_mnoc_cfg",
1108         .id = SM8550_SLAVE_CNOC_MNOC_CFG,
1109         .channels = 1,
1110         .buswidth = 4,
1111         .num_links = 1,
1112         .links = { SM8550_MASTER_CNOC_MNOC_CFG },
1113 };
1114
1115 static struct qcom_icc_node qss_nsp_qtb_cfg = {
1116         .name = "qss_nsp_qtb_cfg",
1117         .id = SM8550_SLAVE_NSP_QTB_CFG,
1118         .channels = 1,
1119         .buswidth = 4,
1120         .num_links = 0,
1121 };
1122
1123 static struct qcom_icc_node qss_pcie_anoc_cfg = {
1124         .name = "qss_pcie_anoc_cfg",
1125         .id = SM8550_SLAVE_PCIE_ANOC_CFG,
1126         .channels = 1,
1127         .buswidth = 4,
1128         .num_links = 1,
1129         .links = { SM8550_MASTER_PCIE_ANOC_CFG },
1130 };
1131
1132 static struct qcom_icc_node xs_qdss_stm = {
1133         .name = "xs_qdss_stm",
1134         .id = SM8550_SLAVE_QDSS_STM,
1135         .channels = 1,
1136         .buswidth = 4,
1137         .num_links = 0,
1138 };
1139
1140 static struct qcom_icc_node xs_sys_tcu_cfg = {
1141         .name = "xs_sys_tcu_cfg",
1142         .id = SM8550_SLAVE_TCU,
1143         .channels = 1,
1144         .buswidth = 8,
1145         .num_links = 0,
1146 };
1147
1148 static struct qcom_icc_node qhs_aoss = {
1149         .name = "qhs_aoss",
1150         .id = SM8550_SLAVE_AOSS,
1151         .channels = 1,
1152         .buswidth = 4,
1153         .num_links = 0,
1154 };
1155
1156 static struct qcom_icc_node qhs_tme_cfg = {
1157         .name = "qhs_tme_cfg",
1158         .id = SM8550_SLAVE_TME_CFG,
1159         .channels = 1,
1160         .buswidth = 4,
1161         .num_links = 0,
1162 };
1163
1164 static struct qcom_icc_node qss_cfg = {
1165         .name = "qss_cfg",
1166         .id = SM8550_SLAVE_CNOC_CFG,
1167         .channels = 1,
1168         .buswidth = 4,
1169         .num_links = 1,
1170         .links = { SM8550_MASTER_CNOC_CFG },
1171 };
1172
1173 static struct qcom_icc_node qss_ddrss_cfg = {
1174         .name = "qss_ddrss_cfg",
1175         .id = SM8550_SLAVE_DDRSS_CFG,
1176         .channels = 1,
1177         .buswidth = 4,
1178         .num_links = 0,
1179 };
1180
1181 static struct qcom_icc_node qxs_boot_imem = {
1182         .name = "qxs_boot_imem",
1183         .id = SM8550_SLAVE_BOOT_IMEM,
1184         .channels = 1,
1185         .buswidth = 8,
1186         .num_links = 0,
1187 };
1188
1189 static struct qcom_icc_node qxs_imem = {
1190         .name = "qxs_imem",
1191         .id = SM8550_SLAVE_IMEM,
1192         .channels = 1,
1193         .buswidth = 8,
1194         .num_links = 0,
1195 };
1196
1197 static struct qcom_icc_node xs_pcie_0 = {
1198         .name = "xs_pcie_0",
1199         .id = SM8550_SLAVE_PCIE_0,
1200         .channels = 1,
1201         .buswidth = 8,
1202         .num_links = 0,
1203 };
1204
1205 static struct qcom_icc_node xs_pcie_1 = {
1206         .name = "xs_pcie_1",
1207         .id = SM8550_SLAVE_PCIE_1,
1208         .channels = 1,
1209         .buswidth = 16,
1210         .num_links = 0,
1211 };
1212
1213 static struct qcom_icc_node qns_gem_noc_cnoc = {
1214         .name = "qns_gem_noc_cnoc",
1215         .id = SM8550_SLAVE_GEM_NOC_CNOC,
1216         .channels = 1,
1217         .buswidth = 16,
1218         .num_links = 1,
1219         .links = { SM8550_MASTER_GEM_NOC_CNOC },
1220 };
1221
1222 static struct qcom_icc_node qns_llcc = {
1223         .name = "qns_llcc",
1224         .id = SM8550_SLAVE_LLCC,
1225         .channels = 4,
1226         .buswidth = 16,
1227         .num_links = 1,
1228         .links = { SM8550_MASTER_LLCC },
1229 };
1230
1231 static struct qcom_icc_node qns_pcie = {
1232         .name = "qns_pcie",
1233         .id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC,
1234         .channels = 1,
1235         .buswidth = 8,
1236         .num_links = 1,
1237         .links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC },
1238 };
1239
1240 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1241         .name = "qns_lpass_ag_noc_gemnoc",
1242         .id = SM8550_SLAVE_LPASS_GEM_NOC,
1243         .channels = 1,
1244         .buswidth = 16,
1245         .num_links = 1,
1246         .links = { SM8550_MASTER_LPASS_GEM_NOC },
1247 };
1248
1249 static struct qcom_icc_node qns_lpass_aggnoc = {
1250         .name = "qns_lpass_aggnoc",
1251         .id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
1252         .channels = 1,
1253         .buswidth = 16,
1254         .num_links = 1,
1255         .links = { SM8550_MASTER_LPIAON_NOC },
1256 };
1257
1258 static struct qcom_icc_node qns_lpi_aon_noc = {
1259         .name = "qns_lpi_aon_noc",
1260         .id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC,
1261         .channels = 1,
1262         .buswidth = 16,
1263         .num_links = 1,
1264         .links = { SM8550_MASTER_LPASS_LPINOC },
1265 };
1266
1267 static struct qcom_icc_node ebi = {
1268         .name = "ebi",
1269         .id = SM8550_SLAVE_EBI1,
1270         .channels = 4,
1271         .buswidth = 4,
1272         .num_links = 0,
1273 };
1274
1275 static struct qcom_icc_node qns_mem_noc_hf = {
1276         .name = "qns_mem_noc_hf",
1277         .id = SM8550_SLAVE_MNOC_HF_MEM_NOC,
1278         .channels = 2,
1279         .buswidth = 32,
1280         .num_links = 1,
1281         .links = { SM8550_MASTER_MNOC_HF_MEM_NOC },
1282 };
1283
1284 static struct qcom_icc_node qns_mem_noc_sf = {
1285         .name = "qns_mem_noc_sf",
1286         .id = SM8550_SLAVE_MNOC_SF_MEM_NOC,
1287         .channels = 2,
1288         .buswidth = 32,
1289         .num_links = 1,
1290         .links = { SM8550_MASTER_MNOC_SF_MEM_NOC },
1291 };
1292
1293 static struct qcom_icc_node srvc_mnoc = {
1294         .name = "srvc_mnoc",
1295         .id = SM8550_SLAVE_SERVICE_MNOC,
1296         .channels = 1,
1297         .buswidth = 4,
1298         .num_links = 0,
1299 };
1300
1301 static struct qcom_icc_node qns_nsp_gemnoc = {
1302         .name = "qns_nsp_gemnoc",
1303         .id = SM8550_SLAVE_CDSP_MEM_NOC,
1304         .channels = 2,
1305         .buswidth = 32,
1306         .num_links = 1,
1307         .links = { SM8550_MASTER_COMPUTE_NOC },
1308 };
1309
1310 static struct qcom_icc_node qns_pcie_mem_noc = {
1311         .name = "qns_pcie_mem_noc",
1312         .id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC,
1313         .channels = 1,
1314         .buswidth = 16,
1315         .num_links = 1,
1316         .links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC },
1317 };
1318
1319 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1320         .name = "srvc_pcie_aggre_noc",
1321         .id = SM8550_SLAVE_SERVICE_PCIE_ANOC,
1322         .channels = 1,
1323         .buswidth = 4,
1324         .num_links = 0,
1325 };
1326
1327 static struct qcom_icc_node qns_gemnoc_gc = {
1328         .name = "qns_gemnoc_gc",
1329         .id = SM8550_SLAVE_SNOC_GEM_NOC_GC,
1330         .channels = 1,
1331         .buswidth = 8,
1332         .num_links = 1,
1333         .links = { SM8550_MASTER_SNOC_GC_MEM_NOC },
1334 };
1335
1336 static struct qcom_icc_node qns_gemnoc_sf = {
1337         .name = "qns_gemnoc_sf",
1338         .id = SM8550_SLAVE_SNOC_GEM_NOC_SF,
1339         .channels = 1,
1340         .buswidth = 16,
1341         .num_links = 1,
1342         .links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
1343 };
1344
1345 static struct qcom_icc_node qns_llcc_disp = {
1346         .name = "qns_llcc_disp",
1347         .id = SM8550_SLAVE_LLCC_DISP,
1348         .channels = 4,
1349         .buswidth = 16,
1350         .num_links = 1,
1351         .links = { SM8550_MASTER_LLCC_DISP },
1352 };
1353
1354 static struct qcom_icc_node ebi_disp = {
1355         .name = "ebi_disp",
1356         .id = SM8550_SLAVE_EBI1_DISP,
1357         .channels = 4,
1358         .buswidth = 4,
1359         .num_links = 0,
1360 };
1361
1362 static struct qcom_icc_node qns_mem_noc_hf_disp = {
1363         .name = "qns_mem_noc_hf_disp",
1364         .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP,
1365         .channels = 2,
1366         .buswidth = 32,
1367         .num_links = 1,
1368         .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_DISP },
1369 };
1370
1371 static struct qcom_icc_node qns_llcc_cam_ife_0 = {
1372         .name = "qns_llcc_cam_ife_0",
1373         .id = SM8550_SLAVE_LLCC_CAM_IFE_0,
1374         .channels = 4,
1375         .buswidth = 16,
1376         .num_links = 1,
1377         .links = { SM8550_MASTER_LLCC_CAM_IFE_0 },
1378 };
1379
1380 static struct qcom_icc_node ebi_cam_ife_0 = {
1381         .name = "ebi_cam_ife_0",
1382         .id = SM8550_SLAVE_EBI1_CAM_IFE_0,
1383         .channels = 4,
1384         .buswidth = 4,
1385         .num_links = 0,
1386 };
1387
1388 static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = {
1389         .name = "qns_mem_noc_hf_cam_ife_0",
1390         .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0,
1391         .channels = 2,
1392         .buswidth = 32,
1393         .num_links = 1,
1394         .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 },
1395 };
1396
1397 static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = {
1398         .name = "qns_mem_noc_sf_cam_ife_0",
1399         .id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0,
1400         .channels = 2,
1401         .buswidth = 32,
1402         .num_links = 1,
1403         .links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 },
1404 };
1405
1406 static struct qcom_icc_node qns_llcc_cam_ife_1 = {
1407         .name = "qns_llcc_cam_ife_1",
1408         .id = SM8550_SLAVE_LLCC_CAM_IFE_1,
1409         .channels = 4,
1410         .buswidth = 16,
1411         .num_links = 1,
1412         .links = { SM8550_MASTER_LLCC_CAM_IFE_1 },
1413 };
1414
1415 static struct qcom_icc_node ebi_cam_ife_1 = {
1416         .name = "ebi_cam_ife_1",
1417         .id = SM8550_SLAVE_EBI1_CAM_IFE_1,
1418         .channels = 4,
1419         .buswidth = 4,
1420         .num_links = 0,
1421 };
1422
1423 static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = {
1424         .name = "qns_mem_noc_hf_cam_ife_1",
1425         .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1,
1426         .channels = 2,
1427         .buswidth = 32,
1428         .num_links = 1,
1429         .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 },
1430 };
1431
1432 static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = {
1433         .name = "qns_mem_noc_sf_cam_ife_1",
1434         .id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1,
1435         .channels = 2,
1436         .buswidth = 32,
1437         .num_links = 1,
1438         .links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 },
1439 };
1440
1441 static struct qcom_icc_node qns_llcc_cam_ife_2 = {
1442         .name = "qns_llcc_cam_ife_2",
1443         .id = SM8550_SLAVE_LLCC_CAM_IFE_2,
1444         .channels = 4,
1445         .buswidth = 16,
1446         .num_links = 1,
1447         .links = { SM8550_MASTER_LLCC_CAM_IFE_2 },
1448 };
1449
1450 static struct qcom_icc_node ebi_cam_ife_2 = {
1451         .name = "ebi_cam_ife_2",
1452         .id = SM8550_SLAVE_EBI1_CAM_IFE_2,
1453         .channels = 4,
1454         .buswidth = 4,
1455         .num_links = 0,
1456 };
1457
1458 static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = {
1459         .name = "qns_mem_noc_hf_cam_ife_2",
1460         .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2,
1461         .channels = 2,
1462         .buswidth = 32,
1463         .num_links = 1,
1464         .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 },
1465 };
1466
1467 static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
1468         .name = "qns_mem_noc_sf_cam_ife_2",
1469         .id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2,
1470         .channels = 2,
1471         .buswidth = 32,
1472         .num_links = 1,
1473         .links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 },
1474 };
1475
1476 static struct qcom_icc_bcm bcm_acv = {
1477         .name = "ACV",
1478         .enable_mask = 0x8,
1479         .num_nodes = 1,
1480         .nodes = { &ebi },
1481 };
1482
1483 static struct qcom_icc_bcm bcm_ce0 = {
1484         .name = "CE0",
1485         .num_nodes = 1,
1486         .nodes = { &qxm_crypto },
1487 };
1488
1489 static struct qcom_icc_bcm bcm_cn0 = {
1490         .name = "CN0",
1491         .enable_mask = 0x1,
1492         .keepalive = true,
1493         .num_nodes = 54,
1494         .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1495                    &qhs_ahb2phy1, &qhs_apss,
1496                    &qhs_camera_cfg, &qhs_clk_ctl,
1497                    &qhs_cpr_cx, &qhs_cpr_mmcx,
1498                    &qhs_cpr_mxa, &qhs_cpr_mxc,
1499                    &qhs_cpr_nspcx, &qhs_crypto0_cfg,
1500                    &qhs_cx_rdpm, &qhs_gpuss_cfg,
1501                    &qhs_i2c, &qhs_imem_cfg,
1502                    &qhs_ipa, &qhs_ipc_router,
1503                    &qhs_mss_cfg, &qhs_mx_rdpm,
1504                    &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1505                    &qhs_pdm, &qhs_pimem_cfg,
1506                    &qhs_prng, &qhs_qdss_cfg,
1507                    &qhs_qspi, &qhs_qup1,
1508                    &qhs_qup2, &qhs_sdc2,
1509                    &qhs_sdc4, &qhs_spss_cfg,
1510                    &qhs_tcsr, &qhs_tlmm,
1511                    &qhs_ufs_mem_cfg, &qhs_usb3_0,
1512                    &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1513                    &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1514                    &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
1515                    &xs_qdss_stm, &xs_sys_tcu_cfg,
1516                    &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1517                    &qhs_aoss, &qhs_tme_cfg,
1518                    &qss_cfg, &qss_ddrss_cfg,
1519                    &qxs_boot_imem, &qxs_imem,
1520                    &xs_pcie_0, &xs_pcie_1 },
1521 };
1522
1523 static struct qcom_icc_bcm bcm_cn1 = {
1524         .name = "CN1",
1525         .num_nodes = 1,
1526         .nodes = { &qhs_display_cfg },
1527 };
1528
1529 static struct qcom_icc_bcm bcm_co0 = {
1530         .name = "CO0",
1531         .enable_mask = 0x1,
1532         .num_nodes = 2,
1533         .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1534 };
1535
1536 static struct qcom_icc_bcm bcm_lp0 = {
1537         .name = "LP0",
1538         .num_nodes = 2,
1539         .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1540 };
1541
1542 static struct qcom_icc_bcm bcm_mc0 = {
1543         .name = "MC0",
1544         .keepalive = true,
1545         .num_nodes = 1,
1546         .nodes = { &ebi },
1547 };
1548
1549 static struct qcom_icc_bcm bcm_mm0 = {
1550         .name = "MM0",
1551         .num_nodes = 1,
1552         .nodes = { &qns_mem_noc_hf },
1553 };
1554
1555 static struct qcom_icc_bcm bcm_mm1 = {
1556         .name = "MM1",
1557         .enable_mask = 0x1,
1558         .num_nodes = 8,
1559         .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1560                    &qnm_camnoc_sf, &qnm_vapss_hcp,
1561                    &qnm_video_cv_cpu, &qnm_video_cvp,
1562                    &qnm_video_v_cpu, &qns_mem_noc_sf },
1563 };
1564
1565 static struct qcom_icc_bcm bcm_qup0 = {
1566         .name = "QUP0",
1567         .keepalive = true,
1568         .vote_scale = 1,
1569         .num_nodes = 1,
1570         .nodes = { &qup0_core_slave },
1571 };
1572
1573 static struct qcom_icc_bcm bcm_qup1 = {
1574         .name = "QUP1",
1575         .keepalive = true,
1576         .vote_scale = 1,
1577         .num_nodes = 1,
1578         .nodes = { &qup1_core_slave },
1579 };
1580
1581 static struct qcom_icc_bcm bcm_qup2 = {
1582         .name = "QUP2",
1583         .keepalive = true,
1584         .vote_scale = 1,
1585         .num_nodes = 1,
1586         .nodes = { &qup2_core_slave },
1587 };
1588
1589 static struct qcom_icc_bcm bcm_sh0 = {
1590         .name = "SH0",
1591         .keepalive = true,
1592         .num_nodes = 1,
1593         .nodes = { &qns_llcc },
1594 };
1595
1596 static struct qcom_icc_bcm bcm_sh1 = {
1597         .name = "SH1",
1598         .enable_mask = 0x1,
1599         .num_nodes = 13,
1600         .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1601                    &chm_apps, &qnm_gpu,
1602                    &qnm_mdsp, &qnm_mnoc_hf,
1603                    &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1604                    &qnm_pcie, &qnm_snoc_gc,
1605                    &qnm_snoc_sf, &qns_gem_noc_cnoc,
1606                    &qns_pcie },
1607 };
1608
1609 static struct qcom_icc_bcm bcm_sn0 = {
1610         .name = "SN0",
1611         .keepalive = true,
1612         .num_nodes = 1,
1613         .nodes = { &qns_gemnoc_sf },
1614 };
1615
1616 static struct qcom_icc_bcm bcm_sn1 = {
1617         .name = "SN1",
1618         .enable_mask = 0x1,
1619         .num_nodes = 3,
1620         .nodes = { &qhm_gic, &xm_gic,
1621                    &qns_gemnoc_gc },
1622 };
1623
1624 static struct qcom_icc_bcm bcm_sn2 = {
1625         .name = "SN2",
1626         .num_nodes = 1,
1627         .nodes = { &qnm_aggre1_noc },
1628 };
1629
1630 static struct qcom_icc_bcm bcm_sn3 = {
1631         .name = "SN3",
1632         .num_nodes = 1,
1633         .nodes = { &qnm_aggre2_noc },
1634 };
1635
1636 static struct qcom_icc_bcm bcm_sn7 = {
1637         .name = "SN7",
1638         .num_nodes = 1,
1639         .nodes = { &qns_pcie_mem_noc },
1640 };
1641
1642 static struct qcom_icc_bcm bcm_acv_disp = {
1643         .name = "ACV",
1644         .enable_mask = 0x1,
1645         .num_nodes = 1,
1646         .nodes = { &ebi_disp },
1647 };
1648
1649 static struct qcom_icc_bcm bcm_mc0_disp = {
1650         .name = "MC0",
1651         .num_nodes = 1,
1652         .nodes = { &ebi_disp },
1653 };
1654
1655 static struct qcom_icc_bcm bcm_mm0_disp = {
1656         .name = "MM0",
1657         .num_nodes = 1,
1658         .nodes = { &qns_mem_noc_hf_disp },
1659 };
1660
1661 static struct qcom_icc_bcm bcm_sh0_disp = {
1662         .name = "SH0",
1663         .num_nodes = 1,
1664         .nodes = { &qns_llcc_disp },
1665 };
1666
1667 static struct qcom_icc_bcm bcm_sh1_disp = {
1668         .name = "SH1",
1669         .enable_mask = 0x1,
1670         .num_nodes = 2,
1671         .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
1672 };
1673
1674 static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
1675         .name = "ACV",
1676         .enable_mask = 0x0,
1677         .num_nodes = 1,
1678         .nodes = { &ebi_cam_ife_0 },
1679 };
1680
1681 static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = {
1682         .name = "MC0",
1683         .num_nodes = 1,
1684         .nodes = { &ebi_cam_ife_0 },
1685 };
1686
1687 static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
1688         .name = "MM0",
1689         .num_nodes = 1,
1690         .nodes = { &qns_mem_noc_hf_cam_ife_0 },
1691 };
1692
1693 static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
1694         .name = "MM1",
1695         .enable_mask = 0x1,
1696         .num_nodes = 4,
1697         .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
1698                    &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
1699 };
1700
1701 static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
1702         .name = "SH0",
1703         .num_nodes = 1,
1704         .nodes = { &qns_llcc_cam_ife_0 },
1705 };
1706
1707 static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
1708         .name = "SH1",
1709         .enable_mask = 0x1,
1710         .num_nodes = 3,
1711         .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
1712                    &qnm_pcie_cam_ife_0 },
1713 };
1714
1715 static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
1716         .name = "ACV",
1717         .enable_mask = 0x0,
1718         .num_nodes = 1,
1719         .nodes = { &ebi_cam_ife_1 },
1720 };
1721
1722 static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = {
1723         .name = "MC0",
1724         .num_nodes = 1,
1725         .nodes = { &ebi_cam_ife_1 },
1726 };
1727
1728 static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
1729         .name = "MM0",
1730         .num_nodes = 1,
1731         .nodes = { &qns_mem_noc_hf_cam_ife_1 },
1732 };
1733
1734 static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
1735         .name = "MM1",
1736         .enable_mask = 0x1,
1737         .num_nodes = 4,
1738         .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
1739                    &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
1740 };
1741
1742 static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
1743         .name = "SH0",
1744         .num_nodes = 1,
1745         .nodes = { &qns_llcc_cam_ife_1 },
1746 };
1747
1748 static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
1749         .name = "SH1",
1750         .enable_mask = 0x1,
1751         .num_nodes = 3,
1752         .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
1753                    &qnm_pcie_cam_ife_1 },
1754 };
1755
1756 static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
1757         .name = "ACV",
1758         .enable_mask = 0x0,
1759         .num_nodes = 1,
1760         .nodes = { &ebi_cam_ife_2 },
1761 };
1762
1763 static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = {
1764         .name = "MC0",
1765         .num_nodes = 1,
1766         .nodes = { &ebi_cam_ife_2 },
1767 };
1768
1769 static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
1770         .name = "MM0",
1771         .num_nodes = 1,
1772         .nodes = { &qns_mem_noc_hf_cam_ife_2 },
1773 };
1774
1775 static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
1776         .name = "MM1",
1777         .enable_mask = 0x1,
1778         .num_nodes = 4,
1779         .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
1780                    &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
1781 };
1782
1783 static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
1784         .name = "SH0",
1785         .num_nodes = 1,
1786         .nodes = { &qns_llcc_cam_ife_2 },
1787 };
1788
1789 static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
1790         .name = "SH1",
1791         .enable_mask = 0x1,
1792         .num_nodes = 3,
1793         .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
1794                    &qnm_pcie_cam_ife_2 },
1795 };
1796
1797 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1798 };
1799
1800 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1801         [MASTER_QSPI_0] = &qhm_qspi,
1802         [MASTER_QUP_1] = &qhm_qup1,
1803         [MASTER_SDCC_4] = &xm_sdc4,
1804         [MASTER_UFS_MEM] = &xm_ufs_mem,
1805         [MASTER_USB3_0] = &xm_usb3_0,
1806         [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1807 };
1808
1809 static const struct qcom_icc_desc sm8550_aggre1_noc = {
1810         .nodes = aggre1_noc_nodes,
1811         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1812         .bcms = aggre1_noc_bcms,
1813         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1814 };
1815
1816 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1817         &bcm_ce0,
1818 };
1819
1820 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1821         [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1822         [MASTER_QUP_2] = &qhm_qup2,
1823         [MASTER_CRYPTO] = &qxm_crypto,
1824         [MASTER_IPA] = &qxm_ipa,
1825         [MASTER_SP] = &qxm_sp,
1826         [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1827         [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1828         [MASTER_SDCC_2] = &xm_sdc2,
1829         [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1830 };
1831
1832 static const struct qcom_icc_desc sm8550_aggre2_noc = {
1833         .nodes = aggre2_noc_nodes,
1834         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1835         .bcms = aggre2_noc_bcms,
1836         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1837 };
1838
1839 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1840         &bcm_qup0,
1841         &bcm_qup1,
1842         &bcm_qup2,
1843 };
1844
1845 static struct qcom_icc_node * const clk_virt_nodes[] = {
1846         [MASTER_QUP_CORE_0] = &qup0_core_master,
1847         [MASTER_QUP_CORE_1] = &qup1_core_master,
1848         [MASTER_QUP_CORE_2] = &qup2_core_master,
1849         [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1850         [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1851         [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1852 };
1853
1854 static const struct qcom_icc_desc sm8550_clk_virt = {
1855         .nodes = clk_virt_nodes,
1856         .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1857         .bcms = clk_virt_bcms,
1858         .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1859 };
1860
1861 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1862         &bcm_cn0,
1863         &bcm_cn1,
1864 };
1865
1866 static struct qcom_icc_node * const config_noc_nodes[] = {
1867         [MASTER_CNOC_CFG] = &qsm_cfg,
1868         [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1869         [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1870         [SLAVE_APPSS] = &qhs_apss,
1871         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1872         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1873         [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1874         [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1875         [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1876         [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1877         [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1878         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1879         [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1880         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1881         [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1882         [SLAVE_I2C] = &qhs_i2c,
1883         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1884         [SLAVE_IPA_CFG] = &qhs_ipa,
1885         [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1886         [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1887         [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1888         [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1889         [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1890         [SLAVE_PDM] = &qhs_pdm,
1891         [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1892         [SLAVE_PRNG] = &qhs_prng,
1893         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1894         [SLAVE_QSPI_0] = &qhs_qspi,
1895         [SLAVE_QUP_1] = &qhs_qup1,
1896         [SLAVE_QUP_2] = &qhs_qup2,
1897         [SLAVE_SDCC_2] = &qhs_sdc2,
1898         [SLAVE_SDCC_4] = &qhs_sdc4,
1899         [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1900         [SLAVE_TCSR] = &qhs_tcsr,
1901         [SLAVE_TLMM] = &qhs_tlmm,
1902         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1903         [SLAVE_USB3_0] = &qhs_usb3_0,
1904         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1905         [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1906         [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1907         [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1908         [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1909         [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1910         [SLAVE_QDSS_STM] = &xs_qdss_stm,
1911         [SLAVE_TCU] = &xs_sys_tcu_cfg,
1912 };
1913
1914 static const struct qcom_icc_desc sm8550_config_noc = {
1915         .nodes = config_noc_nodes,
1916         .num_nodes = ARRAY_SIZE(config_noc_nodes),
1917         .bcms = config_noc_bcms,
1918         .num_bcms = ARRAY_SIZE(config_noc_bcms),
1919 };
1920
1921 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1922         &bcm_cn0,
1923 };
1924
1925 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1926         [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1927         [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1928         [SLAVE_AOSS] = &qhs_aoss,
1929         [SLAVE_TME_CFG] = &qhs_tme_cfg,
1930         [SLAVE_CNOC_CFG] = &qss_cfg,
1931         [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1932         [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1933         [SLAVE_IMEM] = &qxs_imem,
1934         [SLAVE_PCIE_0] = &xs_pcie_0,
1935         [SLAVE_PCIE_1] = &xs_pcie_1,
1936 };
1937
1938 static const struct qcom_icc_desc sm8550_cnoc_main = {
1939         .nodes = cnoc_main_nodes,
1940         .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1941         .bcms = cnoc_main_bcms,
1942         .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1943 };
1944
1945 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1946         &bcm_sh0,
1947         &bcm_sh1,
1948         &bcm_sh0_disp,
1949         &bcm_sh1_disp,
1950         &bcm_sh0_cam_ife_0,
1951         &bcm_sh1_cam_ife_0,
1952         &bcm_sh0_cam_ife_1,
1953         &bcm_sh1_cam_ife_1,
1954         &bcm_sh0_cam_ife_2,
1955         &bcm_sh1_cam_ife_2,
1956 };
1957
1958 static struct qcom_icc_node * const gem_noc_nodes[] = {
1959         [MASTER_GPU_TCU] = &alm_gpu_tcu,
1960         [MASTER_SYS_TCU] = &alm_sys_tcu,
1961         [MASTER_APPSS_PROC] = &chm_apps,
1962         [MASTER_GFX3D] = &qnm_gpu,
1963         [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1964         [MASTER_MSS_PROC] = &qnm_mdsp,
1965         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1966         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1967         [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1968         [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1969         [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1970         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1971         [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1972         [SLAVE_LLCC] = &qns_llcc,
1973         [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1974         [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1975         [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1976         [SLAVE_LLCC_DISP] = &qns_llcc_disp,
1977         [MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0,
1978         [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0,
1979         [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0,
1980         [SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0,
1981         [MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1,
1982         [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1,
1983         [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1,
1984         [SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1,
1985         [MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2,
1986         [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2,
1987         [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2,
1988         [SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2,
1989 };
1990
1991 static const struct qcom_icc_desc sm8550_gem_noc = {
1992         .nodes = gem_noc_nodes,
1993         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1994         .bcms = gem_noc_bcms,
1995         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1996 };
1997
1998 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1999 };
2000
2001 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2002         [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
2003         [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
2004 };
2005
2006 static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
2007         .nodes = lpass_ag_noc_nodes,
2008         .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2009         .bcms = lpass_ag_noc_bcms,
2010         .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2011 };
2012
2013 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
2014         &bcm_lp0,
2015 };
2016
2017 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
2018         [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
2019         [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
2020 };
2021
2022 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
2023         .nodes = lpass_lpiaon_noc_nodes,
2024         .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
2025         .bcms = lpass_lpiaon_noc_bcms,
2026         .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
2027 };
2028
2029 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
2030 };
2031
2032 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
2033         [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
2034         [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
2035 };
2036
2037 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
2038         .nodes = lpass_lpicx_noc_nodes,
2039         .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
2040         .bcms = lpass_lpicx_noc_bcms,
2041         .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
2042 };
2043
2044 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2045         &bcm_acv,
2046         &bcm_mc0,
2047         &bcm_acv_disp,
2048         &bcm_mc0_disp,
2049         &bcm_acv_cam_ife_0,
2050         &bcm_mc0_cam_ife_0,
2051         &bcm_acv_cam_ife_1,
2052         &bcm_mc0_cam_ife_1,
2053         &bcm_acv_cam_ife_2,
2054         &bcm_mc0_cam_ife_2,
2055 };
2056
2057 static struct qcom_icc_node * const mc_virt_nodes[] = {
2058         [MASTER_LLCC] = &llcc_mc,
2059         [SLAVE_EBI1] = &ebi,
2060         [MASTER_LLCC_DISP] = &llcc_mc_disp,
2061         [SLAVE_EBI1_DISP] = &ebi_disp,
2062         [MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0,
2063         [SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0,
2064         [MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1,
2065         [SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1,
2066         [MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2,
2067         [SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2,
2068 };
2069
2070 static const struct qcom_icc_desc sm8550_mc_virt = {
2071         .nodes = mc_virt_nodes,
2072         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
2073         .bcms = mc_virt_bcms,
2074         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
2075 };
2076
2077 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2078         &bcm_mm0,
2079         &bcm_mm1,
2080         &bcm_mm0_disp,
2081         &bcm_mm0_cam_ife_0,
2082         &bcm_mm1_cam_ife_0,
2083         &bcm_mm0_cam_ife_1,
2084         &bcm_mm1_cam_ife_1,
2085         &bcm_mm0_cam_ife_2,
2086         &bcm_mm1_cam_ife_2,
2087 };
2088
2089 static struct qcom_icc_node * const mmss_noc_nodes[] = {
2090         [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2091         [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2092         [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2093         [MASTER_MDP] = &qnm_mdp,
2094         [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
2095         [MASTER_VIDEO] = &qnm_video,
2096         [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
2097         [MASTER_VIDEO_PROC] = &qnm_video_cvp,
2098         [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2099         [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
2100         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2101         [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2102         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2103         [MASTER_MDP_DISP] = &qnm_mdp_disp,
2104         [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
2105         [MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0,
2106         [MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0,
2107         [MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0,
2108         [SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0,
2109         [SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0,
2110         [MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1,
2111         [MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1,
2112         [MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1,
2113         [SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1,
2114         [SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1,
2115         [MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2,
2116         [MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2,
2117         [MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2,
2118         [SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2,
2119         [SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2,
2120 };
2121
2122 static const struct qcom_icc_desc sm8550_mmss_noc = {
2123         .nodes = mmss_noc_nodes,
2124         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2125         .bcms = mmss_noc_bcms,
2126         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2127 };
2128
2129 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
2130         &bcm_co0,
2131 };
2132
2133 static struct qcom_icc_node * const nsp_noc_nodes[] = {
2134         [MASTER_CDSP_PROC] = &qxm_nsp,
2135         [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2136 };
2137
2138 static const struct qcom_icc_desc sm8550_nsp_noc = {
2139         .nodes = nsp_noc_nodes,
2140         .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
2141         .bcms = nsp_noc_bcms,
2142         .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
2143 };
2144
2145 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2146         &bcm_sn7,
2147 };
2148
2149 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2150         [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
2151         [MASTER_PCIE_0] = &xm_pcie3_0,
2152         [MASTER_PCIE_1] = &xm_pcie3_1,
2153         [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2154         [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
2155 };
2156
2157 static const struct qcom_icc_desc sm8550_pcie_anoc = {
2158         .nodes = pcie_anoc_nodes,
2159         .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2160         .bcms = pcie_anoc_bcms,
2161         .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2162 };
2163
2164 static struct qcom_icc_bcm * const system_noc_bcms[] = {
2165         &bcm_sn0,
2166         &bcm_sn1,
2167         &bcm_sn2,
2168         &bcm_sn3,
2169 };
2170
2171 static struct qcom_icc_node * const system_noc_nodes[] = {
2172         [MASTER_GIC_AHB] = &qhm_gic,
2173         [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2174         [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2175         [MASTER_GIC] = &xm_gic,
2176         [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2177         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2178 };
2179
2180 static const struct qcom_icc_desc sm8550_system_noc = {
2181         .nodes = system_noc_nodes,
2182         .num_nodes = ARRAY_SIZE(system_noc_nodes),
2183         .bcms = system_noc_bcms,
2184         .num_bcms = ARRAY_SIZE(system_noc_bcms),
2185 };
2186
2187 static const struct of_device_id qnoc_of_match[] = {
2188         { .compatible = "qcom,sm8550-aggre1-noc",
2189           .data = &sm8550_aggre1_noc},
2190         { .compatible = "qcom,sm8550-aggre2-noc",
2191           .data = &sm8550_aggre2_noc},
2192         { .compatible = "qcom,sm8550-clk-virt",
2193           .data = &sm8550_clk_virt},
2194         { .compatible = "qcom,sm8550-config-noc",
2195           .data = &sm8550_config_noc},
2196         { .compatible = "qcom,sm8550-cnoc-main",
2197           .data = &sm8550_cnoc_main},
2198         { .compatible = "qcom,sm8550-gem-noc",
2199           .data = &sm8550_gem_noc},
2200         { .compatible = "qcom,sm8550-lpass-ag-noc",
2201           .data = &sm8550_lpass_ag_noc},
2202         { .compatible = "qcom,sm8550-lpass-lpiaon-noc",
2203           .data = &sm8550_lpass_lpiaon_noc},
2204         { .compatible = "qcom,sm8550-lpass-lpicx-noc",
2205           .data = &sm8550_lpass_lpicx_noc},
2206         { .compatible = "qcom,sm8550-mc-virt",
2207           .data = &sm8550_mc_virt},
2208         { .compatible = "qcom,sm8550-mmss-noc",
2209           .data = &sm8550_mmss_noc},
2210         { .compatible = "qcom,sm8550-nsp-noc",
2211           .data = &sm8550_nsp_noc},
2212         { .compatible = "qcom,sm8550-pcie-anoc",
2213           .data = &sm8550_pcie_anoc},
2214         { .compatible = "qcom,sm8550-system-noc",
2215           .data = &sm8550_system_noc},
2216         { }
2217 };
2218 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2219
2220 static struct platform_driver qnoc_driver = {
2221         .probe = qcom_icc_rpmh_probe,
2222         .remove_new = qcom_icc_rpmh_remove,
2223         .driver = {
2224                 .name = "qnoc-sm8550",
2225                 .of_match_table = qnoc_of_match,
2226                 .sync_state = icc_sync_state,
2227         },
2228 };
2229
2230 static int __init qnoc_driver_init(void)
2231 {
2232         return platform_driver_register(&qnoc_driver);
2233 }
2234 core_initcall(qnoc_driver_init);
2235
2236 static void __exit qnoc_driver_exit(void)
2237 {
2238         platform_driver_unregister(&qnoc_driver);
2239 }
2240 module_exit(qnoc_driver_exit);
2241
2242 MODULE_DESCRIPTION("sm8550 NoC driver");
2243 MODULE_LICENSE("GPL");