1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <linux/device.h>
7 #include <linux/interconnect.h>
8 #include <linux/interconnect-provider.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <dt-bindings/interconnect/qcom,sdx65.h>
14 #include "bcm-voter.h"
18 static struct qcom_icc_node llcc_mc = {
20 .id = SDX65_MASTER_LLCC,
24 .links = { SDX65_SLAVE_EBI1 },
27 static struct qcom_icc_node acm_tcu = {
29 .id = SDX65_MASTER_TCU_0,
33 .links = { SDX65_SLAVE_LLCC,
34 SDX65_SLAVE_MEM_NOC_SNOC,
35 SDX65_SLAVE_MEM_NOC_PCIE_SNOC
39 static struct qcom_icc_node qnm_snoc_gc = {
40 .name = "qnm_snoc_gc",
41 .id = SDX65_MASTER_SNOC_GC_MEM_NOC,
45 .links = { SDX65_SLAVE_LLCC },
48 static struct qcom_icc_node xm_apps_rdwr = {
49 .name = "xm_apps_rdwr",
50 .id = SDX65_MASTER_APPSS_PROC,
54 .links = { SDX65_SLAVE_LLCC,
55 SDX65_SLAVE_MEM_NOC_SNOC,
56 SDX65_SLAVE_MEM_NOC_PCIE_SNOC
60 static struct qcom_icc_node qhm_audio = {
62 .id = SDX65_MASTER_AUDIO,
66 .links = { SDX65_SLAVE_ANOC_SNOC },
69 static struct qcom_icc_node qhm_blsp1 = {
71 .id = SDX65_MASTER_BLSP_1,
75 .links = { SDX65_SLAVE_ANOC_SNOC },
78 static struct qcom_icc_node qhm_qdss_bam = {
79 .name = "qhm_qdss_bam",
80 .id = SDX65_MASTER_QDSS_BAM,
84 .links = { SDX65_SLAVE_AOSS,
88 SDX65_SLAVE_CRYPTO_0_CFG,
89 SDX65_SLAVE_CNOC_DDRSS,
94 SDX65_SLAVE_PCIE_PARF,
100 SDX65_SLAVE_SNOC_CFG,
101 SDX65_SLAVE_SPMI_FETCHER,
102 SDX65_SLAVE_SPMI_VGI_COEX,
106 SDX65_SLAVE_USB3_PHY_CFG,
107 SDX65_SLAVE_SNOC_MEM_NOC_GC,
113 static struct qcom_icc_node qhm_qpic = {
115 .id = SDX65_MASTER_QPIC,
119 .links = { SDX65_SLAVE_AOSS,
122 SDX65_SLAVE_ANOC_SNOC
126 static struct qcom_icc_node qhm_snoc_cfg = {
127 .name = "qhm_snoc_cfg",
128 .id = SDX65_MASTER_SNOC_CFG,
132 .links = { SDX65_SLAVE_SERVICE_SNOC },
135 static struct qcom_icc_node qhm_spmi_fetcher1 = {
136 .name = "qhm_spmi_fetcher1",
137 .id = SDX65_MASTER_SPMI_FETCHER,
141 .links = { SDX65_SLAVE_AOSS,
142 SDX65_SLAVE_ANOC_SNOC
146 static struct qcom_icc_node qnm_aggre_noc = {
147 .name = "qnm_aggre_noc",
148 .id = SDX65_MASTER_ANOC_SNOC,
152 .links = { SDX65_SLAVE_AOSS,
157 SDX65_SLAVE_CRYPTO_0_CFG,
158 SDX65_SLAVE_CNOC_DDRSS,
160 SDX65_SLAVE_IMEM_CFG,
162 SDX65_SLAVE_CNOC_MSS,
163 SDX65_SLAVE_PCIE_PARF,
166 SDX65_SLAVE_QDSS_CFG,
169 SDX65_SLAVE_SNOC_CFG,
170 SDX65_SLAVE_SPMI_FETCHER,
171 SDX65_SLAVE_SPMI_VGI_COEX,
175 SDX65_SLAVE_USB3_PHY_CFG,
176 SDX65_SLAVE_SNOC_MEM_NOC_GC,
179 SDX65_SLAVE_QDSS_STM,
184 static struct qcom_icc_node qnm_ipa = {
186 .id = SDX65_MASTER_IPA,
190 .links = { SDX65_SLAVE_AOSS,
194 SDX65_SLAVE_CRYPTO_0_CFG,
195 SDX65_SLAVE_CNOC_DDRSS,
197 SDX65_SLAVE_IMEM_CFG,
199 SDX65_SLAVE_CNOC_MSS,
200 SDX65_SLAVE_PCIE_PARF,
203 SDX65_SLAVE_QDSS_CFG,
206 SDX65_SLAVE_SNOC_CFG,
207 SDX65_SLAVE_SPMI_FETCHER,
211 SDX65_SLAVE_USB3_PHY_CFG,
212 SDX65_SLAVE_SNOC_MEM_NOC_GC,
219 static struct qcom_icc_node qnm_memnoc = {
220 .name = "qnm_memnoc",
221 .id = SDX65_MASTER_MEM_NOC_SNOC,
225 .links = { SDX65_SLAVE_AOSS,
230 SDX65_SLAVE_CRYPTO_0_CFG,
231 SDX65_SLAVE_CNOC_DDRSS,
233 SDX65_SLAVE_IMEM_CFG,
235 SDX65_SLAVE_CNOC_MSS,
236 SDX65_SLAVE_PCIE_PARF,
239 SDX65_SLAVE_QDSS_CFG,
242 SDX65_SLAVE_SNOC_CFG,
243 SDX65_SLAVE_SPMI_FETCHER,
244 SDX65_SLAVE_SPMI_VGI_COEX,
248 SDX65_SLAVE_USB3_PHY_CFG,
250 SDX65_SLAVE_QDSS_STM,
255 static struct qcom_icc_node qnm_memnoc_pcie = {
256 .name = "qnm_memnoc_pcie",
257 .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC,
261 .links = { SDX65_SLAVE_PCIE_0 },
264 static struct qcom_icc_node qxm_crypto = {
265 .name = "qxm_crypto",
266 .id = SDX65_MASTER_CRYPTO,
270 .links = { SDX65_SLAVE_AOSS,
271 SDX65_SLAVE_ANOC_SNOC
275 static struct qcom_icc_node xm_ipa2pcie_slv = {
276 .name = "xm_ipa2pcie_slv",
277 .id = SDX65_MASTER_IPA_PCIE,
281 .links = { SDX65_SLAVE_PCIE_0 },
284 static struct qcom_icc_node xm_pcie = {
286 .id = SDX65_MASTER_PCIE_0,
290 .links = { SDX65_SLAVE_ANOC_SNOC },
293 static struct qcom_icc_node xm_qdss_etr = {
294 .name = "xm_qdss_etr",
295 .id = SDX65_MASTER_QDSS_ETR,
299 .links = { SDX65_SLAVE_AOSS,
303 SDX65_SLAVE_CRYPTO_0_CFG,
304 SDX65_SLAVE_CNOC_DDRSS,
306 SDX65_SLAVE_IMEM_CFG,
308 SDX65_SLAVE_CNOC_MSS,
309 SDX65_SLAVE_PCIE_PARF,
312 SDX65_SLAVE_QDSS_CFG,
315 SDX65_SLAVE_SNOC_CFG,
316 SDX65_SLAVE_SPMI_FETCHER,
317 SDX65_SLAVE_SPMI_VGI_COEX,
321 SDX65_SLAVE_USB3_PHY_CFG,
322 SDX65_SLAVE_SNOC_MEM_NOC_GC,
328 static struct qcom_icc_node xm_sdc1 = {
330 .id = SDX65_MASTER_SDCC_1,
334 .links = { SDX65_SLAVE_AOSS,
337 SDX65_SLAVE_ANOC_SNOC
341 static struct qcom_icc_node xm_usb3 = {
343 .id = SDX65_MASTER_USB3,
347 .links = { SDX65_SLAVE_ANOC_SNOC },
350 static struct qcom_icc_node ebi = {
352 .id = SDX65_SLAVE_EBI1,
357 static struct qcom_icc_node qns_llcc = {
359 .id = SDX65_SLAVE_LLCC,
363 .links = { SDX65_MASTER_LLCC },
366 static struct qcom_icc_node qns_memnoc_snoc = {
367 .name = "qns_memnoc_snoc",
368 .id = SDX65_SLAVE_MEM_NOC_SNOC,
372 .links = { SDX65_MASTER_MEM_NOC_SNOC },
375 static struct qcom_icc_node qns_sys_pcie = {
376 .name = "qns_sys_pcie",
377 .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC,
381 .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC },
384 static struct qcom_icc_node qhs_aoss = {
386 .id = SDX65_SLAVE_AOSS,
391 static struct qcom_icc_node qhs_apss = {
393 .id = SDX65_SLAVE_APPSS,
398 static struct qcom_icc_node qhs_audio = {
400 .id = SDX65_SLAVE_AUDIO,
405 static struct qcom_icc_node qhs_blsp1 = {
407 .id = SDX65_SLAVE_BLSP_1,
412 static struct qcom_icc_node qhs_clk_ctl = {
413 .name = "qhs_clk_ctl",
414 .id = SDX65_SLAVE_CLK_CTL,
419 static struct qcom_icc_node qhs_crypto0_cfg = {
420 .name = "qhs_crypto0_cfg",
421 .id = SDX65_SLAVE_CRYPTO_0_CFG,
426 static struct qcom_icc_node qhs_ddrss_cfg = {
427 .name = "qhs_ddrss_cfg",
428 .id = SDX65_SLAVE_CNOC_DDRSS,
433 static struct qcom_icc_node qhs_ecc_cfg = {
434 .name = "qhs_ecc_cfg",
435 .id = SDX65_SLAVE_ECC_CFG,
440 static struct qcom_icc_node qhs_imem_cfg = {
441 .name = "qhs_imem_cfg",
442 .id = SDX65_SLAVE_IMEM_CFG,
447 static struct qcom_icc_node qhs_ipa = {
449 .id = SDX65_SLAVE_IPA_CFG,
454 static struct qcom_icc_node qhs_mss_cfg = {
455 .name = "qhs_mss_cfg",
456 .id = SDX65_SLAVE_CNOC_MSS,
461 static struct qcom_icc_node qhs_pcie_parf = {
462 .name = "qhs_pcie_parf",
463 .id = SDX65_SLAVE_PCIE_PARF,
468 static struct qcom_icc_node qhs_pdm = {
470 .id = SDX65_SLAVE_PDM,
475 static struct qcom_icc_node qhs_prng = {
477 .id = SDX65_SLAVE_PRNG,
482 static struct qcom_icc_node qhs_qdss_cfg = {
483 .name = "qhs_qdss_cfg",
484 .id = SDX65_SLAVE_QDSS_CFG,
489 static struct qcom_icc_node qhs_qpic = {
491 .id = SDX65_SLAVE_QPIC,
496 static struct qcom_icc_node qhs_sdc1 = {
498 .id = SDX65_SLAVE_SDCC_1,
503 static struct qcom_icc_node qhs_snoc_cfg = {
504 .name = "qhs_snoc_cfg",
505 .id = SDX65_SLAVE_SNOC_CFG,
509 .links = { SDX65_MASTER_SNOC_CFG },
512 static struct qcom_icc_node qhs_spmi_fetcher = {
513 .name = "qhs_spmi_fetcher",
514 .id = SDX65_SLAVE_SPMI_FETCHER,
519 static struct qcom_icc_node qhs_spmi_vgi_coex = {
520 .name = "qhs_spmi_vgi_coex",
521 .id = SDX65_SLAVE_SPMI_VGI_COEX,
526 static struct qcom_icc_node qhs_tcsr = {
528 .id = SDX65_SLAVE_TCSR,
533 static struct qcom_icc_node qhs_tlmm = {
535 .id = SDX65_SLAVE_TLMM,
540 static struct qcom_icc_node qhs_usb3 = {
542 .id = SDX65_SLAVE_USB3,
547 static struct qcom_icc_node qhs_usb3_phy = {
548 .name = "qhs_usb3_phy",
549 .id = SDX65_SLAVE_USB3_PHY_CFG,
554 static struct qcom_icc_node qns_aggre_noc = {
555 .name = "qns_aggre_noc",
556 .id = SDX65_SLAVE_ANOC_SNOC,
560 .links = { SDX65_MASTER_ANOC_SNOC },
563 static struct qcom_icc_node qns_snoc_memnoc = {
564 .name = "qns_snoc_memnoc",
565 .id = SDX65_SLAVE_SNOC_MEM_NOC_GC,
569 .links = { SDX65_MASTER_SNOC_GC_MEM_NOC },
572 static struct qcom_icc_node qxs_imem = {
574 .id = SDX65_SLAVE_IMEM,
579 static struct qcom_icc_node srvc_snoc = {
581 .id = SDX65_SLAVE_SERVICE_SNOC,
586 static struct qcom_icc_node xs_pcie = {
588 .id = SDX65_SLAVE_PCIE_0,
593 static struct qcom_icc_node xs_qdss_stm = {
594 .name = "xs_qdss_stm",
595 .id = SDX65_SLAVE_QDSS_STM,
600 static struct qcom_icc_node xs_sys_tcu_cfg = {
601 .name = "xs_sys_tcu_cfg",
602 .id = SDX65_SLAVE_TCU,
607 static struct qcom_icc_bcm bcm_ce0 = {
611 .nodes = { &qxm_crypto },
614 static struct qcom_icc_bcm bcm_mc0 = {
621 static struct qcom_icc_bcm bcm_pn0 = {
625 .nodes = { &qhm_snoc_cfg,
654 static struct qcom_icc_bcm bcm_pn1 = {
658 .nodes = { &xm_sdc1 },
661 static struct qcom_icc_bcm bcm_pn2 = {
665 .nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
668 static struct qcom_icc_bcm bcm_pn3 = {
672 .nodes = { &qhm_blsp1, &qhm_qpic },
675 static struct qcom_icc_bcm bcm_pn4 = {
679 .nodes = { &qxm_crypto },
682 static struct qcom_icc_bcm bcm_sh0 = {
686 .nodes = { &qns_llcc },
689 static struct qcom_icc_bcm bcm_sh1 = {
693 .nodes = { &qns_memnoc_snoc },
696 static struct qcom_icc_bcm bcm_sh3 = {
700 .nodes = { &xm_apps_rdwr },
703 static struct qcom_icc_bcm bcm_sn0 = {
707 .nodes = { &qns_snoc_memnoc },
710 static struct qcom_icc_bcm bcm_sn1 = {
714 .nodes = { &qxs_imem },
717 static struct qcom_icc_bcm bcm_sn2 = {
721 .nodes = { &xs_qdss_stm },
724 static struct qcom_icc_bcm bcm_sn3 = {
728 .nodes = { &xs_sys_tcu_cfg },
731 static struct qcom_icc_bcm bcm_sn5 = {
735 .nodes = { &xs_pcie },
738 static struct qcom_icc_bcm bcm_sn6 = {
742 .nodes = { &qhm_qdss_bam, &xm_qdss_etr },
745 static struct qcom_icc_bcm bcm_sn7 = {
749 .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc },
752 static struct qcom_icc_bcm bcm_sn8 = {
756 .nodes = { &qnm_memnoc },
759 static struct qcom_icc_bcm bcm_sn9 = {
763 .nodes = { &qnm_memnoc_pcie },
766 static struct qcom_icc_bcm bcm_sn10 = {
770 .nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
773 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
777 static struct qcom_icc_node * const mc_virt_nodes[] = {
778 [MASTER_LLCC] = &llcc_mc,
782 static const struct qcom_icc_desc sdx65_mc_virt = {
783 .nodes = mc_virt_nodes,
784 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
785 .bcms = mc_virt_bcms,
786 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
789 static struct qcom_icc_bcm * const mem_noc_bcms[] = {
795 static struct qcom_icc_node * const mem_noc_nodes[] = {
796 [MASTER_TCU_0] = &acm_tcu,
797 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
798 [MASTER_APPSS_PROC] = &xm_apps_rdwr,
799 [SLAVE_LLCC] = &qns_llcc,
800 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
801 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
804 static const struct qcom_icc_desc sdx65_mem_noc = {
805 .nodes = mem_noc_nodes,
806 .num_nodes = ARRAY_SIZE(mem_noc_nodes),
807 .bcms = mem_noc_bcms,
808 .num_bcms = ARRAY_SIZE(mem_noc_bcms),
811 static struct qcom_icc_bcm * const system_noc_bcms[] = {
830 static struct qcom_icc_node * const system_noc_nodes[] = {
831 [MASTER_AUDIO] = &qhm_audio,
832 [MASTER_BLSP_1] = &qhm_blsp1,
833 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
834 [MASTER_QPIC] = &qhm_qpic,
835 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
836 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
837 [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
838 [MASTER_IPA] = &qnm_ipa,
839 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
840 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
841 [MASTER_CRYPTO] = &qxm_crypto,
842 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
843 [MASTER_PCIE_0] = &xm_pcie,
844 [MASTER_QDSS_ETR] = &xm_qdss_etr,
845 [MASTER_SDCC_1] = &xm_sdc1,
846 [MASTER_USB3] = &xm_usb3,
847 [SLAVE_AOSS] = &qhs_aoss,
848 [SLAVE_APPSS] = &qhs_apss,
849 [SLAVE_AUDIO] = &qhs_audio,
850 [SLAVE_BLSP_1] = &qhs_blsp1,
851 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
852 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
853 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
854 [SLAVE_ECC_CFG] = &qhs_ecc_cfg,
855 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
856 [SLAVE_IPA_CFG] = &qhs_ipa,
857 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
858 [SLAVE_PCIE_PARF] = &qhs_pcie_parf,
859 [SLAVE_PDM] = &qhs_pdm,
860 [SLAVE_PRNG] = &qhs_prng,
861 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
862 [SLAVE_QPIC] = &qhs_qpic,
863 [SLAVE_SDCC_1] = &qhs_sdc1,
864 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
865 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
866 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
867 [SLAVE_TCSR] = &qhs_tcsr,
868 [SLAVE_TLMM] = &qhs_tlmm,
869 [SLAVE_USB3] = &qhs_usb3,
870 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
871 [SLAVE_ANOC_SNOC] = &qns_aggre_noc,
872 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
873 [SLAVE_IMEM] = &qxs_imem,
874 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
875 [SLAVE_PCIE_0] = &xs_pcie,
876 [SLAVE_QDSS_STM] = &xs_qdss_stm,
877 [SLAVE_TCU] = &xs_sys_tcu_cfg,
880 static const struct qcom_icc_desc sdx65_system_noc = {
881 .nodes = system_noc_nodes,
882 .num_nodes = ARRAY_SIZE(system_noc_nodes),
883 .bcms = system_noc_bcms,
884 .num_bcms = ARRAY_SIZE(system_noc_bcms),
887 static const struct of_device_id qnoc_of_match[] = {
888 { .compatible = "qcom,sdx65-mc-virt",
889 .data = &sdx65_mc_virt},
890 { .compatible = "qcom,sdx65-mem-noc",
891 .data = &sdx65_mem_noc},
892 { .compatible = "qcom,sdx65-system-noc",
893 .data = &sdx65_system_noc},
896 MODULE_DEVICE_TABLE(of, qnoc_of_match);
898 static struct platform_driver qnoc_driver = {
899 .probe = qcom_icc_rpmh_probe,
900 .remove_new = qcom_icc_rpmh_remove,
902 .name = "qnoc-sdx65",
903 .of_match_table = qnoc_of_match,
904 .sync_state = icc_sync_state,
907 module_platform_driver(qnoc_driver);
909 MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver");
910 MODULE_LICENSE("GPL v2");