1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
4 * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
7 #include <dt-bindings/interconnect/qcom,sdm660.h>
8 #include <linux/device.h>
9 #include <linux/interconnect-provider.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
20 SDM660_MASTER_IPA = 1,
21 SDM660_MASTER_CNOC_A2NOC,
29 SDM660_MASTER_CRYPTO_C0,
30 SDM660_MASTER_GNOC_BIMC,
32 SDM660_MASTER_MNOC_BIMC,
33 SDM660_MASTER_SNOC_BIMC,
35 SDM660_MASTER_SNOC_CNOC,
36 SDM660_MASTER_QDSS_DAP,
37 SDM660_MASTER_APPS_PROC,
38 SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
39 SDM660_MASTER_CNOC_MNOC_CFG,
46 SDM660_MASTER_QDSS_ETR,
47 SDM660_MASTER_QDSS_BAM,
48 SDM660_MASTER_SNOC_CFG,
49 SDM660_MASTER_BIMC_SNOC,
50 SDM660_MASTER_A2NOC_SNOC,
51 SDM660_MASTER_GNOC_SNOC,
53 SDM660_SLAVE_A2NOC_SNOC,
56 SDM660_SLAVE_BIMC_SNOC,
57 SDM660_SLAVE_CNOC_A2NOC,
59 SDM660_SLAVE_PMIC_ARB,
60 SDM660_SLAVE_TLMM_NORTH,
62 SDM660_SLAVE_PIMEM_CFG,
63 SDM660_SLAVE_IMEM_CFG,
64 SDM660_SLAVE_MESSAGE_RAM,
66 SDM660_SLAVE_BIMC_CFG,
69 SDM660_SLAVE_QDSS_CFG,
70 SDM660_SLAVE_CNOC_MNOC_CFG,
71 SDM660_SLAVE_SNOC_CFG,
75 SDM660_SLAVE_TLMM_SOUTH,
77 SDM660_SLAVE_A2NOC_CFG,
78 SDM660_SLAVE_A2NOC_SMMU_CFG,
79 SDM660_SLAVE_GPUSS_CFG,
84 SDM660_SLAVE_TLMM_CENTER,
87 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
90 SDM660_SLAVE_SRVC_CNOC,
91 SDM660_SLAVE_GNOC_BIMC,
92 SDM660_SLAVE_GNOC_SNOC,
93 SDM660_SLAVE_CAMERA_CFG,
94 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
95 SDM660_SLAVE_MISC_CFG,
96 SDM660_SLAVE_VENUS_THROTTLE_CFG,
97 SDM660_SLAVE_VENUS_CFG,
98 SDM660_SLAVE_MMSS_CLK_XPU_CFG,
99 SDM660_SLAVE_MMSS_CLK_CFG,
100 SDM660_SLAVE_MNOC_MPU_CFG,
101 SDM660_SLAVE_DISPLAY_CFG,
102 SDM660_SLAVE_CSI_PHY_CFG,
103 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
104 SDM660_SLAVE_SMMU_CFG,
105 SDM660_SLAVE_MNOC_BIMC,
106 SDM660_SLAVE_SRVC_MNOC,
112 SDM660_SLAVE_SNOC_BIMC,
113 SDM660_SLAVE_SNOC_CNOC,
116 SDM660_SLAVE_QDSS_STM,
117 SDM660_SLAVE_SRVC_SNOC,
127 static const char * const mm_intf_clocks[] = {
131 static const char * const a2noc_intf_clocks[] = {
139 static const u16 mas_ipa_links[] = {
140 SDM660_SLAVE_A2NOC_SNOC
143 static struct qcom_icc_node mas_ipa = {
145 .id = SDM660_MASTER_IPA,
149 .qos.ap_owned = true,
150 .qos.qos_mode = NOC_QOS_MODE_FIXED,
154 .num_links = ARRAY_SIZE(mas_ipa_links),
155 .links = mas_ipa_links,
158 static const u16 mas_cnoc_a2noc_links[] = {
159 SDM660_SLAVE_A2NOC_SNOC
162 static struct qcom_icc_node mas_cnoc_a2noc = {
163 .name = "mas_cnoc_a2noc",
164 .id = SDM660_MASTER_CNOC_A2NOC,
168 .qos.ap_owned = true,
169 .qos.qos_mode = NOC_QOS_MODE_INVALID,
170 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links),
171 .links = mas_cnoc_a2noc_links,
174 static const u16 mas_sdcc_1_links[] = {
175 SDM660_SLAVE_A2NOC_SNOC
178 static struct qcom_icc_node mas_sdcc_1 = {
179 .name = "mas_sdcc_1",
180 .id = SDM660_MASTER_SDCC_1,
184 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
185 .links = mas_sdcc_1_links,
188 static const u16 mas_sdcc_2_links[] = {
189 SDM660_SLAVE_A2NOC_SNOC
192 static struct qcom_icc_node mas_sdcc_2 = {
193 .name = "mas_sdcc_2",
194 .id = SDM660_MASTER_SDCC_2,
198 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
199 .links = mas_sdcc_2_links,
202 static const u16 mas_blsp_1_links[] = {
203 SDM660_SLAVE_A2NOC_SNOC
206 static struct qcom_icc_node mas_blsp_1 = {
207 .name = "mas_blsp_1",
208 .id = SDM660_MASTER_BLSP_1,
212 .num_links = ARRAY_SIZE(mas_blsp_1_links),
213 .links = mas_blsp_1_links,
216 static const u16 mas_blsp_2_links[] = {
217 SDM660_SLAVE_A2NOC_SNOC
220 static struct qcom_icc_node mas_blsp_2 = {
221 .name = "mas_blsp_2",
222 .id = SDM660_MASTER_BLSP_2,
226 .num_links = ARRAY_SIZE(mas_blsp_2_links),
227 .links = mas_blsp_2_links,
230 static const u16 mas_ufs_links[] = {
231 SDM660_SLAVE_A2NOC_SNOC
234 static struct qcom_icc_node mas_ufs = {
236 .id = SDM660_MASTER_UFS,
240 .qos.ap_owned = true,
241 .qos.qos_mode = NOC_QOS_MODE_FIXED,
245 .num_links = ARRAY_SIZE(mas_ufs_links),
246 .links = mas_ufs_links,
249 static const u16 mas_usb_hs_links[] = {
250 SDM660_SLAVE_A2NOC_SNOC
253 static struct qcom_icc_node mas_usb_hs = {
254 .name = "mas_usb_hs",
255 .id = SDM660_MASTER_USB_HS,
259 .qos.ap_owned = true,
260 .qos.qos_mode = NOC_QOS_MODE_FIXED,
264 .num_links = ARRAY_SIZE(mas_usb_hs_links),
265 .links = mas_usb_hs_links,
268 static const u16 mas_usb3_links[] = {
269 SDM660_SLAVE_A2NOC_SNOC
272 static struct qcom_icc_node mas_usb3 = {
274 .id = SDM660_MASTER_USB3,
278 .qos.ap_owned = true,
279 .qos.qos_mode = NOC_QOS_MODE_FIXED,
283 .num_links = ARRAY_SIZE(mas_usb3_links),
284 .links = mas_usb3_links,
287 static const u16 mas_crypto_links[] = {
288 SDM660_SLAVE_A2NOC_SNOC
291 static struct qcom_icc_node mas_crypto = {
292 .name = "mas_crypto",
293 .id = SDM660_MASTER_CRYPTO_C0,
297 .qos.ap_owned = true,
298 .qos.qos_mode = NOC_QOS_MODE_FIXED,
302 .num_links = ARRAY_SIZE(mas_crypto_links),
303 .links = mas_crypto_links,
306 static const u16 mas_gnoc_bimc_links[] = {
310 static struct qcom_icc_node mas_gnoc_bimc = {
311 .name = "mas_gnoc_bimc",
312 .id = SDM660_MASTER_GNOC_BIMC,
316 .qos.ap_owned = true,
317 .qos.qos_mode = NOC_QOS_MODE_FIXED,
321 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links),
322 .links = mas_gnoc_bimc_links,
325 static const u16 mas_oxili_links[] = {
326 SDM660_SLAVE_HMSS_L3,
328 SDM660_SLAVE_BIMC_SNOC
331 static struct qcom_icc_node mas_oxili = {
333 .id = SDM660_MASTER_OXILI,
337 .qos.ap_owned = true,
338 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
342 .num_links = ARRAY_SIZE(mas_oxili_links),
343 .links = mas_oxili_links,
346 static const u16 mas_mnoc_bimc_links[] = {
347 SDM660_SLAVE_HMSS_L3,
349 SDM660_SLAVE_BIMC_SNOC
352 static struct qcom_icc_node mas_mnoc_bimc = {
353 .name = "mas_mnoc_bimc",
354 .id = SDM660_MASTER_MNOC_BIMC,
358 .qos.ap_owned = true,
359 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
363 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links),
364 .links = mas_mnoc_bimc_links,
367 static const u16 mas_snoc_bimc_links[] = {
368 SDM660_SLAVE_HMSS_L3,
372 static struct qcom_icc_node mas_snoc_bimc = {
373 .name = "mas_snoc_bimc",
374 .id = SDM660_MASTER_SNOC_BIMC,
378 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
379 .links = mas_snoc_bimc_links,
382 static const u16 mas_pimem_links[] = {
383 SDM660_SLAVE_HMSS_L3,
387 static struct qcom_icc_node mas_pimem = {
389 .id = SDM660_MASTER_PIMEM,
393 .qos.ap_owned = true,
394 .qos.qos_mode = NOC_QOS_MODE_FIXED,
398 .num_links = ARRAY_SIZE(mas_pimem_links),
399 .links = mas_pimem_links,
402 static const u16 mas_snoc_cnoc_links[] = {
403 SDM660_SLAVE_CLK_CTL,
404 SDM660_SLAVE_QDSS_CFG,
406 SDM660_SLAVE_SRVC_CNOC,
407 SDM660_SLAVE_UFS_CFG,
409 SDM660_SLAVE_A2NOC_SMMU_CFG,
410 SDM660_SLAVE_SNOC_CFG,
411 SDM660_SLAVE_TLMM_SOUTH,
413 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
417 SDM660_SLAVE_PMIC_ARB,
419 SDM660_SLAVE_MSS_CFG,
420 SDM660_SLAVE_GPUSS_CFG,
421 SDM660_SLAVE_IMEM_CFG,
423 SDM660_SLAVE_A2NOC_CFG,
424 SDM660_SLAVE_TLMM_NORTH,
427 SDM660_SLAVE_TLMM_CENTER,
428 SDM660_SLAVE_AHB2PHY,
431 SDM660_SLAVE_PIMEM_CFG,
433 SDM660_SLAVE_MESSAGE_RAM,
434 SDM660_SLAVE_BIMC_CFG,
435 SDM660_SLAVE_CNOC_MNOC_CFG
438 static struct qcom_icc_node mas_snoc_cnoc = {
439 .name = "mas_snoc_cnoc",
440 .id = SDM660_MASTER_SNOC_CNOC,
444 .qos.ap_owned = true,
445 .qos.qos_mode = NOC_QOS_MODE_INVALID,
446 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
447 .links = mas_snoc_cnoc_links,
450 static const u16 mas_qdss_dap_links[] = {
451 SDM660_SLAVE_CLK_CTL,
452 SDM660_SLAVE_QDSS_CFG,
454 SDM660_SLAVE_SRVC_CNOC,
455 SDM660_SLAVE_UFS_CFG,
457 SDM660_SLAVE_A2NOC_SMMU_CFG,
458 SDM660_SLAVE_SNOC_CFG,
459 SDM660_SLAVE_TLMM_SOUTH,
461 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
465 SDM660_SLAVE_PMIC_ARB,
467 SDM660_SLAVE_MSS_CFG,
468 SDM660_SLAVE_GPUSS_CFG,
469 SDM660_SLAVE_IMEM_CFG,
471 SDM660_SLAVE_A2NOC_CFG,
472 SDM660_SLAVE_TLMM_NORTH,
475 SDM660_SLAVE_TLMM_CENTER,
476 SDM660_SLAVE_AHB2PHY,
479 SDM660_SLAVE_PIMEM_CFG,
481 SDM660_SLAVE_MESSAGE_RAM,
482 SDM660_SLAVE_CNOC_A2NOC,
483 SDM660_SLAVE_BIMC_CFG,
484 SDM660_SLAVE_CNOC_MNOC_CFG
487 static struct qcom_icc_node mas_qdss_dap = {
488 .name = "mas_qdss_dap",
489 .id = SDM660_MASTER_QDSS_DAP,
493 .qos.ap_owned = true,
494 .qos.qos_mode = NOC_QOS_MODE_INVALID,
495 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
496 .links = mas_qdss_dap_links,
499 static const u16 mas_apss_proc_links[] = {
500 SDM660_SLAVE_GNOC_SNOC,
501 SDM660_SLAVE_GNOC_BIMC
504 static struct qcom_icc_node mas_apss_proc = {
505 .name = "mas_apss_proc",
506 .id = SDM660_MASTER_APPS_PROC,
510 .qos.ap_owned = true,
511 .qos.qos_mode = NOC_QOS_MODE_INVALID,
512 .num_links = ARRAY_SIZE(mas_apss_proc_links),
513 .links = mas_apss_proc_links,
516 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
517 SDM660_SLAVE_VENUS_THROTTLE_CFG,
518 SDM660_SLAVE_VENUS_CFG,
519 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
520 SDM660_SLAVE_SMMU_CFG,
521 SDM660_SLAVE_CAMERA_CFG,
522 SDM660_SLAVE_CSI_PHY_CFG,
523 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
524 SDM660_SLAVE_DISPLAY_CFG,
525 SDM660_SLAVE_MMSS_CLK_CFG,
526 SDM660_SLAVE_MNOC_MPU_CFG,
527 SDM660_SLAVE_MISC_CFG,
528 SDM660_SLAVE_MMSS_CLK_XPU_CFG
531 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
532 .name = "mas_cnoc_mnoc_mmss_cfg",
533 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
537 .qos.ap_owned = true,
538 .qos.qos_mode = NOC_QOS_MODE_INVALID,
539 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
540 .links = mas_cnoc_mnoc_mmss_cfg_links,
543 static const u16 mas_cnoc_mnoc_cfg_links[] = {
544 SDM660_SLAVE_SRVC_MNOC
547 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
548 .name = "mas_cnoc_mnoc_cfg",
549 .id = SDM660_MASTER_CNOC_MNOC_CFG,
553 .qos.ap_owned = true,
554 .qos.qos_mode = NOC_QOS_MODE_INVALID,
555 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
556 .links = mas_cnoc_mnoc_cfg_links,
559 static const u16 mas_cpp_links[] = {
560 SDM660_SLAVE_MNOC_BIMC
563 static struct qcom_icc_node mas_cpp = {
565 .id = SDM660_MASTER_CPP,
569 .qos.ap_owned = true,
570 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
574 .num_links = ARRAY_SIZE(mas_cpp_links),
575 .links = mas_cpp_links,
578 static const u16 mas_jpeg_links[] = {
579 SDM660_SLAVE_MNOC_BIMC
582 static struct qcom_icc_node mas_jpeg = {
584 .id = SDM660_MASTER_JPEG,
588 .qos.ap_owned = true,
589 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
593 .num_links = ARRAY_SIZE(mas_jpeg_links),
594 .links = mas_jpeg_links,
597 static const u16 mas_mdp_p0_links[] = {
598 SDM660_SLAVE_MNOC_BIMC
601 static struct qcom_icc_node mas_mdp_p0 = {
602 .name = "mas_mdp_p0",
603 .id = SDM660_MASTER_MDP_P0,
608 .qos.ap_owned = true,
609 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
613 .num_links = ARRAY_SIZE(mas_mdp_p0_links),
614 .links = mas_mdp_p0_links,
617 static const u16 mas_mdp_p1_links[] = {
618 SDM660_SLAVE_MNOC_BIMC
621 static struct qcom_icc_node mas_mdp_p1 = {
622 .name = "mas_mdp_p1",
623 .id = SDM660_MASTER_MDP_P1,
628 .qos.ap_owned = true,
629 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
633 .num_links = ARRAY_SIZE(mas_mdp_p1_links),
634 .links = mas_mdp_p1_links,
637 static const u16 mas_venus_links[] = {
638 SDM660_SLAVE_MNOC_BIMC
641 static struct qcom_icc_node mas_venus = {
643 .id = SDM660_MASTER_VENUS,
647 .qos.ap_owned = true,
648 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
652 .num_links = ARRAY_SIZE(mas_venus_links),
653 .links = mas_venus_links,
656 static const u16 mas_vfe_links[] = {
657 SDM660_SLAVE_MNOC_BIMC
660 static struct qcom_icc_node mas_vfe = {
662 .id = SDM660_MASTER_VFE,
666 .qos.ap_owned = true,
667 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
671 .num_links = ARRAY_SIZE(mas_vfe_links),
672 .links = mas_vfe_links,
675 static const u16 mas_qdss_etr_links[] = {
678 SDM660_SLAVE_SNOC_CNOC,
679 SDM660_SLAVE_SNOC_BIMC
682 static struct qcom_icc_node mas_qdss_etr = {
683 .name = "mas_qdss_etr",
684 .id = SDM660_MASTER_QDSS_ETR,
688 .qos.ap_owned = true,
689 .qos.qos_mode = NOC_QOS_MODE_FIXED,
693 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
694 .links = mas_qdss_etr_links,
697 static const u16 mas_qdss_bam_links[] = {
700 SDM660_SLAVE_SNOC_CNOC,
701 SDM660_SLAVE_SNOC_BIMC
704 static struct qcom_icc_node mas_qdss_bam = {
705 .name = "mas_qdss_bam",
706 .id = SDM660_MASTER_QDSS_BAM,
710 .qos.ap_owned = true,
711 .qos.qos_mode = NOC_QOS_MODE_FIXED,
715 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
716 .links = mas_qdss_bam_links,
719 static const u16 mas_snoc_cfg_links[] = {
720 SDM660_SLAVE_SRVC_SNOC
723 static struct qcom_icc_node mas_snoc_cfg = {
724 .name = "mas_snoc_cfg",
725 .id = SDM660_MASTER_SNOC_CFG,
729 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
730 .links = mas_snoc_cfg_links,
733 static const u16 mas_bimc_snoc_links[] = {
736 SDM660_SLAVE_QDSS_STM,
740 SDM660_SLAVE_SNOC_CNOC,
745 static struct qcom_icc_node mas_bimc_snoc = {
746 .name = "mas_bimc_snoc",
747 .id = SDM660_MASTER_BIMC_SNOC,
751 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
752 .links = mas_bimc_snoc_links,
755 static const u16 mas_gnoc_snoc_links[] = {
758 SDM660_SLAVE_QDSS_STM,
762 SDM660_SLAVE_SNOC_CNOC,
767 static struct qcom_icc_node mas_gnoc_snoc = {
768 .name = "mas_gnoc_snoc",
769 .id = SDM660_MASTER_GNOC_SNOC,
773 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links),
774 .links = mas_gnoc_snoc_links,
777 static const u16 mas_a2noc_snoc_links[] = {
780 SDM660_SLAVE_QDSS_STM,
783 SDM660_SLAVE_SNOC_BIMC,
785 SDM660_SLAVE_SNOC_CNOC,
790 static struct qcom_icc_node mas_a2noc_snoc = {
791 .name = "mas_a2noc_snoc",
792 .id = SDM660_MASTER_A2NOC_SNOC,
796 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
797 .links = mas_a2noc_snoc_links,
800 static const u16 slv_a2noc_snoc_links[] = {
801 SDM660_MASTER_A2NOC_SNOC
804 static struct qcom_icc_node slv_a2noc_snoc = {
805 .name = "slv_a2noc_snoc",
806 .id = SDM660_SLAVE_A2NOC_SNOC,
810 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
811 .links = slv_a2noc_snoc_links,
814 static struct qcom_icc_node slv_ebi = {
816 .id = SDM660_SLAVE_EBI,
822 static struct qcom_icc_node slv_hmss_l3 = {
823 .name = "slv_hmss_l3",
824 .id = SDM660_SLAVE_HMSS_L3,
830 static const u16 slv_bimc_snoc_links[] = {
831 SDM660_MASTER_BIMC_SNOC
834 static struct qcom_icc_node slv_bimc_snoc = {
835 .name = "slv_bimc_snoc",
836 .id = SDM660_SLAVE_BIMC_SNOC,
840 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
841 .links = slv_bimc_snoc_links,
844 static const u16 slv_cnoc_a2noc_links[] = {
845 SDM660_MASTER_CNOC_A2NOC
848 static struct qcom_icc_node slv_cnoc_a2noc = {
849 .name = "slv_cnoc_a2noc",
850 .id = SDM660_SLAVE_CNOC_A2NOC,
854 .qos.ap_owned = true,
855 .qos.qos_mode = NOC_QOS_MODE_INVALID,
856 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links),
857 .links = slv_cnoc_a2noc_links,
860 static struct qcom_icc_node slv_mpm = {
862 .id = SDM660_SLAVE_MPM,
866 .qos.ap_owned = true,
867 .qos.qos_mode = NOC_QOS_MODE_INVALID,
870 static struct qcom_icc_node slv_pmic_arb = {
871 .name = "slv_pmic_arb",
872 .id = SDM660_SLAVE_PMIC_ARB,
876 .qos.ap_owned = true,
877 .qos.qos_mode = NOC_QOS_MODE_INVALID,
880 static struct qcom_icc_node slv_tlmm_north = {
881 .name = "slv_tlmm_north",
882 .id = SDM660_SLAVE_TLMM_NORTH,
886 .qos.ap_owned = true,
887 .qos.qos_mode = NOC_QOS_MODE_INVALID,
890 static struct qcom_icc_node slv_tcsr = {
892 .id = SDM660_SLAVE_TCSR,
896 .qos.ap_owned = true,
897 .qos.qos_mode = NOC_QOS_MODE_INVALID,
900 static struct qcom_icc_node slv_pimem_cfg = {
901 .name = "slv_pimem_cfg",
902 .id = SDM660_SLAVE_PIMEM_CFG,
906 .qos.ap_owned = true,
907 .qos.qos_mode = NOC_QOS_MODE_INVALID,
910 static struct qcom_icc_node slv_imem_cfg = {
911 .name = "slv_imem_cfg",
912 .id = SDM660_SLAVE_IMEM_CFG,
916 .qos.ap_owned = true,
917 .qos.qos_mode = NOC_QOS_MODE_INVALID,
920 static struct qcom_icc_node slv_message_ram = {
921 .name = "slv_message_ram",
922 .id = SDM660_SLAVE_MESSAGE_RAM,
926 .qos.ap_owned = true,
927 .qos.qos_mode = NOC_QOS_MODE_INVALID,
930 static struct qcom_icc_node slv_glm = {
932 .id = SDM660_SLAVE_GLM,
936 .qos.ap_owned = true,
937 .qos.qos_mode = NOC_QOS_MODE_INVALID,
940 static struct qcom_icc_node slv_bimc_cfg = {
941 .name = "slv_bimc_cfg",
942 .id = SDM660_SLAVE_BIMC_CFG,
946 .qos.ap_owned = true,
947 .qos.qos_mode = NOC_QOS_MODE_INVALID,
950 static struct qcom_icc_node slv_prng = {
952 .id = SDM660_SLAVE_PRNG,
956 .qos.ap_owned = true,
957 .qos.qos_mode = NOC_QOS_MODE_INVALID,
960 static struct qcom_icc_node slv_spdm = {
962 .id = SDM660_SLAVE_SPDM,
966 .qos.ap_owned = true,
967 .qos.qos_mode = NOC_QOS_MODE_INVALID,
970 static struct qcom_icc_node slv_qdss_cfg = {
971 .name = "slv_qdss_cfg",
972 .id = SDM660_SLAVE_QDSS_CFG,
976 .qos.ap_owned = true,
977 .qos.qos_mode = NOC_QOS_MODE_INVALID,
980 static const u16 slv_cnoc_mnoc_cfg_links[] = {
981 SDM660_MASTER_CNOC_MNOC_CFG
984 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
985 .name = "slv_cnoc_mnoc_cfg",
986 .id = SDM660_SLAVE_CNOC_MNOC_CFG,
990 .qos.ap_owned = true,
991 .qos.qos_mode = NOC_QOS_MODE_INVALID,
992 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
993 .links = slv_cnoc_mnoc_cfg_links,
996 static struct qcom_icc_node slv_snoc_cfg = {
997 .name = "slv_snoc_cfg",
998 .id = SDM660_SLAVE_SNOC_CFG,
1002 .qos.ap_owned = true,
1003 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1006 static struct qcom_icc_node slv_qm_cfg = {
1007 .name = "slv_qm_cfg",
1008 .id = SDM660_SLAVE_QM_CFG,
1012 .qos.ap_owned = true,
1013 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1016 static struct qcom_icc_node slv_clk_ctl = {
1017 .name = "slv_clk_ctl",
1018 .id = SDM660_SLAVE_CLK_CTL,
1022 .qos.ap_owned = true,
1023 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1026 static struct qcom_icc_node slv_mss_cfg = {
1027 .name = "slv_mss_cfg",
1028 .id = SDM660_SLAVE_MSS_CFG,
1032 .qos.ap_owned = true,
1033 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1036 static struct qcom_icc_node slv_tlmm_south = {
1037 .name = "slv_tlmm_south",
1038 .id = SDM660_SLAVE_TLMM_SOUTH,
1042 .qos.ap_owned = true,
1043 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1046 static struct qcom_icc_node slv_ufs_cfg = {
1047 .name = "slv_ufs_cfg",
1048 .id = SDM660_SLAVE_UFS_CFG,
1052 .qos.ap_owned = true,
1053 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1056 static struct qcom_icc_node slv_a2noc_cfg = {
1057 .name = "slv_a2noc_cfg",
1058 .id = SDM660_SLAVE_A2NOC_CFG,
1062 .qos.ap_owned = true,
1063 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1066 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1067 .name = "slv_a2noc_smmu_cfg",
1068 .id = SDM660_SLAVE_A2NOC_SMMU_CFG,
1072 .qos.ap_owned = true,
1073 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1076 static struct qcom_icc_node slv_gpuss_cfg = {
1077 .name = "slv_gpuss_cfg",
1078 .id = SDM660_SLAVE_GPUSS_CFG,
1082 .qos.ap_owned = true,
1083 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1086 static struct qcom_icc_node slv_ahb2phy = {
1087 .name = "slv_ahb2phy",
1088 .id = SDM660_SLAVE_AHB2PHY,
1092 .qos.ap_owned = true,
1093 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1096 static struct qcom_icc_node slv_blsp_1 = {
1097 .name = "slv_blsp_1",
1098 .id = SDM660_SLAVE_BLSP_1,
1102 .qos.ap_owned = true,
1103 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1106 static struct qcom_icc_node slv_sdcc_1 = {
1107 .name = "slv_sdcc_1",
1108 .id = SDM660_SLAVE_SDCC_1,
1112 .qos.ap_owned = true,
1113 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1116 static struct qcom_icc_node slv_sdcc_2 = {
1117 .name = "slv_sdcc_2",
1118 .id = SDM660_SLAVE_SDCC_2,
1122 .qos.ap_owned = true,
1123 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1126 static struct qcom_icc_node slv_tlmm_center = {
1127 .name = "slv_tlmm_center",
1128 .id = SDM660_SLAVE_TLMM_CENTER,
1132 .qos.ap_owned = true,
1133 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1136 static struct qcom_icc_node slv_blsp_2 = {
1137 .name = "slv_blsp_2",
1138 .id = SDM660_SLAVE_BLSP_2,
1142 .qos.ap_owned = true,
1143 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1146 static struct qcom_icc_node slv_pdm = {
1148 .id = SDM660_SLAVE_PDM,
1152 .qos.ap_owned = true,
1153 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1156 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1157 SDM660_MASTER_CNOC_MNOC_MMSS_CFG
1160 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1161 .name = "slv_cnoc_mnoc_mmss_cfg",
1162 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
1166 .qos.ap_owned = true,
1167 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1168 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1169 .links = slv_cnoc_mnoc_mmss_cfg_links,
1172 static struct qcom_icc_node slv_usb_hs = {
1173 .name = "slv_usb_hs",
1174 .id = SDM660_SLAVE_USB_HS,
1178 .qos.ap_owned = true,
1179 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1182 static struct qcom_icc_node slv_usb3_0 = {
1183 .name = "slv_usb3_0",
1184 .id = SDM660_SLAVE_USB3_0,
1188 .qos.ap_owned = true,
1189 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1192 static struct qcom_icc_node slv_srvc_cnoc = {
1193 .name = "slv_srvc_cnoc",
1194 .id = SDM660_SLAVE_SRVC_CNOC,
1198 .qos.ap_owned = true,
1199 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1202 static const u16 slv_gnoc_bimc_links[] = {
1203 SDM660_MASTER_GNOC_BIMC
1206 static struct qcom_icc_node slv_gnoc_bimc = {
1207 .name = "slv_gnoc_bimc",
1208 .id = SDM660_SLAVE_GNOC_BIMC,
1212 .qos.ap_owned = true,
1213 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1214 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links),
1215 .links = slv_gnoc_bimc_links,
1218 static const u16 slv_gnoc_snoc_links[] = {
1219 SDM660_MASTER_GNOC_SNOC
1222 static struct qcom_icc_node slv_gnoc_snoc = {
1223 .name = "slv_gnoc_snoc",
1224 .id = SDM660_SLAVE_GNOC_SNOC,
1228 .qos.ap_owned = true,
1229 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1230 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links),
1231 .links = slv_gnoc_snoc_links,
1234 static struct qcom_icc_node slv_camera_cfg = {
1235 .name = "slv_camera_cfg",
1236 .id = SDM660_SLAVE_CAMERA_CFG,
1240 .qos.ap_owned = true,
1241 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1244 static struct qcom_icc_node slv_camera_throttle_cfg = {
1245 .name = "slv_camera_throttle_cfg",
1246 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG,
1250 .qos.ap_owned = true,
1251 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1254 static struct qcom_icc_node slv_misc_cfg = {
1255 .name = "slv_misc_cfg",
1256 .id = SDM660_SLAVE_MISC_CFG,
1260 .qos.ap_owned = true,
1261 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1264 static struct qcom_icc_node slv_venus_throttle_cfg = {
1265 .name = "slv_venus_throttle_cfg",
1266 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG,
1270 .qos.ap_owned = true,
1271 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1274 static struct qcom_icc_node slv_venus_cfg = {
1275 .name = "slv_venus_cfg",
1276 .id = SDM660_SLAVE_VENUS_CFG,
1280 .qos.ap_owned = true,
1281 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1284 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
1285 .name = "slv_mmss_clk_xpu_cfg",
1286 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG,
1290 .qos.ap_owned = true,
1291 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1294 static struct qcom_icc_node slv_mmss_clk_cfg = {
1295 .name = "slv_mmss_clk_cfg",
1296 .id = SDM660_SLAVE_MMSS_CLK_CFG,
1300 .qos.ap_owned = true,
1301 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1304 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1305 .name = "slv_mnoc_mpu_cfg",
1306 .id = SDM660_SLAVE_MNOC_MPU_CFG,
1310 .qos.ap_owned = true,
1311 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1314 static struct qcom_icc_node slv_display_cfg = {
1315 .name = "slv_display_cfg",
1316 .id = SDM660_SLAVE_DISPLAY_CFG,
1320 .qos.ap_owned = true,
1321 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1324 static struct qcom_icc_node slv_csi_phy_cfg = {
1325 .name = "slv_csi_phy_cfg",
1326 .id = SDM660_SLAVE_CSI_PHY_CFG,
1330 .qos.ap_owned = true,
1331 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1334 static struct qcom_icc_node slv_display_throttle_cfg = {
1335 .name = "slv_display_throttle_cfg",
1336 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
1340 .qos.ap_owned = true,
1341 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1344 static struct qcom_icc_node slv_smmu_cfg = {
1345 .name = "slv_smmu_cfg",
1346 .id = SDM660_SLAVE_SMMU_CFG,
1350 .qos.ap_owned = true,
1351 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1354 static const u16 slv_mnoc_bimc_links[] = {
1355 SDM660_MASTER_MNOC_BIMC
1358 static struct qcom_icc_node slv_mnoc_bimc = {
1359 .name = "slv_mnoc_bimc",
1360 .id = SDM660_SLAVE_MNOC_BIMC,
1364 .qos.ap_owned = true,
1365 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1366 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1367 .links = slv_mnoc_bimc_links,
1370 static struct qcom_icc_node slv_srvc_mnoc = {
1371 .name = "slv_srvc_mnoc",
1372 .id = SDM660_SLAVE_SRVC_MNOC,
1376 .qos.ap_owned = true,
1377 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1380 static struct qcom_icc_node slv_hmss = {
1382 .id = SDM660_SLAVE_HMSS,
1386 .qos.ap_owned = true,
1387 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1390 static struct qcom_icc_node slv_lpass = {
1391 .name = "slv_lpass",
1392 .id = SDM660_SLAVE_LPASS,
1396 .qos.ap_owned = true,
1397 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1400 static struct qcom_icc_node slv_wlan = {
1402 .id = SDM660_SLAVE_WLAN,
1408 static struct qcom_icc_node slv_cdsp = {
1410 .id = SDM660_SLAVE_CDSP,
1414 .qos.ap_owned = true,
1415 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1418 static struct qcom_icc_node slv_ipa = {
1420 .id = SDM660_SLAVE_IPA,
1424 .qos.ap_owned = true,
1425 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1428 static const u16 slv_snoc_bimc_links[] = {
1429 SDM660_MASTER_SNOC_BIMC
1432 static struct qcom_icc_node slv_snoc_bimc = {
1433 .name = "slv_snoc_bimc",
1434 .id = SDM660_SLAVE_SNOC_BIMC,
1438 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1439 .links = slv_snoc_bimc_links,
1442 static const u16 slv_snoc_cnoc_links[] = {
1443 SDM660_MASTER_SNOC_CNOC
1446 static struct qcom_icc_node slv_snoc_cnoc = {
1447 .name = "slv_snoc_cnoc",
1448 .id = SDM660_SLAVE_SNOC_CNOC,
1452 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1453 .links = slv_snoc_cnoc_links,
1456 static struct qcom_icc_node slv_imem = {
1458 .id = SDM660_SLAVE_IMEM,
1464 static struct qcom_icc_node slv_pimem = {
1465 .name = "slv_pimem",
1466 .id = SDM660_SLAVE_PIMEM,
1472 static struct qcom_icc_node slv_qdss_stm = {
1473 .name = "slv_qdss_stm",
1474 .id = SDM660_SLAVE_QDSS_STM,
1480 static struct qcom_icc_node slv_srvc_snoc = {
1481 .name = "slv_srvc_snoc",
1482 .id = SDM660_SLAVE_SRVC_SNOC,
1488 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = {
1489 [MASTER_IPA] = &mas_ipa,
1490 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
1491 [MASTER_SDCC_1] = &mas_sdcc_1,
1492 [MASTER_SDCC_2] = &mas_sdcc_2,
1493 [MASTER_BLSP_1] = &mas_blsp_1,
1494 [MASTER_BLSP_2] = &mas_blsp_2,
1495 [MASTER_UFS] = &mas_ufs,
1496 [MASTER_USB_HS] = &mas_usb_hs,
1497 [MASTER_USB3] = &mas_usb3,
1498 [MASTER_CRYPTO_C0] = &mas_crypto,
1499 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
1502 static const struct regmap_config sdm660_a2noc_regmap_config = {
1506 .max_register = 0x20000,
1510 static const struct qcom_icc_desc sdm660_a2noc = {
1511 .type = QCOM_ICC_NOC,
1512 .nodes = sdm660_a2noc_nodes,
1513 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1514 .bus_clk_desc = &aggre2_clk,
1515 .intf_clocks = a2noc_intf_clocks,
1516 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1517 .regmap_cfg = &sdm660_a2noc_regmap_config,
1520 static struct qcom_icc_node * const sdm660_bimc_nodes[] = {
1521 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
1522 [MASTER_OXILI] = &mas_oxili,
1523 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1524 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1525 [MASTER_PIMEM] = &mas_pimem,
1526 [SLAVE_EBI] = &slv_ebi,
1527 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1528 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1531 static const struct regmap_config sdm660_bimc_regmap_config = {
1535 .max_register = 0x80000,
1539 static const struct qcom_icc_desc sdm660_bimc = {
1540 .type = QCOM_ICC_BIMC,
1541 .nodes = sdm660_bimc_nodes,
1542 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
1543 .bus_clk_desc = &bimc_clk,
1544 .regmap_cfg = &sdm660_bimc_regmap_config,
1548 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = {
1549 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1550 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1551 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
1552 [SLAVE_MPM] = &slv_mpm,
1553 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1554 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1555 [SLAVE_TCSR] = &slv_tcsr,
1556 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1557 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1558 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1559 [SLAVE_GLM] = &slv_glm,
1560 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1561 [SLAVE_PRNG] = &slv_prng,
1562 [SLAVE_SPDM] = &slv_spdm,
1563 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1564 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1565 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1566 [SLAVE_QM_CFG] = &slv_qm_cfg,
1567 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1568 [SLAVE_MSS_CFG] = &slv_mss_cfg,
1569 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1570 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1571 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1572 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1573 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
1574 [SLAVE_AHB2PHY] = &slv_ahb2phy,
1575 [SLAVE_BLSP_1] = &slv_blsp_1,
1576 [SLAVE_SDCC_1] = &slv_sdcc_1,
1577 [SLAVE_SDCC_2] = &slv_sdcc_2,
1578 [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
1579 [SLAVE_BLSP_2] = &slv_blsp_2,
1580 [SLAVE_PDM] = &slv_pdm,
1581 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
1582 [SLAVE_USB_HS] = &slv_usb_hs,
1583 [SLAVE_USB3_0] = &slv_usb3_0,
1584 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
1587 static const struct regmap_config sdm660_cnoc_regmap_config = {
1591 .max_register = 0x10000,
1595 static const struct qcom_icc_desc sdm660_cnoc = {
1596 .type = QCOM_ICC_NOC,
1597 .nodes = sdm660_cnoc_nodes,
1598 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
1599 .bus_clk_desc = &bus_2_clk,
1600 .regmap_cfg = &sdm660_cnoc_regmap_config,
1603 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = {
1604 [MASTER_APSS_PROC] = &mas_apss_proc,
1605 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
1606 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
1609 static const struct regmap_config sdm660_gnoc_regmap_config = {
1613 .max_register = 0xe000,
1617 static const struct qcom_icc_desc sdm660_gnoc = {
1618 .type = QCOM_ICC_NOC,
1619 .nodes = sdm660_gnoc_nodes,
1620 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1621 .regmap_cfg = &sdm660_gnoc_regmap_config,
1624 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
1625 [MASTER_CPP] = &mas_cpp,
1626 [MASTER_JPEG] = &mas_jpeg,
1627 [MASTER_MDP_P0] = &mas_mdp_p0,
1628 [MASTER_MDP_P1] = &mas_mdp_p1,
1629 [MASTER_VENUS] = &mas_venus,
1630 [MASTER_VFE] = &mas_vfe,
1631 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1632 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1633 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1634 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1635 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1636 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1637 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1638 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
1639 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
1640 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1641 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1642 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
1643 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1644 [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
1645 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
1646 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1649 static const struct regmap_config sdm660_mnoc_regmap_config = {
1653 .max_register = 0x10000,
1657 static const struct qcom_icc_desc sdm660_mnoc = {
1658 .type = QCOM_ICC_NOC,
1659 .nodes = sdm660_mnoc_nodes,
1660 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1661 .bus_clk_desc = &mmaxi_0_clk,
1662 .intf_clocks = mm_intf_clocks,
1663 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
1664 .regmap_cfg = &sdm660_mnoc_regmap_config,
1668 static struct qcom_icc_node * const sdm660_snoc_nodes[] = {
1669 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1670 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1671 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1672 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1673 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
1674 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
1675 [SLAVE_HMSS] = &slv_hmss,
1676 [SLAVE_LPASS] = &slv_lpass,
1677 [SLAVE_WLAN] = &slv_wlan,
1678 [SLAVE_CDSP] = &slv_cdsp,
1679 [SLAVE_IPA] = &slv_ipa,
1680 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1681 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1682 [SLAVE_IMEM] = &slv_imem,
1683 [SLAVE_PIMEM] = &slv_pimem,
1684 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1685 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1688 static const struct regmap_config sdm660_snoc_regmap_config = {
1692 .max_register = 0x20000,
1696 static const struct qcom_icc_desc sdm660_snoc = {
1697 .type = QCOM_ICC_NOC,
1698 .nodes = sdm660_snoc_nodes,
1699 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
1700 .bus_clk_desc = &bus_1_clk,
1701 .regmap_cfg = &sdm660_snoc_regmap_config,
1704 static const struct of_device_id sdm660_noc_of_match[] = {
1705 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
1706 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
1707 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
1708 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
1709 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
1710 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
1713 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
1715 static struct platform_driver sdm660_noc_driver = {
1716 .probe = qnoc_probe,
1717 .remove = qnoc_remove,
1719 .name = "qnoc-sdm660",
1720 .of_match_table = sdm660_noc_of_match,
1723 module_platform_driver(sdm660_noc_driver);
1724 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
1725 MODULE_LICENSE("GPL v2");