1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sc7280.h>
14 #include "bcm-voter.h"
18 static struct qcom_icc_node qhm_qspi = {
20 .id = SC7280_MASTER_QSPI_0,
24 .links = { SC7280_SLAVE_A1NOC_SNOC },
27 static struct qcom_icc_node qhm_qup0 = {
29 .id = SC7280_MASTER_QUP_0,
33 .links = { SC7280_SLAVE_A1NOC_SNOC },
36 static struct qcom_icc_node qhm_qup1 = {
38 .id = SC7280_MASTER_QUP_1,
42 .links = { SC7280_SLAVE_A1NOC_SNOC },
45 static struct qcom_icc_node qnm_a1noc_cfg = {
46 .name = "qnm_a1noc_cfg",
47 .id = SC7280_MASTER_A1NOC_CFG,
51 .links = { SC7280_SLAVE_SERVICE_A1NOC },
54 static struct qcom_icc_node xm_sdc1 = {
56 .id = SC7280_MASTER_SDCC_1,
60 .links = { SC7280_SLAVE_A1NOC_SNOC },
63 static struct qcom_icc_node xm_sdc2 = {
65 .id = SC7280_MASTER_SDCC_2,
69 .links = { SC7280_SLAVE_A1NOC_SNOC },
72 static struct qcom_icc_node xm_sdc4 = {
74 .id = SC7280_MASTER_SDCC_4,
78 .links = { SC7280_SLAVE_A1NOC_SNOC },
81 static struct qcom_icc_node xm_ufs_mem = {
83 .id = SC7280_MASTER_UFS_MEM,
87 .links = { SC7280_SLAVE_A1NOC_SNOC },
90 static struct qcom_icc_node xm_usb2 = {
92 .id = SC7280_MASTER_USB2,
96 .links = { SC7280_SLAVE_A1NOC_SNOC },
99 static struct qcom_icc_node xm_usb3_0 = {
101 .id = SC7280_MASTER_USB3_0,
105 .links = { SC7280_SLAVE_A1NOC_SNOC },
108 static struct qcom_icc_node qhm_qdss_bam = {
109 .name = "qhm_qdss_bam",
110 .id = SC7280_MASTER_QDSS_BAM,
114 .links = { SC7280_SLAVE_A2NOC_SNOC },
117 static struct qcom_icc_node qnm_a2noc_cfg = {
118 .name = "qnm_a2noc_cfg",
119 .id = SC7280_MASTER_A2NOC_CFG,
123 .links = { SC7280_SLAVE_SERVICE_A2NOC },
126 static struct qcom_icc_node qnm_cnoc_datapath = {
127 .name = "qnm_cnoc_datapath",
128 .id = SC7280_MASTER_CNOC_A2NOC,
132 .links = { SC7280_SLAVE_A2NOC_SNOC },
135 static struct qcom_icc_node qxm_crypto = {
136 .name = "qxm_crypto",
137 .id = SC7280_MASTER_CRYPTO,
141 .links = { SC7280_SLAVE_A2NOC_SNOC },
144 static struct qcom_icc_node qxm_ipa = {
146 .id = SC7280_MASTER_IPA,
150 .links = { SC7280_SLAVE_A2NOC_SNOC },
153 static struct qcom_icc_node xm_pcie3_0 = {
154 .name = "xm_pcie3_0",
155 .id = SC7280_MASTER_PCIE_0,
159 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
162 static struct qcom_icc_node xm_pcie3_1 = {
163 .name = "xm_pcie3_1",
164 .id = SC7280_MASTER_PCIE_1,
167 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
170 static struct qcom_icc_node xm_qdss_etr = {
171 .name = "xm_qdss_etr",
172 .id = SC7280_MASTER_QDSS_ETR,
176 .links = { SC7280_SLAVE_A2NOC_SNOC },
179 static struct qcom_icc_node qup0_core_master = {
180 .name = "qup0_core_master",
181 .id = SC7280_MASTER_QUP_CORE_0,
185 .links = { SC7280_SLAVE_QUP_CORE_0 },
188 static struct qcom_icc_node qup1_core_master = {
189 .name = "qup1_core_master",
190 .id = SC7280_MASTER_QUP_CORE_1,
194 .links = { SC7280_SLAVE_QUP_CORE_1 },
197 static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
198 .name = "qnm_cnoc3_cnoc2",
199 .id = SC7280_MASTER_CNOC3_CNOC2,
203 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
204 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
205 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
206 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
207 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
208 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
209 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
210 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
211 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
212 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
213 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
214 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
215 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
216 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
217 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
218 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
219 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
220 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
221 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
222 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
223 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
224 SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
227 static struct qcom_icc_node xm_qdss_dap = {
228 .name = "xm_qdss_dap",
229 .id = SC7280_MASTER_QDSS_DAP,
233 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
234 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
235 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
236 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
237 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
238 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
239 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
240 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
241 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
242 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
243 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
244 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
245 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
246 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
247 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
248 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
249 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
250 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
251 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
252 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
253 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
254 SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
255 SC7280_SLAVE_SNOC_CFG },
258 static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
259 .name = "qnm_cnoc2_cnoc3",
260 .id = SC7280_MASTER_CNOC2_CNOC3,
264 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
265 SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
266 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
267 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
271 static struct qcom_icc_node qnm_gemnoc_cnoc = {
272 .name = "qnm_gemnoc_cnoc",
273 .id = SC7280_MASTER_GEM_NOC_CNOC,
277 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
278 SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
279 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
280 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
284 static struct qcom_icc_node qnm_gemnoc_pcie = {
285 .name = "qnm_gemnoc_pcie",
286 .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
290 .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
293 static struct qcom_icc_node qnm_cnoc_dc_noc = {
294 .name = "qnm_cnoc_dc_noc",
295 .id = SC7280_MASTER_CNOC_DC_NOC,
299 .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
302 static struct qcom_icc_node alm_gpu_tcu = {
303 .name = "alm_gpu_tcu",
304 .id = SC7280_MASTER_GPU_TCU,
308 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
311 static struct qcom_icc_node alm_sys_tcu = {
312 .name = "alm_sys_tcu",
313 .id = SC7280_MASTER_SYS_TCU,
317 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
320 static struct qcom_icc_node chm_apps = {
322 .id = SC7280_MASTER_APPSS_PROC,
326 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
327 SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
330 static struct qcom_icc_node qnm_cmpnoc = {
331 .name = "qnm_cmpnoc",
332 .id = SC7280_MASTER_COMPUTE_NOC,
336 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
339 static struct qcom_icc_node qnm_gemnoc_cfg = {
340 .name = "qnm_gemnoc_cfg",
341 .id = SC7280_MASTER_GEM_NOC_CFG,
345 .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
346 SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
347 SC7280_SLAVE_SERVICE_GEM_NOC },
350 static struct qcom_icc_node qnm_gpu = {
352 .id = SC7280_MASTER_GFX3D,
356 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
359 static struct qcom_icc_node qnm_mnoc_hf = {
360 .name = "qnm_mnoc_hf",
361 .id = SC7280_MASTER_MNOC_HF_MEM_NOC,
365 .links = { SC7280_SLAVE_LLCC },
368 static struct qcom_icc_node qnm_mnoc_sf = {
369 .name = "qnm_mnoc_sf",
370 .id = SC7280_MASTER_MNOC_SF_MEM_NOC,
374 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
377 static struct qcom_icc_node qnm_pcie = {
379 .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
383 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
386 static struct qcom_icc_node qnm_snoc_gc = {
387 .name = "qnm_snoc_gc",
388 .id = SC7280_MASTER_SNOC_GC_MEM_NOC,
392 .links = { SC7280_SLAVE_LLCC },
395 static struct qcom_icc_node qnm_snoc_sf = {
396 .name = "qnm_snoc_sf",
397 .id = SC7280_MASTER_SNOC_SF_MEM_NOC,
401 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
402 SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
405 static struct qcom_icc_node qhm_config_noc = {
406 .name = "qhm_config_noc",
407 .id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
411 .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
412 SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
413 SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
416 static struct qcom_icc_node llcc_mc = {
418 .id = SC7280_MASTER_LLCC,
422 .links = { SC7280_SLAVE_EBI1 },
425 static struct qcom_icc_node qnm_mnoc_cfg = {
426 .name = "qnm_mnoc_cfg",
427 .id = SC7280_MASTER_CNOC_MNOC_CFG,
431 .links = { SC7280_SLAVE_SERVICE_MNOC },
434 static struct qcom_icc_node qnm_video0 = {
435 .name = "qnm_video0",
436 .id = SC7280_MASTER_VIDEO_P0,
440 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
443 static struct qcom_icc_node qnm_video_cpu = {
444 .name = "qnm_video_cpu",
445 .id = SC7280_MASTER_VIDEO_PROC,
449 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
452 static struct qcom_icc_node qxm_camnoc_hf = {
453 .name = "qxm_camnoc_hf",
454 .id = SC7280_MASTER_CAMNOC_HF,
458 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
461 static struct qcom_icc_node qxm_camnoc_icp = {
462 .name = "qxm_camnoc_icp",
463 .id = SC7280_MASTER_CAMNOC_ICP,
467 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
470 static struct qcom_icc_node qxm_camnoc_sf = {
471 .name = "qxm_camnoc_sf",
472 .id = SC7280_MASTER_CAMNOC_SF,
476 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
479 static struct qcom_icc_node qxm_mdp0 = {
481 .id = SC7280_MASTER_MDP0,
485 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
488 static struct qcom_icc_node qhm_nsp_noc_config = {
489 .name = "qhm_nsp_noc_config",
490 .id = SC7280_MASTER_CDSP_NOC_CFG,
494 .links = { SC7280_SLAVE_SERVICE_NSP_NOC },
497 static struct qcom_icc_node qxm_nsp = {
499 .id = SC7280_MASTER_CDSP_PROC,
503 .links = { SC7280_SLAVE_CDSP_MEM_NOC },
506 static struct qcom_icc_node qnm_aggre1_noc = {
507 .name = "qnm_aggre1_noc",
508 .id = SC7280_MASTER_A1NOC_SNOC,
512 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
515 static struct qcom_icc_node qnm_aggre2_noc = {
516 .name = "qnm_aggre2_noc",
517 .id = SC7280_MASTER_A2NOC_SNOC,
521 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
524 static struct qcom_icc_node qnm_snoc_cfg = {
525 .name = "qnm_snoc_cfg",
526 .id = SC7280_MASTER_SNOC_CFG,
530 .links = { SC7280_SLAVE_SERVICE_SNOC },
533 static struct qcom_icc_node qxm_pimem = {
535 .id = SC7280_MASTER_PIMEM,
539 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
542 static struct qcom_icc_node xm_gic = {
544 .id = SC7280_MASTER_GIC,
548 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
551 static struct qcom_icc_node qns_a1noc_snoc = {
552 .name = "qns_a1noc_snoc",
553 .id = SC7280_SLAVE_A1NOC_SNOC,
557 .links = { SC7280_MASTER_A1NOC_SNOC },
560 static struct qcom_icc_node srvc_aggre1_noc = {
561 .name = "srvc_aggre1_noc",
562 .id = SC7280_SLAVE_SERVICE_A1NOC,
568 static struct qcom_icc_node qns_a2noc_snoc = {
569 .name = "qns_a2noc_snoc",
570 .id = SC7280_SLAVE_A2NOC_SNOC,
574 .links = { SC7280_MASTER_A2NOC_SNOC },
577 static struct qcom_icc_node qns_pcie_mem_noc = {
578 .name = "qns_pcie_mem_noc",
579 .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
583 .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
586 static struct qcom_icc_node srvc_aggre2_noc = {
587 .name = "srvc_aggre2_noc",
588 .id = SC7280_SLAVE_SERVICE_A2NOC,
594 static struct qcom_icc_node qup0_core_slave = {
595 .name = "qup0_core_slave",
596 .id = SC7280_SLAVE_QUP_CORE_0,
602 static struct qcom_icc_node qup1_core_slave = {
603 .name = "qup1_core_slave",
604 .id = SC7280_SLAVE_QUP_CORE_1,
610 static struct qcom_icc_node qhs_ahb2phy0 = {
611 .name = "qhs_ahb2phy0",
612 .id = SC7280_SLAVE_AHB2PHY_SOUTH,
618 static struct qcom_icc_node qhs_ahb2phy1 = {
619 .name = "qhs_ahb2phy1",
620 .id = SC7280_SLAVE_AHB2PHY_NORTH,
626 static struct qcom_icc_node qhs_camera_cfg = {
627 .name = "qhs_camera_cfg",
628 .id = SC7280_SLAVE_CAMERA_CFG,
634 static struct qcom_icc_node qhs_clk_ctl = {
635 .name = "qhs_clk_ctl",
636 .id = SC7280_SLAVE_CLK_CTL,
642 static struct qcom_icc_node qhs_compute_cfg = {
643 .name = "qhs_compute_cfg",
644 .id = SC7280_SLAVE_CDSP_CFG,
648 .links = { SC7280_MASTER_CDSP_NOC_CFG },
651 static struct qcom_icc_node qhs_cpr_cx = {
652 .name = "qhs_cpr_cx",
653 .id = SC7280_SLAVE_RBCPR_CX_CFG,
659 static struct qcom_icc_node qhs_cpr_mx = {
660 .name = "qhs_cpr_mx",
661 .id = SC7280_SLAVE_RBCPR_MX_CFG,
667 static struct qcom_icc_node qhs_crypto0_cfg = {
668 .name = "qhs_crypto0_cfg",
669 .id = SC7280_SLAVE_CRYPTO_0_CFG,
675 static struct qcom_icc_node qhs_cx_rdpm = {
676 .name = "qhs_cx_rdpm",
677 .id = SC7280_SLAVE_CX_RDPM,
683 static struct qcom_icc_node qhs_dcc_cfg = {
684 .name = "qhs_dcc_cfg",
685 .id = SC7280_SLAVE_DCC_CFG,
691 static struct qcom_icc_node qhs_display_cfg = {
692 .name = "qhs_display_cfg",
693 .id = SC7280_SLAVE_DISPLAY_CFG,
699 static struct qcom_icc_node qhs_gpuss_cfg = {
700 .name = "qhs_gpuss_cfg",
701 .id = SC7280_SLAVE_GFX3D_CFG,
707 static struct qcom_icc_node qhs_hwkm = {
709 .id = SC7280_SLAVE_HWKM,
715 static struct qcom_icc_node qhs_imem_cfg = {
716 .name = "qhs_imem_cfg",
717 .id = SC7280_SLAVE_IMEM_CFG,
723 static struct qcom_icc_node qhs_ipa = {
725 .id = SC7280_SLAVE_IPA_CFG,
731 static struct qcom_icc_node qhs_ipc_router = {
732 .name = "qhs_ipc_router",
733 .id = SC7280_SLAVE_IPC_ROUTER_CFG,
739 static struct qcom_icc_node qhs_lpass_cfg = {
740 .name = "qhs_lpass_cfg",
741 .id = SC7280_SLAVE_LPASS,
745 .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
748 static struct qcom_icc_node qhs_mss_cfg = {
749 .name = "qhs_mss_cfg",
750 .id = SC7280_SLAVE_CNOC_MSS,
756 static struct qcom_icc_node qhs_mx_rdpm = {
757 .name = "qhs_mx_rdpm",
758 .id = SC7280_SLAVE_MX_RDPM,
764 static struct qcom_icc_node qhs_pcie0_cfg = {
765 .name = "qhs_pcie0_cfg",
766 .id = SC7280_SLAVE_PCIE_0_CFG,
772 static struct qcom_icc_node qhs_pcie1_cfg = {
773 .name = "qhs_pcie1_cfg",
774 .id = SC7280_SLAVE_PCIE_1_CFG,
780 static struct qcom_icc_node qhs_pdm = {
782 .id = SC7280_SLAVE_PDM,
788 static struct qcom_icc_node qhs_pimem_cfg = {
789 .name = "qhs_pimem_cfg",
790 .id = SC7280_SLAVE_PIMEM_CFG,
796 static struct qcom_icc_node qhs_pka_wrapper_cfg = {
797 .name = "qhs_pka_wrapper_cfg",
798 .id = SC7280_SLAVE_PKA_WRAPPER_CFG,
804 static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
805 .name = "qhs_pmu_wrapper_cfg",
806 .id = SC7280_SLAVE_PMU_WRAPPER_CFG,
812 static struct qcom_icc_node qhs_qdss_cfg = {
813 .name = "qhs_qdss_cfg",
814 .id = SC7280_SLAVE_QDSS_CFG,
820 static struct qcom_icc_node qhs_qspi = {
822 .id = SC7280_SLAVE_QSPI_0,
828 static struct qcom_icc_node qhs_qup0 = {
830 .id = SC7280_SLAVE_QUP_0,
836 static struct qcom_icc_node qhs_qup1 = {
838 .id = SC7280_SLAVE_QUP_1,
844 static struct qcom_icc_node qhs_sdc1 = {
846 .id = SC7280_SLAVE_SDCC_1,
852 static struct qcom_icc_node qhs_sdc2 = {
854 .id = SC7280_SLAVE_SDCC_2,
860 static struct qcom_icc_node qhs_sdc4 = {
862 .id = SC7280_SLAVE_SDCC_4,
868 static struct qcom_icc_node qhs_security = {
869 .name = "qhs_security",
870 .id = SC7280_SLAVE_SECURITY,
876 static struct qcom_icc_node qhs_tcsr = {
878 .id = SC7280_SLAVE_TCSR,
884 static struct qcom_icc_node qhs_tlmm = {
886 .id = SC7280_SLAVE_TLMM,
892 static struct qcom_icc_node qhs_ufs_mem_cfg = {
893 .name = "qhs_ufs_mem_cfg",
894 .id = SC7280_SLAVE_UFS_MEM_CFG,
900 static struct qcom_icc_node qhs_usb2 = {
902 .id = SC7280_SLAVE_USB2,
908 static struct qcom_icc_node qhs_usb3_0 = {
909 .name = "qhs_usb3_0",
910 .id = SC7280_SLAVE_USB3_0,
916 static struct qcom_icc_node qhs_venus_cfg = {
917 .name = "qhs_venus_cfg",
918 .id = SC7280_SLAVE_VENUS_CFG,
924 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
925 .name = "qhs_vsense_ctrl_cfg",
926 .id = SC7280_SLAVE_VSENSE_CTRL_CFG,
932 static struct qcom_icc_node qns_a1_noc_cfg = {
933 .name = "qns_a1_noc_cfg",
934 .id = SC7280_SLAVE_A1NOC_CFG,
938 .links = { SC7280_MASTER_A1NOC_CFG },
941 static struct qcom_icc_node qns_a2_noc_cfg = {
942 .name = "qns_a2_noc_cfg",
943 .id = SC7280_SLAVE_A2NOC_CFG,
947 .links = { SC7280_MASTER_A2NOC_CFG },
950 static struct qcom_icc_node qns_cnoc2_cnoc3 = {
951 .name = "qns_cnoc2_cnoc3",
952 .id = SC7280_SLAVE_CNOC2_CNOC3,
956 .links = { SC7280_MASTER_CNOC2_CNOC3 },
959 static struct qcom_icc_node qns_mnoc_cfg = {
960 .name = "qns_mnoc_cfg",
961 .id = SC7280_SLAVE_CNOC_MNOC_CFG,
965 .links = { SC7280_MASTER_CNOC_MNOC_CFG },
968 static struct qcom_icc_node qns_snoc_cfg = {
969 .name = "qns_snoc_cfg",
970 .id = SC7280_SLAVE_SNOC_CFG,
974 .links = { SC7280_MASTER_SNOC_CFG },
977 static struct qcom_icc_node qhs_aoss = {
979 .id = SC7280_SLAVE_AOSS,
985 static struct qcom_icc_node qhs_apss = {
987 .id = SC7280_SLAVE_APPSS,
993 static struct qcom_icc_node qns_cnoc3_cnoc2 = {
994 .name = "qns_cnoc3_cnoc2",
995 .id = SC7280_SLAVE_CNOC3_CNOC2,
999 .links = { SC7280_MASTER_CNOC3_CNOC2 },
1002 static struct qcom_icc_node qns_cnoc_a2noc = {
1003 .name = "qns_cnoc_a2noc",
1004 .id = SC7280_SLAVE_CNOC_A2NOC,
1008 .links = { SC7280_MASTER_CNOC_A2NOC },
1011 static struct qcom_icc_node qns_ddrss_cfg = {
1012 .name = "qns_ddrss_cfg",
1013 .id = SC7280_SLAVE_DDRSS_CFG,
1017 .links = { SC7280_MASTER_CNOC_DC_NOC },
1020 static struct qcom_icc_node qxs_boot_imem = {
1021 .name = "qxs_boot_imem",
1022 .id = SC7280_SLAVE_BOOT_IMEM,
1028 static struct qcom_icc_node qxs_imem = {
1030 .id = SC7280_SLAVE_IMEM,
1036 static struct qcom_icc_node qxs_pimem = {
1037 .name = "qxs_pimem",
1038 .id = SC7280_SLAVE_PIMEM,
1044 static struct qcom_icc_node xs_pcie_0 = {
1045 .name = "xs_pcie_0",
1046 .id = SC7280_SLAVE_PCIE_0,
1052 static struct qcom_icc_node xs_pcie_1 = {
1053 .name = "xs_pcie_1",
1054 .id = SC7280_SLAVE_PCIE_1,
1060 static struct qcom_icc_node xs_qdss_stm = {
1061 .name = "xs_qdss_stm",
1062 .id = SC7280_SLAVE_QDSS_STM,
1068 static struct qcom_icc_node xs_sys_tcu_cfg = {
1069 .name = "xs_sys_tcu_cfg",
1070 .id = SC7280_SLAVE_TCU,
1076 static struct qcom_icc_node qhs_llcc = {
1078 .id = SC7280_SLAVE_LLCC_CFG,
1084 static struct qcom_icc_node qns_gemnoc = {
1085 .name = "qns_gemnoc",
1086 .id = SC7280_SLAVE_GEM_NOC_CFG,
1090 .links = { SC7280_MASTER_GEM_NOC_CFG },
1093 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1094 .name = "qhs_mdsp_ms_mpu_cfg",
1095 .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
1101 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1102 .name = "qhs_modem_ms_mpu_cfg",
1103 .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
1109 static struct qcom_icc_node qns_gem_noc_cnoc = {
1110 .name = "qns_gem_noc_cnoc",
1111 .id = SC7280_SLAVE_GEM_NOC_CNOC,
1115 .links = { SC7280_MASTER_GEM_NOC_CNOC },
1118 static struct qcom_icc_node qns_llcc = {
1120 .id = SC7280_SLAVE_LLCC,
1124 .links = { SC7280_MASTER_LLCC },
1127 static struct qcom_icc_node qns_pcie = {
1129 .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
1133 .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
1136 static struct qcom_icc_node srvc_even_gemnoc = {
1137 .name = "srvc_even_gemnoc",
1138 .id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
1144 static struct qcom_icc_node srvc_odd_gemnoc = {
1145 .name = "srvc_odd_gemnoc",
1146 .id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
1152 static struct qcom_icc_node srvc_sys_gemnoc = {
1153 .name = "srvc_sys_gemnoc",
1154 .id = SC7280_SLAVE_SERVICE_GEM_NOC,
1160 static struct qcom_icc_node qhs_lpass_core = {
1161 .name = "qhs_lpass_core",
1162 .id = SC7280_SLAVE_LPASS_CORE_CFG,
1168 static struct qcom_icc_node qhs_lpass_lpi = {
1169 .name = "qhs_lpass_lpi",
1170 .id = SC7280_SLAVE_LPASS_LPI_CFG,
1176 static struct qcom_icc_node qhs_lpass_mpu = {
1177 .name = "qhs_lpass_mpu",
1178 .id = SC7280_SLAVE_LPASS_MPU_CFG,
1184 static struct qcom_icc_node qhs_lpass_top = {
1185 .name = "qhs_lpass_top",
1186 .id = SC7280_SLAVE_LPASS_TOP_CFG,
1192 static struct qcom_icc_node srvc_niu_aml_noc = {
1193 .name = "srvc_niu_aml_noc",
1194 .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
1200 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1201 .name = "srvc_niu_lpass_agnoc",
1202 .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
1208 static struct qcom_icc_node ebi = {
1210 .id = SC7280_SLAVE_EBI1,
1216 static struct qcom_icc_node qns_mem_noc_hf = {
1217 .name = "qns_mem_noc_hf",
1218 .id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
1222 .links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
1225 static struct qcom_icc_node qns_mem_noc_sf = {
1226 .name = "qns_mem_noc_sf",
1227 .id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
1231 .links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
1234 static struct qcom_icc_node srvc_mnoc = {
1235 .name = "srvc_mnoc",
1236 .id = SC7280_SLAVE_SERVICE_MNOC,
1242 static struct qcom_icc_node qns_nsp_gemnoc = {
1243 .name = "qns_nsp_gemnoc",
1244 .id = SC7280_SLAVE_CDSP_MEM_NOC,
1248 .links = { SC7280_MASTER_COMPUTE_NOC },
1251 static struct qcom_icc_node service_nsp_noc = {
1252 .name = "service_nsp_noc",
1253 .id = SC7280_SLAVE_SERVICE_NSP_NOC,
1259 static struct qcom_icc_node qns_gemnoc_gc = {
1260 .name = "qns_gemnoc_gc",
1261 .id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
1265 .links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
1268 static struct qcom_icc_node qns_gemnoc_sf = {
1269 .name = "qns_gemnoc_sf",
1270 .id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
1274 .links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
1277 static struct qcom_icc_node srvc_snoc = {
1278 .name = "srvc_snoc",
1279 .id = SC7280_SLAVE_SERVICE_SNOC,
1285 static struct qcom_icc_bcm bcm_acv = {
1291 static struct qcom_icc_bcm bcm_ce0 = {
1294 .nodes = { &qxm_crypto },
1297 static struct qcom_icc_bcm bcm_cn0 = {
1301 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1304 static struct qcom_icc_bcm bcm_cn1 = {
1307 .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap,
1308 &qhs_ahb2phy0, &qhs_ahb2phy1,
1309 &qhs_camera_cfg, &qhs_clk_ctl,
1310 &qhs_compute_cfg, &qhs_cpr_cx,
1311 &qhs_cpr_mx, &qhs_crypto0_cfg,
1312 &qhs_cx_rdpm, &qhs_dcc_cfg,
1313 &qhs_display_cfg, &qhs_gpuss_cfg,
1314 &qhs_hwkm, &qhs_imem_cfg,
1315 &qhs_ipa, &qhs_ipc_router,
1316 &qhs_mss_cfg, &qhs_mx_rdpm,
1317 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1318 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
1319 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
1320 &qhs_qup0, &qhs_qup1,
1321 &qhs_security, &qhs_tcsr,
1322 &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2,
1323 &qhs_usb3_0, &qhs_venus_cfg,
1324 &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg,
1325 &qns_a2_noc_cfg, &qns_cnoc2_cnoc3,
1326 &qns_mnoc_cfg, &qns_snoc_cfg,
1327 &qnm_cnoc2_cnoc3, &qhs_aoss,
1328 &qhs_apss, &qns_cnoc3_cnoc2,
1329 &qns_cnoc_a2noc, &qns_ddrss_cfg },
1332 static struct qcom_icc_bcm bcm_cn2 = {
1335 .nodes = { &qhs_lpass_cfg, &qhs_pdm,
1336 &qhs_qspi, &qhs_sdc1,
1337 &qhs_sdc2, &qhs_sdc4 },
1340 static struct qcom_icc_bcm bcm_co0 = {
1343 .nodes = { &qns_nsp_gemnoc },
1346 static struct qcom_icc_bcm bcm_co3 = {
1349 .nodes = { &qxm_nsp },
1352 static struct qcom_icc_bcm bcm_mc0 = {
1359 static struct qcom_icc_bcm bcm_mm0 = {
1363 .nodes = { &qns_mem_noc_hf },
1366 static struct qcom_icc_bcm bcm_mm1 = {
1369 .nodes = { &qxm_camnoc_hf, &qxm_mdp0 },
1372 static struct qcom_icc_bcm bcm_mm4 = {
1375 .nodes = { &qns_mem_noc_sf },
1378 static struct qcom_icc_bcm bcm_mm5 = {
1381 .nodes = { &qnm_video0, &qxm_camnoc_icp,
1385 static struct qcom_icc_bcm bcm_qup0 = {
1389 .nodes = { &qup0_core_slave },
1392 static struct qcom_icc_bcm bcm_qup1 = {
1396 .nodes = { &qup1_core_slave },
1399 static struct qcom_icc_bcm bcm_sh0 = {
1403 .nodes = { &qns_llcc },
1406 static struct qcom_icc_bcm bcm_sh2 = {
1409 .nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1412 static struct qcom_icc_bcm bcm_sh3 = {
1415 .nodes = { &qnm_cmpnoc },
1418 static struct qcom_icc_bcm bcm_sh4 = {
1421 .nodes = { &chm_apps },
1424 static struct qcom_icc_bcm bcm_sn0 = {
1428 .nodes = { &qns_gemnoc_sf },
1431 static struct qcom_icc_bcm bcm_sn2 = {
1434 .nodes = { &qns_gemnoc_gc },
1437 static struct qcom_icc_bcm bcm_sn3 = {
1440 .nodes = { &qxs_pimem },
1443 static struct qcom_icc_bcm bcm_sn4 = {
1446 .nodes = { &xs_qdss_stm },
1449 static struct qcom_icc_bcm bcm_sn5 = {
1452 .nodes = { &xm_pcie3_0 },
1455 static struct qcom_icc_bcm bcm_sn6 = {
1458 .nodes = { &xm_pcie3_1 },
1461 static struct qcom_icc_bcm bcm_sn7 = {
1464 .nodes = { &qnm_aggre1_noc },
1467 static struct qcom_icc_bcm bcm_sn8 = {
1470 .nodes = { &qnm_aggre2_noc },
1473 static struct qcom_icc_bcm bcm_sn14 = {
1476 .nodes = { &qns_pcie_mem_noc },
1479 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1485 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1486 [MASTER_QSPI_0] = &qhm_qspi,
1487 [MASTER_QUP_0] = &qhm_qup0,
1488 [MASTER_QUP_1] = &qhm_qup1,
1489 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1490 [MASTER_PCIE_0] = &xm_pcie3_0,
1491 [MASTER_PCIE_1] = &xm_pcie3_1,
1492 [MASTER_SDCC_1] = &xm_sdc1,
1493 [MASTER_SDCC_2] = &xm_sdc2,
1494 [MASTER_SDCC_4] = &xm_sdc4,
1495 [MASTER_UFS_MEM] = &xm_ufs_mem,
1496 [MASTER_USB2] = &xm_usb2,
1497 [MASTER_USB3_0] = &xm_usb3_0,
1498 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1499 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1500 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1503 static const struct qcom_icc_desc sc7280_aggre1_noc = {
1504 .nodes = aggre1_noc_nodes,
1505 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1506 .bcms = aggre1_noc_bcms,
1507 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1510 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1514 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1515 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1516 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1517 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1518 [MASTER_CRYPTO] = &qxm_crypto,
1519 [MASTER_IPA] = &qxm_ipa,
1520 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1521 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1522 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1525 static const struct qcom_icc_desc sc7280_aggre2_noc = {
1526 .nodes = aggre2_noc_nodes,
1527 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1528 .bcms = aggre2_noc_bcms,
1529 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1532 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1537 static struct qcom_icc_node * const clk_virt_nodes[] = {
1538 [MASTER_QUP_CORE_0] = &qup0_core_master,
1539 [MASTER_QUP_CORE_1] = &qup1_core_master,
1540 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1541 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1544 static const struct qcom_icc_desc sc7280_clk_virt = {
1545 .nodes = clk_virt_nodes,
1546 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1547 .bcms = clk_virt_bcms,
1548 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1551 static struct qcom_icc_bcm * const cnoc2_bcms[] = {
1556 static struct qcom_icc_node * const cnoc2_nodes[] = {
1557 [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2,
1558 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1559 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1560 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1561 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1562 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1563 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1564 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1565 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1566 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1567 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1568 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1569 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1570 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1571 [SLAVE_HWKM] = &qhs_hwkm,
1572 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1573 [SLAVE_IPA_CFG] = &qhs_ipa,
1574 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1575 [SLAVE_LPASS] = &qhs_lpass_cfg,
1576 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1577 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1578 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1579 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1580 [SLAVE_PDM] = &qhs_pdm,
1581 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1582 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1583 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1584 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1585 [SLAVE_QSPI_0] = &qhs_qspi,
1586 [SLAVE_QUP_0] = &qhs_qup0,
1587 [SLAVE_QUP_1] = &qhs_qup1,
1588 [SLAVE_SDCC_1] = &qhs_sdc1,
1589 [SLAVE_SDCC_2] = &qhs_sdc2,
1590 [SLAVE_SDCC_4] = &qhs_sdc4,
1591 [SLAVE_SECURITY] = &qhs_security,
1592 [SLAVE_TCSR] = &qhs_tcsr,
1593 [SLAVE_TLMM] = &qhs_tlmm,
1594 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1595 [SLAVE_USB2] = &qhs_usb2,
1596 [SLAVE_USB3_0] = &qhs_usb3_0,
1597 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1598 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1599 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1600 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1601 [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3,
1602 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1603 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1606 static const struct qcom_icc_desc sc7280_cnoc2 = {
1607 .nodes = cnoc2_nodes,
1608 .num_nodes = ARRAY_SIZE(cnoc2_nodes),
1610 .num_bcms = ARRAY_SIZE(cnoc2_bcms),
1613 static struct qcom_icc_bcm * const cnoc3_bcms[] = {
1620 static struct qcom_icc_node * const cnoc3_nodes[] = {
1621 [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3,
1622 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1623 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1624 [SLAVE_AOSS] = &qhs_aoss,
1625 [SLAVE_APPSS] = &qhs_apss,
1626 [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2,
1627 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1628 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1629 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1630 [SLAVE_IMEM] = &qxs_imem,
1631 [SLAVE_PIMEM] = &qxs_pimem,
1632 [SLAVE_PCIE_0] = &xs_pcie_0,
1633 [SLAVE_PCIE_1] = &xs_pcie_1,
1634 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1635 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1638 static const struct qcom_icc_desc sc7280_cnoc3 = {
1639 .nodes = cnoc3_nodes,
1640 .num_nodes = ARRAY_SIZE(cnoc3_nodes),
1642 .num_bcms = ARRAY_SIZE(cnoc3_bcms),
1645 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1648 static struct qcom_icc_node * const dc_noc_nodes[] = {
1649 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1650 [SLAVE_LLCC_CFG] = &qhs_llcc,
1651 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1654 static const struct qcom_icc_desc sc7280_dc_noc = {
1655 .nodes = dc_noc_nodes,
1656 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1657 .bcms = dc_noc_bcms,
1658 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1661 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1668 static struct qcom_icc_node * const gem_noc_nodes[] = {
1669 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1670 [MASTER_SYS_TCU] = &alm_sys_tcu,
1671 [MASTER_APPSS_PROC] = &chm_apps,
1672 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1673 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1674 [MASTER_GFX3D] = &qnm_gpu,
1675 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1676 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1677 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1678 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1679 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1680 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1681 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1682 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1683 [SLAVE_LLCC] = &qns_llcc,
1684 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1685 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1686 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1687 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1690 static const struct qcom_icc_desc sc7280_gem_noc = {
1691 .nodes = gem_noc_nodes,
1692 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1693 .bcms = gem_noc_bcms,
1694 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1697 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1700 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1701 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1702 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1703 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1704 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1705 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1706 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1707 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1710 static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
1711 .nodes = lpass_ag_noc_nodes,
1712 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1713 .bcms = lpass_ag_noc_bcms,
1714 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1717 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1722 static struct qcom_icc_node * const mc_virt_nodes[] = {
1723 [MASTER_LLCC] = &llcc_mc,
1724 [SLAVE_EBI1] = &ebi,
1727 static const struct qcom_icc_desc sc7280_mc_virt = {
1728 .nodes = mc_virt_nodes,
1729 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1730 .bcms = mc_virt_bcms,
1731 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1734 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1741 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1742 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1743 [MASTER_VIDEO_P0] = &qnm_video0,
1744 [MASTER_VIDEO_PROC] = &qnm_video_cpu,
1745 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
1746 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
1747 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1748 [MASTER_MDP0] = &qxm_mdp0,
1749 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1750 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1751 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1754 static const struct qcom_icc_desc sc7280_mmss_noc = {
1755 .nodes = mmss_noc_nodes,
1756 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1757 .bcms = mmss_noc_bcms,
1758 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1761 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1766 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1767 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1768 [MASTER_CDSP_PROC] = &qxm_nsp,
1769 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1770 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1773 static const struct qcom_icc_desc sc7280_nsp_noc = {
1774 .nodes = nsp_noc_nodes,
1775 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1776 .bcms = nsp_noc_bcms,
1777 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1780 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1787 static struct qcom_icc_node * const system_noc_nodes[] = {
1788 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1789 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1790 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1791 [MASTER_PIMEM] = &qxm_pimem,
1792 [MASTER_GIC] = &xm_gic,
1793 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1794 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1795 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1798 static const struct qcom_icc_desc sc7280_system_noc = {
1799 .nodes = system_noc_nodes,
1800 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1801 .bcms = system_noc_bcms,
1802 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1805 static const struct of_device_id qnoc_of_match[] = {
1806 { .compatible = "qcom,sc7280-aggre1-noc",
1807 .data = &sc7280_aggre1_noc},
1808 { .compatible = "qcom,sc7280-aggre2-noc",
1809 .data = &sc7280_aggre2_noc},
1810 { .compatible = "qcom,sc7280-clk-virt",
1811 .data = &sc7280_clk_virt},
1812 { .compatible = "qcom,sc7280-cnoc2",
1813 .data = &sc7280_cnoc2},
1814 { .compatible = "qcom,sc7280-cnoc3",
1815 .data = &sc7280_cnoc3},
1816 { .compatible = "qcom,sc7280-dc-noc",
1817 .data = &sc7280_dc_noc},
1818 { .compatible = "qcom,sc7280-gem-noc",
1819 .data = &sc7280_gem_noc},
1820 { .compatible = "qcom,sc7280-lpass-ag-noc",
1821 .data = &sc7280_lpass_ag_noc},
1822 { .compatible = "qcom,sc7280-mc-virt",
1823 .data = &sc7280_mc_virt},
1824 { .compatible = "qcom,sc7280-mmss-noc",
1825 .data = &sc7280_mmss_noc},
1826 { .compatible = "qcom,sc7280-nsp-noc",
1827 .data = &sc7280_nsp_noc},
1828 { .compatible = "qcom,sc7280-system-noc",
1829 .data = &sc7280_system_noc},
1832 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1834 static struct platform_driver qnoc_driver = {
1835 .probe = qcom_icc_rpmh_probe,
1836 .remove = qcom_icc_rpmh_remove,
1838 .name = "qnoc-sc7280",
1839 .of_match_table = qnoc_of_match,
1840 .sync_state = icc_sync_state,
1843 module_platform_driver(qnoc_driver);
1845 MODULE_DESCRIPTION("SC7280 NoC driver");
1846 MODULE_LICENSE("GPL v2");